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mac80211: Update IBSS beacon timestamp properly
[linux-2.6/linux-2.6-openrd.git] / drivers / net / tc35815.c
blobb52a1c088f37717ff19e82df83ee0bd4743bd352
1 /*
2 * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
3 *
4 * Based on skelton.c by Donald Becker.
5 *
6 * This driver is a replacement of older and less maintained version.
7 * This is a header of the older version:
8 * -----<snip>-----
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: MontaVista Software, Inc.
11 * ahennessy@mvista.com
12 * Copyright (C) 2000-2001 Toshiba Corporation
13 * static const char *version =
14 * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
15 * -----<snip>-----
16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 *
21 * (C) Copyright TOSHIBA CORPORATION 2004-2005
22 * All Rights Reserved.
23 */
24
25 #ifdef TC35815_NAPI
26 #define DRV_VERSION "1.37-NAPI"
27 #else
28 #define DRV_VERSION "1.37"
29 #endif
30 static const char *version = "tc35815.c:v" DRV_VERSION "\n";
31 #define MODNAME "tc35815"
32
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/types.h>
36 #include <linux/fcntl.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/in.h>
40 #include <linux/if_vlan.h>
41 #include <linux/slab.h>
42 #include <linux/string.h>
43 #include <linux/spinlock.h>
44 #include <linux/errno.h>
45 #include <linux/init.h>
46 #include <linux/netdevice.h>
47 #include <linux/etherdevice.h>
48 #include <linux/skbuff.h>
49 #include <linux/delay.h>
50 #include <linux/pci.h>
51 #include <linux/phy.h>
52 #include <linux/workqueue.h>
53 #include <linux/platform_device.h>
54 #include <asm/io.h>
55 #include <asm/byteorder.h>
56
57 /* First, a few definitions that the brave might change. */
58
59 #define GATHER_TXINT /* On-Demand Tx Interrupt */
60 #define WORKAROUND_LOSTCAR
61 #define WORKAROUND_100HALF_PROMISC
62 /* #define TC35815_USE_PACKEDBUFFER */
63
64 enum tc35815_chiptype {
65 TC35815CF = 0,
66 TC35815_NWU,
67 TC35815_TX4939,
68 };
69
70 /* indexed by tc35815_chiptype, above */
71 static const struct {
72 const char *name;
73 } chip_info[] __devinitdata = {
74 { "TOSHIBA TC35815CF 10/100BaseTX" },
75 { "TOSHIBA TC35815 with Wake on LAN" },
76 { "TOSHIBA TC35815/TX4939" },
77 };
78
79 static const struct pci_device_id tc35815_pci_tbl[] = {
80 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
81 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
82 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
83 {0,}
84 };
85 MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
86
87 /* see MODULE_PARM_DESC */
88 static struct tc35815_options {
89 int speed;
90 int duplex;
91 } options;
92
93 /*
94 * Registers
95 */
96 struct tc35815_regs {
97 __u32 DMA_Ctl; /* 0x00 */
98 __u32 TxFrmPtr;
99 __u32 TxThrsh;
100 __u32 TxPollCtr;
101 __u32 BLFrmPtr;
102 __u32 RxFragSize;
103 __u32 Int_En;
104 __u32 FDA_Bas;
105 __u32 FDA_Lim; /* 0x20 */
106 __u32 Int_Src;
107 __u32 unused0[2];
108 __u32 PauseCnt;
109 __u32 RemPauCnt;
110 __u32 TxCtlFrmStat;
111 __u32 unused1;
112 __u32 MAC_Ctl; /* 0x40 */
113 __u32 CAM_Ctl;
114 __u32 Tx_Ctl;
115 __u32 Tx_Stat;
116 __u32 Rx_Ctl;
117 __u32 Rx_Stat;
118 __u32 MD_Data;
119 __u32 MD_CA;
120 __u32 CAM_Adr; /* 0x60 */
121 __u32 CAM_Data;
122 __u32 CAM_Ena;
123 __u32 PROM_Ctl;
124 __u32 PROM_Data;
125 __u32 Algn_Cnt;
126 __u32 CRC_Cnt;
127 __u32 Miss_Cnt;
128 };
129
130 /*
131 * Bit assignments
132 */
133 /* DMA_Ctl bit asign ------------------------------------------------------- */
134 #define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
135 #define DMA_RxAlign_1 0x00400000
136 #define DMA_RxAlign_2 0x00800000
137 #define DMA_RxAlign_3 0x00c00000
138 #define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
139 #define DMA_IntMask 0x00040000 /* 1:Interupt mask */
140 #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
141 #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
142 #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
143 #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
144 #define DMA_TestMode 0x00002000 /* 1:Test Mode */
145 #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
146 #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
147
148 /* RxFragSize bit asign ---------------------------------------------------- */
149 #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
150 #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
151
152 /* MAC_Ctl bit asign ------------------------------------------------------- */
153 #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
154 #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
155 #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
156 #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
157 #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
158 #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
159 #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
160 #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
161 #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
162 #define MAC_Reset 0x00000004 /* 1:Software Reset */
163 #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
164 #define MAC_HaltReq 0x00000001 /* 1:Halt request */
165
166 /* PROM_Ctl bit asign ------------------------------------------------------ */
167 #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
168 #define PROM_Read 0x00004000 /*10:Read operation */
169 #define PROM_Write 0x00002000 /*01:Write operation */
170 #define PROM_Erase 0x00006000 /*11:Erase operation */
171 /*00:Enable or Disable Writting, */
172 /* as specified in PROM_Addr. */
173 #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
174 /*00xxxx: disable */
175
176 /* CAM_Ctl bit asign ------------------------------------------------------- */
177 #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
178 #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
179 /* accept other */
180 #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
181 #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
182 #define CAM_StationAcc 0x00000001 /* 1:unicast accept */
183
184 /* CAM_Ena bit asign ------------------------------------------------------- */
185 #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
186 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
187 #define CAM_Ena_Bit(index) (1 << (index))
188 #define CAM_ENTRY_DESTINATION 0
189 #define CAM_ENTRY_SOURCE 1
190 #define CAM_ENTRY_MACCTL 20
191
192 /* Tx_Ctl bit asign -------------------------------------------------------- */
193 #define Tx_En 0x00000001 /* 1:Transmit enable */
194 #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
195 #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
196 #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
197 #define Tx_FBack 0x00000010 /* 1:Fast Back-off */
198 #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
199 #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
200 #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
201 #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
202 #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
203 #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
204 #define Tx_EnComp 0x00004000 /* 1:Enable Completion */
205
206 /* Tx_Stat bit asign ------------------------------------------------------- */
207 #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
208 #define Tx_ExColl 0x00000010 /* Excessive Collision */
209 #define Tx_TXDefer 0x00000020 /* Transmit Defered */
210 #define Tx_Paused 0x00000040 /* Transmit Paused */
211 #define Tx_IntTx 0x00000080 /* Interrupt on Tx */
212 #define Tx_Under 0x00000100 /* Underrun */
213 #define Tx_Defer 0x00000200 /* Deferral */
214 #define Tx_NCarr 0x00000400 /* No Carrier */
215 #define Tx_10Stat 0x00000800 /* 10Mbps Status */
216 #define Tx_LateColl 0x00001000 /* Late Collision */
217 #define Tx_TxPar 0x00002000 /* Tx Parity Error */
218 #define Tx_Comp 0x00004000 /* Completion */
219 #define Tx_Halted 0x00008000 /* Tx Halted */
220 #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
221
222 /* Rx_Ctl bit asign -------------------------------------------------------- */
223 #define Rx_EnGood 0x00004000 /* 1:Enable Good */
224 #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
225 #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
226 #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
227 #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
228 #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
229 #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
230 #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
231 #define Rx_ShortEn 0x00000008 /* 1:Short Enable */
232 #define Rx_LongEn 0x00000004 /* 1:Long Enable */
233 #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
234 #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
235
236 /* Rx_Stat bit asign ------------------------------------------------------- */
237 #define Rx_Halted 0x00008000 /* Rx Halted */
238 #define Rx_Good 0x00004000 /* Rx Good */
239 #define Rx_RxPar 0x00002000 /* Rx Parity Error */
240 #define Rx_TypePkt 0x00001000 /* Rx Type Packet */
241 #define Rx_LongErr 0x00000800 /* Rx Long Error */
242 #define Rx_Over 0x00000400 /* Rx Overflow */
243 #define Rx_CRCErr 0x00000200 /* Rx CRC Error */
244 #define Rx_Align 0x00000100 /* Rx Alignment Error */
245 #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
246 #define Rx_IntRx 0x00000040 /* Rx Interrupt */
247 #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
248 #define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */
249
250 #define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */
251
252 /* Int_En bit asign -------------------------------------------------------- */
253 #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
254 #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */
255 #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
256 #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
257 #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
258 #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
259 #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
260 #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
261 #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
262 #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
263 #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
264 #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
265 /* Exhausted Enable */
266
267 /* Int_Src bit asign ------------------------------------------------------- */
268 #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
269 #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
270 #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
271 #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
272 #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
273 #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
274 #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
275 #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
276 #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
277 #define Int_SWInt 0x00000020 /* 1:Software request & Clear */
278 #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
279 #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
280 #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
281 #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
282 #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
283
284 /* MD_CA bit asign --------------------------------------------------------- */
285 #define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */
286 #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
287 #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
288
289
290 /*
291 * Descriptors
292 */
293
294 /* Frame descripter */
295 struct FDesc {
296 volatile __u32 FDNext;
297 volatile __u32 FDSystem;
298 volatile __u32 FDStat;
299 volatile __u32 FDCtl;
300 };
301
302 /* Buffer descripter */
303 struct BDesc {
304 volatile __u32 BuffData;
305 volatile __u32 BDCtl;
306 };
307
308 #define FD_ALIGN 16
309
310 /* Frame Descripter bit asign ---------------------------------------------- */
311 #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
312 #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
313 #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
314 #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
315 #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
316 #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
317 #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
318 #define FD_FrmOpt_Packing 0x04000000 /* Rx only */
319 #define FD_CownsFD 0x80000000 /* FD Controller owner bit */
320 #define FD_Next_EOL 0x00000001 /* FD EOL indicator */
321 #define FD_BDCnt_SHIFT 16
322
323 /* Buffer Descripter bit asign --------------------------------------------- */
324 #define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */
325 #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
326 #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
327 #define BD_CownsBD 0x80000000 /* BD Controller owner bit */
328 #define BD_RxBDID_SHIFT 16
329 #define BD_RxBDSeqN_SHIFT 24
330
331
332 /* Some useful constants. */
333 #undef NO_CHECK_CARRIER /* Does not check No-Carrier with TP */
334
335 #ifdef NO_CHECK_CARRIER
336 #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
337 Tx_EnExColl | Tx_EnExDefer | Tx_EnUnder | \
338 Tx_En) /* maybe 0x7b01 */
339 #else
340 #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
341 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
342 Tx_En) /* maybe 0x7b01 */
343 #endif
344 #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
345 | Rx_EnCRCErr | Rx_EnAlign | Rx_StripCRC | Rx_RxEn) /* maybe 0x6f11 */
346 #define INT_EN_CMD (Int_NRAbtEn | \
347 Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
348 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
349 Int_STargAbtEn | \
350 Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
351 #define DMA_CTL_CMD DMA_BURST_SIZE
352 #define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF)
353
354 /* Tuning parameters */
355 #define DMA_BURST_SIZE 32
356 #define TX_THRESHOLD 1024
357 /* used threshold with packet max byte for low pci transfer ability.*/
358 #define TX_THRESHOLD_MAX 1536
359 /* setting threshold max value when overrun error occured this count. */
360 #define TX_THRESHOLD_KEEP_LIMIT 10
361
362 /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
363 #ifdef TC35815_USE_PACKEDBUFFER
364 #define FD_PAGE_NUM 2
365 #define RX_BUF_NUM 8 /* >= 2 */
366 #define RX_FD_NUM 250 /* >= 32 */
367 #define TX_FD_NUM 128
368 #define RX_BUF_SIZE PAGE_SIZE
369 #else /* TC35815_USE_PACKEDBUFFER */
370 #define FD_PAGE_NUM 4
371 #define RX_BUF_NUM 128 /* < 256 */
372 #define RX_FD_NUM 256 /* >= 32 */
373 #define TX_FD_NUM 128
374 #if RX_CTL_CMD & Rx_LongEn
375 #define RX_BUF_SIZE PAGE_SIZE
376 #elif RX_CTL_CMD & Rx_StripCRC
377 #define RX_BUF_SIZE \
378 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
379 #else
380 #define RX_BUF_SIZE \
381 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
382 #endif
383 #endif /* TC35815_USE_PACKEDBUFFER */
384 #define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */
385 #define NAPI_WEIGHT 16
386
387 struct TxFD {
388 struct FDesc fd;
389 struct BDesc bd;
390 struct BDesc unused;
391 };
392
393 struct RxFD {
394 struct FDesc fd;
395 struct BDesc bd[0]; /* variable length */
396 };
397
398 struct FrFD {
399 struct FDesc fd;
400 struct BDesc bd[RX_BUF_NUM];
401 };
402
403
404 #define tc_readl(addr) ioread32(addr)
405 #define tc_writel(d, addr) iowrite32(d, addr)
406
407 #define TC35815_TX_TIMEOUT msecs_to_jiffies(400)
408
409 /* Information that need to be kept for each controller. */
410 struct tc35815_local {
411 struct pci_dev *pci_dev;
412
413 struct net_device *dev;
414 struct napi_struct napi;
415
416 /* statistics */
417 struct {
418 int max_tx_qlen;
419 int tx_ints;
420 int rx_ints;
421 int tx_underrun;
422 } lstats;
423
424 /* Tx control lock. This protects the transmit buffer ring
425 * state along with the "tx full" state of the driver. This
426 * means all netif_queue flow control actions are protected
427 * by this lock as well.
428 */
429 spinlock_t lock;
430
431 struct mii_bus *mii_bus;
432 struct phy_device *phy_dev;
433 int duplex;
434 int speed;
435 int link;
436 struct work_struct restart_work;
437
438 /*
439 * Transmitting: Batch Mode.
440 * 1 BD in 1 TxFD.
441 * Receiving: Packing Mode. (TC35815_USE_PACKEDBUFFER)
442 * 1 circular FD for Free Buffer List.
443 * RX_BUF_NUM BD in Free Buffer FD.
444 * One Free Buffer BD has PAGE_SIZE data buffer.
445 * Or Non-Packing Mode.
446 * 1 circular FD for Free Buffer List.
447 * RX_BUF_NUM BD in Free Buffer FD.
448 * One Free Buffer BD has ETH_FRAME_LEN data buffer.
449 */
450 void *fd_buf; /* for TxFD, RxFD, FrFD */
451 dma_addr_t fd_buf_dma;
452 struct TxFD *tfd_base;
453 unsigned int tfd_start;
454 unsigned int tfd_end;
455 struct RxFD *rfd_base;
456 struct RxFD *rfd_limit;
457 struct RxFD *rfd_cur;
458 struct FrFD *fbl_ptr;
459 #ifdef TC35815_USE_PACKEDBUFFER
460 unsigned char fbl_curid;
461 void *data_buf[RX_BUF_NUM]; /* packing */
462 dma_addr_t data_buf_dma[RX_BUF_NUM];
463 struct {
464 struct sk_buff *skb;
465 dma_addr_t skb_dma;
466 } tx_skbs[TX_FD_NUM];
467 #else
468 unsigned int fbl_count;
469 struct {
470 struct sk_buff *skb;
471 dma_addr_t skb_dma;
472 } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
473 #endif
474 u32 msg_enable;
475 enum tc35815_chiptype chiptype;
476 };
477
478 static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
479 {
480 return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
481 }
482 #ifdef DEBUG
483 static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
484 {
485 return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
486 }
487 #endif
488 #ifdef TC35815_USE_PACKEDBUFFER
489 static inline void *rxbuf_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
490 {
491 int i;
492 for (i = 0; i < RX_BUF_NUM; i++) {
493 if (bus >= lp->data_buf_dma[i] &&
494 bus < lp->data_buf_dma[i] + PAGE_SIZE)
495 return (void *)((u8 *)lp->data_buf[i] +
496 (bus - lp->data_buf_dma[i]));
497 }
498 return NULL;
499 }
500
501 #define TC35815_DMA_SYNC_ONDEMAND
502 static void *alloc_rxbuf_page(struct pci_dev *hwdev, dma_addr_t *dma_handle)
503 {
504 #ifdef TC35815_DMA_SYNC_ONDEMAND
505 void *buf;
506 /* pci_map + pci_dma_sync will be more effective than
507 * pci_alloc_consistent on some archs. */
508 buf = (void *)__get_free_page(GFP_ATOMIC);
509 if (!buf)
510 return NULL;
511 *dma_handle = pci_map_single(hwdev, buf, PAGE_SIZE,
512 PCI_DMA_FROMDEVICE);
513 if (pci_dma_mapping_error(hwdev, *dma_handle)) {
514 free_page((unsigned long)buf);
515 return NULL;
516 }
517 return buf;
518 #else
519 return pci_alloc_consistent(hwdev, PAGE_SIZE, dma_handle);
520 #endif
521 }
522
523 static void free_rxbuf_page(struct pci_dev *hwdev, void *buf, dma_addr_t dma_handle)
524 {
525 #ifdef TC35815_DMA_SYNC_ONDEMAND
526 pci_unmap_single(hwdev, dma_handle, PAGE_SIZE, PCI_DMA_FROMDEVICE);
527 free_page((unsigned long)buf);
528 #else
529 pci_free_consistent(hwdev, PAGE_SIZE, buf, dma_handle);
530 #endif
531 }
532 #else /* TC35815_USE_PACKEDBUFFER */
533 static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
534 struct pci_dev *hwdev,
535 dma_addr_t *dma_handle)
536 {
537 struct sk_buff *skb;
538 skb = dev_alloc_skb(RX_BUF_SIZE);
539 if (!skb)
540 return NULL;
541 *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
542 PCI_DMA_FROMDEVICE);
543 if (pci_dma_mapping_error(hwdev, *dma_handle)) {
544 dev_kfree_skb_any(skb);
545 return NULL;
546 }
547 skb_reserve(skb, 2); /* make IP header 4byte aligned */
548 return skb;
549 }
550
551 static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
552 {
553 pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
554 PCI_DMA_FROMDEVICE);
555 dev_kfree_skb_any(skb);
556 }
557 #endif /* TC35815_USE_PACKEDBUFFER */
558
559 /* Index to functions, as function prototypes. */
560
561 static int tc35815_open(struct net_device *dev);
562 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
563 static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
564 #ifdef TC35815_NAPI
565 static int tc35815_rx(struct net_device *dev, int limit);
566 static int tc35815_poll(struct napi_struct *napi, int budget);
567 #else
568 static void tc35815_rx(struct net_device *dev);
569 #endif
570 static void tc35815_txdone(struct net_device *dev);
571 static int tc35815_close(struct net_device *dev);
572 static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
573 static void tc35815_set_multicast_list(struct net_device *dev);
574 static void tc35815_tx_timeout(struct net_device *dev);
575 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
576 #ifdef CONFIG_NET_POLL_CONTROLLER
577 static void tc35815_poll_controller(struct net_device *dev);
578 #endif
579 static const struct ethtool_ops tc35815_ethtool_ops;
580
581 /* Example routines you must write ;->. */
582 static void tc35815_chip_reset(struct net_device *dev);
583 static void tc35815_chip_init(struct net_device *dev);
584
585 #ifdef DEBUG
586 static void panic_queues(struct net_device *dev);
587 #endif
588
589 static void tc35815_restart_work(struct work_struct *work);
590
591 static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
592 {
593 struct net_device *dev = bus->priv;
594 struct tc35815_regs __iomem *tr =
595 (struct tc35815_regs __iomem *)dev->base_addr;
596 unsigned long timeout = jiffies + 10;
597
598 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
599 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
600 if (time_after(jiffies, timeout))
601 return -EIO;
602 cpu_relax();
603 }
604 return tc_readl(&tr->MD_Data) & 0xffff;
605 }
606
607 static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
608 {
609 struct net_device *dev = bus->priv;
610 struct tc35815_regs __iomem *tr =
611 (struct tc35815_regs __iomem *)dev->base_addr;
612 unsigned long timeout = jiffies + 10;
613
614 tc_writel(val, &tr->MD_Data);
615 tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
616 &tr->MD_CA);
617 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
618 if (time_after(jiffies, timeout))
619 return -EIO;
620 cpu_relax();
621 }
622 return 0;
623 }
624
625 static void tc_handle_link_change(struct net_device *dev)
626 {
627 struct tc35815_local *lp = netdev_priv(dev);
628 struct phy_device *phydev = lp->phy_dev;
629 unsigned long flags;
630 int status_change = 0;
631
632 spin_lock_irqsave(&lp->lock, flags);
633 if (phydev->link &&
634 (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
635 struct tc35815_regs __iomem *tr =
636 (struct tc35815_regs __iomem *)dev->base_addr;
637 u32 reg;
638
639 reg = tc_readl(&tr->MAC_Ctl);
640 reg |= MAC_HaltReq;
641 tc_writel(reg, &tr->MAC_Ctl);
642 if (phydev->duplex == DUPLEX_FULL)
643 reg |= MAC_FullDup;
644 else
645 reg &= ~MAC_FullDup;
646 tc_writel(reg, &tr->MAC_Ctl);
647 reg &= ~MAC_HaltReq;
648 tc_writel(reg, &tr->MAC_Ctl);
649
650 /*
651 * TX4939 PCFG.SPEEDn bit will be changed on
652 * NETDEV_CHANGE event.
653 */
654
655 #if !defined(NO_CHECK_CARRIER) && defined(WORKAROUND_LOSTCAR)
656 /*
657 * WORKAROUND: enable LostCrS only if half duplex
658 * operation.
659 * (TX4939 does not have EnLCarr)
660 */
661 if (phydev->duplex == DUPLEX_HALF &&
662 lp->chiptype != TC35815_TX4939)
663 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
664 &tr->Tx_Ctl);
665 #endif
666
667 lp->speed = phydev->speed;
668 lp->duplex = phydev->duplex;
669 status_change = 1;
670 }
671
672 if (phydev->link != lp->link) {
673 if (phydev->link) {
674 #ifdef WORKAROUND_100HALF_PROMISC
675 /* delayed promiscuous enabling */
676 if (dev->flags & IFF_PROMISC)
677 tc35815_set_multicast_list(dev);
678 #endif
679 } else {
680 lp->speed = 0;
681 lp->duplex = -1;
682 }
683 lp->link = phydev->link;
684
685 status_change = 1;
686 }
687 spin_unlock_irqrestore(&lp->lock, flags);
688
689 if (status_change && netif_msg_link(lp)) {
690 phy_print_status(phydev);
691 #ifdef DEBUG
692 printk(KERN_DEBUG
693 "%s: MII BMCR %04x BMSR %04x LPA %04x\n",
694 dev->name,
695 phy_read(phydev, MII_BMCR),
696 phy_read(phydev, MII_BMSR),
697 phy_read(phydev, MII_LPA));
698 #endif
699 }
700 }
701
702 static int tc_mii_probe(struct net_device *dev)
703 {
704 struct tc35815_local *lp = netdev_priv(dev);
705 struct phy_device *phydev = NULL;
706 int phy_addr;
707 u32 dropmask;
708
709 /* find the first phy */
710 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
711 if (lp->mii_bus->phy_map[phy_addr]) {
712 if (phydev) {
713 printk(KERN_ERR "%s: multiple PHYs found\n",
714 dev->name);
715 return -EINVAL;
716 }
717 phydev = lp->mii_bus->phy_map[phy_addr];
718 break;
719 }
720 }
721
722 if (!phydev) {
723 printk(KERN_ERR "%s: no PHY found\n", dev->name);
724 return -ENODEV;
725 }
726
727 /* attach the mac to the phy */
728 phydev = phy_connect(dev, dev_name(&phydev->dev),
729 &tc_handle_link_change, 0,
730 lp->chiptype == TC35815_TX4939 ?
731 PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
732 if (IS_ERR(phydev)) {
733 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
734 return PTR_ERR(phydev);
735 }
736 printk(KERN_INFO "%s: attached PHY driver [%s] "
737 "(mii_bus:phy_addr=%s, id=%x)\n",
738 dev->name, phydev->drv->name, dev_name(&phydev->dev),
739 phydev->phy_id);
740
741 /* mask with MAC supported features */
742 phydev->supported &= PHY_BASIC_FEATURES;
743 dropmask = 0;
744 if (options.speed == 10)
745 dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
746 else if (options.speed == 100)
747 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
748 if (options.duplex == 1)
749 dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
750 else if (options.duplex == 2)
751 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
752 phydev->supported &= ~dropmask;
753 phydev->advertising = phydev->supported;
754
755 lp->link = 0;
756 lp->speed = 0;
757 lp->duplex = -1;
758 lp->phy_dev = phydev;
759
760 return 0;
761 }
762
763 static int tc_mii_init(struct net_device *dev)
764 {
765 struct tc35815_local *lp = netdev_priv(dev);
766 int err;
767 int i;
768
769 lp->mii_bus = mdiobus_alloc();
770 if (lp->mii_bus == NULL) {
771 err = -ENOMEM;
772 goto err_out;
773 }
774
775 lp->mii_bus->name = "tc35815_mii_bus";
776 lp->mii_bus->read = tc_mdio_read;
777 lp->mii_bus->write = tc_mdio_write;
778 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
779 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
780 lp->mii_bus->priv = dev;
781 lp->mii_bus->parent = &lp->pci_dev->dev;
782 lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
783 if (!lp->mii_bus->irq) {
784 err = -ENOMEM;
785 goto err_out_free_mii_bus;
786 }
787
788 for (i = 0; i < PHY_MAX_ADDR; i++)
789 lp->mii_bus->irq[i] = PHY_POLL;
790
791 err = mdiobus_register(lp->mii_bus);
792 if (err)
793 goto err_out_free_mdio_irq;
794 err = tc_mii_probe(dev);
795 if (err)
796 goto err_out_unregister_bus;
797 return 0;
798
799 err_out_unregister_bus:
800 mdiobus_unregister(lp->mii_bus);
801 err_out_free_mdio_irq:
802 kfree(lp->mii_bus->irq);
803 err_out_free_mii_bus:
804 mdiobus_free(lp->mii_bus);
805 err_out:
806 return err;
807 }
808
809 #ifdef CONFIG_CPU_TX49XX
810 /*
811 * Find a platform_device providing a MAC address. The platform code
812 * should provide a "tc35815-mac" device with a MAC address in its
813 * platform_data.
814 */
815 static int __devinit tc35815_mac_match(struct device *dev, void *data)
816 {
817 struct platform_device *plat_dev = to_platform_device(dev);
818 struct pci_dev *pci_dev = data;
819 unsigned int id = pci_dev->irq;
820 return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
821 }
822
823 static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
824 {
825 struct tc35815_local *lp = netdev_priv(dev);
826 struct device *pd = bus_find_device(&platform_bus_type, NULL,
827 lp->pci_dev, tc35815_mac_match);
828 if (pd) {
829 if (pd->platform_data)
830 memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
831 put_device(pd);
832 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
833 }
834 return -ENODEV;
835 }
836 #else
837 static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
838 {
839 return -ENODEV;
840 }
841 #endif
842
843 static int __devinit tc35815_init_dev_addr(struct net_device *dev)
844 {
845 struct tc35815_regs __iomem *tr =
846 (struct tc35815_regs __iomem *)dev->base_addr;
847 int i;
848
849 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
850 ;
851 for (i = 0; i < 6; i += 2) {
852 unsigned short data;
853 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
854 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
855 ;
856 data = tc_readl(&tr->PROM_Data);
857 dev->dev_addr[i] = data & 0xff;
858 dev->dev_addr[i+1] = data >> 8;
859 }
860 if (!is_valid_ether_addr(dev->dev_addr))
861 return tc35815_read_plat_dev_addr(dev);
862 return 0;
863 }
864
865 static int __devinit tc35815_init_one(struct pci_dev *pdev,
866 const struct pci_device_id *ent)
867 {
868 void __iomem *ioaddr = NULL;
869 struct net_device *dev;
870 struct tc35815_local *lp;
871 int rc;
872
873 static int printed_version;
874 if (!printed_version++) {
875 printk(version);
876 dev_printk(KERN_DEBUG, &pdev->dev,
877 "speed:%d duplex:%d\n",
878 options.speed, options.duplex);
879 }
880
881 if (!pdev->irq) {
882 dev_warn(&pdev->dev, "no IRQ assigned.\n");
883 return -ENODEV;
884 }
885
886 /* dev zeroed in alloc_etherdev */
887 dev = alloc_etherdev(sizeof(*lp));
888 if (dev == NULL) {
889 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
890 return -ENOMEM;
891 }
892 SET_NETDEV_DEV(dev, &pdev->dev);
893 lp = netdev_priv(dev);
894 lp->dev = dev;
895
896 /* enable device (incl. PCI PM wakeup), and bus-mastering */
897 rc = pcim_enable_device(pdev);
898 if (rc)
899 goto err_out;
900 rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
901 if (rc)
902 goto err_out;
903 pci_set_master(pdev);
904 ioaddr = pcim_iomap_table(pdev)[1];
905
906 /* Initialize the device structure. */
907 dev->open = tc35815_open;
908 dev->hard_start_xmit = tc35815_send_packet;
909 dev->stop = tc35815_close;
910 dev->get_stats = tc35815_get_stats;
911 dev->set_multicast_list = tc35815_set_multicast_list;
912 dev->do_ioctl = tc35815_ioctl;
913 dev->ethtool_ops = &tc35815_ethtool_ops;
914 dev->tx_timeout = tc35815_tx_timeout;
915 dev->watchdog_timeo = TC35815_TX_TIMEOUT;
916 #ifdef TC35815_NAPI
917 netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
918 #endif
919 #ifdef CONFIG_NET_POLL_CONTROLLER
920 dev->poll_controller = tc35815_poll_controller;
921 #endif
922
923 dev->irq = pdev->irq;
924 dev->base_addr = (unsigned long)ioaddr;
925
926 INIT_WORK(&lp->restart_work, tc35815_restart_work);
927 spin_lock_init(&lp->lock);
928 lp->pci_dev = pdev;
929 lp->chiptype = ent->driver_data;
930
931 lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
932 pci_set_drvdata(pdev, dev);
933
934 /* Soft reset the chip. */
935 tc35815_chip_reset(dev);
936
937 /* Retrieve the ethernet address. */
938 if (tc35815_init_dev_addr(dev)) {
939 dev_warn(&pdev->dev, "not valid ether addr\n");
940 random_ether_addr(dev->dev_addr);
941 }
942
943 rc = register_netdev(dev);
944 if (rc)
945 goto err_out;
946
947 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
948 printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
949 dev->name,
950 chip_info[ent->driver_data].name,
951 dev->base_addr,
952 dev->dev_addr,
953 dev->irq);
954
955 rc = tc_mii_init(dev);
956 if (rc)
957 goto err_out_unregister;
958
959 return 0;
960
961 err_out_unregister:
962 unregister_netdev(dev);
963 err_out:
964 free_netdev(dev);
965 return rc;
966 }
967
968
969 static void __devexit tc35815_remove_one(struct pci_dev *pdev)
970 {
971 struct net_device *dev = pci_get_drvdata(pdev);
972 struct tc35815_local *lp = netdev_priv(dev);
973
974 phy_disconnect(lp->phy_dev);
975 mdiobus_unregister(lp->mii_bus);
976 kfree(lp->mii_bus->irq);
977 mdiobus_free(lp->mii_bus);
978 unregister_netdev(dev);
979 free_netdev(dev);
980 pci_set_drvdata(pdev, NULL);
981 }
982
983 static int
984 tc35815_init_queues(struct net_device *dev)
985 {
986 struct tc35815_local *lp = netdev_priv(dev);
987 int i;
988 unsigned long fd_addr;
989
990 if (!lp->fd_buf) {
991 BUG_ON(sizeof(struct FDesc) +
992 sizeof(struct BDesc) * RX_BUF_NUM +
993 sizeof(struct FDesc) * RX_FD_NUM +
994 sizeof(struct TxFD) * TX_FD_NUM >
995 PAGE_SIZE * FD_PAGE_NUM);
996
997 lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
998 PAGE_SIZE * FD_PAGE_NUM,
999 &lp->fd_buf_dma);
1000 if (!lp->fd_buf)
1001 return -ENOMEM;
1002 for (i = 0; i < RX_BUF_NUM; i++) {
1003 #ifdef TC35815_USE_PACKEDBUFFER
1004 lp->data_buf[i] =
1005 alloc_rxbuf_page(lp->pci_dev,
1006 &lp->data_buf_dma[i]);
1007 if (!lp->data_buf[i]) {
1008 while (--i >= 0) {
1009 free_rxbuf_page(lp->pci_dev,
1010 lp->data_buf[i],
1011 lp->data_buf_dma[i]);
1012 lp->data_buf[i] = NULL;
1013 }
1014 pci_free_consistent(lp->pci_dev,
1015 PAGE_SIZE * FD_PAGE_NUM,
1016 lp->fd_buf,
1017 lp->fd_buf_dma);
1018 lp->fd_buf = NULL;
1019 return -ENOMEM;
1020 }
1021 #else
1022 lp->rx_skbs[i].skb =
1023 alloc_rxbuf_skb(dev, lp->pci_dev,
1024 &lp->rx_skbs[i].skb_dma);
1025 if (!lp->rx_skbs[i].skb) {
1026 while (--i >= 0) {
1027 free_rxbuf_skb(lp->pci_dev,
1028 lp->rx_skbs[i].skb,
1029 lp->rx_skbs[i].skb_dma);
1030 lp->rx_skbs[i].skb = NULL;
1031 }
1032 pci_free_consistent(lp->pci_dev,
1033 PAGE_SIZE * FD_PAGE_NUM,
1034 lp->fd_buf,
1035 lp->fd_buf_dma);
1036 lp->fd_buf = NULL;
1037 return -ENOMEM;
1038 }
1039 #endif
1040 }
1041 printk(KERN_DEBUG "%s: FD buf %p DataBuf",
1042 dev->name, lp->fd_buf);
1043 #ifdef TC35815_USE_PACKEDBUFFER
1044 printk(" DataBuf");
1045 for (i = 0; i < RX_BUF_NUM; i++)
1046 printk(" %p", lp->data_buf[i]);
1047 #endif
1048 printk("\n");
1049 } else {
1050 for (i = 0; i < FD_PAGE_NUM; i++)
1051 clear_page((void *)((unsigned long)lp->fd_buf +
1052 i * PAGE_SIZE));
1053 }
1054 fd_addr = (unsigned long)lp->fd_buf;
1055
1056 /* Free Descriptors (for Receive) */
1057 lp->rfd_base = (struct RxFD *)fd_addr;
1058 fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
1059 for (i = 0; i < RX_FD_NUM; i++)
1060 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
1061 lp->rfd_cur = lp->rfd_base;
1062 lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
1063
1064 /* Transmit Descriptors */
1065 lp->tfd_base = (struct TxFD *)fd_addr;
1066 fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
1067 for (i = 0; i < TX_FD_NUM; i++) {
1068 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
1069 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1070 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
1071 }
1072 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
1073 lp->tfd_start = 0;
1074 lp->tfd_end = 0;
1075
1076 /* Buffer List (for Receive) */
1077 lp->fbl_ptr = (struct FrFD *)fd_addr;
1078 lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
1079 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
1080 #ifndef TC35815_USE_PACKEDBUFFER
1081 /*
1082 * move all allocated skbs to head of rx_skbs[] array.
1083 * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
1084 * tc35815_rx() had failed.
1085 */
1086 lp->fbl_count = 0;
1087 for (i = 0; i < RX_BUF_NUM; i++) {
1088 if (lp->rx_skbs[i].skb) {
1089 if (i != lp->fbl_count) {
1090 lp->rx_skbs[lp->fbl_count].skb =
1091 lp->rx_skbs[i].skb;
1092 lp->rx_skbs[lp->fbl_count].skb_dma =
1093 lp->rx_skbs[i].skb_dma;
1094 }
1095 lp->fbl_count++;
1096 }
1097 }
1098 #endif
1099 for (i = 0; i < RX_BUF_NUM; i++) {
1100 #ifdef TC35815_USE_PACKEDBUFFER
1101 lp->fbl_ptr->bd[i].BuffData = cpu_to_le32(lp->data_buf_dma[i]);
1102 #else
1103 if (i >= lp->fbl_count) {
1104 lp->fbl_ptr->bd[i].BuffData = 0;
1105 lp->fbl_ptr->bd[i].BDCtl = 0;
1106 continue;
1107 }
1108 lp->fbl_ptr->bd[i].BuffData =
1109 cpu_to_le32(lp->rx_skbs[i].skb_dma);
1110 #endif
1111 /* BDID is index of FrFD.bd[] */
1112 lp->fbl_ptr->bd[i].BDCtl =
1113 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
1114 RX_BUF_SIZE);
1115 }
1116 #ifdef TC35815_USE_PACKEDBUFFER
1117 lp->fbl_curid = 0;
1118 #endif
1119
1120 printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
1121 dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
1122 return 0;
1123 }
1124
1125 static void
1126 tc35815_clear_queues(struct net_device *dev)
1127 {
1128 struct tc35815_local *lp = netdev_priv(dev);
1129 int i;
1130
1131 for (i = 0; i < TX_FD_NUM; i++) {
1132 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1133 struct sk_buff *skb =
1134 fdsystem != 0xffffffff ?
1135 lp->tx_skbs[fdsystem].skb : NULL;
1136 #ifdef DEBUG
1137 if (lp->tx_skbs[i].skb != skb) {
1138 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1139 panic_queues(dev);
1140 }
1141 #else
1142 BUG_ON(lp->tx_skbs[i].skb != skb);
1143 #endif
1144 if (skb) {
1145 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1146 lp->tx_skbs[i].skb = NULL;
1147 lp->tx_skbs[i].skb_dma = 0;
1148 dev_kfree_skb_any(skb);
1149 }
1150 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1151 }
1152
1153 tc35815_init_queues(dev);
1154 }
1155
1156 static void
1157 tc35815_free_queues(struct net_device *dev)
1158 {
1159 struct tc35815_local *lp = netdev_priv(dev);
1160 int i;
1161
1162 if (lp->tfd_base) {
1163 for (i = 0; i < TX_FD_NUM; i++) {
1164 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1165 struct sk_buff *skb =
1166 fdsystem != 0xffffffff ?
1167 lp->tx_skbs[fdsystem].skb : NULL;
1168 #ifdef DEBUG
1169 if (lp->tx_skbs[i].skb != skb) {
1170 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1171 panic_queues(dev);
1172 }
1173 #else
1174 BUG_ON(lp->tx_skbs[i].skb != skb);
1175 #endif
1176 if (skb) {
1177 dev_kfree_skb(skb);
1178 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1179 lp->tx_skbs[i].skb = NULL;
1180 lp->tx_skbs[i].skb_dma = 0;
1181 }
1182 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1183 }
1184 }
1185
1186 lp->rfd_base = NULL;
1187 lp->rfd_limit = NULL;
1188 lp->rfd_cur = NULL;
1189 lp->fbl_ptr = NULL;
1190
1191 for (i = 0; i < RX_BUF_NUM; i++) {
1192 #ifdef TC35815_USE_PACKEDBUFFER
1193 if (lp->data_buf[i]) {
1194 free_rxbuf_page(lp->pci_dev,
1195 lp->data_buf[i], lp->data_buf_dma[i]);
1196 lp->data_buf[i] = NULL;
1197 }
1198 #else
1199 if (lp->rx_skbs[i].skb) {
1200 free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1201 lp->rx_skbs[i].skb_dma);
1202 lp->rx_skbs[i].skb = NULL;
1203 }
1204 #endif
1205 }
1206 if (lp->fd_buf) {
1207 pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
1208 lp->fd_buf, lp->fd_buf_dma);
1209 lp->fd_buf = NULL;
1210 }
1211 }
1212
1213 static void
1214 dump_txfd(struct TxFD *fd)
1215 {
1216 printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1217 le32_to_cpu(fd->fd.FDNext),
1218 le32_to_cpu(fd->fd.FDSystem),
1219 le32_to_cpu(fd->fd.FDStat),
1220 le32_to_cpu(fd->fd.FDCtl));
1221 printk("BD: ");
1222 printk(" %08x %08x",
1223 le32_to_cpu(fd->bd.BuffData),
1224 le32_to_cpu(fd->bd.BDCtl));
1225 printk("\n");
1226 }
1227
1228 static int
1229 dump_rxfd(struct RxFD *fd)
1230 {
1231 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1232 if (bd_count > 8)
1233 bd_count = 8;
1234 printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1235 le32_to_cpu(fd->fd.FDNext),
1236 le32_to_cpu(fd->fd.FDSystem),
1237 le32_to_cpu(fd->fd.FDStat),
1238 le32_to_cpu(fd->fd.FDCtl));
1239 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
1240 return 0;
1241 printk("BD: ");
1242 for (i = 0; i < bd_count; i++)
1243 printk(" %08x %08x",
1244 le32_to_cpu(fd->bd[i].BuffData),
1245 le32_to_cpu(fd->bd[i].BDCtl));
1246 printk("\n");
1247 return bd_count;
1248 }
1249
1250 #if defined(DEBUG) || defined(TC35815_USE_PACKEDBUFFER)
1251 static void
1252 dump_frfd(struct FrFD *fd)
1253 {
1254 int i;
1255 printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1256 le32_to_cpu(fd->fd.FDNext),
1257 le32_to_cpu(fd->fd.FDSystem),
1258 le32_to_cpu(fd->fd.FDStat),
1259 le32_to_cpu(fd->fd.FDCtl));
1260 printk("BD: ");
1261 for (i = 0; i < RX_BUF_NUM; i++)
1262 printk(" %08x %08x",
1263 le32_to_cpu(fd->bd[i].BuffData),
1264 le32_to_cpu(fd->bd[i].BDCtl));
1265 printk("\n");
1266 }
1267 #endif
1268
1269 #ifdef DEBUG
1270 static void
1271 panic_queues(struct net_device *dev)
1272 {
1273 struct tc35815_local *lp = netdev_priv(dev);
1274 int i;
1275
1276 printk("TxFD base %p, start %u, end %u\n",
1277 lp->tfd_base, lp->tfd_start, lp->tfd_end);
1278 printk("RxFD base %p limit %p cur %p\n",
1279 lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1280 printk("FrFD %p\n", lp->fbl_ptr);
1281 for (i = 0; i < TX_FD_NUM; i++)
1282 dump_txfd(&lp->tfd_base[i]);
1283 for (i = 0; i < RX_FD_NUM; i++) {
1284 int bd_count = dump_rxfd(&lp->rfd_base[i]);
1285 i += (bd_count + 1) / 2; /* skip BDs */
1286 }
1287 dump_frfd(lp->fbl_ptr);
1288 panic("%s: Illegal queue state.", dev->name);
1289 }
1290 #endif
1291
1292 static void print_eth(const u8 *add)
1293 {
1294 printk(KERN_DEBUG "print_eth(%p)\n", add);
1295 printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
1296 add + 6, add, add[12], add[13]);
1297 }
1298
1299 static int tc35815_tx_full(struct net_device *dev)
1300 {
1301 struct tc35815_local *lp = netdev_priv(dev);
1302 return ((lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end);
1303 }
1304
1305 static void tc35815_restart(struct net_device *dev)
1306 {
1307 struct tc35815_local *lp = netdev_priv(dev);
1308
1309 if (lp->phy_dev) {
1310 int timeout;
1311
1312 phy_write(lp->phy_dev, MII_BMCR, BMCR_RESET);
1313 timeout = 100;
1314 while (--timeout) {
1315 if (!(phy_read(lp->phy_dev, MII_BMCR) & BMCR_RESET))
1316 break;
1317 udelay(1);
1318 }
1319 if (!timeout)
1320 printk(KERN_ERR "%s: BMCR reset failed.\n", dev->name);
1321 }
1322
1323 spin_lock_irq(&lp->lock);
1324 tc35815_chip_reset(dev);
1325 tc35815_clear_queues(dev);
1326 tc35815_chip_init(dev);
1327 /* Reconfigure CAM again since tc35815_chip_init() initialize it. */
1328 tc35815_set_multicast_list(dev);
1329 spin_unlock_irq(&lp->lock);
1330
1331 netif_wake_queue(dev);
1332 }
1333
1334 static void tc35815_restart_work(struct work_struct *work)
1335 {
1336 struct tc35815_local *lp =
1337 container_of(work, struct tc35815_local, restart_work);
1338 struct net_device *dev = lp->dev;
1339
1340 tc35815_restart(dev);
1341 }
1342
1343 static void tc35815_schedule_restart(struct net_device *dev)
1344 {
1345 struct tc35815_local *lp = netdev_priv(dev);
1346 struct tc35815_regs __iomem *tr =
1347 (struct tc35815_regs __iomem *)dev->base_addr;
1348
1349 /* disable interrupts */
1350 tc_writel(0, &tr->Int_En);
1351 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1352 schedule_work(&lp->restart_work);
1353 }
1354
1355 static void tc35815_tx_timeout(struct net_device *dev)
1356 {
1357 struct tc35815_regs __iomem *tr =
1358 (struct tc35815_regs __iomem *)dev->base_addr;
1359
1360 printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1361 dev->name, tc_readl(&tr->Tx_Stat));
1362
1363 /* Try to restart the adaptor. */
1364 tc35815_schedule_restart(dev);
1365 dev->stats.tx_errors++;
1366 }
1367
1368 /*
1369 * Open/initialize the controller. This is called (in the current kernel)
1370 * sometime after booting when the 'ifconfig' program is run.
1371 *
1372 * This routine should set everything up anew at each open, even
1373 * registers that "should" only need to be set once at boot, so that
1374 * there is non-reboot way to recover if something goes wrong.
1375 */
1376 static int
1377 tc35815_open(struct net_device *dev)
1378 {
1379 struct tc35815_local *lp = netdev_priv(dev);
1380
1381 /*
1382 * This is used if the interrupt line can turned off (shared).
1383 * See 3c503.c for an example of selecting the IRQ at config-time.
1384 */
1385 if (request_irq(dev->irq, &tc35815_interrupt, IRQF_SHARED,
1386 dev->name, dev))
1387 return -EAGAIN;
1388
1389 tc35815_chip_reset(dev);
1390
1391 if (tc35815_init_queues(dev) != 0) {
1392 free_irq(dev->irq, dev);
1393 return -EAGAIN;
1394 }
1395
1396 #ifdef TC35815_NAPI
1397 napi_enable(&lp->napi);
1398 #endif
1399
1400 /* Reset the hardware here. Don't forget to set the station address. */
1401 spin_lock_irq(&lp->lock);
1402 tc35815_chip_init(dev);
1403 spin_unlock_irq(&lp->lock);
1404
1405 netif_carrier_off(dev);
1406 /* schedule a link state check */
1407 phy_start(lp->phy_dev);
1408
1409 /* We are now ready to accept transmit requeusts from
1410 * the queueing layer of the networking.
1411 */
1412 netif_start_queue(dev);
1413
1414 return 0;
1415 }
1416
1417 /* This will only be invoked if your driver is _not_ in XOFF state.
1418 * What this means is that you need not check it, and that this
1419 * invariant will hold if you make sure that the netif_*_queue()
1420 * calls are done at the proper times.
1421 */
1422 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1423 {
1424 struct tc35815_local *lp = netdev_priv(dev);
1425 struct TxFD *txfd;
1426 unsigned long flags;
1427
1428 /* If some error occurs while trying to transmit this
1429 * packet, you should return '1' from this function.
1430 * In such a case you _may not_ do anything to the
1431 * SKB, it is still owned by the network queueing
1432 * layer when an error is returned. This means you
1433 * may not modify any SKB fields, you may not free
1434 * the SKB, etc.
1435 */
1436
1437 /* This is the most common case for modern hardware.
1438 * The spinlock protects this code from the TX complete
1439 * hardware interrupt handler. Queue flow control is
1440 * thus managed under this lock as well.
1441 */
1442 spin_lock_irqsave(&lp->lock, flags);
1443
1444 /* failsafe... (handle txdone now if half of FDs are used) */
1445 if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1446 TX_FD_NUM / 2)
1447 tc35815_txdone(dev);
1448
1449 if (netif_msg_pktdata(lp))
1450 print_eth(skb->data);
1451 #ifdef DEBUG
1452 if (lp->tx_skbs[lp->tfd_start].skb) {
1453 printk("%s: tx_skbs conflict.\n", dev->name);
1454 panic_queues(dev);
1455 }
1456 #else
1457 BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1458 #endif
1459 lp->tx_skbs[lp->tfd_start].skb = skb;
1460 lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1461
1462 /*add to ring */
1463 txfd = &lp->tfd_base[lp->tfd_start];
1464 txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1465 txfd->bd.BDCtl = cpu_to_le32(skb->len);
1466 txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1467 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1468
1469 if (lp->tfd_start == lp->tfd_end) {
1470 struct tc35815_regs __iomem *tr =
1471 (struct tc35815_regs __iomem *)dev->base_addr;
1472 /* Start DMA Transmitter. */
1473 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1474 #ifdef GATHER_TXINT
1475 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1476 #endif
1477 if (netif_msg_tx_queued(lp)) {
1478 printk("%s: starting TxFD.\n", dev->name);
1479 dump_txfd(txfd);
1480 }
1481 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1482 } else {
1483 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1484 if (netif_msg_tx_queued(lp)) {
1485 printk("%s: queueing TxFD.\n", dev->name);
1486 dump_txfd(txfd);
1487 }
1488 }
1489 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1490
1491 dev->trans_start = jiffies;
1492
1493 /* If we just used up the very last entry in the
1494 * TX ring on this device, tell the queueing
1495 * layer to send no more.
1496 */
1497 if (tc35815_tx_full(dev)) {
1498 if (netif_msg_tx_queued(lp))
1499 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1500 netif_stop_queue(dev);
1501 }
1502
1503 /* When the TX completion hw interrupt arrives, this
1504 * is when the transmit statistics are updated.
1505 */
1506
1507 spin_unlock_irqrestore(&lp->lock, flags);
1508 return 0;
1509 }
1510
1511 #define FATAL_ERROR_INT \
1512 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1513 static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1514 {
1515 static int count;
1516 printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
1517 dev->name, status);
1518 if (status & Int_IntPCI)
1519 printk(" IntPCI");
1520 if (status & Int_DmParErr)
1521 printk(" DmParErr");
1522 if (status & Int_IntNRAbt)
1523 printk(" IntNRAbt");
1524 printk("\n");
1525 if (count++ > 100)
1526 panic("%s: Too many fatal errors.", dev->name);
1527 printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1528 /* Try to restart the adaptor. */
1529 tc35815_schedule_restart(dev);
1530 }
1531
1532 #ifdef TC35815_NAPI
1533 static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
1534 #else
1535 static int tc35815_do_interrupt(struct net_device *dev, u32 status)
1536 #endif
1537 {
1538 struct tc35815_local *lp = netdev_priv(dev);
1539 struct tc35815_regs __iomem *tr =
1540 (struct tc35815_regs __iomem *)dev->base_addr;
1541 int ret = -1;
1542
1543 /* Fatal errors... */
1544 if (status & FATAL_ERROR_INT) {
1545 tc35815_fatal_error_interrupt(dev, status);
1546 return 0;
1547 }
1548 /* recoverable errors */
1549 if (status & Int_IntFDAEx) {
1550 /* disable FDAEx int. (until we make rooms...) */
1551 tc_writel(tc_readl(&tr->Int_En) & ~Int_FDAExEn, &tr->Int_En);
1552 printk(KERN_WARNING
1553 "%s: Free Descriptor Area Exhausted (%#x).\n",
1554 dev->name, status);
1555 dev->stats.rx_dropped++;
1556 ret = 0;
1557 }
1558 if (status & Int_IntBLEx) {
1559 /* disable BLEx int. (until we make rooms...) */
1560 tc_writel(tc_readl(&tr->Int_En) & ~Int_BLExEn, &tr->Int_En);
1561 printk(KERN_WARNING
1562 "%s: Buffer List Exhausted (%#x).\n",
1563 dev->name, status);
1564 dev->stats.rx_dropped++;
1565 ret = 0;
1566 }
1567 if (status & Int_IntExBD) {
1568 printk(KERN_WARNING
1569 "%s: Excessive Buffer Descriptiors (%#x).\n",
1570 dev->name, status);
1571 dev->stats.rx_length_errors++;
1572 ret = 0;
1573 }
1574
1575 /* normal notification */
1576 if (status & Int_IntMacRx) {
1577 /* Got a packet(s). */
1578 #ifdef TC35815_NAPI
1579 ret = tc35815_rx(dev, limit);
1580 #else
1581 tc35815_rx(dev);
1582 ret = 0;
1583 #endif
1584 lp->lstats.rx_ints++;
1585 }
1586 if (status & Int_IntMacTx) {
1587 /* Transmit complete. */
1588 lp->lstats.tx_ints++;
1589 tc35815_txdone(dev);
1590 netif_wake_queue(dev);
1591 ret = 0;
1592 }
1593 return ret;
1594 }
1595
1596 /*
1597 * The typical workload of the driver:
1598 * Handle the network interface interrupts.
1599 */
1600 static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1601 {
1602 struct net_device *dev = dev_id;
1603 struct tc35815_local *lp = netdev_priv(dev);
1604 struct tc35815_regs __iomem *tr =
1605 (struct tc35815_regs __iomem *)dev->base_addr;
1606 #ifdef TC35815_NAPI
1607 u32 dmactl = tc_readl(&tr->DMA_Ctl);
1608
1609 if (!(dmactl & DMA_IntMask)) {
1610 /* disable interrupts */
1611 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1612 if (napi_schedule_prep(&lp->napi))
1613 __napi_schedule(&lp->napi);
1614 else {
1615 printk(KERN_ERR "%s: interrupt taken in poll\n",
1616 dev->name);
1617 BUG();
1618 }
1619 (void)tc_readl(&tr->Int_Src); /* flush */
1620 return IRQ_HANDLED;
1621 }
1622 return IRQ_NONE;
1623 #else
1624 int handled;
1625 u32 status;
1626
1627 spin_lock(&lp->lock);
1628 status = tc_readl(&tr->Int_Src);
1629 tc_writel(status, &tr->Int_Src); /* write to clear */
1630 handled = tc35815_do_interrupt(dev, status);
1631 (void)tc_readl(&tr->Int_Src); /* flush */
1632 spin_unlock(&lp->lock);
1633 return IRQ_RETVAL(handled >= 0);
1634 #endif /* TC35815_NAPI */
1635 }
1636
1637 #ifdef CONFIG_NET_POLL_CONTROLLER
1638 static void tc35815_poll_controller(struct net_device *dev)
1639 {
1640 disable_irq(dev->irq);
1641 tc35815_interrupt(dev->irq, dev);
1642 enable_irq(dev->irq);
1643 }
1644 #endif
1645
1646 /* We have a good packet(s), get it/them out of the buffers. */
1647 #ifdef TC35815_NAPI
1648 static int
1649 tc35815_rx(struct net_device *dev, int limit)
1650 #else
1651 static void
1652 tc35815_rx(struct net_device *dev)
1653 #endif
1654 {
1655 struct tc35815_local *lp = netdev_priv(dev);
1656 unsigned int fdctl;
1657 int i;
1658 int buf_free_count = 0;
1659 int fd_free_count = 0;
1660 #ifdef TC35815_NAPI
1661 int received = 0;
1662 #endif
1663
1664 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1665 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1666 int pkt_len = fdctl & FD_FDLength_MASK;
1667 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1668 #ifdef DEBUG
1669 struct RxFD *next_rfd;
1670 #endif
1671 #if (RX_CTL_CMD & Rx_StripCRC) == 0
1672 pkt_len -= ETH_FCS_LEN;
1673 #endif
1674
1675 if (netif_msg_rx_status(lp))
1676 dump_rxfd(lp->rfd_cur);
1677 if (status & Rx_Good) {
1678 struct sk_buff *skb;
1679 unsigned char *data;
1680 int cur_bd;
1681 #ifdef TC35815_USE_PACKEDBUFFER
1682 int offset;
1683 #endif
1684
1685 #ifdef TC35815_NAPI
1686 if (--limit < 0)
1687 break;
1688 #endif
1689 #ifdef TC35815_USE_PACKEDBUFFER
1690 BUG_ON(bd_count > 2);
1691 skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN);
1692 if (skb == NULL) {
1693 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n",
1694 dev->name);
1695 dev->stats.rx_dropped++;
1696 break;
1697 }
1698 skb_reserve(skb, NET_IP_ALIGN);
1699
1700 data = skb_put(skb, pkt_len);
1701
1702 /* copy from receive buffer */
1703 cur_bd = 0;
1704 offset = 0;
1705 while (offset < pkt_len && cur_bd < bd_count) {
1706 int len = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BDCtl) &
1707 BD_BuffLength_MASK;
1708 dma_addr_t dma = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BuffData);
1709 void *rxbuf = rxbuf_bus_to_virt(lp, dma);
1710 if (offset + len > pkt_len)
1711 len = pkt_len - offset;
1712 #ifdef TC35815_DMA_SYNC_ONDEMAND
1713 pci_dma_sync_single_for_cpu(lp->pci_dev,
1714 dma, len,
1715 PCI_DMA_FROMDEVICE);
1716 #endif
1717 memcpy(data + offset, rxbuf, len);
1718 #ifdef TC35815_DMA_SYNC_ONDEMAND
1719 pci_dma_sync_single_for_device(lp->pci_dev,
1720 dma, len,
1721 PCI_DMA_FROMDEVICE);
1722 #endif
1723 offset += len;
1724 cur_bd++;
1725 }
1726 #else /* TC35815_USE_PACKEDBUFFER */
1727 BUG_ON(bd_count > 1);
1728 cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1729 & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1730 #ifdef DEBUG
1731 if (cur_bd >= RX_BUF_NUM) {
1732 printk("%s: invalid BDID.\n", dev->name);
1733 panic_queues(dev);
1734 }
1735 BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1736 (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1737 if (!lp->rx_skbs[cur_bd].skb) {
1738 printk("%s: NULL skb.\n", dev->name);
1739 panic_queues(dev);
1740 }
1741 #else
1742 BUG_ON(cur_bd >= RX_BUF_NUM);
1743 #endif
1744 skb = lp->rx_skbs[cur_bd].skb;
1745 prefetch(skb->data);
1746 lp->rx_skbs[cur_bd].skb = NULL;
1747 pci_unmap_single(lp->pci_dev,
1748 lp->rx_skbs[cur_bd].skb_dma,
1749 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1750 if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN)
1751 memmove(skb->data, skb->data - NET_IP_ALIGN,
1752 pkt_len);
1753 data = skb_put(skb, pkt_len);
1754 #endif /* TC35815_USE_PACKEDBUFFER */
1755 if (netif_msg_pktdata(lp))
1756 print_eth(data);
1757 skb->protocol = eth_type_trans(skb, dev);
1758 #ifdef TC35815_NAPI
1759 netif_receive_skb(skb);
1760 received++;
1761 #else
1762 netif_rx(skb);
1763 #endif
1764 dev->stats.rx_packets++;
1765 dev->stats.rx_bytes += pkt_len;
1766 } else {
1767 dev->stats.rx_errors++;
1768 printk(KERN_DEBUG "%s: Rx error (status %x)\n",
1769 dev->name, status & Rx_Stat_Mask);
1770 /* WORKAROUND: LongErr and CRCErr means Overflow. */
1771 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1772 status &= ~(Rx_LongErr|Rx_CRCErr);
1773 status |= Rx_Over;
1774 }
1775 if (status & Rx_LongErr)
1776 dev->stats.rx_length_errors++;
1777 if (status & Rx_Over)
1778 dev->stats.rx_fifo_errors++;
1779 if (status & Rx_CRCErr)
1780 dev->stats.rx_crc_errors++;
1781 if (status & Rx_Align)
1782 dev->stats.rx_frame_errors++;
1783 }
1784
1785 if (bd_count > 0) {
1786 /* put Free Buffer back to controller */
1787 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1788 unsigned char id =
1789 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1790 #ifdef DEBUG
1791 if (id >= RX_BUF_NUM) {
1792 printk("%s: invalid BDID.\n", dev->name);
1793 panic_queues(dev);
1794 }
1795 #else
1796 BUG_ON(id >= RX_BUF_NUM);
1797 #endif
1798 /* free old buffers */
1799 #ifdef TC35815_USE_PACKEDBUFFER
1800 while (lp->fbl_curid != id)
1801 #else
1802 lp->fbl_count--;
1803 while (lp->fbl_count < RX_BUF_NUM)
1804 #endif
1805 {
1806 #ifdef TC35815_USE_PACKEDBUFFER
1807 unsigned char curid = lp->fbl_curid;
1808 #else
1809 unsigned char curid =
1810 (id + 1 + lp->fbl_count) % RX_BUF_NUM;
1811 #endif
1812 struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1813 #ifdef DEBUG
1814 bdctl = le32_to_cpu(bd->BDCtl);
1815 if (bdctl & BD_CownsBD) {
1816 printk("%s: Freeing invalid BD.\n",
1817 dev->name);
1818 panic_queues(dev);
1819 }
1820 #endif
1821 /* pass BD to controller */
1822 #ifndef TC35815_USE_PACKEDBUFFER
1823 if (!lp->rx_skbs[curid].skb) {
1824 lp->rx_skbs[curid].skb =
1825 alloc_rxbuf_skb(dev,
1826 lp->pci_dev,
1827 &lp->rx_skbs[curid].skb_dma);
1828 if (!lp->rx_skbs[curid].skb)
1829 break; /* try on next reception */
1830 bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1831 }
1832 #endif /* TC35815_USE_PACKEDBUFFER */
1833 /* Note: BDLength was modified by chip. */
1834 bd->BDCtl = cpu_to_le32(BD_CownsBD |
1835 (curid << BD_RxBDID_SHIFT) |
1836 RX_BUF_SIZE);
1837 #ifdef TC35815_USE_PACKEDBUFFER
1838 lp->fbl_curid = (curid + 1) % RX_BUF_NUM;
1839 if (netif_msg_rx_status(lp)) {
1840 printk("%s: Entering new FBD %d\n",
1841 dev->name, lp->fbl_curid);
1842 dump_frfd(lp->fbl_ptr);
1843 }
1844 #else
1845 lp->fbl_count++;
1846 #endif
1847 buf_free_count++;
1848 }
1849 }
1850
1851 /* put RxFD back to controller */
1852 #ifdef DEBUG
1853 next_rfd = fd_bus_to_virt(lp,
1854 le32_to_cpu(lp->rfd_cur->fd.FDNext));
1855 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1856 printk("%s: RxFD FDNext invalid.\n", dev->name);
1857 panic_queues(dev);
1858 }
1859 #endif
1860 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1861 /* pass FD to controller */
1862 #ifdef DEBUG
1863 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1864 #else
1865 lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1866 #endif
1867 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1868 lp->rfd_cur++;
1869 fd_free_count++;
1870 }
1871 if (lp->rfd_cur > lp->rfd_limit)
1872 lp->rfd_cur = lp->rfd_base;
1873 #ifdef DEBUG
1874 if (lp->rfd_cur != next_rfd)
1875 printk("rfd_cur = %p, next_rfd %p\n",
1876 lp->rfd_cur, next_rfd);
1877 #endif
1878 }
1879
1880 /* re-enable BL/FDA Exhaust interrupts. */
1881 if (fd_free_count) {
1882 struct tc35815_regs __iomem *tr =
1883 (struct tc35815_regs __iomem *)dev->base_addr;
1884 u32 en, en_old = tc_readl(&tr->Int_En);
1885 en = en_old | Int_FDAExEn;
1886 if (buf_free_count)
1887 en |= Int_BLExEn;
1888 if (en != en_old)
1889 tc_writel(en, &tr->Int_En);
1890 }
1891 #ifdef TC35815_NAPI
1892 return received;
1893 #endif
1894 }
1895
1896 #ifdef TC35815_NAPI
1897 static int tc35815_poll(struct napi_struct *napi, int budget)
1898 {
1899 struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1900 struct net_device *dev = lp->dev;
1901 struct tc35815_regs __iomem *tr =
1902 (struct tc35815_regs __iomem *)dev->base_addr;
1903 int received = 0, handled;
1904 u32 status;
1905
1906 spin_lock(&lp->lock);
1907 status = tc_readl(&tr->Int_Src);
1908 do {
1909 tc_writel(status, &tr->Int_Src); /* write to clear */
1910
1911 handled = tc35815_do_interrupt(dev, status, limit);
1912 if (handled >= 0) {
1913 received += handled;
1914 if (received >= budget)
1915 break;
1916 }
1917 status = tc_readl(&tr->Int_Src);
1918 } while (status);
1919 spin_unlock(&lp->lock);
1920
1921 if (received < budget) {
1922 napi_complete(napi);
1923 /* enable interrupts */
1924 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1925 }
1926 return received;
1927 }
1928 #endif
1929
1930 #ifdef NO_CHECK_CARRIER
1931 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1932 #else
1933 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1934 #endif
1935
1936 static void
1937 tc35815_check_tx_stat(struct net_device *dev, int status)
1938 {
1939 struct tc35815_local *lp = netdev_priv(dev);
1940 const char *msg = NULL;
1941
1942 /* count collisions */
1943 if (status & Tx_ExColl)
1944 dev->stats.collisions += 16;
1945 if (status & Tx_TxColl_MASK)
1946 dev->stats.collisions += status & Tx_TxColl_MASK;
1947
1948 #ifndef NO_CHECK_CARRIER
1949 /* TX4939 does not have NCarr */
1950 if (lp->chiptype == TC35815_TX4939)
1951 status &= ~Tx_NCarr;
1952 #ifdef WORKAROUND_LOSTCAR
1953 /* WORKAROUND: ignore LostCrS in full duplex operation */
1954 if (!lp->link || lp->duplex == DUPLEX_FULL)
1955 status &= ~Tx_NCarr;
1956 #endif
1957 #endif
1958
1959 if (!(status & TX_STA_ERR)) {
1960 /* no error. */
1961 dev->stats.tx_packets++;
1962 return;
1963 }
1964
1965 dev->stats.tx_errors++;
1966 if (status & Tx_ExColl) {
1967 dev->stats.tx_aborted_errors++;
1968 msg = "Excessive Collision.";
1969 }
1970 if (status & Tx_Under) {
1971 dev->stats.tx_fifo_errors++;
1972 msg = "Tx FIFO Underrun.";
1973 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1974 lp->lstats.tx_underrun++;
1975 if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1976 struct tc35815_regs __iomem *tr =
1977 (struct tc35815_regs __iomem *)dev->base_addr;
1978 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1979 msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1980 }
1981 }
1982 }
1983 if (status & Tx_Defer) {
1984 dev->stats.tx_fifo_errors++;
1985 msg = "Excessive Deferral.";
1986 }
1987 #ifndef NO_CHECK_CARRIER
1988 if (status & Tx_NCarr) {
1989 dev->stats.tx_carrier_errors++;
1990 msg = "Lost Carrier Sense.";
1991 }
1992 #endif
1993 if (status & Tx_LateColl) {
1994 dev->stats.tx_aborted_errors++;
1995 msg = "Late Collision.";
1996 }
1997 if (status & Tx_TxPar) {
1998 dev->stats.tx_fifo_errors++;
1999 msg = "Transmit Parity Error.";
2000 }
2001 if (status & Tx_SQErr) {
2002 dev->stats.tx_heartbeat_errors++;
2003 msg = "Signal Quality Error.";
2004 }
2005 if (msg && netif_msg_tx_err(lp))
2006 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
2007 }
2008
2009 /* This handles TX complete events posted by the device
2010 * via interrupts.
2011 */
2012 static void
2013 tc35815_txdone(struct net_device *dev)
2014 {
2015 struct tc35815_local *lp = netdev_priv(dev);
2016 struct TxFD *txfd;
2017 unsigned int fdctl;
2018
2019 txfd = &lp->tfd_base[lp->tfd_end];
2020 while (lp->tfd_start != lp->tfd_end &&
2021 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
2022 int status = le32_to_cpu(txfd->fd.FDStat);
2023 struct sk_buff *skb;
2024 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
2025 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
2026
2027 if (netif_msg_tx_done(lp)) {
2028 printk("%s: complete TxFD.\n", dev->name);
2029 dump_txfd(txfd);
2030 }
2031 tc35815_check_tx_stat(dev, status);
2032
2033 skb = fdsystem != 0xffffffff ?
2034 lp->tx_skbs[fdsystem].skb : NULL;
2035 #ifdef DEBUG
2036 if (lp->tx_skbs[lp->tfd_end].skb != skb) {
2037 printk("%s: tx_skbs mismatch.\n", dev->name);
2038 panic_queues(dev);
2039 }
2040 #else
2041 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
2042 #endif
2043 if (skb) {
2044 dev->stats.tx_bytes += skb->len;
2045 pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
2046 lp->tx_skbs[lp->tfd_end].skb = NULL;
2047 lp->tx_skbs[lp->tfd_end].skb_dma = 0;
2048 #ifdef TC35815_NAPI
2049 dev_kfree_skb_any(skb);
2050 #else
2051 dev_kfree_skb_irq(skb);
2052 #endif
2053 }
2054 txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
2055
2056 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
2057 txfd = &lp->tfd_base[lp->tfd_end];
2058 #ifdef DEBUG
2059 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
2060 printk("%s: TxFD FDNext invalid.\n", dev->name);
2061 panic_queues(dev);
2062 }
2063 #endif
2064 if (fdnext & FD_Next_EOL) {
2065 /* DMA Transmitter has been stopping... */
2066 if (lp->tfd_end != lp->tfd_start) {
2067 struct tc35815_regs __iomem *tr =
2068 (struct tc35815_regs __iomem *)dev->base_addr;
2069 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
2070 struct TxFD *txhead = &lp->tfd_base[head];
2071 int qlen = (lp->tfd_start + TX_FD_NUM
2072 - lp->tfd_end) % TX_FD_NUM;
2073
2074 #ifdef DEBUG
2075 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
2076 printk("%s: TxFD FDCtl invalid.\n", dev->name);
2077 panic_queues(dev);
2078 }
2079 #endif
2080 /* log max queue length */
2081 if (lp->lstats.max_tx_qlen < qlen)
2082 lp->lstats.max_tx_qlen = qlen;
2083
2084
2085 /* start DMA Transmitter again */
2086 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
2087 #ifdef GATHER_TXINT
2088 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
2089 #endif
2090 if (netif_msg_tx_queued(lp)) {
2091 printk("%s: start TxFD on queue.\n",
2092 dev->name);
2093 dump_txfd(txfd);
2094 }
2095 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
2096 }
2097 break;
2098 }
2099 }
2100
2101 /* If we had stopped the queue due to a "tx full"
2102 * condition, and space has now been made available,
2103 * wake up the queue.
2104 */
2105 if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
2106 netif_wake_queue(dev);
2107 }
2108
2109 /* The inverse routine to tc35815_open(). */
2110 static int
2111 tc35815_close(struct net_device *dev)
2112 {
2113 struct tc35815_local *lp = netdev_priv(dev);
2114
2115 netif_stop_queue(dev);
2116 #ifdef TC35815_NAPI
2117 napi_disable(&lp->napi);
2118 #endif
2119 if (lp->phy_dev)
2120 phy_stop(lp->phy_dev);
2121 cancel_work_sync(&lp->restart_work);
2122
2123 /* Flush the Tx and disable Rx here. */
2124 tc35815_chip_reset(dev);
2125 free_irq(dev->irq, dev);
2126
2127 tc35815_free_queues(dev);
2128
2129 return 0;
2130
2131 }
2132
2133 /*
2134 * Get the current statistics.
2135 * This may be called with the card open or closed.
2136 */
2137 static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
2138 {
2139 struct tc35815_regs __iomem *tr =
2140 (struct tc35815_regs __iomem *)dev->base_addr;
2141 if (netif_running(dev))
2142 /* Update the statistics from the device registers. */
2143 dev->stats.rx_missed_errors = tc_readl(&tr->Miss_Cnt);
2144
2145 return &dev->stats;
2146 }
2147
2148 static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
2149 {
2150 struct tc35815_local *lp = netdev_priv(dev);
2151 struct tc35815_regs __iomem *tr =
2152 (struct tc35815_regs __iomem *)dev->base_addr;
2153 int cam_index = index * 6;
2154 u32 cam_data;
2155 u32 saved_addr;
2156
2157 saved_addr = tc_readl(&tr->CAM_Adr);
2158
2159 if (netif_msg_hw(lp))
2160 printk(KERN_DEBUG "%s: CAM %d: %pM\n",
2161 dev->name, index, addr);
2162 if (index & 1) {
2163 /* read modify write */
2164 tc_writel(cam_index - 2, &tr->CAM_Adr);
2165 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
2166 cam_data |= addr[0] << 8 | addr[1];
2167 tc_writel(cam_data, &tr->CAM_Data);
2168 /* write whole word */
2169 tc_writel(cam_index + 2, &tr->CAM_Adr);
2170 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
2171 tc_writel(cam_data, &tr->CAM_Data);
2172 } else {
2173 /* write whole word */
2174 tc_writel(cam_index, &tr->CAM_Adr);
2175 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
2176 tc_writel(cam_data, &tr->CAM_Data);
2177 /* read modify write */
2178 tc_writel(cam_index + 4, &tr->CAM_Adr);
2179 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
2180 cam_data |= addr[4] << 24 | (addr[5] << 16);
2181 tc_writel(cam_data, &tr->CAM_Data);
2182 }
2183
2184 tc_writel(saved_addr, &tr->CAM_Adr);
2185 }
2186
2187
2188 /*
2189 * Set or clear the multicast filter for this adaptor.
2190 * num_addrs == -1 Promiscuous mode, receive all packets
2191 * num_addrs == 0 Normal mode, clear multicast list
2192 * num_addrs > 0 Multicast mode, receive normal and MC packets,
2193 * and do best-effort filtering.
2194 */
2195 static void
2196 tc35815_set_multicast_list(struct net_device *dev)
2197 {
2198 struct tc35815_regs __iomem *tr =
2199 (struct tc35815_regs __iomem *)dev->base_addr;
2200
2201 if (dev->flags & IFF_PROMISC) {
2202 #ifdef WORKAROUND_100HALF_PROMISC
2203 /* With some (all?) 100MHalf HUB, controller will hang
2204 * if we enabled promiscuous mode before linkup... */
2205 struct tc35815_local *lp = netdev_priv(dev);
2206
2207 if (!lp->link)
2208 return;
2209 #endif
2210 /* Enable promiscuous mode */
2211 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
2212 } else if ((dev->flags & IFF_ALLMULTI) ||
2213 dev->mc_count > CAM_ENTRY_MAX - 3) {
2214 /* CAM 0, 1, 20 are reserved. */
2215 /* Disable promiscuous mode, use normal mode. */
2216 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
2217 } else if (dev->mc_count) {
2218 struct dev_mc_list *cur_addr = dev->mc_list;
2219 int i;
2220 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
2221
2222 tc_writel(0, &tr->CAM_Ctl);
2223 /* Walk the address list, and load the filter */
2224 for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
2225 if (!cur_addr)
2226 break;
2227 /* entry 0,1 is reserved. */
2228 tc35815_set_cam_entry(dev, i + 2, cur_addr->dmi_addr);
2229 ena_bits |= CAM_Ena_Bit(i + 2);
2230 }
2231 tc_writel(ena_bits, &tr->CAM_Ena);
2232 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2233 } else {
2234 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2235 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2236 }
2237 }
2238
2239 static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2240 {
2241 struct tc35815_local *lp = netdev_priv(dev);
2242 strcpy(info->driver, MODNAME);
2243 strcpy(info->version, DRV_VERSION);
2244 strcpy(info->bus_info, pci_name(lp->pci_dev));
2245 }
2246
2247 static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2248 {
2249 struct tc35815_local *lp = netdev_priv(dev);
2250
2251 if (!lp->phy_dev)
2252 return -ENODEV;
2253 return phy_ethtool_gset(lp->phy_dev, cmd);
2254 }
2255
2256 static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2257 {
2258 struct tc35815_local *lp = netdev_priv(dev);
2259
2260 if (!lp->phy_dev)
2261 return -ENODEV;
2262 return phy_ethtool_sset(lp->phy_dev, cmd);
2263 }
2264
2265 static u32 tc35815_get_msglevel(struct net_device *dev)
2266 {
2267 struct tc35815_local *lp = netdev_priv(dev);
2268 return lp->msg_enable;
2269 }
2270
2271 static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
2272 {
2273 struct tc35815_local *lp = netdev_priv(dev);
2274 lp->msg_enable = datum;
2275 }
2276
2277 static int tc35815_get_sset_count(struct net_device *dev, int sset)
2278 {
2279 struct tc35815_local *lp = netdev_priv(dev);
2280
2281 switch (sset) {
2282 case ETH_SS_STATS:
2283 return sizeof(lp->lstats) / sizeof(int);
2284 default:
2285 return -EOPNOTSUPP;
2286 }
2287 }
2288
2289 static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2290 {
2291 struct tc35815_local *lp = netdev_priv(dev);
2292 data[0] = lp->lstats.max_tx_qlen;
2293 data[1] = lp->lstats.tx_ints;
2294 data[2] = lp->lstats.rx_ints;
2295 data[3] = lp->lstats.tx_underrun;
2296 }
2297
2298 static struct {
2299 const char str[ETH_GSTRING_LEN];
2300 } ethtool_stats_keys[] = {
2301 { "max_tx_qlen" },
2302 { "tx_ints" },
2303 { "rx_ints" },
2304 { "tx_underrun" },
2305 };
2306
2307 static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2308 {
2309 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2310 }
2311
2312 static const struct ethtool_ops tc35815_ethtool_ops = {
2313 .get_drvinfo = tc35815_get_drvinfo,
2314 .get_settings = tc35815_get_settings,
2315 .set_settings = tc35815_set_settings,
2316 .get_link = ethtool_op_get_link,
2317 .get_msglevel = tc35815_get_msglevel,
2318 .set_msglevel = tc35815_set_msglevel,
2319 .get_strings = tc35815_get_strings,
2320 .get_sset_count = tc35815_get_sset_count,
2321 .get_ethtool_stats = tc35815_get_ethtool_stats,
2322 };
2323
2324 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2325 {
2326 struct tc35815_local *lp = netdev_priv(dev);
2327
2328 if (!netif_running(dev))
2329 return -EINVAL;
2330 if (!lp->phy_dev)
2331 return -ENODEV;
2332 return phy_mii_ioctl(lp->phy_dev, if_mii(rq), cmd);
2333 }
2334
2335 static void tc35815_chip_reset(struct net_device *dev)
2336 {
2337 struct tc35815_regs __iomem *tr =
2338 (struct tc35815_regs __iomem *)dev->base_addr;
2339 int i;
2340 /* reset the controller */
2341 tc_writel(MAC_Reset, &tr->MAC_Ctl);
2342 udelay(4); /* 3200ns */
2343 i = 0;
2344 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2345 if (i++ > 100) {
2346 printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2347 break;
2348 }
2349 mdelay(1);
2350 }
2351 tc_writel(0, &tr->MAC_Ctl);
2352
2353 /* initialize registers to default value */
2354 tc_writel(0, &tr->DMA_Ctl);
2355 tc_writel(0, &tr->TxThrsh);
2356 tc_writel(0, &tr->TxPollCtr);
2357 tc_writel(0, &tr->RxFragSize);
2358 tc_writel(0, &tr->Int_En);
2359 tc_writel(0, &tr->FDA_Bas);
2360 tc_writel(0, &tr->FDA_Lim);
2361 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
2362 tc_writel(0, &tr->CAM_Ctl);
2363 tc_writel(0, &tr->Tx_Ctl);
2364 tc_writel(0, &tr->Rx_Ctl);
2365 tc_writel(0, &tr->CAM_Ena);
2366 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
2367
2368 /* initialize internal SRAM */
2369 tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2370 for (i = 0; i < 0x1000; i += 4) {
2371 tc_writel(i, &tr->CAM_Adr);
2372 tc_writel(0, &tr->CAM_Data);
2373 }
2374 tc_writel(0, &tr->DMA_Ctl);
2375 }
2376
2377 static void tc35815_chip_init(struct net_device *dev)
2378 {
2379 struct tc35815_local *lp = netdev_priv(dev);
2380 struct tc35815_regs __iomem *tr =
2381 (struct tc35815_regs __iomem *)dev->base_addr;
2382 unsigned long txctl = TX_CTL_CMD;
2383
2384 /* load station address to CAM */
2385 tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
2386
2387 /* Enable CAM (broadcast and unicast) */
2388 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2389 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2390
2391 /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
2392 if (HAVE_DMA_RXALIGN(lp))
2393 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2394 else
2395 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2396 #ifdef TC35815_USE_PACKEDBUFFER
2397 tc_writel(RxFrag_EnPack | ETH_ZLEN, &tr->RxFragSize); /* Packing */
2398 #else
2399 tc_writel(ETH_ZLEN, &tr->RxFragSize);
2400 #endif
2401 tc_writel(0, &tr->TxPollCtr); /* Batch mode */
2402 tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2403 tc_writel(INT_EN_CMD, &tr->Int_En);
2404
2405 /* set queues */
2406 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2407 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2408 &tr->FDA_Lim);
2409 /*
2410 * Activation method:
2411 * First, enable the MAC Transmitter and the DMA Receive circuits.
2412 * Then enable the DMA Transmitter and the MAC Receive circuits.
2413 */
2414 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
2415 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
2416
2417 /* start MAC transmitter */
2418 #ifndef NO_CHECK_CARRIER
2419 /* TX4939 does not have EnLCarr */
2420 if (lp->chiptype == TC35815_TX4939)
2421 txctl &= ~Tx_EnLCarr;
2422 #ifdef WORKAROUND_LOSTCAR
2423 /* WORKAROUND: ignore LostCrS in full duplex operation */
2424 if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL)
2425 txctl &= ~Tx_EnLCarr;
2426 #endif
2427 #endif /* !NO_CHECK_CARRIER */
2428 #ifdef GATHER_TXINT
2429 txctl &= ~Tx_EnComp; /* disable global tx completion int. */
2430 #endif
2431 tc_writel(txctl, &tr->Tx_Ctl);
2432 }
2433
2434 #ifdef CONFIG_PM
2435 static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2436 {
2437 struct net_device *dev = pci_get_drvdata(pdev);
2438 struct tc35815_local *lp = netdev_priv(dev);
2439 unsigned long flags;
2440
2441 pci_save_state(pdev);
2442 if (!netif_running(dev))
2443 return 0;
2444 netif_device_detach(dev);
2445 if (lp->phy_dev)
2446 phy_stop(lp->phy_dev);
2447 spin_lock_irqsave(&lp->lock, flags);
2448 tc35815_chip_reset(dev);
2449 spin_unlock_irqrestore(&lp->lock, flags);
2450 pci_set_power_state(pdev, PCI_D3hot);
2451 return 0;
2452 }
2453
2454 static int tc35815_resume(struct pci_dev *pdev)
2455 {
2456 struct net_device *dev = pci_get_drvdata(pdev);
2457 struct tc35815_local *lp = netdev_priv(dev);
2458
2459 pci_restore_state(pdev);
2460 if (!netif_running(dev))
2461 return 0;
2462 pci_set_power_state(pdev, PCI_D0);
2463 tc35815_restart(dev);
2464 netif_carrier_off(dev);
2465 if (lp->phy_dev)
2466 phy_start(lp->phy_dev);
2467 netif_device_attach(dev);
2468 return 0;
2469 }
2470 #endif /* CONFIG_PM */
2471
2472 static struct pci_driver tc35815_pci_driver = {
2473 .name = MODNAME,
2474 .id_table = tc35815_pci_tbl,
2475 .probe = tc35815_init_one,
2476 .remove = __devexit_p(tc35815_remove_one),
2477 #ifdef CONFIG_PM
2478 .suspend = tc35815_suspend,
2479 .resume = tc35815_resume,
2480 #endif
2481 };
2482
2483 module_param_named(speed, options.speed, int, 0);
2484 MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2485 module_param_named(duplex, options.duplex, int, 0);
2486 MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
2487
2488 static int __init tc35815_init_module(void)
2489 {
2490 return pci_register_driver(&tc35815_pci_driver);
2491 }
2492
2493 static void __exit tc35815_cleanup_module(void)
2494 {
2495 pci_unregister_driver(&tc35815_pci_driver);
2496 }
2497
2498 module_init(tc35815_init_module);
2499 module_exit(tc35815_cleanup_module);
2500
2501 MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2502 MODULE_LICENSE("GPL");
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