1 /* niu.c: Neptune ethernet driver.
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/module.h>
7 #include <linux/init.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/netdevice.h>
11 #include <linux/ethtool.h>
12 #include <linux/etherdevice.h>
13 #include <linux/platform_device.h>
14 #include <linux/delay.h>
15 #include <linux/bitops.h>
16 #include <linux/mii.h>
17 #include <linux/if_ether.h>
18 #include <linux/if_vlan.h>
21 #include <linux/ipv6.h>
22 #include <linux/log2.h>
23 #include <linux/jiffies.h>
24 #include <linux/crc32.h>
29 #include <linux/of_device.h>
34 #define DRV_MODULE_NAME "niu"
35 #define PFX DRV_MODULE_NAME ": "
36 #define DRV_MODULE_VERSION "1.0"
37 #define DRV_MODULE_RELDATE "Nov 14, 2008"
39 static char version
[] __devinitdata
=
40 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43 MODULE_DESCRIPTION("NIU ethernet driver");
44 MODULE_LICENSE("GPL");
45 MODULE_VERSION(DRV_MODULE_VERSION
);
47 #ifndef DMA_44BIT_MASK
48 #define DMA_44BIT_MASK 0x00000fffffffffffULL
52 static u64
readq(void __iomem
*reg
)
54 return ((u64
) readl(reg
)) | (((u64
) readl(reg
+ 4UL)) << 32);
57 static void writeq(u64 val
, void __iomem
*reg
)
59 writel(val
& 0xffffffff, reg
);
60 writel(val
>> 32, reg
+ 0x4UL
);
64 static struct pci_device_id niu_pci_tbl
[] = {
65 {PCI_DEVICE(PCI_VENDOR_ID_SUN
, 0xabcd)},
69 MODULE_DEVICE_TABLE(pci
, niu_pci_tbl
);
71 #define NIU_TX_TIMEOUT (5 * HZ)
73 #define nr64(reg) readq(np->regs + (reg))
74 #define nw64(reg, val) writeq((val), np->regs + (reg))
76 #define nr64_mac(reg) readq(np->mac_regs + (reg))
77 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
79 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
80 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
82 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
83 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
85 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
86 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
88 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
91 static int debug
= -1;
92 module_param(debug
, int, 0);
93 MODULE_PARM_DESC(debug
, "NIU debug level");
95 #define niudbg(TYPE, f, a...) \
96 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
97 printk(KERN_DEBUG PFX f, ## a); \
100 #define niuinfo(TYPE, f, a...) \
101 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
102 printk(KERN_INFO PFX f, ## a); \
105 #define niuwarn(TYPE, f, a...) \
106 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
107 printk(KERN_WARNING PFX f, ## a); \
110 #define niu_lock_parent(np, flags) \
111 spin_lock_irqsave(&np->parent->lock, flags)
112 #define niu_unlock_parent(np, flags) \
113 spin_unlock_irqrestore(&np->parent->lock, flags)
115 static int serdes_init_10g_serdes(struct niu
*np
);
117 static int __niu_wait_bits_clear_mac(struct niu
*np
, unsigned long reg
,
118 u64 bits
, int limit
, int delay
)
120 while (--limit
>= 0) {
121 u64 val
= nr64_mac(reg
);
132 static int __niu_set_and_wait_clear_mac(struct niu
*np
, unsigned long reg
,
133 u64 bits
, int limit
, int delay
,
134 const char *reg_name
)
139 err
= __niu_wait_bits_clear_mac(np
, reg
, bits
, limit
, delay
);
141 dev_err(np
->device
, PFX
"%s: bits (%llx) of register %s "
142 "would not clear, val[%llx]\n",
143 np
->dev
->name
, (unsigned long long) bits
, reg_name
,
144 (unsigned long long) nr64_mac(reg
));
148 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
149 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
150 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
153 static int __niu_wait_bits_clear_ipp(struct niu
*np
, unsigned long reg
,
154 u64 bits
, int limit
, int delay
)
156 while (--limit
>= 0) {
157 u64 val
= nr64_ipp(reg
);
168 static int __niu_set_and_wait_clear_ipp(struct niu
*np
, unsigned long reg
,
169 u64 bits
, int limit
, int delay
,
170 const char *reg_name
)
179 err
= __niu_wait_bits_clear_ipp(np
, reg
, bits
, limit
, delay
);
181 dev_err(np
->device
, PFX
"%s: bits (%llx) of register %s "
182 "would not clear, val[%llx]\n",
183 np
->dev
->name
, (unsigned long long) bits
, reg_name
,
184 (unsigned long long) nr64_ipp(reg
));
188 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
189 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
190 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
193 static int __niu_wait_bits_clear(struct niu
*np
, unsigned long reg
,
194 u64 bits
, int limit
, int delay
)
196 while (--limit
>= 0) {
208 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
209 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
210 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
213 static int __niu_set_and_wait_clear(struct niu
*np
, unsigned long reg
,
214 u64 bits
, int limit
, int delay
,
215 const char *reg_name
)
220 err
= __niu_wait_bits_clear(np
, reg
, bits
, limit
, delay
);
222 dev_err(np
->device
, PFX
"%s: bits (%llx) of register %s "
223 "would not clear, val[%llx]\n",
224 np
->dev
->name
, (unsigned long long) bits
, reg_name
,
225 (unsigned long long) nr64(reg
));
229 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
230 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
231 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
234 static void niu_ldg_rearm(struct niu
*np
, struct niu_ldg
*lp
, int on
)
236 u64 val
= (u64
) lp
->timer
;
239 val
|= LDG_IMGMT_ARM
;
241 nw64(LDG_IMGMT(lp
->ldg_num
), val
);
244 static int niu_ldn_irq_enable(struct niu
*np
, int ldn
, int on
)
246 unsigned long mask_reg
, bits
;
249 if (ldn
< 0 || ldn
> LDN_MAX
)
253 mask_reg
= LD_IM0(ldn
);
256 mask_reg
= LD_IM1(ldn
- 64);
260 val
= nr64(mask_reg
);
270 static int niu_enable_ldn_in_ldg(struct niu
*np
, struct niu_ldg
*lp
, int on
)
272 struct niu_parent
*parent
= np
->parent
;
275 for (i
= 0; i
<= LDN_MAX
; i
++) {
278 if (parent
->ldg_map
[i
] != lp
->ldg_num
)
281 err
= niu_ldn_irq_enable(np
, i
, on
);
288 static int niu_enable_interrupts(struct niu
*np
, int on
)
292 for (i
= 0; i
< np
->num_ldg
; i
++) {
293 struct niu_ldg
*lp
= &np
->ldg
[i
];
296 err
= niu_enable_ldn_in_ldg(np
, lp
, on
);
300 for (i
= 0; i
< np
->num_ldg
; i
++)
301 niu_ldg_rearm(np
, &np
->ldg
[i
], on
);
306 static u32
phy_encode(u32 type
, int port
)
308 return (type
<< (port
* 2));
311 static u32
phy_decode(u32 val
, int port
)
313 return (val
>> (port
* 2)) & PORT_TYPE_MASK
;
316 static int mdio_wait(struct niu
*np
)
321 while (--limit
> 0) {
322 val
= nr64(MIF_FRAME_OUTPUT
);
323 if ((val
>> MIF_FRAME_OUTPUT_TA_SHIFT
) & 0x1)
324 return val
& MIF_FRAME_OUTPUT_DATA
;
332 static int mdio_read(struct niu
*np
, int port
, int dev
, int reg
)
336 nw64(MIF_FRAME_OUTPUT
, MDIO_ADDR_OP(port
, dev
, reg
));
341 nw64(MIF_FRAME_OUTPUT
, MDIO_READ_OP(port
, dev
));
342 return mdio_wait(np
);
345 static int mdio_write(struct niu
*np
, int port
, int dev
, int reg
, int data
)
349 nw64(MIF_FRAME_OUTPUT
, MDIO_ADDR_OP(port
, dev
, reg
));
354 nw64(MIF_FRAME_OUTPUT
, MDIO_WRITE_OP(port
, dev
, data
));
362 static int mii_read(struct niu
*np
, int port
, int reg
)
364 nw64(MIF_FRAME_OUTPUT
, MII_READ_OP(port
, reg
));
365 return mdio_wait(np
);
368 static int mii_write(struct niu
*np
, int port
, int reg
, int data
)
372 nw64(MIF_FRAME_OUTPUT
, MII_WRITE_OP(port
, reg
, data
));
380 static int esr2_set_tx_cfg(struct niu
*np
, unsigned long channel
, u32 val
)
384 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
385 ESR2_TI_PLL_TX_CFG_L(channel
),
388 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
389 ESR2_TI_PLL_TX_CFG_H(channel
),
394 static int esr2_set_rx_cfg(struct niu
*np
, unsigned long channel
, u32 val
)
398 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
399 ESR2_TI_PLL_RX_CFG_L(channel
),
402 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
403 ESR2_TI_PLL_RX_CFG_H(channel
),
408 /* Mode is always 10G fiber. */
409 static int serdes_init_niu_10g_fiber(struct niu
*np
)
411 struct niu_link_config
*lp
= &np
->link_config
;
415 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
);
416 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
417 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
418 PLL_RX_CFG_EQ_LP_ADAPTIVE
);
420 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
421 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
423 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
424 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
426 tx_cfg
|= PLL_TX_CFG_ENTEST
;
427 rx_cfg
|= PLL_RX_CFG_ENTEST
;
430 /* Initialize all 4 lanes of the SERDES. */
431 for (i
= 0; i
< 4; i
++) {
432 int err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
437 for (i
= 0; i
< 4; i
++) {
438 int err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
446 static int serdes_init_niu_1g_serdes(struct niu
*np
)
448 struct niu_link_config
*lp
= &np
->link_config
;
449 u16 pll_cfg
, pll_sts
;
451 u64
uninitialized_var(sig
), mask
, val
;
456 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
|
457 PLL_TX_CFG_RATE_HALF
);
458 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
459 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
460 PLL_RX_CFG_RATE_HALF
);
463 rx_cfg
|= PLL_RX_CFG_EQ_LP_ADAPTIVE
;
465 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
466 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
468 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
469 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
471 tx_cfg
|= PLL_TX_CFG_ENTEST
;
472 rx_cfg
|= PLL_RX_CFG_ENTEST
;
475 /* Initialize PLL for 1G */
476 pll_cfg
= (PLL_CFG_ENPLL
| PLL_CFG_MPY_8X
);
478 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
479 ESR2_TI_PLL_CFG_L
, pll_cfg
);
481 dev_err(np
->device
, PFX
"NIU Port %d "
482 "serdes_init_niu_1g_serdes: "
483 "mdio write to ESR2_TI_PLL_CFG_L failed", np
->port
);
487 pll_sts
= PLL_CFG_ENPLL
;
489 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
490 ESR2_TI_PLL_STS_L
, pll_sts
);
492 dev_err(np
->device
, PFX
"NIU Port %d "
493 "serdes_init_niu_1g_serdes: "
494 "mdio write to ESR2_TI_PLL_STS_L failed", np
->port
);
500 /* Initialize all 4 lanes of the SERDES. */
501 for (i
= 0; i
< 4; i
++) {
502 err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
507 for (i
= 0; i
< 4; i
++) {
508 err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
515 val
= (ESR_INT_SRDY0_P0
| ESR_INT_DET0_P0
);
520 val
= (ESR_INT_SRDY0_P1
| ESR_INT_DET0_P1
);
528 while (max_retry
--) {
529 sig
= nr64(ESR_INT_SIGNALS
);
530 if ((sig
& mask
) == val
)
536 if ((sig
& mask
) != val
) {
537 dev_err(np
->device
, PFX
"Port %u signal bits [%08x] are not "
538 "[%08x]\n", np
->port
, (int) (sig
& mask
), (int) val
);
545 static int serdes_init_niu_10g_serdes(struct niu
*np
)
547 struct niu_link_config
*lp
= &np
->link_config
;
548 u32 tx_cfg
, rx_cfg
, pll_cfg
, pll_sts
;
550 u64
uninitialized_var(sig
), mask
, val
;
554 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
);
555 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
556 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
557 PLL_RX_CFG_EQ_LP_ADAPTIVE
);
559 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
560 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
562 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
563 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
565 tx_cfg
|= PLL_TX_CFG_ENTEST
;
566 rx_cfg
|= PLL_RX_CFG_ENTEST
;
569 /* Initialize PLL for 10G */
570 pll_cfg
= (PLL_CFG_ENPLL
| PLL_CFG_MPY_10X
);
572 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
573 ESR2_TI_PLL_CFG_L
, pll_cfg
& 0xffff);
575 dev_err(np
->device
, PFX
"NIU Port %d "
576 "serdes_init_niu_10g_serdes: "
577 "mdio write to ESR2_TI_PLL_CFG_L failed", np
->port
);
581 pll_sts
= PLL_CFG_ENPLL
;
583 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
584 ESR2_TI_PLL_STS_L
, pll_sts
& 0xffff);
586 dev_err(np
->device
, PFX
"NIU Port %d "
587 "serdes_init_niu_10g_serdes: "
588 "mdio write to ESR2_TI_PLL_STS_L failed", np
->port
);
594 /* Initialize all 4 lanes of the SERDES. */
595 for (i
= 0; i
< 4; i
++) {
596 err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
601 for (i
= 0; i
< 4; i
++) {
602 err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
607 /* check if serdes is ready */
611 mask
= ESR_INT_SIGNALS_P0_BITS
;
612 val
= (ESR_INT_SRDY0_P0
|
622 mask
= ESR_INT_SIGNALS_P1_BITS
;
623 val
= (ESR_INT_SRDY0_P1
|
636 while (max_retry
--) {
637 sig
= nr64(ESR_INT_SIGNALS
);
638 if ((sig
& mask
) == val
)
644 if ((sig
& mask
) != val
) {
645 pr_info(PFX
"NIU Port %u signal bits [%08x] are not "
646 "[%08x] for 10G...trying 1G\n",
647 np
->port
, (int) (sig
& mask
), (int) val
);
649 /* 10G failed, try initializing at 1G */
650 err
= serdes_init_niu_1g_serdes(np
);
652 np
->flags
&= ~NIU_FLAGS_10G
;
653 np
->mac_xcvr
= MAC_XCVR_PCS
;
655 dev_err(np
->device
, PFX
"Port %u 10G/1G SERDES "
656 "Link Failed \n", np
->port
);
663 static int esr_read_rxtx_ctrl(struct niu
*np
, unsigned long chan
, u32
*val
)
667 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
, ESR_RXTX_CTRL_L(chan
));
669 *val
= (err
& 0xffff);
670 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
671 ESR_RXTX_CTRL_H(chan
));
673 *val
|= ((err
& 0xffff) << 16);
679 static int esr_read_glue0(struct niu
*np
, unsigned long chan
, u32
*val
)
683 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
684 ESR_GLUE_CTRL0_L(chan
));
686 *val
= (err
& 0xffff);
687 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
688 ESR_GLUE_CTRL0_H(chan
));
690 *val
|= ((err
& 0xffff) << 16);
697 static int esr_read_reset(struct niu
*np
, u32
*val
)
701 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
702 ESR_RXTX_RESET_CTRL_L
);
704 *val
= (err
& 0xffff);
705 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
706 ESR_RXTX_RESET_CTRL_H
);
708 *val
|= ((err
& 0xffff) << 16);
715 static int esr_write_rxtx_ctrl(struct niu
*np
, unsigned long chan
, u32 val
)
719 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
720 ESR_RXTX_CTRL_L(chan
), val
& 0xffff);
722 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
723 ESR_RXTX_CTRL_H(chan
), (val
>> 16));
727 static int esr_write_glue0(struct niu
*np
, unsigned long chan
, u32 val
)
731 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
732 ESR_GLUE_CTRL0_L(chan
), val
& 0xffff);
734 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
735 ESR_GLUE_CTRL0_H(chan
), (val
>> 16));
739 static int esr_reset(struct niu
*np
)
741 u32
uninitialized_var(reset
);
744 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
745 ESR_RXTX_RESET_CTRL_L
, 0x0000);
748 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
749 ESR_RXTX_RESET_CTRL_H
, 0xffff);
754 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
755 ESR_RXTX_RESET_CTRL_L
, 0xffff);
760 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
761 ESR_RXTX_RESET_CTRL_H
, 0x0000);
766 err
= esr_read_reset(np
, &reset
);
770 dev_err(np
->device
, PFX
"Port %u ESR_RESET "
771 "did not clear [%08x]\n",
779 static int serdes_init_10g(struct niu
*np
)
781 struct niu_link_config
*lp
= &np
->link_config
;
782 unsigned long ctrl_reg
, test_cfg_reg
, i
;
783 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
788 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
789 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
792 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
793 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
799 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
800 ENET_SERDES_CTRL_SDET_1
|
801 ENET_SERDES_CTRL_SDET_2
|
802 ENET_SERDES_CTRL_SDET_3
|
803 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
804 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
805 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
806 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
807 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
808 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
809 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
810 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
813 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
814 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
815 ENET_SERDES_TEST_MD_0_SHIFT
) |
816 (ENET_TEST_MD_PAD_LOOPBACK
<<
817 ENET_SERDES_TEST_MD_1_SHIFT
) |
818 (ENET_TEST_MD_PAD_LOOPBACK
<<
819 ENET_SERDES_TEST_MD_2_SHIFT
) |
820 (ENET_TEST_MD_PAD_LOOPBACK
<<
821 ENET_SERDES_TEST_MD_3_SHIFT
));
824 nw64(ctrl_reg
, ctrl_val
);
825 nw64(test_cfg_reg
, test_cfg_val
);
827 /* Initialize all 4 lanes of the SERDES. */
828 for (i
= 0; i
< 4; i
++) {
829 u32 rxtx_ctrl
, glue0
;
831 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
834 err
= esr_read_glue0(np
, i
, &glue0
);
838 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
839 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
840 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
842 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
843 ESR_GLUE_CTRL0_THCNT
|
844 ESR_GLUE_CTRL0_BLTIME
);
845 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
846 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
847 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
848 (BLTIME_300_CYCLES
<<
849 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
851 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
854 err
= esr_write_glue0(np
, i
, glue0
);
863 sig
= nr64(ESR_INT_SIGNALS
);
866 mask
= ESR_INT_SIGNALS_P0_BITS
;
867 val
= (ESR_INT_SRDY0_P0
|
877 mask
= ESR_INT_SIGNALS_P1_BITS
;
878 val
= (ESR_INT_SRDY0_P1
|
891 if ((sig
& mask
) != val
) {
892 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
893 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
896 dev_err(np
->device
, PFX
"Port %u signal bits [%08x] are not "
897 "[%08x]\n", np
->port
, (int) (sig
& mask
), (int) val
);
900 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
)
901 np
->flags
|= NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
905 static int serdes_init_1g(struct niu
*np
)
909 val
= nr64(ENET_SERDES_1_PLL_CFG
);
910 val
&= ~ENET_SERDES_PLL_FBDIV2
;
913 val
|= ENET_SERDES_PLL_HRATE0
;
916 val
|= ENET_SERDES_PLL_HRATE1
;
919 val
|= ENET_SERDES_PLL_HRATE2
;
922 val
|= ENET_SERDES_PLL_HRATE3
;
927 nw64(ENET_SERDES_1_PLL_CFG
, val
);
932 static int serdes_init_1g_serdes(struct niu
*np
)
934 struct niu_link_config
*lp
= &np
->link_config
;
935 unsigned long ctrl_reg
, test_cfg_reg
, pll_cfg
, i
;
936 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
938 u64 reset_val
, val_rd
;
940 val
= ENET_SERDES_PLL_HRATE0
| ENET_SERDES_PLL_HRATE1
|
941 ENET_SERDES_PLL_HRATE2
| ENET_SERDES_PLL_HRATE3
|
942 ENET_SERDES_PLL_FBDIV0
;
945 reset_val
= ENET_SERDES_RESET_0
;
946 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
947 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
948 pll_cfg
= ENET_SERDES_0_PLL_CFG
;
951 reset_val
= ENET_SERDES_RESET_1
;
952 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
953 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
954 pll_cfg
= ENET_SERDES_1_PLL_CFG
;
960 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
961 ENET_SERDES_CTRL_SDET_1
|
962 ENET_SERDES_CTRL_SDET_2
|
963 ENET_SERDES_CTRL_SDET_3
|
964 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
965 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
966 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
967 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
968 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
969 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
970 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
971 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
974 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
975 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
976 ENET_SERDES_TEST_MD_0_SHIFT
) |
977 (ENET_TEST_MD_PAD_LOOPBACK
<<
978 ENET_SERDES_TEST_MD_1_SHIFT
) |
979 (ENET_TEST_MD_PAD_LOOPBACK
<<
980 ENET_SERDES_TEST_MD_2_SHIFT
) |
981 (ENET_TEST_MD_PAD_LOOPBACK
<<
982 ENET_SERDES_TEST_MD_3_SHIFT
));
985 nw64(ENET_SERDES_RESET
, reset_val
);
987 val_rd
= nr64(ENET_SERDES_RESET
);
988 val_rd
&= ~reset_val
;
990 nw64(ctrl_reg
, ctrl_val
);
991 nw64(test_cfg_reg
, test_cfg_val
);
992 nw64(ENET_SERDES_RESET
, val_rd
);
995 /* Initialize all 4 lanes of the SERDES. */
996 for (i
= 0; i
< 4; i
++) {
997 u32 rxtx_ctrl
, glue0
;
999 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
1002 err
= esr_read_glue0(np
, i
, &glue0
);
1006 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
1007 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
1008 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
1010 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
1011 ESR_GLUE_CTRL0_THCNT
|
1012 ESR_GLUE_CTRL0_BLTIME
);
1013 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
1014 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
1015 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
1016 (BLTIME_300_CYCLES
<<
1017 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
1019 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
1022 err
= esr_write_glue0(np
, i
, glue0
);
1028 sig
= nr64(ESR_INT_SIGNALS
);
1031 val
= (ESR_INT_SRDY0_P0
| ESR_INT_DET0_P0
);
1036 val
= (ESR_INT_SRDY0_P1
| ESR_INT_DET0_P1
);
1044 if ((sig
& mask
) != val
) {
1045 dev_err(np
->device
, PFX
"Port %u signal bits [%08x] are not "
1046 "[%08x]\n", np
->port
, (int) (sig
& mask
), (int) val
);
1053 static int link_status_1g_serdes(struct niu
*np
, int *link_up_p
)
1055 struct niu_link_config
*lp
= &np
->link_config
;
1059 unsigned long flags
;
1063 current_speed
= SPEED_INVALID
;
1064 current_duplex
= DUPLEX_INVALID
;
1066 spin_lock_irqsave(&np
->lock
, flags
);
1068 val
= nr64_pcs(PCS_MII_STAT
);
1070 if (val
& PCS_MII_STAT_LINK_STATUS
) {
1072 current_speed
= SPEED_1000
;
1073 current_duplex
= DUPLEX_FULL
;
1076 lp
->active_speed
= current_speed
;
1077 lp
->active_duplex
= current_duplex
;
1078 spin_unlock_irqrestore(&np
->lock
, flags
);
1080 *link_up_p
= link_up
;
1084 static int link_status_10g_serdes(struct niu
*np
, int *link_up_p
)
1086 unsigned long flags
;
1087 struct niu_link_config
*lp
= &np
->link_config
;
1094 if (!(np
->flags
& NIU_FLAGS_10G
))
1095 return link_status_1g_serdes(np
, link_up_p
);
1097 current_speed
= SPEED_INVALID
;
1098 current_duplex
= DUPLEX_INVALID
;
1099 spin_lock_irqsave(&np
->lock
, flags
);
1101 val
= nr64_xpcs(XPCS_STATUS(0));
1102 val2
= nr64_mac(XMAC_INTER2
);
1103 if (val2
& 0x01000000)
1106 if ((val
& 0x1000ULL
) && link_ok
) {
1108 current_speed
= SPEED_10000
;
1109 current_duplex
= DUPLEX_FULL
;
1111 lp
->active_speed
= current_speed
;
1112 lp
->active_duplex
= current_duplex
;
1113 spin_unlock_irqrestore(&np
->lock
, flags
);
1114 *link_up_p
= link_up
;
1118 static int link_status_mii(struct niu
*np
, int *link_up_p
)
1120 struct niu_link_config
*lp
= &np
->link_config
;
1122 int bmsr
, advert
, ctrl1000
, stat1000
, lpa
, bmcr
, estatus
;
1123 int supported
, advertising
, active_speed
, active_duplex
;
1125 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1126 if (unlikely(err
< 0))
1130 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1131 if (unlikely(err
< 0))
1135 err
= mii_read(np
, np
->phy_addr
, MII_ADVERTISE
);
1136 if (unlikely(err
< 0))
1140 err
= mii_read(np
, np
->phy_addr
, MII_LPA
);
1141 if (unlikely(err
< 0))
1145 if (likely(bmsr
& BMSR_ESTATEN
)) {
1146 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1147 if (unlikely(err
< 0))
1151 err
= mii_read(np
, np
->phy_addr
, MII_CTRL1000
);
1152 if (unlikely(err
< 0))
1156 err
= mii_read(np
, np
->phy_addr
, MII_STAT1000
);
1157 if (unlikely(err
< 0))
1161 estatus
= ctrl1000
= stat1000
= 0;
1164 if (bmsr
& BMSR_ANEGCAPABLE
)
1165 supported
|= SUPPORTED_Autoneg
;
1166 if (bmsr
& BMSR_10HALF
)
1167 supported
|= SUPPORTED_10baseT_Half
;
1168 if (bmsr
& BMSR_10FULL
)
1169 supported
|= SUPPORTED_10baseT_Full
;
1170 if (bmsr
& BMSR_100HALF
)
1171 supported
|= SUPPORTED_100baseT_Half
;
1172 if (bmsr
& BMSR_100FULL
)
1173 supported
|= SUPPORTED_100baseT_Full
;
1174 if (estatus
& ESTATUS_1000_THALF
)
1175 supported
|= SUPPORTED_1000baseT_Half
;
1176 if (estatus
& ESTATUS_1000_TFULL
)
1177 supported
|= SUPPORTED_1000baseT_Full
;
1178 lp
->supported
= supported
;
1181 if (advert
& ADVERTISE_10HALF
)
1182 advertising
|= ADVERTISED_10baseT_Half
;
1183 if (advert
& ADVERTISE_10FULL
)
1184 advertising
|= ADVERTISED_10baseT_Full
;
1185 if (advert
& ADVERTISE_100HALF
)
1186 advertising
|= ADVERTISED_100baseT_Half
;
1187 if (advert
& ADVERTISE_100FULL
)
1188 advertising
|= ADVERTISED_100baseT_Full
;
1189 if (ctrl1000
& ADVERTISE_1000HALF
)
1190 advertising
|= ADVERTISED_1000baseT_Half
;
1191 if (ctrl1000
& ADVERTISE_1000FULL
)
1192 advertising
|= ADVERTISED_1000baseT_Full
;
1194 if (bmcr
& BMCR_ANENABLE
) {
1197 lp
->active_autoneg
= 1;
1198 advertising
|= ADVERTISED_Autoneg
;
1201 neg1000
= (ctrl1000
<< 2) & stat1000
;
1203 if (neg1000
& (LPA_1000FULL
| LPA_1000HALF
))
1204 active_speed
= SPEED_1000
;
1205 else if (neg
& LPA_100
)
1206 active_speed
= SPEED_100
;
1207 else if (neg
& (LPA_10HALF
| LPA_10FULL
))
1208 active_speed
= SPEED_10
;
1210 active_speed
= SPEED_INVALID
;
1212 if ((neg1000
& LPA_1000FULL
) || (neg
& LPA_DUPLEX
))
1213 active_duplex
= DUPLEX_FULL
;
1214 else if (active_speed
!= SPEED_INVALID
)
1215 active_duplex
= DUPLEX_HALF
;
1217 active_duplex
= DUPLEX_INVALID
;
1219 lp
->active_autoneg
= 0;
1221 if ((bmcr
& BMCR_SPEED1000
) && !(bmcr
& BMCR_SPEED100
))
1222 active_speed
= SPEED_1000
;
1223 else if (bmcr
& BMCR_SPEED100
)
1224 active_speed
= SPEED_100
;
1226 active_speed
= SPEED_10
;
1228 if (bmcr
& BMCR_FULLDPLX
)
1229 active_duplex
= DUPLEX_FULL
;
1231 active_duplex
= DUPLEX_HALF
;
1234 lp
->active_advertising
= advertising
;
1235 lp
->active_speed
= active_speed
;
1236 lp
->active_duplex
= active_duplex
;
1237 *link_up_p
= !!(bmsr
& BMSR_LSTATUS
);
1242 static int link_status_1g_rgmii(struct niu
*np
, int *link_up_p
)
1244 struct niu_link_config
*lp
= &np
->link_config
;
1245 u16 current_speed
, bmsr
;
1246 unsigned long flags
;
1251 current_speed
= SPEED_INVALID
;
1252 current_duplex
= DUPLEX_INVALID
;
1254 spin_lock_irqsave(&np
->lock
, flags
);
1258 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1263 if (bmsr
& BMSR_LSTATUS
) {
1264 u16 adv
, lpa
, common
, estat
;
1266 err
= mii_read(np
, np
->phy_addr
, MII_ADVERTISE
);
1271 err
= mii_read(np
, np
->phy_addr
, MII_LPA
);
1278 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1283 current_speed
= SPEED_1000
;
1284 current_duplex
= DUPLEX_FULL
;
1287 lp
->active_speed
= current_speed
;
1288 lp
->active_duplex
= current_duplex
;
1292 spin_unlock_irqrestore(&np
->lock
, flags
);
1294 *link_up_p
= link_up
;
1298 static int link_status_1g(struct niu
*np
, int *link_up_p
)
1300 struct niu_link_config
*lp
= &np
->link_config
;
1301 unsigned long flags
;
1304 spin_lock_irqsave(&np
->lock
, flags
);
1306 err
= link_status_mii(np
, link_up_p
);
1307 lp
->supported
|= SUPPORTED_TP
;
1308 lp
->active_advertising
|= ADVERTISED_TP
;
1310 spin_unlock_irqrestore(&np
->lock
, flags
);
1314 static int bcm8704_reset(struct niu
*np
)
1318 err
= mdio_read(np
, np
->phy_addr
,
1319 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
1323 err
= mdio_write(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1329 while (--limit
>= 0) {
1330 err
= mdio_read(np
, np
->phy_addr
,
1331 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
1334 if (!(err
& BMCR_RESET
))
1338 dev_err(np
->device
, PFX
"Port %u PHY will not reset "
1339 "(bmcr=%04x)\n", np
->port
, (err
& 0xffff));
1345 /* When written, certain PHY registers need to be read back twice
1346 * in order for the bits to settle properly.
1348 static int bcm8704_user_dev3_readback(struct niu
*np
, int reg
)
1350 int err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, reg
);
1353 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, reg
);
1359 static int bcm8706_init_user_dev3(struct niu
*np
)
1364 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1365 BCM8704_USER_OPT_DIGITAL_CTRL
);
1368 err
&= ~USER_ODIG_CTRL_GPIOS
;
1369 err
|= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT
);
1370 err
|= USER_ODIG_CTRL_RESV2
;
1371 err
= mdio_write(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1372 BCM8704_USER_OPT_DIGITAL_CTRL
, err
);
1381 static int bcm8704_init_user_dev3(struct niu
*np
)
1385 err
= mdio_write(np
, np
->phy_addr
,
1386 BCM8704_USER_DEV3_ADDR
, BCM8704_USER_CONTROL
,
1387 (USER_CONTROL_OPTXRST_LVL
|
1388 USER_CONTROL_OPBIASFLT_LVL
|
1389 USER_CONTROL_OBTMPFLT_LVL
|
1390 USER_CONTROL_OPPRFLT_LVL
|
1391 USER_CONTROL_OPTXFLT_LVL
|
1392 USER_CONTROL_OPRXLOS_LVL
|
1393 USER_CONTROL_OPRXFLT_LVL
|
1394 USER_CONTROL_OPTXON_LVL
|
1395 (0x3f << USER_CONTROL_RES1_SHIFT
)));
1399 err
= mdio_write(np
, np
->phy_addr
,
1400 BCM8704_USER_DEV3_ADDR
, BCM8704_USER_PMD_TX_CONTROL
,
1401 (USER_PMD_TX_CTL_XFP_CLKEN
|
1402 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH
) |
1403 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH
) |
1404 USER_PMD_TX_CTL_TSCK_LPWREN
));
1408 err
= bcm8704_user_dev3_readback(np
, BCM8704_USER_CONTROL
);
1411 err
= bcm8704_user_dev3_readback(np
, BCM8704_USER_PMD_TX_CONTROL
);
1415 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1416 BCM8704_USER_OPT_DIGITAL_CTRL
);
1419 err
&= ~USER_ODIG_CTRL_GPIOS
;
1420 err
|= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT
);
1421 err
= mdio_write(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1422 BCM8704_USER_OPT_DIGITAL_CTRL
, err
);
1431 static int mrvl88x2011_act_led(struct niu
*np
, int val
)
1435 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1436 MRVL88X2011_LED_8_TO_11_CTL
);
1440 err
&= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT
,MRVL88X2011_LED_CTL_MASK
);
1441 err
|= MRVL88X2011_LED(MRVL88X2011_LED_ACT
,val
);
1443 return mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1444 MRVL88X2011_LED_8_TO_11_CTL
, err
);
1447 static int mrvl88x2011_led_blink_rate(struct niu
*np
, int rate
)
1451 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1452 MRVL88X2011_LED_BLINK_CTL
);
1454 err
&= ~MRVL88X2011_LED_BLKRATE_MASK
;
1457 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1458 MRVL88X2011_LED_BLINK_CTL
, err
);
1464 static int xcvr_init_10g_mrvl88x2011(struct niu
*np
)
1468 /* Set LED functions */
1469 err
= mrvl88x2011_led_blink_rate(np
, MRVL88X2011_LED_BLKRATE_134MS
);
1474 err
= mrvl88x2011_act_led(np
, MRVL88X2011_LED_CTL_OFF
);
1478 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1479 MRVL88X2011_GENERAL_CTL
);
1483 err
|= MRVL88X2011_ENA_XFPREFCLK
;
1485 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1486 MRVL88X2011_GENERAL_CTL
, err
);
1490 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1491 MRVL88X2011_PMA_PMD_CTL_1
);
1495 if (np
->link_config
.loopback_mode
== LOOPBACK_MAC
)
1496 err
|= MRVL88X2011_LOOPBACK
;
1498 err
&= ~MRVL88X2011_LOOPBACK
;
1500 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1501 MRVL88X2011_PMA_PMD_CTL_1
, err
);
1506 return mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1507 MRVL88X2011_10G_PMD_TX_DIS
, MRVL88X2011_ENA_PMDTX
);
1511 static int xcvr_diag_bcm870x(struct niu
*np
)
1513 u16 analog_stat0
, tx_alarm_status
;
1517 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
1521 pr_info(PFX
"Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1524 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, 0x20);
1527 pr_info(PFX
"Port %u USER_DEV3(0x20) [%04x]\n",
1530 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1534 pr_info(PFX
"Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1538 /* XXX dig this out it might not be so useful XXX */
1539 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1540 BCM8704_USER_ANALOG_STATUS0
);
1543 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1544 BCM8704_USER_ANALOG_STATUS0
);
1549 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1550 BCM8704_USER_TX_ALARM_STATUS
);
1553 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1554 BCM8704_USER_TX_ALARM_STATUS
);
1557 tx_alarm_status
= err
;
1559 if (analog_stat0
!= 0x03fc) {
1560 if ((analog_stat0
== 0x43bc) && (tx_alarm_status
!= 0)) {
1561 pr_info(PFX
"Port %u cable not connected "
1562 "or bad cable.\n", np
->port
);
1563 } else if (analog_stat0
== 0x639c) {
1564 pr_info(PFX
"Port %u optical module is bad "
1565 "or missing.\n", np
->port
);
1572 static int xcvr_10g_set_lb_bcm870x(struct niu
*np
)
1574 struct niu_link_config
*lp
= &np
->link_config
;
1577 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1582 err
&= ~BMCR_LOOPBACK
;
1584 if (lp
->loopback_mode
== LOOPBACK_MAC
)
1585 err
|= BMCR_LOOPBACK
;
1587 err
= mdio_write(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1595 static int xcvr_init_10g_bcm8706(struct niu
*np
)
1600 if ((np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) &&
1601 (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) == 0)
1604 val
= nr64_mac(XMAC_CONFIG
);
1605 val
&= ~XMAC_CONFIG_LED_POLARITY
;
1606 val
|= XMAC_CONFIG_FORCE_LED_ON
;
1607 nw64_mac(XMAC_CONFIG
, val
);
1609 val
= nr64(MIF_CONFIG
);
1610 val
|= MIF_CONFIG_INDIRECT_MODE
;
1611 nw64(MIF_CONFIG
, val
);
1613 err
= bcm8704_reset(np
);
1617 err
= xcvr_10g_set_lb_bcm870x(np
);
1621 err
= bcm8706_init_user_dev3(np
);
1625 err
= xcvr_diag_bcm870x(np
);
1632 static int xcvr_init_10g_bcm8704(struct niu
*np
)
1636 err
= bcm8704_reset(np
);
1640 err
= bcm8704_init_user_dev3(np
);
1644 err
= xcvr_10g_set_lb_bcm870x(np
);
1648 err
= xcvr_diag_bcm870x(np
);
1655 static int xcvr_init_10g(struct niu
*np
)
1660 val
= nr64_mac(XMAC_CONFIG
);
1661 val
&= ~XMAC_CONFIG_LED_POLARITY
;
1662 val
|= XMAC_CONFIG_FORCE_LED_ON
;
1663 nw64_mac(XMAC_CONFIG
, val
);
1665 /* XXX shared resource, lock parent XXX */
1666 val
= nr64(MIF_CONFIG
);
1667 val
|= MIF_CONFIG_INDIRECT_MODE
;
1668 nw64(MIF_CONFIG
, val
);
1670 phy_id
= phy_decode(np
->parent
->port_phy
, np
->port
);
1671 phy_id
= np
->parent
->phy_probe_info
.phy_id
[phy_id
][np
->port
];
1673 /* handle different phy types */
1674 switch (phy_id
& NIU_PHY_ID_MASK
) {
1675 case NIU_PHY_ID_MRVL88X2011
:
1676 err
= xcvr_init_10g_mrvl88x2011(np
);
1679 default: /* bcom 8704 */
1680 err
= xcvr_init_10g_bcm8704(np
);
1687 static int mii_reset(struct niu
*np
)
1691 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, BMCR_RESET
);
1696 while (--limit
>= 0) {
1698 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1701 if (!(err
& BMCR_RESET
))
1705 dev_err(np
->device
, PFX
"Port %u MII would not reset, "
1706 "bmcr[%04x]\n", np
->port
, err
);
1713 static int xcvr_init_1g_rgmii(struct niu
*np
)
1717 u16 bmcr
, bmsr
, estat
;
1719 val
= nr64(MIF_CONFIG
);
1720 val
&= ~MIF_CONFIG_INDIRECT_MODE
;
1721 nw64(MIF_CONFIG
, val
);
1723 err
= mii_reset(np
);
1727 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1733 if (bmsr
& BMSR_ESTATEN
) {
1734 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1741 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1745 if (bmsr
& BMSR_ESTATEN
) {
1748 if (estat
& ESTATUS_1000_TFULL
)
1749 ctrl1000
|= ADVERTISE_1000FULL
;
1750 err
= mii_write(np
, np
->phy_addr
, MII_CTRL1000
, ctrl1000
);
1755 bmcr
= (BMCR_SPEED1000
| BMCR_FULLDPLX
);
1757 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1761 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1764 bmcr
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1766 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1773 static int mii_init_common(struct niu
*np
)
1775 struct niu_link_config
*lp
= &np
->link_config
;
1776 u16 bmcr
, bmsr
, adv
, estat
;
1779 err
= mii_reset(np
);
1783 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1789 if (bmsr
& BMSR_ESTATEN
) {
1790 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1797 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1801 if (lp
->loopback_mode
== LOOPBACK_MAC
) {
1802 bmcr
|= BMCR_LOOPBACK
;
1803 if (lp
->active_speed
== SPEED_1000
)
1804 bmcr
|= BMCR_SPEED1000
;
1805 if (lp
->active_duplex
== DUPLEX_FULL
)
1806 bmcr
|= BMCR_FULLDPLX
;
1809 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
1812 aux
= (BCM5464R_AUX_CTL_EXT_LB
|
1813 BCM5464R_AUX_CTL_WRITE_1
);
1814 err
= mii_write(np
, np
->phy_addr
, BCM5464R_AUX_CTL
, aux
);
1822 adv
= ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
;
1823 if ((bmsr
& BMSR_10HALF
) &&
1824 (lp
->advertising
& ADVERTISED_10baseT_Half
))
1825 adv
|= ADVERTISE_10HALF
;
1826 if ((bmsr
& BMSR_10FULL
) &&
1827 (lp
->advertising
& ADVERTISED_10baseT_Full
))
1828 adv
|= ADVERTISE_10FULL
;
1829 if ((bmsr
& BMSR_100HALF
) &&
1830 (lp
->advertising
& ADVERTISED_100baseT_Half
))
1831 adv
|= ADVERTISE_100HALF
;
1832 if ((bmsr
& BMSR_100FULL
) &&
1833 (lp
->advertising
& ADVERTISED_100baseT_Full
))
1834 adv
|= ADVERTISE_100FULL
;
1835 err
= mii_write(np
, np
->phy_addr
, MII_ADVERTISE
, adv
);
1839 if (likely(bmsr
& BMSR_ESTATEN
)) {
1841 if ((estat
& ESTATUS_1000_THALF
) &&
1842 (lp
->advertising
& ADVERTISED_1000baseT_Half
))
1843 ctrl1000
|= ADVERTISE_1000HALF
;
1844 if ((estat
& ESTATUS_1000_TFULL
) &&
1845 (lp
->advertising
& ADVERTISED_1000baseT_Full
))
1846 ctrl1000
|= ADVERTISE_1000FULL
;
1847 err
= mii_write(np
, np
->phy_addr
,
1848 MII_CTRL1000
, ctrl1000
);
1853 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
1858 if (lp
->duplex
== DUPLEX_FULL
) {
1859 bmcr
|= BMCR_FULLDPLX
;
1861 } else if (lp
->duplex
== DUPLEX_HALF
)
1866 if (lp
->speed
== SPEED_1000
) {
1867 /* if X-full requested while not supported, or
1868 X-half requested while not supported... */
1869 if ((fulldpx
&& !(estat
& ESTATUS_1000_TFULL
)) ||
1870 (!fulldpx
&& !(estat
& ESTATUS_1000_THALF
)))
1872 bmcr
|= BMCR_SPEED1000
;
1873 } else if (lp
->speed
== SPEED_100
) {
1874 if ((fulldpx
&& !(bmsr
& BMSR_100FULL
)) ||
1875 (!fulldpx
&& !(bmsr
& BMSR_100HALF
)))
1877 bmcr
|= BMCR_SPEED100
;
1878 } else if (lp
->speed
== SPEED_10
) {
1879 if ((fulldpx
&& !(bmsr
& BMSR_10FULL
)) ||
1880 (!fulldpx
&& !(bmsr
& BMSR_10HALF
)))
1886 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1891 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1896 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1901 pr_info(PFX
"Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1902 np
->port
, bmcr
, bmsr
);
1908 static int xcvr_init_1g(struct niu
*np
)
1912 /* XXX shared resource, lock parent XXX */
1913 val
= nr64(MIF_CONFIG
);
1914 val
&= ~MIF_CONFIG_INDIRECT_MODE
;
1915 nw64(MIF_CONFIG
, val
);
1917 return mii_init_common(np
);
1920 static int niu_xcvr_init(struct niu
*np
)
1922 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1927 err
= ops
->xcvr_init(np
);
1932 static int niu_serdes_init(struct niu
*np
)
1934 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1938 if (ops
->serdes_init
)
1939 err
= ops
->serdes_init(np
);
1944 static void niu_init_xif(struct niu
*);
1945 static void niu_handle_led(struct niu
*, int status
);
1947 static int niu_link_status_common(struct niu
*np
, int link_up
)
1949 struct niu_link_config
*lp
= &np
->link_config
;
1950 struct net_device
*dev
= np
->dev
;
1951 unsigned long flags
;
1953 if (!netif_carrier_ok(dev
) && link_up
) {
1954 niuinfo(LINK
, "%s: Link is up at %s, %s duplex\n",
1956 (lp
->active_speed
== SPEED_10000
?
1958 (lp
->active_speed
== SPEED_1000
?
1960 (lp
->active_speed
== SPEED_100
?
1961 "100Mbit/sec" : "10Mbit/sec"))),
1962 (lp
->active_duplex
== DUPLEX_FULL
?
1965 spin_lock_irqsave(&np
->lock
, flags
);
1967 niu_handle_led(np
, 1);
1968 spin_unlock_irqrestore(&np
->lock
, flags
);
1970 netif_carrier_on(dev
);
1971 } else if (netif_carrier_ok(dev
) && !link_up
) {
1972 niuwarn(LINK
, "%s: Link is down\n", dev
->name
);
1973 spin_lock_irqsave(&np
->lock
, flags
);
1974 niu_handle_led(np
, 0);
1975 spin_unlock_irqrestore(&np
->lock
, flags
);
1976 netif_carrier_off(dev
);
1982 static int link_status_10g_mrvl(struct niu
*np
, int *link_up_p
)
1984 int err
, link_up
, pma_status
, pcs_status
;
1988 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1989 MRVL88X2011_10G_PMD_STATUS_2
);
1993 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1994 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1995 MRVL88X2011_PMA_PMD_STATUS_1
);
1999 pma_status
= ((err
& MRVL88X2011_LNK_STATUS_OK
) ? 1 : 0);
2001 /* Check PMC Register : 3.0001.2 == 1: read twice */
2002 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
2003 MRVL88X2011_PMA_PMD_STATUS_1
);
2007 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
2008 MRVL88X2011_PMA_PMD_STATUS_1
);
2012 pcs_status
= ((err
& MRVL88X2011_LNK_STATUS_OK
) ? 1 : 0);
2014 /* Check XGXS Register : 4.0018.[0-3,12] */
2015 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV4_ADDR
,
2016 MRVL88X2011_10G_XGXS_LANE_STAT
);
2020 if (err
== (PHYXS_XGXS_LANE_STAT_ALINGED
| PHYXS_XGXS_LANE_STAT_LANE3
|
2021 PHYXS_XGXS_LANE_STAT_LANE2
| PHYXS_XGXS_LANE_STAT_LANE1
|
2022 PHYXS_XGXS_LANE_STAT_LANE0
| PHYXS_XGXS_LANE_STAT_MAGIC
|
2024 link_up
= (pma_status
&& pcs_status
) ? 1 : 0;
2026 np
->link_config
.active_speed
= SPEED_10000
;
2027 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2030 mrvl88x2011_act_led(np
, (link_up
?
2031 MRVL88X2011_LED_CTL_PCS_ACT
:
2032 MRVL88X2011_LED_CTL_OFF
));
2034 *link_up_p
= link_up
;
2038 static int link_status_10g_bcm8706(struct niu
*np
, int *link_up_p
)
2043 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
2044 BCM8704_PMD_RCV_SIGDET
);
2047 if (!(err
& PMD_RCV_SIGDET_GLOBAL
)) {
2052 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
2053 BCM8704_PCS_10G_R_STATUS
);
2057 if (!(err
& PCS_10G_R_STATUS_BLK_LOCK
)) {
2062 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
2063 BCM8704_PHYXS_XGXS_LANE_STAT
);
2066 if (err
!= (PHYXS_XGXS_LANE_STAT_ALINGED
|
2067 PHYXS_XGXS_LANE_STAT_MAGIC
|
2068 PHYXS_XGXS_LANE_STAT_PATTEST
|
2069 PHYXS_XGXS_LANE_STAT_LANE3
|
2070 PHYXS_XGXS_LANE_STAT_LANE2
|
2071 PHYXS_XGXS_LANE_STAT_LANE1
|
2072 PHYXS_XGXS_LANE_STAT_LANE0
)) {
2074 np
->link_config
.active_speed
= SPEED_INVALID
;
2075 np
->link_config
.active_duplex
= DUPLEX_INVALID
;
2080 np
->link_config
.active_speed
= SPEED_10000
;
2081 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2085 *link_up_p
= link_up
;
2086 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
)
2091 static int link_status_10g_bcom(struct niu
*np
, int *link_up_p
)
2097 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
2098 BCM8704_PMD_RCV_SIGDET
);
2101 if (!(err
& PMD_RCV_SIGDET_GLOBAL
)) {
2106 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
2107 BCM8704_PCS_10G_R_STATUS
);
2110 if (!(err
& PCS_10G_R_STATUS_BLK_LOCK
)) {
2115 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
2116 BCM8704_PHYXS_XGXS_LANE_STAT
);
2120 if (err
!= (PHYXS_XGXS_LANE_STAT_ALINGED
|
2121 PHYXS_XGXS_LANE_STAT_MAGIC
|
2122 PHYXS_XGXS_LANE_STAT_LANE3
|
2123 PHYXS_XGXS_LANE_STAT_LANE2
|
2124 PHYXS_XGXS_LANE_STAT_LANE1
|
2125 PHYXS_XGXS_LANE_STAT_LANE0
)) {
2131 np
->link_config
.active_speed
= SPEED_10000
;
2132 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2136 *link_up_p
= link_up
;
2140 static int link_status_10g(struct niu
*np
, int *link_up_p
)
2142 unsigned long flags
;
2145 spin_lock_irqsave(&np
->lock
, flags
);
2147 if (np
->link_config
.loopback_mode
== LOOPBACK_DISABLED
) {
2150 phy_id
= phy_decode(np
->parent
->port_phy
, np
->port
);
2151 phy_id
= np
->parent
->phy_probe_info
.phy_id
[phy_id
][np
->port
];
2153 /* handle different phy types */
2154 switch (phy_id
& NIU_PHY_ID_MASK
) {
2155 case NIU_PHY_ID_MRVL88X2011
:
2156 err
= link_status_10g_mrvl(np
, link_up_p
);
2159 default: /* bcom 8704 */
2160 err
= link_status_10g_bcom(np
, link_up_p
);
2165 spin_unlock_irqrestore(&np
->lock
, flags
);
2170 static int niu_10g_phy_present(struct niu
*np
)
2174 sig
= nr64(ESR_INT_SIGNALS
);
2177 mask
= ESR_INT_SIGNALS_P0_BITS
;
2178 val
= (ESR_INT_SRDY0_P0
|
2181 ESR_INT_XDP_P0_CH3
|
2182 ESR_INT_XDP_P0_CH2
|
2183 ESR_INT_XDP_P0_CH1
|
2184 ESR_INT_XDP_P0_CH0
);
2188 mask
= ESR_INT_SIGNALS_P1_BITS
;
2189 val
= (ESR_INT_SRDY0_P1
|
2192 ESR_INT_XDP_P1_CH3
|
2193 ESR_INT_XDP_P1_CH2
|
2194 ESR_INT_XDP_P1_CH1
|
2195 ESR_INT_XDP_P1_CH0
);
2202 if ((sig
& mask
) != val
)
2207 static int link_status_10g_hotplug(struct niu
*np
, int *link_up_p
)
2209 unsigned long flags
;
2212 int phy_present_prev
;
2214 spin_lock_irqsave(&np
->lock
, flags
);
2216 if (np
->link_config
.loopback_mode
== LOOPBACK_DISABLED
) {
2217 phy_present_prev
= (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) ?
2219 phy_present
= niu_10g_phy_present(np
);
2220 if (phy_present
!= phy_present_prev
) {
2223 np
->flags
|= NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
2224 if (np
->phy_ops
->xcvr_init
)
2225 err
= np
->phy_ops
->xcvr_init(np
);
2228 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
2231 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
2233 niuwarn(LINK
, "%s: Hotplug PHY Removed\n",
2237 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
)
2238 err
= link_status_10g_bcm8706(np
, link_up_p
);
2241 spin_unlock_irqrestore(&np
->lock
, flags
);
2246 static int niu_link_status(struct niu
*np
, int *link_up_p
)
2248 const struct niu_phy_ops
*ops
= np
->phy_ops
;
2252 if (ops
->link_status
)
2253 err
= ops
->link_status(np
, link_up_p
);
2258 static void niu_timer(unsigned long __opaque
)
2260 struct niu
*np
= (struct niu
*) __opaque
;
2264 err
= niu_link_status(np
, &link_up
);
2266 niu_link_status_common(np
, link_up
);
2268 if (netif_carrier_ok(np
->dev
))
2272 np
->timer
.expires
= jiffies
+ off
;
2274 add_timer(&np
->timer
);
2277 static const struct niu_phy_ops phy_ops_10g_serdes
= {
2278 .serdes_init
= serdes_init_10g_serdes
,
2279 .link_status
= link_status_10g_serdes
,
2282 static const struct niu_phy_ops phy_ops_10g_serdes_niu
= {
2283 .serdes_init
= serdes_init_niu_10g_serdes
,
2284 .link_status
= link_status_10g_serdes
,
2287 static const struct niu_phy_ops phy_ops_1g_serdes_niu
= {
2288 .serdes_init
= serdes_init_niu_1g_serdes
,
2289 .link_status
= link_status_1g_serdes
,
2292 static const struct niu_phy_ops phy_ops_1g_rgmii
= {
2293 .xcvr_init
= xcvr_init_1g_rgmii
,
2294 .link_status
= link_status_1g_rgmii
,
2297 static const struct niu_phy_ops phy_ops_10g_fiber_niu
= {
2298 .serdes_init
= serdes_init_niu_10g_fiber
,
2299 .xcvr_init
= xcvr_init_10g
,
2300 .link_status
= link_status_10g
,
2303 static const struct niu_phy_ops phy_ops_10g_fiber
= {
2304 .serdes_init
= serdes_init_10g
,
2305 .xcvr_init
= xcvr_init_10g
,
2306 .link_status
= link_status_10g
,
2309 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug
= {
2310 .serdes_init
= serdes_init_10g
,
2311 .xcvr_init
= xcvr_init_10g_bcm8706
,
2312 .link_status
= link_status_10g_hotplug
,
2315 static const struct niu_phy_ops phy_ops_10g_copper
= {
2316 .serdes_init
= serdes_init_10g
,
2317 .link_status
= link_status_10g
, /* XXX */
2320 static const struct niu_phy_ops phy_ops_1g_fiber
= {
2321 .serdes_init
= serdes_init_1g
,
2322 .xcvr_init
= xcvr_init_1g
,
2323 .link_status
= link_status_1g
,
2326 static const struct niu_phy_ops phy_ops_1g_copper
= {
2327 .xcvr_init
= xcvr_init_1g
,
2328 .link_status
= link_status_1g
,
2331 struct niu_phy_template
{
2332 const struct niu_phy_ops
*ops
;
2336 static const struct niu_phy_template phy_template_niu_10g_fiber
= {
2337 .ops
= &phy_ops_10g_fiber_niu
,
2338 .phy_addr_base
= 16,
2341 static const struct niu_phy_template phy_template_niu_10g_serdes
= {
2342 .ops
= &phy_ops_10g_serdes_niu
,
2346 static const struct niu_phy_template phy_template_niu_1g_serdes
= {
2347 .ops
= &phy_ops_1g_serdes_niu
,
2351 static const struct niu_phy_template phy_template_10g_fiber
= {
2352 .ops
= &phy_ops_10g_fiber
,
2356 static const struct niu_phy_template phy_template_10g_fiber_hotplug
= {
2357 .ops
= &phy_ops_10g_fiber_hotplug
,
2361 static const struct niu_phy_template phy_template_10g_copper
= {
2362 .ops
= &phy_ops_10g_copper
,
2363 .phy_addr_base
= 10,
2366 static const struct niu_phy_template phy_template_1g_fiber
= {
2367 .ops
= &phy_ops_1g_fiber
,
2371 static const struct niu_phy_template phy_template_1g_copper
= {
2372 .ops
= &phy_ops_1g_copper
,
2376 static const struct niu_phy_template phy_template_1g_rgmii
= {
2377 .ops
= &phy_ops_1g_rgmii
,
2381 static const struct niu_phy_template phy_template_10g_serdes
= {
2382 .ops
= &phy_ops_10g_serdes
,
2386 static int niu_atca_port_num
[4] = {
2390 static int serdes_init_10g_serdes(struct niu
*np
)
2392 struct niu_link_config
*lp
= &np
->link_config
;
2393 unsigned long ctrl_reg
, test_cfg_reg
, pll_cfg
, i
;
2394 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
2399 reset_val
= ENET_SERDES_RESET_0
;
2400 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
2401 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
2402 pll_cfg
= ENET_SERDES_0_PLL_CFG
;
2405 reset_val
= ENET_SERDES_RESET_1
;
2406 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
2407 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
2408 pll_cfg
= ENET_SERDES_1_PLL_CFG
;
2414 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
2415 ENET_SERDES_CTRL_SDET_1
|
2416 ENET_SERDES_CTRL_SDET_2
|
2417 ENET_SERDES_CTRL_SDET_3
|
2418 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
2419 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
2420 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
2421 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
2422 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
2423 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
2424 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
2425 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
2428 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
2429 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
2430 ENET_SERDES_TEST_MD_0_SHIFT
) |
2431 (ENET_TEST_MD_PAD_LOOPBACK
<<
2432 ENET_SERDES_TEST_MD_1_SHIFT
) |
2433 (ENET_TEST_MD_PAD_LOOPBACK
<<
2434 ENET_SERDES_TEST_MD_2_SHIFT
) |
2435 (ENET_TEST_MD_PAD_LOOPBACK
<<
2436 ENET_SERDES_TEST_MD_3_SHIFT
));
2440 nw64(pll_cfg
, ENET_SERDES_PLL_FBDIV2
);
2441 nw64(ctrl_reg
, ctrl_val
);
2442 nw64(test_cfg_reg
, test_cfg_val
);
2444 /* Initialize all 4 lanes of the SERDES. */
2445 for (i
= 0; i
< 4; i
++) {
2446 u32 rxtx_ctrl
, glue0
;
2449 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
2452 err
= esr_read_glue0(np
, i
, &glue0
);
2456 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
2457 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
2458 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
2460 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
2461 ESR_GLUE_CTRL0_THCNT
|
2462 ESR_GLUE_CTRL0_BLTIME
);
2463 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
2464 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
2465 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
2466 (BLTIME_300_CYCLES
<<
2467 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
2469 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
2472 err
= esr_write_glue0(np
, i
, glue0
);
2478 sig
= nr64(ESR_INT_SIGNALS
);
2481 mask
= ESR_INT_SIGNALS_P0_BITS
;
2482 val
= (ESR_INT_SRDY0_P0
|
2485 ESR_INT_XDP_P0_CH3
|
2486 ESR_INT_XDP_P0_CH2
|
2487 ESR_INT_XDP_P0_CH1
|
2488 ESR_INT_XDP_P0_CH0
);
2492 mask
= ESR_INT_SIGNALS_P1_BITS
;
2493 val
= (ESR_INT_SRDY0_P1
|
2496 ESR_INT_XDP_P1_CH3
|
2497 ESR_INT_XDP_P1_CH2
|
2498 ESR_INT_XDP_P1_CH1
|
2499 ESR_INT_XDP_P1_CH0
);
2506 if ((sig
& mask
) != val
) {
2508 err
= serdes_init_1g_serdes(np
);
2510 np
->flags
&= ~NIU_FLAGS_10G
;
2511 np
->mac_xcvr
= MAC_XCVR_PCS
;
2513 dev_err(np
->device
, PFX
"Port %u 10G/1G SERDES Link Failed \n",
2522 static int niu_determine_phy_disposition(struct niu
*np
)
2524 struct niu_parent
*parent
= np
->parent
;
2525 u8 plat_type
= parent
->plat_type
;
2526 const struct niu_phy_template
*tp
;
2527 u32 phy_addr_off
= 0;
2529 if (plat_type
== PLAT_TYPE_NIU
) {
2533 NIU_FLAGS_XCVR_SERDES
)) {
2534 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
2536 tp
= &phy_template_niu_10g_serdes
;
2538 case NIU_FLAGS_XCVR_SERDES
:
2540 tp
= &phy_template_niu_1g_serdes
;
2542 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
2545 tp
= &phy_template_niu_10g_fiber
;
2546 phy_addr_off
+= np
->port
;
2553 NIU_FLAGS_XCVR_SERDES
)) {
2556 tp
= &phy_template_1g_copper
;
2557 if (plat_type
== PLAT_TYPE_VF_P0
)
2559 else if (plat_type
== PLAT_TYPE_VF_P1
)
2562 phy_addr_off
+= (np
->port
^ 0x3);
2567 tp
= &phy_template_10g_copper
;
2570 case NIU_FLAGS_FIBER
:
2572 tp
= &phy_template_1g_fiber
;
2575 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
2577 tp
= &phy_template_10g_fiber
;
2578 if (plat_type
== PLAT_TYPE_VF_P0
||
2579 plat_type
== PLAT_TYPE_VF_P1
)
2581 phy_addr_off
+= np
->port
;
2582 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
2583 tp
= &phy_template_10g_fiber_hotplug
;
2591 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
2592 case NIU_FLAGS_XCVR_SERDES
| NIU_FLAGS_FIBER
:
2593 case NIU_FLAGS_XCVR_SERDES
:
2597 tp
= &phy_template_10g_serdes
;
2601 tp
= &phy_template_1g_rgmii
;
2607 phy_addr_off
= niu_atca_port_num
[np
->port
];
2615 np
->phy_ops
= tp
->ops
;
2616 np
->phy_addr
= tp
->phy_addr_base
+ phy_addr_off
;
2621 static int niu_init_link(struct niu
*np
)
2623 struct niu_parent
*parent
= np
->parent
;
2626 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
2627 err
= niu_xcvr_init(np
);
2632 err
= niu_serdes_init(np
);
2636 err
= niu_xcvr_init(np
);
2638 niu_link_status(np
, &ignore
);
2642 static void niu_set_primary_mac(struct niu
*np
, unsigned char *addr
)
2644 u16 reg0
= addr
[4] << 8 | addr
[5];
2645 u16 reg1
= addr
[2] << 8 | addr
[3];
2646 u16 reg2
= addr
[0] << 8 | addr
[1];
2648 if (np
->flags
& NIU_FLAGS_XMAC
) {
2649 nw64_mac(XMAC_ADDR0
, reg0
);
2650 nw64_mac(XMAC_ADDR1
, reg1
);
2651 nw64_mac(XMAC_ADDR2
, reg2
);
2653 nw64_mac(BMAC_ADDR0
, reg0
);
2654 nw64_mac(BMAC_ADDR1
, reg1
);
2655 nw64_mac(BMAC_ADDR2
, reg2
);
2659 static int niu_num_alt_addr(struct niu
*np
)
2661 if (np
->flags
& NIU_FLAGS_XMAC
)
2662 return XMAC_NUM_ALT_ADDR
;
2664 return BMAC_NUM_ALT_ADDR
;
2667 static int niu_set_alt_mac(struct niu
*np
, int index
, unsigned char *addr
)
2669 u16 reg0
= addr
[4] << 8 | addr
[5];
2670 u16 reg1
= addr
[2] << 8 | addr
[3];
2671 u16 reg2
= addr
[0] << 8 | addr
[1];
2673 if (index
>= niu_num_alt_addr(np
))
2676 if (np
->flags
& NIU_FLAGS_XMAC
) {
2677 nw64_mac(XMAC_ALT_ADDR0(index
), reg0
);
2678 nw64_mac(XMAC_ALT_ADDR1(index
), reg1
);
2679 nw64_mac(XMAC_ALT_ADDR2(index
), reg2
);
2681 nw64_mac(BMAC_ALT_ADDR0(index
), reg0
);
2682 nw64_mac(BMAC_ALT_ADDR1(index
), reg1
);
2683 nw64_mac(BMAC_ALT_ADDR2(index
), reg2
);
2689 static int niu_enable_alt_mac(struct niu
*np
, int index
, int on
)
2694 if (index
>= niu_num_alt_addr(np
))
2697 if (np
->flags
& NIU_FLAGS_XMAC
) {
2698 reg
= XMAC_ADDR_CMPEN
;
2701 reg
= BMAC_ADDR_CMPEN
;
2702 mask
= 1 << (index
+ 1);
2705 val
= nr64_mac(reg
);
2715 static void __set_rdc_table_num_hw(struct niu
*np
, unsigned long reg
,
2716 int num
, int mac_pref
)
2718 u64 val
= nr64_mac(reg
);
2719 val
&= ~(HOST_INFO_MACRDCTBLN
| HOST_INFO_MPR
);
2722 val
|= HOST_INFO_MPR
;
2726 static int __set_rdc_table_num(struct niu
*np
,
2727 int xmac_index
, int bmac_index
,
2728 int rdc_table_num
, int mac_pref
)
2732 if (rdc_table_num
& ~HOST_INFO_MACRDCTBLN
)
2734 if (np
->flags
& NIU_FLAGS_XMAC
)
2735 reg
= XMAC_HOST_INFO(xmac_index
);
2737 reg
= BMAC_HOST_INFO(bmac_index
);
2738 __set_rdc_table_num_hw(np
, reg
, rdc_table_num
, mac_pref
);
2742 static int niu_set_primary_mac_rdc_table(struct niu
*np
, int table_num
,
2745 return __set_rdc_table_num(np
, 17, 0, table_num
, mac_pref
);
2748 static int niu_set_multicast_mac_rdc_table(struct niu
*np
, int table_num
,
2751 return __set_rdc_table_num(np
, 16, 8, table_num
, mac_pref
);
2754 static int niu_set_alt_mac_rdc_table(struct niu
*np
, int idx
,
2755 int table_num
, int mac_pref
)
2757 if (idx
>= niu_num_alt_addr(np
))
2759 return __set_rdc_table_num(np
, idx
, idx
+ 1, table_num
, mac_pref
);
2762 static u64
vlan_entry_set_parity(u64 reg_val
)
2767 port01_mask
= 0x00ff;
2768 port23_mask
= 0xff00;
2770 if (hweight64(reg_val
& port01_mask
) & 1)
2771 reg_val
|= ENET_VLAN_TBL_PARITY0
;
2773 reg_val
&= ~ENET_VLAN_TBL_PARITY0
;
2775 if (hweight64(reg_val
& port23_mask
) & 1)
2776 reg_val
|= ENET_VLAN_TBL_PARITY1
;
2778 reg_val
&= ~ENET_VLAN_TBL_PARITY1
;
2783 static void vlan_tbl_write(struct niu
*np
, unsigned long index
,
2784 int port
, int vpr
, int rdc_table
)
2786 u64 reg_val
= nr64(ENET_VLAN_TBL(index
));
2788 reg_val
&= ~((ENET_VLAN_TBL_VPR
|
2789 ENET_VLAN_TBL_VLANRDCTBLN
) <<
2790 ENET_VLAN_TBL_SHIFT(port
));
2792 reg_val
|= (ENET_VLAN_TBL_VPR
<<
2793 ENET_VLAN_TBL_SHIFT(port
));
2794 reg_val
|= (rdc_table
<< ENET_VLAN_TBL_SHIFT(port
));
2796 reg_val
= vlan_entry_set_parity(reg_val
);
2798 nw64(ENET_VLAN_TBL(index
), reg_val
);
2801 static void vlan_tbl_clear(struct niu
*np
)
2805 for (i
= 0; i
< ENET_VLAN_TBL_NUM_ENTRIES
; i
++)
2806 nw64(ENET_VLAN_TBL(i
), 0);
2809 static int tcam_wait_bit(struct niu
*np
, u64 bit
)
2813 while (--limit
> 0) {
2814 if (nr64(TCAM_CTL
) & bit
)
2824 static int tcam_flush(struct niu
*np
, int index
)
2826 nw64(TCAM_KEY_0
, 0x00);
2827 nw64(TCAM_KEY_MASK_0
, 0xff);
2828 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_WRITE
| index
));
2830 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2834 static int tcam_read(struct niu
*np
, int index
,
2835 u64
*key
, u64
*mask
)
2839 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_READ
| index
));
2840 err
= tcam_wait_bit(np
, TCAM_CTL_STAT
);
2842 key
[0] = nr64(TCAM_KEY_0
);
2843 key
[1] = nr64(TCAM_KEY_1
);
2844 key
[2] = nr64(TCAM_KEY_2
);
2845 key
[3] = nr64(TCAM_KEY_3
);
2846 mask
[0] = nr64(TCAM_KEY_MASK_0
);
2847 mask
[1] = nr64(TCAM_KEY_MASK_1
);
2848 mask
[2] = nr64(TCAM_KEY_MASK_2
);
2849 mask
[3] = nr64(TCAM_KEY_MASK_3
);
2855 static int tcam_write(struct niu
*np
, int index
,
2856 u64
*key
, u64
*mask
)
2858 nw64(TCAM_KEY_0
, key
[0]);
2859 nw64(TCAM_KEY_1
, key
[1]);
2860 nw64(TCAM_KEY_2
, key
[2]);
2861 nw64(TCAM_KEY_3
, key
[3]);
2862 nw64(TCAM_KEY_MASK_0
, mask
[0]);
2863 nw64(TCAM_KEY_MASK_1
, mask
[1]);
2864 nw64(TCAM_KEY_MASK_2
, mask
[2]);
2865 nw64(TCAM_KEY_MASK_3
, mask
[3]);
2866 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_WRITE
| index
));
2868 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2872 static int tcam_assoc_read(struct niu
*np
, int index
, u64
*data
)
2876 nw64(TCAM_CTL
, (TCAM_CTL_RWC_RAM_READ
| index
));
2877 err
= tcam_wait_bit(np
, TCAM_CTL_STAT
);
2879 *data
= nr64(TCAM_KEY_1
);
2885 static int tcam_assoc_write(struct niu
*np
, int index
, u64 assoc_data
)
2887 nw64(TCAM_KEY_1
, assoc_data
);
2888 nw64(TCAM_CTL
, (TCAM_CTL_RWC_RAM_WRITE
| index
));
2890 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2893 static void tcam_enable(struct niu
*np
, int on
)
2895 u64 val
= nr64(FFLP_CFG_1
);
2898 val
&= ~FFLP_CFG_1_TCAM_DIS
;
2900 val
|= FFLP_CFG_1_TCAM_DIS
;
2901 nw64(FFLP_CFG_1
, val
);
2904 static void tcam_set_lat_and_ratio(struct niu
*np
, u64 latency
, u64 ratio
)
2906 u64 val
= nr64(FFLP_CFG_1
);
2908 val
&= ~(FFLP_CFG_1_FFLPINITDONE
|
2910 FFLP_CFG_1_CAMRATIO
);
2911 val
|= (latency
<< FFLP_CFG_1_CAMLAT_SHIFT
);
2912 val
|= (ratio
<< FFLP_CFG_1_CAMRATIO_SHIFT
);
2913 nw64(FFLP_CFG_1
, val
);
2915 val
= nr64(FFLP_CFG_1
);
2916 val
|= FFLP_CFG_1_FFLPINITDONE
;
2917 nw64(FFLP_CFG_1
, val
);
2920 static int tcam_user_eth_class_enable(struct niu
*np
, unsigned long class,
2926 if (class < CLASS_CODE_ETHERTYPE1
||
2927 class > CLASS_CODE_ETHERTYPE2
)
2930 reg
= L2_CLS(class - CLASS_CODE_ETHERTYPE1
);
2942 static int tcam_user_eth_class_set(struct niu
*np
, unsigned long class,
2948 if (class < CLASS_CODE_ETHERTYPE1
||
2949 class > CLASS_CODE_ETHERTYPE2
||
2950 (ether_type
& ~(u64
)0xffff) != 0)
2953 reg
= L2_CLS(class - CLASS_CODE_ETHERTYPE1
);
2955 val
&= ~L2_CLS_ETYPE
;
2956 val
|= (ether_type
<< L2_CLS_ETYPE_SHIFT
);
2963 static int tcam_user_ip_class_enable(struct niu
*np
, unsigned long class,
2969 if (class < CLASS_CODE_USER_PROG1
||
2970 class > CLASS_CODE_USER_PROG4
)
2973 reg
= L3_CLS(class - CLASS_CODE_USER_PROG1
);
2976 val
|= L3_CLS_VALID
;
2978 val
&= ~L3_CLS_VALID
;
2984 static int tcam_user_ip_class_set(struct niu
*np
, unsigned long class,
2985 int ipv6
, u64 protocol_id
,
2986 u64 tos_mask
, u64 tos_val
)
2991 if (class < CLASS_CODE_USER_PROG1
||
2992 class > CLASS_CODE_USER_PROG4
||
2993 (protocol_id
& ~(u64
)0xff) != 0 ||
2994 (tos_mask
& ~(u64
)0xff) != 0 ||
2995 (tos_val
& ~(u64
)0xff) != 0)
2998 reg
= L3_CLS(class - CLASS_CODE_USER_PROG1
);
3000 val
&= ~(L3_CLS_IPVER
| L3_CLS_PID
|
3001 L3_CLS_TOSMASK
| L3_CLS_TOS
);
3003 val
|= L3_CLS_IPVER
;
3004 val
|= (protocol_id
<< L3_CLS_PID_SHIFT
);
3005 val
|= (tos_mask
<< L3_CLS_TOSMASK_SHIFT
);
3006 val
|= (tos_val
<< L3_CLS_TOS_SHIFT
);
3012 static int tcam_early_init(struct niu
*np
)
3018 tcam_set_lat_and_ratio(np
,
3019 DEFAULT_TCAM_LATENCY
,
3020 DEFAULT_TCAM_ACCESS_RATIO
);
3021 for (i
= CLASS_CODE_ETHERTYPE1
; i
<= CLASS_CODE_ETHERTYPE2
; i
++) {
3022 err
= tcam_user_eth_class_enable(np
, i
, 0);
3026 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_USER_PROG4
; i
++) {
3027 err
= tcam_user_ip_class_enable(np
, i
, 0);
3035 static int tcam_flush_all(struct niu
*np
)
3039 for (i
= 0; i
< np
->parent
->tcam_num_entries
; i
++) {
3040 int err
= tcam_flush(np
, i
);
3047 static u64
hash_addr_regval(unsigned long index
, unsigned long num_entries
)
3049 return ((u64
)index
| (num_entries
== 1 ?
3050 HASH_TBL_ADDR_AUTOINC
: 0));
3054 static int hash_read(struct niu
*np
, unsigned long partition
,
3055 unsigned long index
, unsigned long num_entries
,
3058 u64 val
= hash_addr_regval(index
, num_entries
);
3061 if (partition
>= FCRAM_NUM_PARTITIONS
||
3062 index
+ num_entries
> FCRAM_SIZE
)
3065 nw64(HASH_TBL_ADDR(partition
), val
);
3066 for (i
= 0; i
< num_entries
; i
++)
3067 data
[i
] = nr64(HASH_TBL_DATA(partition
));
3073 static int hash_write(struct niu
*np
, unsigned long partition
,
3074 unsigned long index
, unsigned long num_entries
,
3077 u64 val
= hash_addr_regval(index
, num_entries
);
3080 if (partition
>= FCRAM_NUM_PARTITIONS
||
3081 index
+ (num_entries
* 8) > FCRAM_SIZE
)
3084 nw64(HASH_TBL_ADDR(partition
), val
);
3085 for (i
= 0; i
< num_entries
; i
++)
3086 nw64(HASH_TBL_DATA(partition
), data
[i
]);
3091 static void fflp_reset(struct niu
*np
)
3095 nw64(FFLP_CFG_1
, FFLP_CFG_1_PIO_FIO_RST
);
3097 nw64(FFLP_CFG_1
, 0);
3099 val
= FFLP_CFG_1_FCRAMOUTDR_NORMAL
| FFLP_CFG_1_FFLPINITDONE
;
3100 nw64(FFLP_CFG_1
, val
);
3103 static void fflp_set_timings(struct niu
*np
)
3105 u64 val
= nr64(FFLP_CFG_1
);
3107 val
&= ~FFLP_CFG_1_FFLPINITDONE
;
3108 val
|= (DEFAULT_FCRAMRATIO
<< FFLP_CFG_1_FCRAMRATIO_SHIFT
);
3109 nw64(FFLP_CFG_1
, val
);
3111 val
= nr64(FFLP_CFG_1
);
3112 val
|= FFLP_CFG_1_FFLPINITDONE
;
3113 nw64(FFLP_CFG_1
, val
);
3115 val
= nr64(FCRAM_REF_TMR
);
3116 val
&= ~(FCRAM_REF_TMR_MAX
| FCRAM_REF_TMR_MIN
);
3117 val
|= (DEFAULT_FCRAM_REFRESH_MAX
<< FCRAM_REF_TMR_MAX_SHIFT
);
3118 val
|= (DEFAULT_FCRAM_REFRESH_MIN
<< FCRAM_REF_TMR_MIN_SHIFT
);
3119 nw64(FCRAM_REF_TMR
, val
);
3122 static int fflp_set_partition(struct niu
*np
, u64 partition
,
3123 u64 mask
, u64 base
, int enable
)
3128 if (partition
>= FCRAM_NUM_PARTITIONS
||
3129 (mask
& ~(u64
)0x1f) != 0 ||
3130 (base
& ~(u64
)0x1f) != 0)
3133 reg
= FLW_PRT_SEL(partition
);
3136 val
&= ~(FLW_PRT_SEL_EXT
| FLW_PRT_SEL_MASK
| FLW_PRT_SEL_BASE
);
3137 val
|= (mask
<< FLW_PRT_SEL_MASK_SHIFT
);
3138 val
|= (base
<< FLW_PRT_SEL_BASE_SHIFT
);
3140 val
|= FLW_PRT_SEL_EXT
;
3146 static int fflp_disable_all_partitions(struct niu
*np
)
3150 for (i
= 0; i
< FCRAM_NUM_PARTITIONS
; i
++) {
3151 int err
= fflp_set_partition(np
, 0, 0, 0, 0);
3158 static void fflp_llcsnap_enable(struct niu
*np
, int on
)
3160 u64 val
= nr64(FFLP_CFG_1
);
3163 val
|= FFLP_CFG_1_LLCSNAP
;
3165 val
&= ~FFLP_CFG_1_LLCSNAP
;
3166 nw64(FFLP_CFG_1
, val
);
3169 static void fflp_errors_enable(struct niu
*np
, int on
)
3171 u64 val
= nr64(FFLP_CFG_1
);
3174 val
&= ~FFLP_CFG_1_ERRORDIS
;
3176 val
|= FFLP_CFG_1_ERRORDIS
;
3177 nw64(FFLP_CFG_1
, val
);
3180 static int fflp_hash_clear(struct niu
*np
)
3182 struct fcram_hash_ipv4 ent
;
3185 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3186 memset(&ent
, 0, sizeof(ent
));
3187 ent
.header
= HASH_HEADER_EXT
;
3189 for (i
= 0; i
< FCRAM_SIZE
; i
+= sizeof(ent
)) {
3190 int err
= hash_write(np
, 0, i
, 1, (u64
*) &ent
);
3197 static int fflp_early_init(struct niu
*np
)
3199 struct niu_parent
*parent
;
3200 unsigned long flags
;
3203 niu_lock_parent(np
, flags
);
3205 parent
= np
->parent
;
3207 if (!(parent
->flags
& PARENT_FLGS_CLS_HWINIT
)) {
3208 niudbg(PROBE
, "fflp_early_init: Initting hw on port %u\n",
3210 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
3212 fflp_set_timings(np
);
3213 err
= fflp_disable_all_partitions(np
);
3215 niudbg(PROBE
, "fflp_disable_all_partitions "
3216 "failed, err=%d\n", err
);
3221 err
= tcam_early_init(np
);
3223 niudbg(PROBE
, "tcam_early_init failed, err=%d\n",
3227 fflp_llcsnap_enable(np
, 1);
3228 fflp_errors_enable(np
, 0);
3232 err
= tcam_flush_all(np
);
3234 niudbg(PROBE
, "tcam_flush_all failed, err=%d\n",
3238 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
3239 err
= fflp_hash_clear(np
);
3241 niudbg(PROBE
, "fflp_hash_clear failed, "
3249 niudbg(PROBE
, "fflp_early_init: Success\n");
3250 parent
->flags
|= PARENT_FLGS_CLS_HWINIT
;
3253 niu_unlock_parent(np
, flags
);
3257 static int niu_set_flow_key(struct niu
*np
, unsigned long class_code
, u64 key
)
3259 if (class_code
< CLASS_CODE_USER_PROG1
||
3260 class_code
> CLASS_CODE_SCTP_IPV6
)
3263 nw64(FLOW_KEY(class_code
- CLASS_CODE_USER_PROG1
), key
);
3267 static int niu_set_tcam_key(struct niu
*np
, unsigned long class_code
, u64 key
)
3269 if (class_code
< CLASS_CODE_USER_PROG1
||
3270 class_code
> CLASS_CODE_SCTP_IPV6
)
3273 nw64(TCAM_KEY(class_code
- CLASS_CODE_USER_PROG1
), key
);
3277 /* Entries for the ports are interleaved in the TCAM */
3278 static u16
tcam_get_index(struct niu
*np
, u16 idx
)
3280 /* One entry reserved for IP fragment rule */
3281 if (idx
>= (np
->clas
.tcam_sz
- 1))
3283 return (np
->clas
.tcam_top
+ ((idx
+1) * np
->parent
->num_ports
));
3286 static u16
tcam_get_size(struct niu
*np
)
3288 /* One entry reserved for IP fragment rule */
3289 return np
->clas
.tcam_sz
- 1;
3292 static u16
tcam_get_valid_entry_cnt(struct niu
*np
)
3294 /* One entry reserved for IP fragment rule */
3295 return np
->clas
.tcam_valid_entries
- 1;
3298 static void niu_rx_skb_append(struct sk_buff
*skb
, struct page
*page
,
3299 u32 offset
, u32 size
)
3301 int i
= skb_shinfo(skb
)->nr_frags
;
3302 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
3305 frag
->page_offset
= offset
;
3309 skb
->data_len
+= size
;
3310 skb
->truesize
+= size
;
3312 skb_shinfo(skb
)->nr_frags
= i
+ 1;
3315 static unsigned int niu_hash_rxaddr(struct rx_ring_info
*rp
, u64 a
)
3318 a
^= (a
>> ilog2(MAX_RBR_RING_SIZE
));
3320 return (a
& (MAX_RBR_RING_SIZE
- 1));
3323 static struct page
*niu_find_rxpage(struct rx_ring_info
*rp
, u64 addr
,
3324 struct page
***link
)
3326 unsigned int h
= niu_hash_rxaddr(rp
, addr
);
3327 struct page
*p
, **pp
;
3330 pp
= &rp
->rxhash
[h
];
3331 for (; (p
= *pp
) != NULL
; pp
= (struct page
**) &p
->mapping
) {
3332 if (p
->index
== addr
) {
3341 static void niu_hash_page(struct rx_ring_info
*rp
, struct page
*page
, u64 base
)
3343 unsigned int h
= niu_hash_rxaddr(rp
, base
);
3346 page
->mapping
= (struct address_space
*) rp
->rxhash
[h
];
3347 rp
->rxhash
[h
] = page
;
3350 static int niu_rbr_add_page(struct niu
*np
, struct rx_ring_info
*rp
,
3351 gfp_t mask
, int start_index
)
3357 page
= alloc_page(mask
);
3361 addr
= np
->ops
->map_page(np
->device
, page
, 0,
3362 PAGE_SIZE
, DMA_FROM_DEVICE
);
3364 niu_hash_page(rp
, page
, addr
);
3365 if (rp
->rbr_blocks_per_page
> 1)
3366 atomic_add(rp
->rbr_blocks_per_page
- 1,
3367 &compound_head(page
)->_count
);
3369 for (i
= 0; i
< rp
->rbr_blocks_per_page
; i
++) {
3370 __le32
*rbr
= &rp
->rbr
[start_index
+ i
];
3372 *rbr
= cpu_to_le32(addr
>> RBR_DESCR_ADDR_SHIFT
);
3373 addr
+= rp
->rbr_block_size
;
3379 static void niu_rbr_refill(struct niu
*np
, struct rx_ring_info
*rp
, gfp_t mask
)
3381 int index
= rp
->rbr_index
;
3384 if ((rp
->rbr_pending
% rp
->rbr_blocks_per_page
) == 0) {
3385 int err
= niu_rbr_add_page(np
, rp
, mask
, index
);
3387 if (unlikely(err
)) {
3392 rp
->rbr_index
+= rp
->rbr_blocks_per_page
;
3393 BUG_ON(rp
->rbr_index
> rp
->rbr_table_size
);
3394 if (rp
->rbr_index
== rp
->rbr_table_size
)
3397 if (rp
->rbr_pending
>= rp
->rbr_kick_thresh
) {
3398 nw64(RBR_KICK(rp
->rx_channel
), rp
->rbr_pending
);
3399 rp
->rbr_pending
= 0;
3404 static int niu_rx_pkt_ignore(struct niu
*np
, struct rx_ring_info
*rp
)
3406 unsigned int index
= rp
->rcr_index
;
3411 struct page
*page
, **link
;
3417 val
= le64_to_cpup(&rp
->rcr
[index
]);
3418 addr
= (val
& RCR_ENTRY_PKT_BUF_ADDR
) <<
3419 RCR_ENTRY_PKT_BUF_ADDR_SHIFT
;
3420 page
= niu_find_rxpage(rp
, addr
, &link
);
3422 rcr_size
= rp
->rbr_sizes
[(val
& RCR_ENTRY_PKTBUFSZ
) >>
3423 RCR_ENTRY_PKTBUFSZ_SHIFT
];
3424 if ((page
->index
+ PAGE_SIZE
) - rcr_size
== addr
) {
3425 *link
= (struct page
*) page
->mapping
;
3426 np
->ops
->unmap_page(np
->device
, page
->index
,
3427 PAGE_SIZE
, DMA_FROM_DEVICE
);
3429 page
->mapping
= NULL
;
3431 rp
->rbr_refill_pending
++;
3434 index
= NEXT_RCR(rp
, index
);
3435 if (!(val
& RCR_ENTRY_MULTI
))
3439 rp
->rcr_index
= index
;
3444 static int niu_process_rx_pkt(struct niu
*np
, struct rx_ring_info
*rp
)
3446 unsigned int index
= rp
->rcr_index
;
3447 struct sk_buff
*skb
;
3450 skb
= netdev_alloc_skb(np
->dev
, RX_SKB_ALLOC_SIZE
);
3452 return niu_rx_pkt_ignore(np
, rp
);
3456 struct page
*page
, **link
;
3457 u32 rcr_size
, append_size
;
3462 val
= le64_to_cpup(&rp
->rcr
[index
]);
3464 len
= (val
& RCR_ENTRY_L2_LEN
) >>
3465 RCR_ENTRY_L2_LEN_SHIFT
;
3468 addr
= (val
& RCR_ENTRY_PKT_BUF_ADDR
) <<
3469 RCR_ENTRY_PKT_BUF_ADDR_SHIFT
;
3470 page
= niu_find_rxpage(rp
, addr
, &link
);
3472 rcr_size
= rp
->rbr_sizes
[(val
& RCR_ENTRY_PKTBUFSZ
) >>
3473 RCR_ENTRY_PKTBUFSZ_SHIFT
];
3475 off
= addr
& ~PAGE_MASK
;
3476 append_size
= rcr_size
;
3483 ptype
= (val
>> RCR_ENTRY_PKT_TYPE_SHIFT
);
3484 if ((ptype
== RCR_PKT_TYPE_TCP
||
3485 ptype
== RCR_PKT_TYPE_UDP
) &&
3486 !(val
& (RCR_ENTRY_NOPORT
|
3488 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3490 skb
->ip_summed
= CHECKSUM_NONE
;
3492 if (!(val
& RCR_ENTRY_MULTI
))
3493 append_size
= len
- skb
->len
;
3495 niu_rx_skb_append(skb
, page
, off
, append_size
);
3496 if ((page
->index
+ rp
->rbr_block_size
) - rcr_size
== addr
) {
3497 *link
= (struct page
*) page
->mapping
;
3498 np
->ops
->unmap_page(np
->device
, page
->index
,
3499 PAGE_SIZE
, DMA_FROM_DEVICE
);
3501 page
->mapping
= NULL
;
3502 rp
->rbr_refill_pending
++;
3506 index
= NEXT_RCR(rp
, index
);
3507 if (!(val
& RCR_ENTRY_MULTI
))
3511 rp
->rcr_index
= index
;
3513 skb_reserve(skb
, NET_IP_ALIGN
);
3514 __pskb_pull_tail(skb
, min(len
, NIU_RXPULL_MAX
));
3517 rp
->rx_bytes
+= skb
->len
;
3519 skb
->protocol
= eth_type_trans(skb
, np
->dev
);
3520 skb_record_rx_queue(skb
, rp
->rx_channel
);
3521 netif_receive_skb(skb
);
3526 static int niu_rbr_fill(struct niu
*np
, struct rx_ring_info
*rp
, gfp_t mask
)
3528 int blocks_per_page
= rp
->rbr_blocks_per_page
;
3529 int err
, index
= rp
->rbr_index
;
3532 while (index
< (rp
->rbr_table_size
- blocks_per_page
)) {
3533 err
= niu_rbr_add_page(np
, rp
, mask
, index
);
3537 index
+= blocks_per_page
;
3540 rp
->rbr_index
= index
;
3544 static void niu_rbr_free(struct niu
*np
, struct rx_ring_info
*rp
)
3548 for (i
= 0; i
< MAX_RBR_RING_SIZE
; i
++) {
3551 page
= rp
->rxhash
[i
];
3553 struct page
*next
= (struct page
*) page
->mapping
;
3554 u64 base
= page
->index
;
3556 np
->ops
->unmap_page(np
->device
, base
, PAGE_SIZE
,
3559 page
->mapping
= NULL
;
3567 for (i
= 0; i
< rp
->rbr_table_size
; i
++)
3568 rp
->rbr
[i
] = cpu_to_le32(0);
3572 static int release_tx_packet(struct niu
*np
, struct tx_ring_info
*rp
, int idx
)
3574 struct tx_buff_info
*tb
= &rp
->tx_buffs
[idx
];
3575 struct sk_buff
*skb
= tb
->skb
;
3576 struct tx_pkt_hdr
*tp
;
3580 tp
= (struct tx_pkt_hdr
*) skb
->data
;
3581 tx_flags
= le64_to_cpup(&tp
->flags
);
3584 rp
->tx_bytes
+= (((tx_flags
& TXHDR_LEN
) >> TXHDR_LEN_SHIFT
) -
3585 ((tx_flags
& TXHDR_PAD
) / 2));
3587 len
= skb_headlen(skb
);
3588 np
->ops
->unmap_single(np
->device
, tb
->mapping
,
3589 len
, DMA_TO_DEVICE
);
3591 if (le64_to_cpu(rp
->descr
[idx
]) & TX_DESC_MARK
)
3596 idx
= NEXT_TX(rp
, idx
);
3597 len
-= MAX_TX_DESC_LEN
;
3600 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
3601 tb
= &rp
->tx_buffs
[idx
];
3602 BUG_ON(tb
->skb
!= NULL
);
3603 np
->ops
->unmap_page(np
->device
, tb
->mapping
,
3604 skb_shinfo(skb
)->frags
[i
].size
,
3606 idx
= NEXT_TX(rp
, idx
);
3614 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3616 static void niu_tx_work(struct niu
*np
, struct tx_ring_info
*rp
)
3618 struct netdev_queue
*txq
;
3623 index
= (rp
- np
->tx_rings
);
3624 txq
= netdev_get_tx_queue(np
->dev
, index
);
3627 if (unlikely(!(cs
& (TX_CS_MK
| TX_CS_MMK
))))
3630 tmp
= pkt_cnt
= (cs
& TX_CS_PKT_CNT
) >> TX_CS_PKT_CNT_SHIFT
;
3631 pkt_cnt
= (pkt_cnt
- rp
->last_pkt_cnt
) &
3632 (TX_CS_PKT_CNT
>> TX_CS_PKT_CNT_SHIFT
);
3634 rp
->last_pkt_cnt
= tmp
;
3638 niudbg(TX_DONE
, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3639 np
->dev
->name
, pkt_cnt
, cons
);
3642 cons
= release_tx_packet(np
, rp
, cons
);
3648 if (unlikely(netif_tx_queue_stopped(txq
) &&
3649 (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
)))) {
3650 __netif_tx_lock(txq
, smp_processor_id());
3651 if (netif_tx_queue_stopped(txq
) &&
3652 (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
)))
3653 netif_tx_wake_queue(txq
);
3654 __netif_tx_unlock(txq
);
3658 static inline void niu_sync_rx_discard_stats(struct niu
*np
,
3659 struct rx_ring_info
*rp
,
3662 /* This elaborate scheme is needed for reading the RX discard
3663 * counters, as they are only 16-bit and can overflow quickly,
3664 * and because the overflow indication bit is not usable as
3665 * the counter value does not wrap, but remains at max value
3668 * In theory and in practice counters can be lost in between
3669 * reading nr64() and clearing the counter nw64(). For this
3670 * reason, the number of counter clearings nw64() is
3671 * limited/reduced though the limit parameter.
3673 int rx_channel
= rp
->rx_channel
;
3676 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3677 * following discard events: IPP (Input Port Process),
3678 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3679 * Block Ring) prefetch buffer is empty.
3681 misc
= nr64(RXMISC(rx_channel
));
3682 if (unlikely((misc
& RXMISC_COUNT
) > limit
)) {
3683 nw64(RXMISC(rx_channel
), 0);
3684 rp
->rx_errors
+= misc
& RXMISC_COUNT
;
3686 if (unlikely(misc
& RXMISC_OFLOW
))
3687 dev_err(np
->device
, "rx-%d: Counter overflow "
3688 "RXMISC discard\n", rx_channel
);
3690 niudbg(RX_ERR
, "%s-rx-%d: MISC drop=%u over=%u\n",
3691 np
->dev
->name
, rx_channel
, misc
, misc
-limit
);
3694 /* WRED (Weighted Random Early Discard) by hardware */
3695 wred
= nr64(RED_DIS_CNT(rx_channel
));
3696 if (unlikely((wred
& RED_DIS_CNT_COUNT
) > limit
)) {
3697 nw64(RED_DIS_CNT(rx_channel
), 0);
3698 rp
->rx_dropped
+= wred
& RED_DIS_CNT_COUNT
;
3700 if (unlikely(wred
& RED_DIS_CNT_OFLOW
))
3701 dev_err(np
->device
, "rx-%d: Counter overflow "
3702 "WRED discard\n", rx_channel
);
3704 niudbg(RX_ERR
, "%s-rx-%d: WRED drop=%u over=%u\n",
3705 np
->dev
->name
, rx_channel
, wred
, wred
-limit
);
3709 static int niu_rx_work(struct niu
*np
, struct rx_ring_info
*rp
, int budget
)
3711 int qlen
, rcr_done
= 0, work_done
= 0;
3712 struct rxdma_mailbox
*mbox
= rp
->mbox
;
3716 stat
= nr64(RX_DMA_CTL_STAT(rp
->rx_channel
));
3717 qlen
= nr64(RCRSTAT_A(rp
->rx_channel
)) & RCRSTAT_A_QLEN
;
3719 stat
= le64_to_cpup(&mbox
->rx_dma_ctl_stat
);
3720 qlen
= (le64_to_cpup(&mbox
->rcrstat_a
) & RCRSTAT_A_QLEN
);
3722 mbox
->rx_dma_ctl_stat
= 0;
3723 mbox
->rcrstat_a
= 0;
3725 niudbg(RX_STATUS
, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3726 np
->dev
->name
, rp
->rx_channel
, (unsigned long long) stat
, qlen
);
3728 rcr_done
= work_done
= 0;
3729 qlen
= min(qlen
, budget
);
3730 while (work_done
< qlen
) {
3731 rcr_done
+= niu_process_rx_pkt(np
, rp
);
3735 if (rp
->rbr_refill_pending
>= rp
->rbr_kick_thresh
) {
3738 for (i
= 0; i
< rp
->rbr_refill_pending
; i
++)
3739 niu_rbr_refill(np
, rp
, GFP_ATOMIC
);
3740 rp
->rbr_refill_pending
= 0;
3743 stat
= (RX_DMA_CTL_STAT_MEX
|
3744 ((u64
)work_done
<< RX_DMA_CTL_STAT_PKTREAD_SHIFT
) |
3745 ((u64
)rcr_done
<< RX_DMA_CTL_STAT_PTRREAD_SHIFT
));
3747 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
), stat
);
3749 /* Only sync discards stats when qlen indicate potential for drops */
3751 niu_sync_rx_discard_stats(np
, rp
, 0x7FFF);
3756 static int niu_poll_core(struct niu
*np
, struct niu_ldg
*lp
, int budget
)
3759 u32 tx_vec
= (v0
>> 32);
3760 u32 rx_vec
= (v0
& 0xffffffff);
3761 int i
, work_done
= 0;
3763 niudbg(INTR
, "%s: niu_poll_core() v0[%016llx]\n",
3764 np
->dev
->name
, (unsigned long long) v0
);
3766 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
3767 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
3768 if (tx_vec
& (1 << rp
->tx_channel
))
3769 niu_tx_work(np
, rp
);
3770 nw64(LD_IM0(LDN_TXDMA(rp
->tx_channel
)), 0);
3773 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
3774 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
3776 if (rx_vec
& (1 << rp
->rx_channel
)) {
3779 this_work_done
= niu_rx_work(np
, rp
,
3782 budget
-= this_work_done
;
3783 work_done
+= this_work_done
;
3785 nw64(LD_IM0(LDN_RXDMA(rp
->rx_channel
)), 0);
3791 static int niu_poll(struct napi_struct
*napi
, int budget
)
3793 struct niu_ldg
*lp
= container_of(napi
, struct niu_ldg
, napi
);
3794 struct niu
*np
= lp
->np
;
3797 work_done
= niu_poll_core(np
, lp
, budget
);
3799 if (work_done
< budget
) {
3800 napi_complete(napi
);
3801 niu_ldg_rearm(np
, lp
, 1);
3806 static void niu_log_rxchan_errors(struct niu
*np
, struct rx_ring_info
*rp
,
3809 dev_err(np
->device
, PFX
"%s: RX channel %u errors ( ",
3810 np
->dev
->name
, rp
->rx_channel
);
3812 if (stat
& RX_DMA_CTL_STAT_RBR_TMOUT
)
3813 printk("RBR_TMOUT ");
3814 if (stat
& RX_DMA_CTL_STAT_RSP_CNT_ERR
)
3816 if (stat
& RX_DMA_CTL_STAT_BYTE_EN_BUS
)
3817 printk("BYTE_EN_BUS ");
3818 if (stat
& RX_DMA_CTL_STAT_RSP_DAT_ERR
)
3820 if (stat
& RX_DMA_CTL_STAT_RCR_ACK_ERR
)
3822 if (stat
& RX_DMA_CTL_STAT_RCR_SHA_PAR
)
3823 printk("RCR_SHA_PAR ");
3824 if (stat
& RX_DMA_CTL_STAT_RBR_PRE_PAR
)
3825 printk("RBR_PRE_PAR ");
3826 if (stat
& RX_DMA_CTL_STAT_CONFIG_ERR
)
3828 if (stat
& RX_DMA_CTL_STAT_RCRINCON
)
3829 printk("RCRINCON ");
3830 if (stat
& RX_DMA_CTL_STAT_RCRFULL
)
3832 if (stat
& RX_DMA_CTL_STAT_RBRFULL
)
3834 if (stat
& RX_DMA_CTL_STAT_RBRLOGPAGE
)
3835 printk("RBRLOGPAGE ");
3836 if (stat
& RX_DMA_CTL_STAT_CFIGLOGPAGE
)
3837 printk("CFIGLOGPAGE ");
3838 if (stat
& RX_DMA_CTL_STAT_DC_FIFO_ERR
)
3844 static int niu_rx_error(struct niu
*np
, struct rx_ring_info
*rp
)
3846 u64 stat
= nr64(RX_DMA_CTL_STAT(rp
->rx_channel
));
3850 if (stat
& (RX_DMA_CTL_STAT_CHAN_FATAL
|
3851 RX_DMA_CTL_STAT_PORT_FATAL
))
3855 dev_err(np
->device
, PFX
"%s: RX channel %u error, stat[%llx]\n",
3856 np
->dev
->name
, rp
->rx_channel
,
3857 (unsigned long long) stat
);
3859 niu_log_rxchan_errors(np
, rp
, stat
);
3862 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
),
3863 stat
& RX_DMA_CTL_WRITE_CLEAR_ERRS
);
3868 static void niu_log_txchan_errors(struct niu
*np
, struct tx_ring_info
*rp
,
3871 dev_err(np
->device
, PFX
"%s: TX channel %u errors ( ",
3872 np
->dev
->name
, rp
->tx_channel
);
3874 if (cs
& TX_CS_MBOX_ERR
)
3876 if (cs
& TX_CS_PKT_SIZE_ERR
)
3877 printk("PKT_SIZE ");
3878 if (cs
& TX_CS_TX_RING_OFLOW
)
3879 printk("TX_RING_OFLOW ");
3880 if (cs
& TX_CS_PREF_BUF_PAR_ERR
)
3881 printk("PREF_BUF_PAR ");
3882 if (cs
& TX_CS_NACK_PREF
)
3883 printk("NACK_PREF ");
3884 if (cs
& TX_CS_NACK_PKT_RD
)
3885 printk("NACK_PKT_RD ");
3886 if (cs
& TX_CS_CONF_PART_ERR
)
3887 printk("CONF_PART ");
3888 if (cs
& TX_CS_PKT_PRT_ERR
)
3894 static int niu_tx_error(struct niu
*np
, struct tx_ring_info
*rp
)
3898 cs
= nr64(TX_CS(rp
->tx_channel
));
3899 logh
= nr64(TX_RNG_ERR_LOGH(rp
->tx_channel
));
3900 logl
= nr64(TX_RNG_ERR_LOGL(rp
->tx_channel
));
3902 dev_err(np
->device
, PFX
"%s: TX channel %u error, "
3903 "cs[%llx] logh[%llx] logl[%llx]\n",
3904 np
->dev
->name
, rp
->tx_channel
,
3905 (unsigned long long) cs
,
3906 (unsigned long long) logh
,
3907 (unsigned long long) logl
);
3909 niu_log_txchan_errors(np
, rp
, cs
);
3914 static int niu_mif_interrupt(struct niu
*np
)
3916 u64 mif_status
= nr64(MIF_STATUS
);
3919 if (np
->flags
& NIU_FLAGS_XMAC
) {
3920 u64 xrxmac_stat
= nr64_mac(XRXMAC_STATUS
);
3922 if (xrxmac_stat
& XRXMAC_STATUS_PHY_MDINT
)
3926 dev_err(np
->device
, PFX
"%s: MIF interrupt, "
3927 "stat[%llx] phy_mdint(%d)\n",
3928 np
->dev
->name
, (unsigned long long) mif_status
, phy_mdint
);
3933 static void niu_xmac_interrupt(struct niu
*np
)
3935 struct niu_xmac_stats
*mp
= &np
->mac_stats
.xmac
;
3938 val
= nr64_mac(XTXMAC_STATUS
);
3939 if (val
& XTXMAC_STATUS_FRAME_CNT_EXP
)
3940 mp
->tx_frames
+= TXMAC_FRM_CNT_COUNT
;
3941 if (val
& XTXMAC_STATUS_BYTE_CNT_EXP
)
3942 mp
->tx_bytes
+= TXMAC_BYTE_CNT_COUNT
;
3943 if (val
& XTXMAC_STATUS_TXFIFO_XFR_ERR
)
3944 mp
->tx_fifo_errors
++;
3945 if (val
& XTXMAC_STATUS_TXMAC_OFLOW
)
3946 mp
->tx_overflow_errors
++;
3947 if (val
& XTXMAC_STATUS_MAX_PSIZE_ERR
)
3948 mp
->tx_max_pkt_size_errors
++;
3949 if (val
& XTXMAC_STATUS_TXMAC_UFLOW
)
3950 mp
->tx_underflow_errors
++;
3952 val
= nr64_mac(XRXMAC_STATUS
);
3953 if (val
& XRXMAC_STATUS_LCL_FLT_STATUS
)
3954 mp
->rx_local_faults
++;
3955 if (val
& XRXMAC_STATUS_RFLT_DET
)
3956 mp
->rx_remote_faults
++;
3957 if (val
& XRXMAC_STATUS_LFLT_CNT_EXP
)
3958 mp
->rx_link_faults
+= LINK_FAULT_CNT_COUNT
;
3959 if (val
& XRXMAC_STATUS_ALIGNERR_CNT_EXP
)
3960 mp
->rx_align_errors
+= RXMAC_ALIGN_ERR_CNT_COUNT
;
3961 if (val
& XRXMAC_STATUS_RXFRAG_CNT_EXP
)
3962 mp
->rx_frags
+= RXMAC_FRAG_CNT_COUNT
;
3963 if (val
& XRXMAC_STATUS_RXMULTF_CNT_EXP
)
3964 mp
->rx_mcasts
+= RXMAC_MC_FRM_CNT_COUNT
;
3965 if (val
& XRXMAC_STATUS_RXBCAST_CNT_EXP
)
3966 mp
->rx_bcasts
+= RXMAC_BC_FRM_CNT_COUNT
;
3967 if (val
& XRXMAC_STATUS_RXBCAST_CNT_EXP
)
3968 mp
->rx_bcasts
+= RXMAC_BC_FRM_CNT_COUNT
;
3969 if (val
& XRXMAC_STATUS_RXHIST1_CNT_EXP
)
3970 mp
->rx_hist_cnt1
+= RXMAC_HIST_CNT1_COUNT
;
3971 if (val
& XRXMAC_STATUS_RXHIST2_CNT_EXP
)
3972 mp
->rx_hist_cnt2
+= RXMAC_HIST_CNT2_COUNT
;
3973 if (val
& XRXMAC_STATUS_RXHIST3_CNT_EXP
)
3974 mp
->rx_hist_cnt3
+= RXMAC_HIST_CNT3_COUNT
;
3975 if (val
& XRXMAC_STATUS_RXHIST4_CNT_EXP
)
3976 mp
->rx_hist_cnt4
+= RXMAC_HIST_CNT4_COUNT
;
3977 if (val
& XRXMAC_STATUS_RXHIST5_CNT_EXP
)
3978 mp
->rx_hist_cnt5
+= RXMAC_HIST_CNT5_COUNT
;
3979 if (val
& XRXMAC_STATUS_RXHIST6_CNT_EXP
)
3980 mp
->rx_hist_cnt6
+= RXMAC_HIST_CNT6_COUNT
;
3981 if (val
& XRXMAC_STATUS_RXHIST7_CNT_EXP
)
3982 mp
->rx_hist_cnt7
+= RXMAC_HIST_CNT7_COUNT
;
3983 if (val
& XRXMAC_STAT_MSK_RXOCTET_CNT_EXP
)
3984 mp
->rx_octets
+= RXMAC_BT_CNT_COUNT
;
3985 if (val
& XRXMAC_STATUS_CVIOLERR_CNT_EXP
)
3986 mp
->rx_code_violations
+= RXMAC_CD_VIO_CNT_COUNT
;
3987 if (val
& XRXMAC_STATUS_LENERR_CNT_EXP
)
3988 mp
->rx_len_errors
+= RXMAC_MPSZER_CNT_COUNT
;
3989 if (val
& XRXMAC_STATUS_CRCERR_CNT_EXP
)
3990 mp
->rx_crc_errors
+= RXMAC_CRC_ER_CNT_COUNT
;
3991 if (val
& XRXMAC_STATUS_RXUFLOW
)
3992 mp
->rx_underflows
++;
3993 if (val
& XRXMAC_STATUS_RXOFLOW
)
3996 val
= nr64_mac(XMAC_FC_STAT
);
3997 if (val
& XMAC_FC_STAT_TX_MAC_NPAUSE
)
3998 mp
->pause_off_state
++;
3999 if (val
& XMAC_FC_STAT_TX_MAC_PAUSE
)
4000 mp
->pause_on_state
++;
4001 if (val
& XMAC_FC_STAT_RX_MAC_RPAUSE
)
4002 mp
->pause_received
++;
4005 static void niu_bmac_interrupt(struct niu
*np
)
4007 struct niu_bmac_stats
*mp
= &np
->mac_stats
.bmac
;
4010 val
= nr64_mac(BTXMAC_STATUS
);
4011 if (val
& BTXMAC_STATUS_UNDERRUN
)
4012 mp
->tx_underflow_errors
++;
4013 if (val
& BTXMAC_STATUS_MAX_PKT_ERR
)
4014 mp
->tx_max_pkt_size_errors
++;
4015 if (val
& BTXMAC_STATUS_BYTE_CNT_EXP
)
4016 mp
->tx_bytes
+= BTXMAC_BYTE_CNT_COUNT
;
4017 if (val
& BTXMAC_STATUS_FRAME_CNT_EXP
)
4018 mp
->tx_frames
+= BTXMAC_FRM_CNT_COUNT
;
4020 val
= nr64_mac(BRXMAC_STATUS
);
4021 if (val
& BRXMAC_STATUS_OVERFLOW
)
4023 if (val
& BRXMAC_STATUS_FRAME_CNT_EXP
)
4024 mp
->rx_frames
+= BRXMAC_FRAME_CNT_COUNT
;
4025 if (val
& BRXMAC_STATUS_ALIGN_ERR_EXP
)
4026 mp
->rx_align_errors
+= BRXMAC_ALIGN_ERR_CNT_COUNT
;
4027 if (val
& BRXMAC_STATUS_CRC_ERR_EXP
)
4028 mp
->rx_crc_errors
+= BRXMAC_ALIGN_ERR_CNT_COUNT
;
4029 if (val
& BRXMAC_STATUS_LEN_ERR_EXP
)
4030 mp
->rx_len_errors
+= BRXMAC_CODE_VIOL_ERR_CNT_COUNT
;
4032 val
= nr64_mac(BMAC_CTRL_STATUS
);
4033 if (val
& BMAC_CTRL_STATUS_NOPAUSE
)
4034 mp
->pause_off_state
++;
4035 if (val
& BMAC_CTRL_STATUS_PAUSE
)
4036 mp
->pause_on_state
++;
4037 if (val
& BMAC_CTRL_STATUS_PAUSE_RECV
)
4038 mp
->pause_received
++;
4041 static int niu_mac_interrupt(struct niu
*np
)
4043 if (np
->flags
& NIU_FLAGS_XMAC
)
4044 niu_xmac_interrupt(np
);
4046 niu_bmac_interrupt(np
);
4051 static void niu_log_device_error(struct niu
*np
, u64 stat
)
4053 dev_err(np
->device
, PFX
"%s: Core device errors ( ",
4056 if (stat
& SYS_ERR_MASK_META2
)
4058 if (stat
& SYS_ERR_MASK_META1
)
4060 if (stat
& SYS_ERR_MASK_PEU
)
4062 if (stat
& SYS_ERR_MASK_TXC
)
4064 if (stat
& SYS_ERR_MASK_RDMC
)
4066 if (stat
& SYS_ERR_MASK_TDMC
)
4068 if (stat
& SYS_ERR_MASK_ZCP
)
4070 if (stat
& SYS_ERR_MASK_FFLP
)
4072 if (stat
& SYS_ERR_MASK_IPP
)
4074 if (stat
& SYS_ERR_MASK_MAC
)
4076 if (stat
& SYS_ERR_MASK_SMX
)
4082 static int niu_device_error(struct niu
*np
)
4084 u64 stat
= nr64(SYS_ERR_STAT
);
4086 dev_err(np
->device
, PFX
"%s: Core device error, stat[%llx]\n",
4087 np
->dev
->name
, (unsigned long long) stat
);
4089 niu_log_device_error(np
, stat
);
4094 static int niu_slowpath_interrupt(struct niu
*np
, struct niu_ldg
*lp
,
4095 u64 v0
, u64 v1
, u64 v2
)
4104 if (v1
& 0x00000000ffffffffULL
) {
4105 u32 rx_vec
= (v1
& 0xffffffff);
4107 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4108 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4110 if (rx_vec
& (1 << rp
->rx_channel
)) {
4111 int r
= niu_rx_error(np
, rp
);
4116 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
),
4117 RX_DMA_CTL_STAT_MEX
);
4122 if (v1
& 0x7fffffff00000000ULL
) {
4123 u32 tx_vec
= (v1
>> 32) & 0x7fffffff;
4125 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4126 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4128 if (tx_vec
& (1 << rp
->tx_channel
)) {
4129 int r
= niu_tx_error(np
, rp
);
4135 if ((v0
| v1
) & 0x8000000000000000ULL
) {
4136 int r
= niu_mif_interrupt(np
);
4142 int r
= niu_mac_interrupt(np
);
4147 int r
= niu_device_error(np
);
4154 niu_enable_interrupts(np
, 0);
4159 static void niu_rxchan_intr(struct niu
*np
, struct rx_ring_info
*rp
,
4162 struct rxdma_mailbox
*mbox
= rp
->mbox
;
4163 u64 stat_write
, stat
= le64_to_cpup(&mbox
->rx_dma_ctl_stat
);
4165 stat_write
= (RX_DMA_CTL_STAT_RCRTHRES
|
4166 RX_DMA_CTL_STAT_RCRTO
);
4167 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
), stat_write
);
4169 niudbg(INTR
, "%s: rxchan_intr stat[%llx]\n",
4170 np
->dev
->name
, (unsigned long long) stat
);
4173 static void niu_txchan_intr(struct niu
*np
, struct tx_ring_info
*rp
,
4176 rp
->tx_cs
= nr64(TX_CS(rp
->tx_channel
));
4178 niudbg(INTR
, "%s: txchan_intr cs[%llx]\n",
4179 np
->dev
->name
, (unsigned long long) rp
->tx_cs
);
4182 static void __niu_fastpath_interrupt(struct niu
*np
, int ldg
, u64 v0
)
4184 struct niu_parent
*parent
= np
->parent
;
4188 tx_vec
= (v0
>> 32);
4189 rx_vec
= (v0
& 0xffffffff);
4191 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4192 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4193 int ldn
= LDN_RXDMA(rp
->rx_channel
);
4195 if (parent
->ldg_map
[ldn
] != ldg
)
4198 nw64(LD_IM0(ldn
), LD_IM0_MASK
);
4199 if (rx_vec
& (1 << rp
->rx_channel
))
4200 niu_rxchan_intr(np
, rp
, ldn
);
4203 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4204 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4205 int ldn
= LDN_TXDMA(rp
->tx_channel
);
4207 if (parent
->ldg_map
[ldn
] != ldg
)
4210 nw64(LD_IM0(ldn
), LD_IM0_MASK
);
4211 if (tx_vec
& (1 << rp
->tx_channel
))
4212 niu_txchan_intr(np
, rp
, ldn
);
4216 static void niu_schedule_napi(struct niu
*np
, struct niu_ldg
*lp
,
4217 u64 v0
, u64 v1
, u64 v2
)
4219 if (likely(napi_schedule_prep(&lp
->napi
))) {
4223 __niu_fastpath_interrupt(np
, lp
->ldg_num
, v0
);
4224 __napi_schedule(&lp
->napi
);
4228 static irqreturn_t
niu_interrupt(int irq
, void *dev_id
)
4230 struct niu_ldg
*lp
= dev_id
;
4231 struct niu
*np
= lp
->np
;
4232 int ldg
= lp
->ldg_num
;
4233 unsigned long flags
;
4236 if (netif_msg_intr(np
))
4237 printk(KERN_DEBUG PFX
"niu_interrupt() ldg[%p](%d) ",
4240 spin_lock_irqsave(&np
->lock
, flags
);
4242 v0
= nr64(LDSV0(ldg
));
4243 v1
= nr64(LDSV1(ldg
));
4244 v2
= nr64(LDSV2(ldg
));
4246 if (netif_msg_intr(np
))
4247 printk("v0[%llx] v1[%llx] v2[%llx]\n",
4248 (unsigned long long) v0
,
4249 (unsigned long long) v1
,
4250 (unsigned long long) v2
);
4252 if (unlikely(!v0
&& !v1
&& !v2
)) {
4253 spin_unlock_irqrestore(&np
->lock
, flags
);
4257 if (unlikely((v0
& ((u64
)1 << LDN_MIF
)) || v1
|| v2
)) {
4258 int err
= niu_slowpath_interrupt(np
, lp
, v0
, v1
, v2
);
4262 if (likely(v0
& ~((u64
)1 << LDN_MIF
)))
4263 niu_schedule_napi(np
, lp
, v0
, v1
, v2
);
4265 niu_ldg_rearm(np
, lp
, 1);
4267 spin_unlock_irqrestore(&np
->lock
, flags
);
4272 static void niu_free_rx_ring_info(struct niu
*np
, struct rx_ring_info
*rp
)
4275 np
->ops
->free_coherent(np
->device
,
4276 sizeof(struct rxdma_mailbox
),
4277 rp
->mbox
, rp
->mbox_dma
);
4281 np
->ops
->free_coherent(np
->device
,
4282 MAX_RCR_RING_SIZE
* sizeof(__le64
),
4283 rp
->rcr
, rp
->rcr_dma
);
4285 rp
->rcr_table_size
= 0;
4289 niu_rbr_free(np
, rp
);
4291 np
->ops
->free_coherent(np
->device
,
4292 MAX_RBR_RING_SIZE
* sizeof(__le32
),
4293 rp
->rbr
, rp
->rbr_dma
);
4295 rp
->rbr_table_size
= 0;
4302 static void niu_free_tx_ring_info(struct niu
*np
, struct tx_ring_info
*rp
)
4305 np
->ops
->free_coherent(np
->device
,
4306 sizeof(struct txdma_mailbox
),
4307 rp
->mbox
, rp
->mbox_dma
);
4313 for (i
= 0; i
< MAX_TX_RING_SIZE
; i
++) {
4314 if (rp
->tx_buffs
[i
].skb
)
4315 (void) release_tx_packet(np
, rp
, i
);
4318 np
->ops
->free_coherent(np
->device
,
4319 MAX_TX_RING_SIZE
* sizeof(__le64
),
4320 rp
->descr
, rp
->descr_dma
);
4329 static void niu_free_channels(struct niu
*np
)
4334 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4335 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4337 niu_free_rx_ring_info(np
, rp
);
4339 kfree(np
->rx_rings
);
4340 np
->rx_rings
= NULL
;
4341 np
->num_rx_rings
= 0;
4345 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4346 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4348 niu_free_tx_ring_info(np
, rp
);
4350 kfree(np
->tx_rings
);
4351 np
->tx_rings
= NULL
;
4352 np
->num_tx_rings
= 0;
4356 static int niu_alloc_rx_ring_info(struct niu
*np
,
4357 struct rx_ring_info
*rp
)
4359 BUILD_BUG_ON(sizeof(struct rxdma_mailbox
) != 64);
4361 rp
->rxhash
= kzalloc(MAX_RBR_RING_SIZE
* sizeof(struct page
*),
4366 rp
->mbox
= np
->ops
->alloc_coherent(np
->device
,
4367 sizeof(struct rxdma_mailbox
),
4368 &rp
->mbox_dma
, GFP_KERNEL
);
4371 if ((unsigned long)rp
->mbox
& (64UL - 1)) {
4372 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
4373 "RXDMA mailbox %p\n", np
->dev
->name
, rp
->mbox
);
4377 rp
->rcr
= np
->ops
->alloc_coherent(np
->device
,
4378 MAX_RCR_RING_SIZE
* sizeof(__le64
),
4379 &rp
->rcr_dma
, GFP_KERNEL
);
4382 if ((unsigned long)rp
->rcr
& (64UL - 1)) {
4383 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
4384 "RXDMA RCR table %p\n", np
->dev
->name
, rp
->rcr
);
4387 rp
->rcr_table_size
= MAX_RCR_RING_SIZE
;
4390 rp
->rbr
= np
->ops
->alloc_coherent(np
->device
,
4391 MAX_RBR_RING_SIZE
* sizeof(__le32
),
4392 &rp
->rbr_dma
, GFP_KERNEL
);
4395 if ((unsigned long)rp
->rbr
& (64UL - 1)) {
4396 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
4397 "RXDMA RBR table %p\n", np
->dev
->name
, rp
->rbr
);
4400 rp
->rbr_table_size
= MAX_RBR_RING_SIZE
;
4402 rp
->rbr_pending
= 0;
4407 static void niu_set_max_burst(struct niu
*np
, struct tx_ring_info
*rp
)
4409 int mtu
= np
->dev
->mtu
;
4411 /* These values are recommended by the HW designers for fair
4412 * utilization of DRR amongst the rings.
4414 rp
->max_burst
= mtu
+ 32;
4415 if (rp
->max_burst
> 4096)
4416 rp
->max_burst
= 4096;
4419 static int niu_alloc_tx_ring_info(struct niu
*np
,
4420 struct tx_ring_info
*rp
)
4422 BUILD_BUG_ON(sizeof(struct txdma_mailbox
) != 64);
4424 rp
->mbox
= np
->ops
->alloc_coherent(np
->device
,
4425 sizeof(struct txdma_mailbox
),
4426 &rp
->mbox_dma
, GFP_KERNEL
);
4429 if ((unsigned long)rp
->mbox
& (64UL - 1)) {
4430 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
4431 "TXDMA mailbox %p\n", np
->dev
->name
, rp
->mbox
);
4435 rp
->descr
= np
->ops
->alloc_coherent(np
->device
,
4436 MAX_TX_RING_SIZE
* sizeof(__le64
),
4437 &rp
->descr_dma
, GFP_KERNEL
);
4440 if ((unsigned long)rp
->descr
& (64UL - 1)) {
4441 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
4442 "TXDMA descr table %p\n", np
->dev
->name
, rp
->descr
);
4446 rp
->pending
= MAX_TX_RING_SIZE
;
4451 /* XXX make these configurable... XXX */
4452 rp
->mark_freq
= rp
->pending
/ 4;
4454 niu_set_max_burst(np
, rp
);
4459 static void niu_size_rbr(struct niu
*np
, struct rx_ring_info
*rp
)
4463 bss
= min(PAGE_SHIFT
, 15);
4465 rp
->rbr_block_size
= 1 << bss
;
4466 rp
->rbr_blocks_per_page
= 1 << (PAGE_SHIFT
-bss
);
4468 rp
->rbr_sizes
[0] = 256;
4469 rp
->rbr_sizes
[1] = 1024;
4470 if (np
->dev
->mtu
> ETH_DATA_LEN
) {
4471 switch (PAGE_SIZE
) {
4473 rp
->rbr_sizes
[2] = 4096;
4477 rp
->rbr_sizes
[2] = 8192;
4481 rp
->rbr_sizes
[2] = 2048;
4483 rp
->rbr_sizes
[3] = rp
->rbr_block_size
;
4486 static int niu_alloc_channels(struct niu
*np
)
4488 struct niu_parent
*parent
= np
->parent
;
4489 int first_rx_channel
, first_tx_channel
;
4493 first_rx_channel
= first_tx_channel
= 0;
4494 for (i
= 0; i
< port
; i
++) {
4495 first_rx_channel
+= parent
->rxchan_per_port
[i
];
4496 first_tx_channel
+= parent
->txchan_per_port
[i
];
4499 np
->num_rx_rings
= parent
->rxchan_per_port
[port
];
4500 np
->num_tx_rings
= parent
->txchan_per_port
[port
];
4502 np
->dev
->real_num_tx_queues
= np
->num_tx_rings
;
4504 np
->rx_rings
= kzalloc(np
->num_rx_rings
* sizeof(struct rx_ring_info
),
4510 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4511 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4514 rp
->rx_channel
= first_rx_channel
+ i
;
4516 err
= niu_alloc_rx_ring_info(np
, rp
);
4520 niu_size_rbr(np
, rp
);
4522 /* XXX better defaults, configurable, etc... XXX */
4523 rp
->nonsyn_window
= 64;
4524 rp
->nonsyn_threshold
= rp
->rcr_table_size
- 64;
4525 rp
->syn_window
= 64;
4526 rp
->syn_threshold
= rp
->rcr_table_size
- 64;
4527 rp
->rcr_pkt_threshold
= 16;
4528 rp
->rcr_timeout
= 8;
4529 rp
->rbr_kick_thresh
= RBR_REFILL_MIN
;
4530 if (rp
->rbr_kick_thresh
< rp
->rbr_blocks_per_page
)
4531 rp
->rbr_kick_thresh
= rp
->rbr_blocks_per_page
;
4533 err
= niu_rbr_fill(np
, rp
, GFP_KERNEL
);
4538 np
->tx_rings
= kzalloc(np
->num_tx_rings
* sizeof(struct tx_ring_info
),
4544 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4545 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4548 rp
->tx_channel
= first_tx_channel
+ i
;
4550 err
= niu_alloc_tx_ring_info(np
, rp
);
4558 niu_free_channels(np
);
4562 static int niu_tx_cs_sng_poll(struct niu
*np
, int channel
)
4566 while (--limit
> 0) {
4567 u64 val
= nr64(TX_CS(channel
));
4568 if (val
& TX_CS_SNG_STATE
)
4574 static int niu_tx_channel_stop(struct niu
*np
, int channel
)
4576 u64 val
= nr64(TX_CS(channel
));
4578 val
|= TX_CS_STOP_N_GO
;
4579 nw64(TX_CS(channel
), val
);
4581 return niu_tx_cs_sng_poll(np
, channel
);
4584 static int niu_tx_cs_reset_poll(struct niu
*np
, int channel
)
4588 while (--limit
> 0) {
4589 u64 val
= nr64(TX_CS(channel
));
4590 if (!(val
& TX_CS_RST
))
4596 static int niu_tx_channel_reset(struct niu
*np
, int channel
)
4598 u64 val
= nr64(TX_CS(channel
));
4602 nw64(TX_CS(channel
), val
);
4604 err
= niu_tx_cs_reset_poll(np
, channel
);
4606 nw64(TX_RING_KICK(channel
), 0);
4611 static int niu_tx_channel_lpage_init(struct niu
*np
, int channel
)
4615 nw64(TX_LOG_MASK1(channel
), 0);
4616 nw64(TX_LOG_VAL1(channel
), 0);
4617 nw64(TX_LOG_MASK2(channel
), 0);
4618 nw64(TX_LOG_VAL2(channel
), 0);
4619 nw64(TX_LOG_PAGE_RELO1(channel
), 0);
4620 nw64(TX_LOG_PAGE_RELO2(channel
), 0);
4621 nw64(TX_LOG_PAGE_HDL(channel
), 0);
4623 val
= (u64
)np
->port
<< TX_LOG_PAGE_VLD_FUNC_SHIFT
;
4624 val
|= (TX_LOG_PAGE_VLD_PAGE0
| TX_LOG_PAGE_VLD_PAGE1
);
4625 nw64(TX_LOG_PAGE_VLD(channel
), val
);
4627 /* XXX TXDMA 32bit mode? XXX */
4632 static void niu_txc_enable_port(struct niu
*np
, int on
)
4634 unsigned long flags
;
4637 niu_lock_parent(np
, flags
);
4638 val
= nr64(TXC_CONTROL
);
4639 mask
= (u64
)1 << np
->port
;
4641 val
|= TXC_CONTROL_ENABLE
| mask
;
4644 if ((val
& ~TXC_CONTROL_ENABLE
) == 0)
4645 val
&= ~TXC_CONTROL_ENABLE
;
4647 nw64(TXC_CONTROL
, val
);
4648 niu_unlock_parent(np
, flags
);
4651 static void niu_txc_set_imask(struct niu
*np
, u64 imask
)
4653 unsigned long flags
;
4656 niu_lock_parent(np
, flags
);
4657 val
= nr64(TXC_INT_MASK
);
4658 val
&= ~TXC_INT_MASK_VAL(np
->port
);
4659 val
|= (imask
<< TXC_INT_MASK_VAL_SHIFT(np
->port
));
4660 niu_unlock_parent(np
, flags
);
4663 static void niu_txc_port_dma_enable(struct niu
*np
, int on
)
4670 for (i
= 0; i
< np
->num_tx_rings
; i
++)
4671 val
|= (1 << np
->tx_rings
[i
].tx_channel
);
4673 nw64(TXC_PORT_DMA(np
->port
), val
);
4676 static int niu_init_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
4678 int err
, channel
= rp
->tx_channel
;
4681 err
= niu_tx_channel_stop(np
, channel
);
4685 err
= niu_tx_channel_reset(np
, channel
);
4689 err
= niu_tx_channel_lpage_init(np
, channel
);
4693 nw64(TXC_DMA_MAX(channel
), rp
->max_burst
);
4694 nw64(TX_ENT_MSK(channel
), 0);
4696 if (rp
->descr_dma
& ~(TX_RNG_CFIG_STADDR_BASE
|
4697 TX_RNG_CFIG_STADDR
)) {
4698 dev_err(np
->device
, PFX
"%s: TX ring channel %d "
4699 "DMA addr (%llx) is not aligned.\n",
4700 np
->dev
->name
, channel
,
4701 (unsigned long long) rp
->descr_dma
);
4705 /* The length field in TX_RNG_CFIG is measured in 64-byte
4706 * blocks. rp->pending is the number of TX descriptors in
4707 * our ring, 8 bytes each, thus we divide by 8 bytes more
4708 * to get the proper value the chip wants.
4710 ring_len
= (rp
->pending
/ 8);
4712 val
= ((ring_len
<< TX_RNG_CFIG_LEN_SHIFT
) |
4714 nw64(TX_RNG_CFIG(channel
), val
);
4716 if (((rp
->mbox_dma
>> 32) & ~TXDMA_MBH_MBADDR
) ||
4717 ((u32
)rp
->mbox_dma
& ~TXDMA_MBL_MBADDR
)) {
4718 dev_err(np
->device
, PFX
"%s: TX ring channel %d "
4719 "MBOX addr (%llx) is has illegal bits.\n",
4720 np
->dev
->name
, channel
,
4721 (unsigned long long) rp
->mbox_dma
);
4724 nw64(TXDMA_MBH(channel
), rp
->mbox_dma
>> 32);
4725 nw64(TXDMA_MBL(channel
), rp
->mbox_dma
& TXDMA_MBL_MBADDR
);
4727 nw64(TX_CS(channel
), 0);
4729 rp
->last_pkt_cnt
= 0;
4734 static void niu_init_rdc_groups(struct niu
*np
)
4736 struct niu_rdc_tables
*tp
= &np
->parent
->rdc_group_cfg
[np
->port
];
4737 int i
, first_table_num
= tp
->first_table_num
;
4739 for (i
= 0; i
< tp
->num_tables
; i
++) {
4740 struct rdc_table
*tbl
= &tp
->tables
[i
];
4741 int this_table
= first_table_num
+ i
;
4744 for (slot
= 0; slot
< NIU_RDC_TABLE_SLOTS
; slot
++)
4745 nw64(RDC_TBL(this_table
, slot
),
4746 tbl
->rxdma_channel
[slot
]);
4749 nw64(DEF_RDC(np
->port
), np
->parent
->rdc_default
[np
->port
]);
4752 static void niu_init_drr_weight(struct niu
*np
)
4754 int type
= phy_decode(np
->parent
->port_phy
, np
->port
);
4759 val
= PT_DRR_WEIGHT_DEFAULT_10G
;
4764 val
= PT_DRR_WEIGHT_DEFAULT_1G
;
4767 nw64(PT_DRR_WT(np
->port
), val
);
4770 static int niu_init_hostinfo(struct niu
*np
)
4772 struct niu_parent
*parent
= np
->parent
;
4773 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
4774 int i
, err
, num_alt
= niu_num_alt_addr(np
);
4775 int first_rdc_table
= tp
->first_table_num
;
4777 err
= niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
4781 err
= niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
4785 for (i
= 0; i
< num_alt
; i
++) {
4786 err
= niu_set_alt_mac_rdc_table(np
, i
, first_rdc_table
, 1);
4794 static int niu_rx_channel_reset(struct niu
*np
, int channel
)
4796 return niu_set_and_wait_clear(np
, RXDMA_CFIG1(channel
),
4797 RXDMA_CFIG1_RST
, 1000, 10,
4801 static int niu_rx_channel_lpage_init(struct niu
*np
, int channel
)
4805 nw64(RX_LOG_MASK1(channel
), 0);
4806 nw64(RX_LOG_VAL1(channel
), 0);
4807 nw64(RX_LOG_MASK2(channel
), 0);
4808 nw64(RX_LOG_VAL2(channel
), 0);
4809 nw64(RX_LOG_PAGE_RELO1(channel
), 0);
4810 nw64(RX_LOG_PAGE_RELO2(channel
), 0);
4811 nw64(RX_LOG_PAGE_HDL(channel
), 0);
4813 val
= (u64
)np
->port
<< RX_LOG_PAGE_VLD_FUNC_SHIFT
;
4814 val
|= (RX_LOG_PAGE_VLD_PAGE0
| RX_LOG_PAGE_VLD_PAGE1
);
4815 nw64(RX_LOG_PAGE_VLD(channel
), val
);
4820 static void niu_rx_channel_wred_init(struct niu
*np
, struct rx_ring_info
*rp
)
4824 val
= (((u64
)rp
->nonsyn_window
<< RDC_RED_PARA_WIN_SHIFT
) |
4825 ((u64
)rp
->nonsyn_threshold
<< RDC_RED_PARA_THRE_SHIFT
) |
4826 ((u64
)rp
->syn_window
<< RDC_RED_PARA_WIN_SYN_SHIFT
) |
4827 ((u64
)rp
->syn_threshold
<< RDC_RED_PARA_THRE_SYN_SHIFT
));
4828 nw64(RDC_RED_PARA(rp
->rx_channel
), val
);
4831 static int niu_compute_rbr_cfig_b(struct rx_ring_info
*rp
, u64
*ret
)
4835 switch (rp
->rbr_block_size
) {
4837 val
|= (RBR_BLKSIZE_4K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4840 val
|= (RBR_BLKSIZE_8K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4843 val
|= (RBR_BLKSIZE_16K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4846 val
|= (RBR_BLKSIZE_32K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4851 val
|= RBR_CFIG_B_VLD2
;
4852 switch (rp
->rbr_sizes
[2]) {
4854 val
|= (RBR_BUFSZ2_2K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4857 val
|= (RBR_BUFSZ2_4K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4860 val
|= (RBR_BUFSZ2_8K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4863 val
|= (RBR_BUFSZ2_16K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4869 val
|= RBR_CFIG_B_VLD1
;
4870 switch (rp
->rbr_sizes
[1]) {
4872 val
|= (RBR_BUFSZ1_1K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4875 val
|= (RBR_BUFSZ1_2K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4878 val
|= (RBR_BUFSZ1_4K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4881 val
|= (RBR_BUFSZ1_8K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4887 val
|= RBR_CFIG_B_VLD0
;
4888 switch (rp
->rbr_sizes
[0]) {
4890 val
|= (RBR_BUFSZ0_256
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4893 val
|= (RBR_BUFSZ0_512
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4896 val
|= (RBR_BUFSZ0_1K
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4899 val
|= (RBR_BUFSZ0_2K
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4910 static int niu_enable_rx_channel(struct niu
*np
, int channel
, int on
)
4912 u64 val
= nr64(RXDMA_CFIG1(channel
));
4916 val
|= RXDMA_CFIG1_EN
;
4918 val
&= ~RXDMA_CFIG1_EN
;
4919 nw64(RXDMA_CFIG1(channel
), val
);
4922 while (--limit
> 0) {
4923 if (nr64(RXDMA_CFIG1(channel
)) & RXDMA_CFIG1_QST
)
4932 static int niu_init_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
4934 int err
, channel
= rp
->rx_channel
;
4937 err
= niu_rx_channel_reset(np
, channel
);
4941 err
= niu_rx_channel_lpage_init(np
, channel
);
4945 niu_rx_channel_wred_init(np
, rp
);
4947 nw64(RX_DMA_ENT_MSK(channel
), RX_DMA_ENT_MSK_RBR_EMPTY
);
4948 nw64(RX_DMA_CTL_STAT(channel
),
4949 (RX_DMA_CTL_STAT_MEX
|
4950 RX_DMA_CTL_STAT_RCRTHRES
|
4951 RX_DMA_CTL_STAT_RCRTO
|
4952 RX_DMA_CTL_STAT_RBR_EMPTY
));
4953 nw64(RXDMA_CFIG1(channel
), rp
->mbox_dma
>> 32);
4954 nw64(RXDMA_CFIG2(channel
), (rp
->mbox_dma
& 0x00000000ffffffc0));
4955 nw64(RBR_CFIG_A(channel
),
4956 ((u64
)rp
->rbr_table_size
<< RBR_CFIG_A_LEN_SHIFT
) |
4957 (rp
->rbr_dma
& (RBR_CFIG_A_STADDR_BASE
| RBR_CFIG_A_STADDR
)));
4958 err
= niu_compute_rbr_cfig_b(rp
, &val
);
4961 nw64(RBR_CFIG_B(channel
), val
);
4962 nw64(RCRCFIG_A(channel
),
4963 ((u64
)rp
->rcr_table_size
<< RCRCFIG_A_LEN_SHIFT
) |
4964 (rp
->rcr_dma
& (RCRCFIG_A_STADDR_BASE
| RCRCFIG_A_STADDR
)));
4965 nw64(RCRCFIG_B(channel
),
4966 ((u64
)rp
->rcr_pkt_threshold
<< RCRCFIG_B_PTHRES_SHIFT
) |
4968 ((u64
)rp
->rcr_timeout
<< RCRCFIG_B_TIMEOUT_SHIFT
));
4970 err
= niu_enable_rx_channel(np
, channel
, 1);
4974 nw64(RBR_KICK(channel
), rp
->rbr_index
);
4976 val
= nr64(RX_DMA_CTL_STAT(channel
));
4977 val
|= RX_DMA_CTL_STAT_RBR_EMPTY
;
4978 nw64(RX_DMA_CTL_STAT(channel
), val
);
4983 static int niu_init_rx_channels(struct niu
*np
)
4985 unsigned long flags
;
4986 u64 seed
= jiffies_64
;
4989 niu_lock_parent(np
, flags
);
4990 nw64(RX_DMA_CK_DIV
, np
->parent
->rxdma_clock_divider
);
4991 nw64(RED_RAN_INIT
, RED_RAN_INIT_OPMODE
| (seed
& RED_RAN_INIT_VAL
));
4992 niu_unlock_parent(np
, flags
);
4994 /* XXX RXDMA 32bit mode? XXX */
4996 niu_init_rdc_groups(np
);
4997 niu_init_drr_weight(np
);
4999 err
= niu_init_hostinfo(np
);
5003 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5004 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5006 err
= niu_init_one_rx_channel(np
, rp
);
5014 static int niu_set_ip_frag_rule(struct niu
*np
)
5016 struct niu_parent
*parent
= np
->parent
;
5017 struct niu_classifier
*cp
= &np
->clas
;
5018 struct niu_tcam_entry
*tp
;
5021 index
= cp
->tcam_top
;
5022 tp
= &parent
->tcam
[index
];
5024 /* Note that the noport bit is the same in both ipv4 and
5025 * ipv6 format TCAM entries.
5027 memset(tp
, 0, sizeof(*tp
));
5028 tp
->key
[1] = TCAM_V4KEY1_NOPORT
;
5029 tp
->key_mask
[1] = TCAM_V4KEY1_NOPORT
;
5030 tp
->assoc_data
= (TCAM_ASSOCDATA_TRES_USE_OFFSET
|
5031 ((u64
)0 << TCAM_ASSOCDATA_OFFSET_SHIFT
));
5032 err
= tcam_write(np
, index
, tp
->key
, tp
->key_mask
);
5035 err
= tcam_assoc_write(np
, index
, tp
->assoc_data
);
5039 cp
->tcam_valid_entries
++;
5044 static int niu_init_classifier_hw(struct niu
*np
)
5046 struct niu_parent
*parent
= np
->parent
;
5047 struct niu_classifier
*cp
= &np
->clas
;
5050 nw64(H1POLY
, cp
->h1_init
);
5051 nw64(H2POLY
, cp
->h2_init
);
5053 err
= niu_init_hostinfo(np
);
5057 for (i
= 0; i
< ENET_VLAN_TBL_NUM_ENTRIES
; i
++) {
5058 struct niu_vlan_rdc
*vp
= &cp
->vlan_mappings
[i
];
5060 vlan_tbl_write(np
, i
, np
->port
,
5061 vp
->vlan_pref
, vp
->rdc_num
);
5064 for (i
= 0; i
< cp
->num_alt_mac_mappings
; i
++) {
5065 struct niu_altmac_rdc
*ap
= &cp
->alt_mac_mappings
[i
];
5067 err
= niu_set_alt_mac_rdc_table(np
, ap
->alt_mac_num
,
5068 ap
->rdc_num
, ap
->mac_pref
);
5073 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_SCTP_IPV6
; i
++) {
5074 int index
= i
- CLASS_CODE_USER_PROG1
;
5076 err
= niu_set_tcam_key(np
, i
, parent
->tcam_key
[index
]);
5079 err
= niu_set_flow_key(np
, i
, parent
->flow_key
[index
]);
5084 err
= niu_set_ip_frag_rule(np
);
5093 static int niu_zcp_write(struct niu
*np
, int index
, u64
*data
)
5095 nw64(ZCP_RAM_DATA0
, data
[0]);
5096 nw64(ZCP_RAM_DATA1
, data
[1]);
5097 nw64(ZCP_RAM_DATA2
, data
[2]);
5098 nw64(ZCP_RAM_DATA3
, data
[3]);
5099 nw64(ZCP_RAM_DATA4
, data
[4]);
5100 nw64(ZCP_RAM_BE
, ZCP_RAM_BE_VAL
);
5102 (ZCP_RAM_ACC_WRITE
|
5103 (0 << ZCP_RAM_ACC_ZFCID_SHIFT
) |
5104 (ZCP_RAM_SEL_CFIFO(np
->port
) << ZCP_RAM_ACC_RAM_SEL_SHIFT
)));
5106 return niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
5110 static int niu_zcp_read(struct niu
*np
, int index
, u64
*data
)
5114 err
= niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
5117 dev_err(np
->device
, PFX
"%s: ZCP read busy won't clear, "
5118 "ZCP_RAM_ACC[%llx]\n", np
->dev
->name
,
5119 (unsigned long long) nr64(ZCP_RAM_ACC
));
5125 (0 << ZCP_RAM_ACC_ZFCID_SHIFT
) |
5126 (ZCP_RAM_SEL_CFIFO(np
->port
) << ZCP_RAM_ACC_RAM_SEL_SHIFT
)));
5128 err
= niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
5131 dev_err(np
->device
, PFX
"%s: ZCP read busy2 won't clear, "
5132 "ZCP_RAM_ACC[%llx]\n", np
->dev
->name
,
5133 (unsigned long long) nr64(ZCP_RAM_ACC
));
5137 data
[0] = nr64(ZCP_RAM_DATA0
);
5138 data
[1] = nr64(ZCP_RAM_DATA1
);
5139 data
[2] = nr64(ZCP_RAM_DATA2
);
5140 data
[3] = nr64(ZCP_RAM_DATA3
);
5141 data
[4] = nr64(ZCP_RAM_DATA4
);
5146 static void niu_zcp_cfifo_reset(struct niu
*np
)
5148 u64 val
= nr64(RESET_CFIFO
);
5150 val
|= RESET_CFIFO_RST(np
->port
);
5151 nw64(RESET_CFIFO
, val
);
5154 val
&= ~RESET_CFIFO_RST(np
->port
);
5155 nw64(RESET_CFIFO
, val
);
5158 static int niu_init_zcp(struct niu
*np
)
5160 u64 data
[5], rbuf
[5];
5163 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
5164 if (np
->port
== 0 || np
->port
== 1)
5165 max
= ATLAS_P0_P1_CFIFO_ENTRIES
;
5167 max
= ATLAS_P2_P3_CFIFO_ENTRIES
;
5169 max
= NIU_CFIFO_ENTRIES
;
5177 for (i
= 0; i
< max
; i
++) {
5178 err
= niu_zcp_write(np
, i
, data
);
5181 err
= niu_zcp_read(np
, i
, rbuf
);
5186 niu_zcp_cfifo_reset(np
);
5187 nw64(CFIFO_ECC(np
->port
), 0);
5188 nw64(ZCP_INT_STAT
, ZCP_INT_STAT_ALL
);
5189 (void) nr64(ZCP_INT_STAT
);
5190 nw64(ZCP_INT_MASK
, ZCP_INT_MASK_ALL
);
5195 static void niu_ipp_write(struct niu
*np
, int index
, u64
*data
)
5197 u64 val
= nr64_ipp(IPP_CFIG
);
5199 nw64_ipp(IPP_CFIG
, val
| IPP_CFIG_DFIFO_PIO_W
);
5200 nw64_ipp(IPP_DFIFO_WR_PTR
, index
);
5201 nw64_ipp(IPP_DFIFO_WR0
, data
[0]);
5202 nw64_ipp(IPP_DFIFO_WR1
, data
[1]);
5203 nw64_ipp(IPP_DFIFO_WR2
, data
[2]);
5204 nw64_ipp(IPP_DFIFO_WR3
, data
[3]);
5205 nw64_ipp(IPP_DFIFO_WR4
, data
[4]);
5206 nw64_ipp(IPP_CFIG
, val
& ~IPP_CFIG_DFIFO_PIO_W
);
5209 static void niu_ipp_read(struct niu
*np
, int index
, u64
*data
)
5211 nw64_ipp(IPP_DFIFO_RD_PTR
, index
);
5212 data
[0] = nr64_ipp(IPP_DFIFO_RD0
);
5213 data
[1] = nr64_ipp(IPP_DFIFO_RD1
);
5214 data
[2] = nr64_ipp(IPP_DFIFO_RD2
);
5215 data
[3] = nr64_ipp(IPP_DFIFO_RD3
);
5216 data
[4] = nr64_ipp(IPP_DFIFO_RD4
);
5219 static int niu_ipp_reset(struct niu
*np
)
5221 return niu_set_and_wait_clear_ipp(np
, IPP_CFIG
, IPP_CFIG_SOFT_RST
,
5222 1000, 100, "IPP_CFIG");
5225 static int niu_init_ipp(struct niu
*np
)
5227 u64 data
[5], rbuf
[5], val
;
5230 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
5231 if (np
->port
== 0 || np
->port
== 1)
5232 max
= ATLAS_P0_P1_DFIFO_ENTRIES
;
5234 max
= ATLAS_P2_P3_DFIFO_ENTRIES
;
5236 max
= NIU_DFIFO_ENTRIES
;
5244 for (i
= 0; i
< max
; i
++) {
5245 niu_ipp_write(np
, i
, data
);
5246 niu_ipp_read(np
, i
, rbuf
);
5249 (void) nr64_ipp(IPP_INT_STAT
);
5250 (void) nr64_ipp(IPP_INT_STAT
);
5252 err
= niu_ipp_reset(np
);
5256 (void) nr64_ipp(IPP_PKT_DIS
);
5257 (void) nr64_ipp(IPP_BAD_CS_CNT
);
5258 (void) nr64_ipp(IPP_ECC
);
5260 (void) nr64_ipp(IPP_INT_STAT
);
5262 nw64_ipp(IPP_MSK
, ~IPP_MSK_ALL
);
5264 val
= nr64_ipp(IPP_CFIG
);
5265 val
&= ~IPP_CFIG_IP_MAX_PKT
;
5266 val
|= (IPP_CFIG_IPP_ENABLE
|
5267 IPP_CFIG_DFIFO_ECC_EN
|
5268 IPP_CFIG_DROP_BAD_CRC
|
5270 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT
));
5271 nw64_ipp(IPP_CFIG
, val
);
5276 static void niu_handle_led(struct niu
*np
, int status
)
5279 val
= nr64_mac(XMAC_CONFIG
);
5281 if ((np
->flags
& NIU_FLAGS_10G
) != 0 &&
5282 (np
->flags
& NIU_FLAGS_FIBER
) != 0) {
5284 val
|= XMAC_CONFIG_LED_POLARITY
;
5285 val
&= ~XMAC_CONFIG_FORCE_LED_ON
;
5287 val
|= XMAC_CONFIG_FORCE_LED_ON
;
5288 val
&= ~XMAC_CONFIG_LED_POLARITY
;
5292 nw64_mac(XMAC_CONFIG
, val
);
5295 static void niu_init_xif_xmac(struct niu
*np
)
5297 struct niu_link_config
*lp
= &np
->link_config
;
5300 if (np
->flags
& NIU_FLAGS_XCVR_SERDES
) {
5301 val
= nr64(MIF_CONFIG
);
5302 val
|= MIF_CONFIG_ATCA_GE
;
5303 nw64(MIF_CONFIG
, val
);
5306 val
= nr64_mac(XMAC_CONFIG
);
5307 val
&= ~XMAC_CONFIG_SEL_POR_CLK_SRC
;
5309 val
|= XMAC_CONFIG_TX_OUTPUT_EN
;
5311 if (lp
->loopback_mode
== LOOPBACK_MAC
) {
5312 val
&= ~XMAC_CONFIG_SEL_POR_CLK_SRC
;
5313 val
|= XMAC_CONFIG_LOOPBACK
;
5315 val
&= ~XMAC_CONFIG_LOOPBACK
;
5318 if (np
->flags
& NIU_FLAGS_10G
) {
5319 val
&= ~XMAC_CONFIG_LFS_DISABLE
;
5321 val
|= XMAC_CONFIG_LFS_DISABLE
;
5322 if (!(np
->flags
& NIU_FLAGS_FIBER
) &&
5323 !(np
->flags
& NIU_FLAGS_XCVR_SERDES
))
5324 val
|= XMAC_CONFIG_1G_PCS_BYPASS
;
5326 val
&= ~XMAC_CONFIG_1G_PCS_BYPASS
;
5329 val
&= ~XMAC_CONFIG_10G_XPCS_BYPASS
;
5331 if (lp
->active_speed
== SPEED_100
)
5332 val
|= XMAC_CONFIG_SEL_CLK_25MHZ
;
5334 val
&= ~XMAC_CONFIG_SEL_CLK_25MHZ
;
5336 nw64_mac(XMAC_CONFIG
, val
);
5338 val
= nr64_mac(XMAC_CONFIG
);
5339 val
&= ~XMAC_CONFIG_MODE_MASK
;
5340 if (np
->flags
& NIU_FLAGS_10G
) {
5341 val
|= XMAC_CONFIG_MODE_XGMII
;
5343 if (lp
->active_speed
== SPEED_1000
)
5344 val
|= XMAC_CONFIG_MODE_GMII
;
5346 val
|= XMAC_CONFIG_MODE_MII
;
5349 nw64_mac(XMAC_CONFIG
, val
);
5352 static void niu_init_xif_bmac(struct niu
*np
)
5354 struct niu_link_config
*lp
= &np
->link_config
;
5357 val
= BMAC_XIF_CONFIG_TX_OUTPUT_EN
;
5359 if (lp
->loopback_mode
== LOOPBACK_MAC
)
5360 val
|= BMAC_XIF_CONFIG_MII_LOOPBACK
;
5362 val
&= ~BMAC_XIF_CONFIG_MII_LOOPBACK
;
5364 if (lp
->active_speed
== SPEED_1000
)
5365 val
|= BMAC_XIF_CONFIG_GMII_MODE
;
5367 val
&= ~BMAC_XIF_CONFIG_GMII_MODE
;
5369 val
&= ~(BMAC_XIF_CONFIG_LINK_LED
|
5370 BMAC_XIF_CONFIG_LED_POLARITY
);
5372 if (!(np
->flags
& NIU_FLAGS_10G
) &&
5373 !(np
->flags
& NIU_FLAGS_FIBER
) &&
5374 lp
->active_speed
== SPEED_100
)
5375 val
|= BMAC_XIF_CONFIG_25MHZ_CLOCK
;
5377 val
&= ~BMAC_XIF_CONFIG_25MHZ_CLOCK
;
5379 nw64_mac(BMAC_XIF_CONFIG
, val
);
5382 static void niu_init_xif(struct niu
*np
)
5384 if (np
->flags
& NIU_FLAGS_XMAC
)
5385 niu_init_xif_xmac(np
);
5387 niu_init_xif_bmac(np
);
5390 static void niu_pcs_mii_reset(struct niu
*np
)
5393 u64 val
= nr64_pcs(PCS_MII_CTL
);
5394 val
|= PCS_MII_CTL_RST
;
5395 nw64_pcs(PCS_MII_CTL
, val
);
5396 while ((--limit
>= 0) && (val
& PCS_MII_CTL_RST
)) {
5398 val
= nr64_pcs(PCS_MII_CTL
);
5402 static void niu_xpcs_reset(struct niu
*np
)
5405 u64 val
= nr64_xpcs(XPCS_CONTROL1
);
5406 val
|= XPCS_CONTROL1_RESET
;
5407 nw64_xpcs(XPCS_CONTROL1
, val
);
5408 while ((--limit
>= 0) && (val
& XPCS_CONTROL1_RESET
)) {
5410 val
= nr64_xpcs(XPCS_CONTROL1
);
5414 static int niu_init_pcs(struct niu
*np
)
5416 struct niu_link_config
*lp
= &np
->link_config
;
5419 switch (np
->flags
& (NIU_FLAGS_10G
|
5421 NIU_FLAGS_XCVR_SERDES
)) {
5422 case NIU_FLAGS_FIBER
:
5424 nw64_pcs(PCS_CONF
, PCS_CONF_MASK
| PCS_CONF_ENABLE
);
5425 nw64_pcs(PCS_DPATH_MODE
, 0);
5426 niu_pcs_mii_reset(np
);
5430 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
5431 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
5433 if (!(np
->flags
& NIU_FLAGS_XMAC
))
5436 /* 10G copper or fiber */
5437 val
= nr64_mac(XMAC_CONFIG
);
5438 val
&= ~XMAC_CONFIG_10G_XPCS_BYPASS
;
5439 nw64_mac(XMAC_CONFIG
, val
);
5443 val
= nr64_xpcs(XPCS_CONTROL1
);
5444 if (lp
->loopback_mode
== LOOPBACK_PHY
)
5445 val
|= XPCS_CONTROL1_LOOPBACK
;
5447 val
&= ~XPCS_CONTROL1_LOOPBACK
;
5448 nw64_xpcs(XPCS_CONTROL1
, val
);
5450 nw64_xpcs(XPCS_DESKEW_ERR_CNT
, 0);
5451 (void) nr64_xpcs(XPCS_SYMERR_CNT01
);
5452 (void) nr64_xpcs(XPCS_SYMERR_CNT23
);
5456 case NIU_FLAGS_XCVR_SERDES
:
5458 niu_pcs_mii_reset(np
);
5459 nw64_pcs(PCS_CONF
, PCS_CONF_MASK
| PCS_CONF_ENABLE
);
5460 nw64_pcs(PCS_DPATH_MODE
, 0);
5465 case NIU_FLAGS_XCVR_SERDES
| NIU_FLAGS_FIBER
:
5466 /* 1G RGMII FIBER */
5467 nw64_pcs(PCS_DPATH_MODE
, PCS_DPATH_MODE_MII
);
5468 niu_pcs_mii_reset(np
);
5478 static int niu_reset_tx_xmac(struct niu
*np
)
5480 return niu_set_and_wait_clear_mac(np
, XTXMAC_SW_RST
,
5481 (XTXMAC_SW_RST_REG_RS
|
5482 XTXMAC_SW_RST_SOFT_RST
),
5483 1000, 100, "XTXMAC_SW_RST");
5486 static int niu_reset_tx_bmac(struct niu
*np
)
5490 nw64_mac(BTXMAC_SW_RST
, BTXMAC_SW_RST_RESET
);
5492 while (--limit
>= 0) {
5493 if (!(nr64_mac(BTXMAC_SW_RST
) & BTXMAC_SW_RST_RESET
))
5498 dev_err(np
->device
, PFX
"Port %u TX BMAC would not reset, "
5499 "BTXMAC_SW_RST[%llx]\n",
5501 (unsigned long long) nr64_mac(BTXMAC_SW_RST
));
5508 static int niu_reset_tx_mac(struct niu
*np
)
5510 if (np
->flags
& NIU_FLAGS_XMAC
)
5511 return niu_reset_tx_xmac(np
);
5513 return niu_reset_tx_bmac(np
);
5516 static void niu_init_tx_xmac(struct niu
*np
, u64 min
, u64 max
)
5520 val
= nr64_mac(XMAC_MIN
);
5521 val
&= ~(XMAC_MIN_TX_MIN_PKT_SIZE
|
5522 XMAC_MIN_RX_MIN_PKT_SIZE
);
5523 val
|= (min
<< XMAC_MIN_RX_MIN_PKT_SIZE_SHFT
);
5524 val
|= (min
<< XMAC_MIN_TX_MIN_PKT_SIZE_SHFT
);
5525 nw64_mac(XMAC_MIN
, val
);
5527 nw64_mac(XMAC_MAX
, max
);
5529 nw64_mac(XTXMAC_STAT_MSK
, ~(u64
)0);
5531 val
= nr64_mac(XMAC_IPG
);
5532 if (np
->flags
& NIU_FLAGS_10G
) {
5533 val
&= ~XMAC_IPG_IPG_XGMII
;
5534 val
|= (IPG_12_15_XGMII
<< XMAC_IPG_IPG_XGMII_SHIFT
);
5536 val
&= ~XMAC_IPG_IPG_MII_GMII
;
5537 val
|= (IPG_12_MII_GMII
<< XMAC_IPG_IPG_MII_GMII_SHIFT
);
5539 nw64_mac(XMAC_IPG
, val
);
5541 val
= nr64_mac(XMAC_CONFIG
);
5542 val
&= ~(XMAC_CONFIG_ALWAYS_NO_CRC
|
5543 XMAC_CONFIG_STRETCH_MODE
|
5544 XMAC_CONFIG_VAR_MIN_IPG_EN
|
5545 XMAC_CONFIG_TX_ENABLE
);
5546 nw64_mac(XMAC_CONFIG
, val
);
5548 nw64_mac(TXMAC_FRM_CNT
, 0);
5549 nw64_mac(TXMAC_BYTE_CNT
, 0);
5552 static void niu_init_tx_bmac(struct niu
*np
, u64 min
, u64 max
)
5556 nw64_mac(BMAC_MIN_FRAME
, min
);
5557 nw64_mac(BMAC_MAX_FRAME
, max
);
5559 nw64_mac(BTXMAC_STATUS_MASK
, ~(u64
)0);
5560 nw64_mac(BMAC_CTRL_TYPE
, 0x8808);
5561 nw64_mac(BMAC_PREAMBLE_SIZE
, 7);
5563 val
= nr64_mac(BTXMAC_CONFIG
);
5564 val
&= ~(BTXMAC_CONFIG_FCS_DISABLE
|
5565 BTXMAC_CONFIG_ENABLE
);
5566 nw64_mac(BTXMAC_CONFIG
, val
);
5569 static void niu_init_tx_mac(struct niu
*np
)
5574 if (np
->dev
->mtu
> ETH_DATA_LEN
)
5579 /* The XMAC_MIN register only accepts values for TX min which
5580 * have the low 3 bits cleared.
5582 BUILD_BUG_ON(min
& 0x7);
5584 if (np
->flags
& NIU_FLAGS_XMAC
)
5585 niu_init_tx_xmac(np
, min
, max
);
5587 niu_init_tx_bmac(np
, min
, max
);
5590 static int niu_reset_rx_xmac(struct niu
*np
)
5594 nw64_mac(XRXMAC_SW_RST
,
5595 XRXMAC_SW_RST_REG_RS
| XRXMAC_SW_RST_SOFT_RST
);
5597 while (--limit
>= 0) {
5598 if (!(nr64_mac(XRXMAC_SW_RST
) & (XRXMAC_SW_RST_REG_RS
|
5599 XRXMAC_SW_RST_SOFT_RST
)))
5604 dev_err(np
->device
, PFX
"Port %u RX XMAC would not reset, "
5605 "XRXMAC_SW_RST[%llx]\n",
5607 (unsigned long long) nr64_mac(XRXMAC_SW_RST
));
5614 static int niu_reset_rx_bmac(struct niu
*np
)
5618 nw64_mac(BRXMAC_SW_RST
, BRXMAC_SW_RST_RESET
);
5620 while (--limit
>= 0) {
5621 if (!(nr64_mac(BRXMAC_SW_RST
) & BRXMAC_SW_RST_RESET
))
5626 dev_err(np
->device
, PFX
"Port %u RX BMAC would not reset, "
5627 "BRXMAC_SW_RST[%llx]\n",
5629 (unsigned long long) nr64_mac(BRXMAC_SW_RST
));
5636 static int niu_reset_rx_mac(struct niu
*np
)
5638 if (np
->flags
& NIU_FLAGS_XMAC
)
5639 return niu_reset_rx_xmac(np
);
5641 return niu_reset_rx_bmac(np
);
5644 static void niu_init_rx_xmac(struct niu
*np
)
5646 struct niu_parent
*parent
= np
->parent
;
5647 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
5648 int first_rdc_table
= tp
->first_table_num
;
5652 nw64_mac(XMAC_ADD_FILT0
, 0);
5653 nw64_mac(XMAC_ADD_FILT1
, 0);
5654 nw64_mac(XMAC_ADD_FILT2
, 0);
5655 nw64_mac(XMAC_ADD_FILT12_MASK
, 0);
5656 nw64_mac(XMAC_ADD_FILT00_MASK
, 0);
5657 for (i
= 0; i
< MAC_NUM_HASH
; i
++)
5658 nw64_mac(XMAC_HASH_TBL(i
), 0);
5659 nw64_mac(XRXMAC_STAT_MSK
, ~(u64
)0);
5660 niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
5661 niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
5663 val
= nr64_mac(XMAC_CONFIG
);
5664 val
&= ~(XMAC_CONFIG_RX_MAC_ENABLE
|
5665 XMAC_CONFIG_PROMISCUOUS
|
5666 XMAC_CONFIG_PROMISC_GROUP
|
5667 XMAC_CONFIG_ERR_CHK_DIS
|
5668 XMAC_CONFIG_RX_CRC_CHK_DIS
|
5669 XMAC_CONFIG_RESERVED_MULTICAST
|
5670 XMAC_CONFIG_RX_CODEV_CHK_DIS
|
5671 XMAC_CONFIG_ADDR_FILTER_EN
|
5672 XMAC_CONFIG_RCV_PAUSE_ENABLE
|
5673 XMAC_CONFIG_STRIP_CRC
|
5674 XMAC_CONFIG_PASS_FLOW_CTRL
|
5675 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN
);
5676 val
|= (XMAC_CONFIG_HASH_FILTER_EN
);
5677 nw64_mac(XMAC_CONFIG
, val
);
5679 nw64_mac(RXMAC_BT_CNT
, 0);
5680 nw64_mac(RXMAC_BC_FRM_CNT
, 0);
5681 nw64_mac(RXMAC_MC_FRM_CNT
, 0);
5682 nw64_mac(RXMAC_FRAG_CNT
, 0);
5683 nw64_mac(RXMAC_HIST_CNT1
, 0);
5684 nw64_mac(RXMAC_HIST_CNT2
, 0);
5685 nw64_mac(RXMAC_HIST_CNT3
, 0);
5686 nw64_mac(RXMAC_HIST_CNT4
, 0);
5687 nw64_mac(RXMAC_HIST_CNT5
, 0);
5688 nw64_mac(RXMAC_HIST_CNT6
, 0);
5689 nw64_mac(RXMAC_HIST_CNT7
, 0);
5690 nw64_mac(RXMAC_MPSZER_CNT
, 0);
5691 nw64_mac(RXMAC_CRC_ER_CNT
, 0);
5692 nw64_mac(RXMAC_CD_VIO_CNT
, 0);
5693 nw64_mac(LINK_FAULT_CNT
, 0);
5696 static void niu_init_rx_bmac(struct niu
*np
)
5698 struct niu_parent
*parent
= np
->parent
;
5699 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
5700 int first_rdc_table
= tp
->first_table_num
;
5704 nw64_mac(BMAC_ADD_FILT0
, 0);
5705 nw64_mac(BMAC_ADD_FILT1
, 0);
5706 nw64_mac(BMAC_ADD_FILT2
, 0);
5707 nw64_mac(BMAC_ADD_FILT12_MASK
, 0);
5708 nw64_mac(BMAC_ADD_FILT00_MASK
, 0);
5709 for (i
= 0; i
< MAC_NUM_HASH
; i
++)
5710 nw64_mac(BMAC_HASH_TBL(i
), 0);
5711 niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
5712 niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
5713 nw64_mac(BRXMAC_STATUS_MASK
, ~(u64
)0);
5715 val
= nr64_mac(BRXMAC_CONFIG
);
5716 val
&= ~(BRXMAC_CONFIG_ENABLE
|
5717 BRXMAC_CONFIG_STRIP_PAD
|
5718 BRXMAC_CONFIG_STRIP_FCS
|
5719 BRXMAC_CONFIG_PROMISC
|
5720 BRXMAC_CONFIG_PROMISC_GRP
|
5721 BRXMAC_CONFIG_ADDR_FILT_EN
|
5722 BRXMAC_CONFIG_DISCARD_DIS
);
5723 val
|= (BRXMAC_CONFIG_HASH_FILT_EN
);
5724 nw64_mac(BRXMAC_CONFIG
, val
);
5726 val
= nr64_mac(BMAC_ADDR_CMPEN
);
5727 val
|= BMAC_ADDR_CMPEN_EN0
;
5728 nw64_mac(BMAC_ADDR_CMPEN
, val
);
5731 static void niu_init_rx_mac(struct niu
*np
)
5733 niu_set_primary_mac(np
, np
->dev
->dev_addr
);
5735 if (np
->flags
& NIU_FLAGS_XMAC
)
5736 niu_init_rx_xmac(np
);
5738 niu_init_rx_bmac(np
);
5741 static void niu_enable_tx_xmac(struct niu
*np
, int on
)
5743 u64 val
= nr64_mac(XMAC_CONFIG
);
5746 val
|= XMAC_CONFIG_TX_ENABLE
;
5748 val
&= ~XMAC_CONFIG_TX_ENABLE
;
5749 nw64_mac(XMAC_CONFIG
, val
);
5752 static void niu_enable_tx_bmac(struct niu
*np
, int on
)
5754 u64 val
= nr64_mac(BTXMAC_CONFIG
);
5757 val
|= BTXMAC_CONFIG_ENABLE
;
5759 val
&= ~BTXMAC_CONFIG_ENABLE
;
5760 nw64_mac(BTXMAC_CONFIG
, val
);
5763 static void niu_enable_tx_mac(struct niu
*np
, int on
)
5765 if (np
->flags
& NIU_FLAGS_XMAC
)
5766 niu_enable_tx_xmac(np
, on
);
5768 niu_enable_tx_bmac(np
, on
);
5771 static void niu_enable_rx_xmac(struct niu
*np
, int on
)
5773 u64 val
= nr64_mac(XMAC_CONFIG
);
5775 val
&= ~(XMAC_CONFIG_HASH_FILTER_EN
|
5776 XMAC_CONFIG_PROMISCUOUS
);
5778 if (np
->flags
& NIU_FLAGS_MCAST
)
5779 val
|= XMAC_CONFIG_HASH_FILTER_EN
;
5780 if (np
->flags
& NIU_FLAGS_PROMISC
)
5781 val
|= XMAC_CONFIG_PROMISCUOUS
;
5784 val
|= XMAC_CONFIG_RX_MAC_ENABLE
;
5786 val
&= ~XMAC_CONFIG_RX_MAC_ENABLE
;
5787 nw64_mac(XMAC_CONFIG
, val
);
5790 static void niu_enable_rx_bmac(struct niu
*np
, int on
)
5792 u64 val
= nr64_mac(BRXMAC_CONFIG
);
5794 val
&= ~(BRXMAC_CONFIG_HASH_FILT_EN
|
5795 BRXMAC_CONFIG_PROMISC
);
5797 if (np
->flags
& NIU_FLAGS_MCAST
)
5798 val
|= BRXMAC_CONFIG_HASH_FILT_EN
;
5799 if (np
->flags
& NIU_FLAGS_PROMISC
)
5800 val
|= BRXMAC_CONFIG_PROMISC
;
5803 val
|= BRXMAC_CONFIG_ENABLE
;
5805 val
&= ~BRXMAC_CONFIG_ENABLE
;
5806 nw64_mac(BRXMAC_CONFIG
, val
);
5809 static void niu_enable_rx_mac(struct niu
*np
, int on
)
5811 if (np
->flags
& NIU_FLAGS_XMAC
)
5812 niu_enable_rx_xmac(np
, on
);
5814 niu_enable_rx_bmac(np
, on
);
5817 static int niu_init_mac(struct niu
*np
)
5822 err
= niu_init_pcs(np
);
5826 err
= niu_reset_tx_mac(np
);
5829 niu_init_tx_mac(np
);
5830 err
= niu_reset_rx_mac(np
);
5833 niu_init_rx_mac(np
);
5835 /* This looks hookey but the RX MAC reset we just did will
5836 * undo some of the state we setup in niu_init_tx_mac() so we
5837 * have to call it again. In particular, the RX MAC reset will
5838 * set the XMAC_MAX register back to it's default value.
5840 niu_init_tx_mac(np
);
5841 niu_enable_tx_mac(np
, 1);
5843 niu_enable_rx_mac(np
, 1);
5848 static void niu_stop_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
5850 (void) niu_tx_channel_stop(np
, rp
->tx_channel
);
5853 static void niu_stop_tx_channels(struct niu
*np
)
5857 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5858 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5860 niu_stop_one_tx_channel(np
, rp
);
5864 static void niu_reset_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
5866 (void) niu_tx_channel_reset(np
, rp
->tx_channel
);
5869 static void niu_reset_tx_channels(struct niu
*np
)
5873 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5874 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5876 niu_reset_one_tx_channel(np
, rp
);
5880 static void niu_stop_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
5882 (void) niu_enable_rx_channel(np
, rp
->rx_channel
, 0);
5885 static void niu_stop_rx_channels(struct niu
*np
)
5889 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5890 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5892 niu_stop_one_rx_channel(np
, rp
);
5896 static void niu_reset_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
5898 int channel
= rp
->rx_channel
;
5900 (void) niu_rx_channel_reset(np
, channel
);
5901 nw64(RX_DMA_ENT_MSK(channel
), RX_DMA_ENT_MSK_ALL
);
5902 nw64(RX_DMA_CTL_STAT(channel
), 0);
5903 (void) niu_enable_rx_channel(np
, channel
, 0);
5906 static void niu_reset_rx_channels(struct niu
*np
)
5910 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5911 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5913 niu_reset_one_rx_channel(np
, rp
);
5917 static void niu_disable_ipp(struct niu
*np
)
5922 rd
= nr64_ipp(IPP_DFIFO_RD_PTR
);
5923 wr
= nr64_ipp(IPP_DFIFO_WR_PTR
);
5925 while (--limit
>= 0 && (rd
!= wr
)) {
5926 rd
= nr64_ipp(IPP_DFIFO_RD_PTR
);
5927 wr
= nr64_ipp(IPP_DFIFO_WR_PTR
);
5930 (rd
!= 0 && wr
!= 1)) {
5931 dev_err(np
->device
, PFX
"%s: IPP would not quiesce, "
5932 "rd_ptr[%llx] wr_ptr[%llx]\n",
5934 (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR
),
5935 (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR
));
5938 val
= nr64_ipp(IPP_CFIG
);
5939 val
&= ~(IPP_CFIG_IPP_ENABLE
|
5940 IPP_CFIG_DFIFO_ECC_EN
|
5941 IPP_CFIG_DROP_BAD_CRC
|
5943 nw64_ipp(IPP_CFIG
, val
);
5945 (void) niu_ipp_reset(np
);
5948 static int niu_init_hw(struct niu
*np
)
5952 niudbg(IFUP
, "%s: Initialize TXC\n", np
->dev
->name
);
5953 niu_txc_enable_port(np
, 1);
5954 niu_txc_port_dma_enable(np
, 1);
5955 niu_txc_set_imask(np
, 0);
5957 niudbg(IFUP
, "%s: Initialize TX channels\n", np
->dev
->name
);
5958 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5959 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5961 err
= niu_init_one_tx_channel(np
, rp
);
5966 niudbg(IFUP
, "%s: Initialize RX channels\n", np
->dev
->name
);
5967 err
= niu_init_rx_channels(np
);
5969 goto out_uninit_tx_channels
;
5971 niudbg(IFUP
, "%s: Initialize classifier\n", np
->dev
->name
);
5972 err
= niu_init_classifier_hw(np
);
5974 goto out_uninit_rx_channels
;
5976 niudbg(IFUP
, "%s: Initialize ZCP\n", np
->dev
->name
);
5977 err
= niu_init_zcp(np
);
5979 goto out_uninit_rx_channels
;
5981 niudbg(IFUP
, "%s: Initialize IPP\n", np
->dev
->name
);
5982 err
= niu_init_ipp(np
);
5984 goto out_uninit_rx_channels
;
5986 niudbg(IFUP
, "%s: Initialize MAC\n", np
->dev
->name
);
5987 err
= niu_init_mac(np
);
5989 goto out_uninit_ipp
;
5994 niudbg(IFUP
, "%s: Uninit IPP\n", np
->dev
->name
);
5995 niu_disable_ipp(np
);
5997 out_uninit_rx_channels
:
5998 niudbg(IFUP
, "%s: Uninit RX channels\n", np
->dev
->name
);
5999 niu_stop_rx_channels(np
);
6000 niu_reset_rx_channels(np
);
6002 out_uninit_tx_channels
:
6003 niudbg(IFUP
, "%s: Uninit TX channels\n", np
->dev
->name
);
6004 niu_stop_tx_channels(np
);
6005 niu_reset_tx_channels(np
);
6010 static void niu_stop_hw(struct niu
*np
)
6012 niudbg(IFDOWN
, "%s: Disable interrupts\n", np
->dev
->name
);
6013 niu_enable_interrupts(np
, 0);
6015 niudbg(IFDOWN
, "%s: Disable RX MAC\n", np
->dev
->name
);
6016 niu_enable_rx_mac(np
, 0);
6018 niudbg(IFDOWN
, "%s: Disable IPP\n", np
->dev
->name
);
6019 niu_disable_ipp(np
);
6021 niudbg(IFDOWN
, "%s: Stop TX channels\n", np
->dev
->name
);
6022 niu_stop_tx_channels(np
);
6024 niudbg(IFDOWN
, "%s: Stop RX channels\n", np
->dev
->name
);
6025 niu_stop_rx_channels(np
);
6027 niudbg(IFDOWN
, "%s: Reset TX channels\n", np
->dev
->name
);
6028 niu_reset_tx_channels(np
);
6030 niudbg(IFDOWN
, "%s: Reset RX channels\n", np
->dev
->name
);
6031 niu_reset_rx_channels(np
);
6034 static void niu_set_irq_name(struct niu
*np
)
6036 int port
= np
->port
;
6039 sprintf(np
->irq_name
[0], "%s:MAC", np
->dev
->name
);
6042 sprintf(np
->irq_name
[1], "%s:MIF", np
->dev
->name
);
6043 sprintf(np
->irq_name
[2], "%s:SYSERR", np
->dev
->name
);
6047 for (i
= 0; i
< np
->num_ldg
- j
; i
++) {
6048 if (i
< np
->num_rx_rings
)
6049 sprintf(np
->irq_name
[i
+j
], "%s-rx-%d",
6051 else if (i
< np
->num_tx_rings
+ np
->num_rx_rings
)
6052 sprintf(np
->irq_name
[i
+j
], "%s-tx-%d", np
->dev
->name
,
6053 i
- np
->num_rx_rings
);
6057 static int niu_request_irq(struct niu
*np
)
6061 niu_set_irq_name(np
);
6064 for (i
= 0; i
< np
->num_ldg
; i
++) {
6065 struct niu_ldg
*lp
= &np
->ldg
[i
];
6067 err
= request_irq(lp
->irq
, niu_interrupt
,
6068 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
,
6069 np
->irq_name
[i
], lp
);
6078 for (j
= 0; j
< i
; j
++) {
6079 struct niu_ldg
*lp
= &np
->ldg
[j
];
6081 free_irq(lp
->irq
, lp
);
6086 static void niu_free_irq(struct niu
*np
)
6090 for (i
= 0; i
< np
->num_ldg
; i
++) {
6091 struct niu_ldg
*lp
= &np
->ldg
[i
];
6093 free_irq(lp
->irq
, lp
);
6097 static void niu_enable_napi(struct niu
*np
)
6101 for (i
= 0; i
< np
->num_ldg
; i
++)
6102 napi_enable(&np
->ldg
[i
].napi
);
6105 static void niu_disable_napi(struct niu
*np
)
6109 for (i
= 0; i
< np
->num_ldg
; i
++)
6110 napi_disable(&np
->ldg
[i
].napi
);
6113 static int niu_open(struct net_device
*dev
)
6115 struct niu
*np
= netdev_priv(dev
);
6118 netif_carrier_off(dev
);
6120 err
= niu_alloc_channels(np
);
6124 err
= niu_enable_interrupts(np
, 0);
6126 goto out_free_channels
;
6128 err
= niu_request_irq(np
);
6130 goto out_free_channels
;
6132 niu_enable_napi(np
);
6134 spin_lock_irq(&np
->lock
);
6136 err
= niu_init_hw(np
);
6138 init_timer(&np
->timer
);
6139 np
->timer
.expires
= jiffies
+ HZ
;
6140 np
->timer
.data
= (unsigned long) np
;
6141 np
->timer
.function
= niu_timer
;
6143 err
= niu_enable_interrupts(np
, 1);
6148 spin_unlock_irq(&np
->lock
);
6151 niu_disable_napi(np
);
6155 netif_tx_start_all_queues(dev
);
6157 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
6158 netif_carrier_on(dev
);
6160 add_timer(&np
->timer
);
6168 niu_free_channels(np
);
6174 static void niu_full_shutdown(struct niu
*np
, struct net_device
*dev
)
6176 cancel_work_sync(&np
->reset_task
);
6178 niu_disable_napi(np
);
6179 netif_tx_stop_all_queues(dev
);
6181 del_timer_sync(&np
->timer
);
6183 spin_lock_irq(&np
->lock
);
6187 spin_unlock_irq(&np
->lock
);
6190 static int niu_close(struct net_device
*dev
)
6192 struct niu
*np
= netdev_priv(dev
);
6194 niu_full_shutdown(np
, dev
);
6198 niu_free_channels(np
);
6200 niu_handle_led(np
, 0);
6205 static void niu_sync_xmac_stats(struct niu
*np
)
6207 struct niu_xmac_stats
*mp
= &np
->mac_stats
.xmac
;
6209 mp
->tx_frames
+= nr64_mac(TXMAC_FRM_CNT
);
6210 mp
->tx_bytes
+= nr64_mac(TXMAC_BYTE_CNT
);
6212 mp
->rx_link_faults
+= nr64_mac(LINK_FAULT_CNT
);
6213 mp
->rx_align_errors
+= nr64_mac(RXMAC_ALIGN_ERR_CNT
);
6214 mp
->rx_frags
+= nr64_mac(RXMAC_FRAG_CNT
);
6215 mp
->rx_mcasts
+= nr64_mac(RXMAC_MC_FRM_CNT
);
6216 mp
->rx_bcasts
+= nr64_mac(RXMAC_BC_FRM_CNT
);
6217 mp
->rx_hist_cnt1
+= nr64_mac(RXMAC_HIST_CNT1
);
6218 mp
->rx_hist_cnt2
+= nr64_mac(RXMAC_HIST_CNT2
);
6219 mp
->rx_hist_cnt3
+= nr64_mac(RXMAC_HIST_CNT3
);
6220 mp
->rx_hist_cnt4
+= nr64_mac(RXMAC_HIST_CNT4
);
6221 mp
->rx_hist_cnt5
+= nr64_mac(RXMAC_HIST_CNT5
);
6222 mp
->rx_hist_cnt6
+= nr64_mac(RXMAC_HIST_CNT6
);
6223 mp
->rx_hist_cnt7
+= nr64_mac(RXMAC_HIST_CNT7
);
6224 mp
->rx_octets
+= nr64_mac(RXMAC_BT_CNT
);
6225 mp
->rx_code_violations
+= nr64_mac(RXMAC_CD_VIO_CNT
);
6226 mp
->rx_len_errors
+= nr64_mac(RXMAC_MPSZER_CNT
);
6227 mp
->rx_crc_errors
+= nr64_mac(RXMAC_CRC_ER_CNT
);
6230 static void niu_sync_bmac_stats(struct niu
*np
)
6232 struct niu_bmac_stats
*mp
= &np
->mac_stats
.bmac
;
6234 mp
->tx_bytes
+= nr64_mac(BTXMAC_BYTE_CNT
);
6235 mp
->tx_frames
+= nr64_mac(BTXMAC_FRM_CNT
);
6237 mp
->rx_frames
+= nr64_mac(BRXMAC_FRAME_CNT
);
6238 mp
->rx_align_errors
+= nr64_mac(BRXMAC_ALIGN_ERR_CNT
);
6239 mp
->rx_crc_errors
+= nr64_mac(BRXMAC_ALIGN_ERR_CNT
);
6240 mp
->rx_len_errors
+= nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT
);
6243 static void niu_sync_mac_stats(struct niu
*np
)
6245 if (np
->flags
& NIU_FLAGS_XMAC
)
6246 niu_sync_xmac_stats(np
);
6248 niu_sync_bmac_stats(np
);
6251 static void niu_get_rx_stats(struct niu
*np
)
6253 unsigned long pkts
, dropped
, errors
, bytes
;
6256 pkts
= dropped
= errors
= bytes
= 0;
6257 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
6258 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
6260 niu_sync_rx_discard_stats(np
, rp
, 0);
6262 pkts
+= rp
->rx_packets
;
6263 bytes
+= rp
->rx_bytes
;
6264 dropped
+= rp
->rx_dropped
;
6265 errors
+= rp
->rx_errors
;
6267 np
->dev
->stats
.rx_packets
= pkts
;
6268 np
->dev
->stats
.rx_bytes
= bytes
;
6269 np
->dev
->stats
.rx_dropped
= dropped
;
6270 np
->dev
->stats
.rx_errors
= errors
;
6273 static void niu_get_tx_stats(struct niu
*np
)
6275 unsigned long pkts
, errors
, bytes
;
6278 pkts
= errors
= bytes
= 0;
6279 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
6280 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
6282 pkts
+= rp
->tx_packets
;
6283 bytes
+= rp
->tx_bytes
;
6284 errors
+= rp
->tx_errors
;
6286 np
->dev
->stats
.tx_packets
= pkts
;
6287 np
->dev
->stats
.tx_bytes
= bytes
;
6288 np
->dev
->stats
.tx_errors
= errors
;
6291 static struct net_device_stats
*niu_get_stats(struct net_device
*dev
)
6293 struct niu
*np
= netdev_priv(dev
);
6295 niu_get_rx_stats(np
);
6296 niu_get_tx_stats(np
);
6301 static void niu_load_hash_xmac(struct niu
*np
, u16
*hash
)
6305 for (i
= 0; i
< 16; i
++)
6306 nw64_mac(XMAC_HASH_TBL(i
), hash
[i
]);
6309 static void niu_load_hash_bmac(struct niu
*np
, u16
*hash
)
6313 for (i
= 0; i
< 16; i
++)
6314 nw64_mac(BMAC_HASH_TBL(i
), hash
[i
]);
6317 static void niu_load_hash(struct niu
*np
, u16
*hash
)
6319 if (np
->flags
& NIU_FLAGS_XMAC
)
6320 niu_load_hash_xmac(np
, hash
);
6322 niu_load_hash_bmac(np
, hash
);
6325 static void niu_set_rx_mode(struct net_device
*dev
)
6327 struct niu
*np
= netdev_priv(dev
);
6328 int i
, alt_cnt
, err
;
6329 struct dev_addr_list
*addr
;
6330 unsigned long flags
;
6331 u16 hash
[16] = { 0, };
6333 spin_lock_irqsave(&np
->lock
, flags
);
6334 niu_enable_rx_mac(np
, 0);
6336 np
->flags
&= ~(NIU_FLAGS_MCAST
| NIU_FLAGS_PROMISC
);
6337 if (dev
->flags
& IFF_PROMISC
)
6338 np
->flags
|= NIU_FLAGS_PROMISC
;
6339 if ((dev
->flags
& IFF_ALLMULTI
) || (dev
->mc_count
> 0))
6340 np
->flags
|= NIU_FLAGS_MCAST
;
6342 alt_cnt
= dev
->uc_count
;
6343 if (alt_cnt
> niu_num_alt_addr(np
)) {
6345 np
->flags
|= NIU_FLAGS_PROMISC
;
6351 for (addr
= dev
->uc_list
; addr
; addr
= addr
->next
) {
6352 err
= niu_set_alt_mac(np
, index
,
6355 printk(KERN_WARNING PFX
"%s: Error %d "
6356 "adding alt mac %d\n",
6357 dev
->name
, err
, index
);
6358 err
= niu_enable_alt_mac(np
, index
, 1);
6360 printk(KERN_WARNING PFX
"%s: Error %d "
6361 "enabling alt mac %d\n",
6362 dev
->name
, err
, index
);
6368 if (np
->flags
& NIU_FLAGS_XMAC
)
6372 for (i
= alt_start
; i
< niu_num_alt_addr(np
); i
++) {
6373 err
= niu_enable_alt_mac(np
, i
, 0);
6375 printk(KERN_WARNING PFX
"%s: Error %d "
6376 "disabling alt mac %d\n",
6380 if (dev
->flags
& IFF_ALLMULTI
) {
6381 for (i
= 0; i
< 16; i
++)
6383 } else if (dev
->mc_count
> 0) {
6384 for (addr
= dev
->mc_list
; addr
; addr
= addr
->next
) {
6385 u32 crc
= ether_crc_le(ETH_ALEN
, addr
->da_addr
);
6388 hash
[crc
>> 4] |= (1 << (15 - (crc
& 0xf)));
6392 if (np
->flags
& NIU_FLAGS_MCAST
)
6393 niu_load_hash(np
, hash
);
6395 niu_enable_rx_mac(np
, 1);
6396 spin_unlock_irqrestore(&np
->lock
, flags
);
6399 static int niu_set_mac_addr(struct net_device
*dev
, void *p
)
6401 struct niu
*np
= netdev_priv(dev
);
6402 struct sockaddr
*addr
= p
;
6403 unsigned long flags
;
6405 if (!is_valid_ether_addr(addr
->sa_data
))
6408 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
6410 if (!netif_running(dev
))
6413 spin_lock_irqsave(&np
->lock
, flags
);
6414 niu_enable_rx_mac(np
, 0);
6415 niu_set_primary_mac(np
, dev
->dev_addr
);
6416 niu_enable_rx_mac(np
, 1);
6417 spin_unlock_irqrestore(&np
->lock
, flags
);
6422 static int niu_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
6427 static void niu_netif_stop(struct niu
*np
)
6429 np
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
6431 niu_disable_napi(np
);
6433 netif_tx_disable(np
->dev
);
6436 static void niu_netif_start(struct niu
*np
)
6438 /* NOTE: unconditional netif_wake_queue is only appropriate
6439 * so long as all callers are assured to have free tx slots
6440 * (such as after niu_init_hw).
6442 netif_tx_wake_all_queues(np
->dev
);
6444 niu_enable_napi(np
);
6446 niu_enable_interrupts(np
, 1);
6449 static void niu_reset_buffers(struct niu
*np
)
6454 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
6455 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
6457 for (j
= 0, k
= 0; j
< MAX_RBR_RING_SIZE
; j
++) {
6460 page
= rp
->rxhash
[j
];
6463 (struct page
*) page
->mapping
;
6464 u64 base
= page
->index
;
6465 base
= base
>> RBR_DESCR_ADDR_SHIFT
;
6466 rp
->rbr
[k
++] = cpu_to_le32(base
);
6470 for (; k
< MAX_RBR_RING_SIZE
; k
++) {
6471 err
= niu_rbr_add_page(np
, rp
, GFP_ATOMIC
, k
);
6476 rp
->rbr_index
= rp
->rbr_table_size
- 1;
6478 rp
->rbr_pending
= 0;
6479 rp
->rbr_refill_pending
= 0;
6483 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
6484 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
6486 for (j
= 0; j
< MAX_TX_RING_SIZE
; j
++) {
6487 if (rp
->tx_buffs
[j
].skb
)
6488 (void) release_tx_packet(np
, rp
, j
);
6491 rp
->pending
= MAX_TX_RING_SIZE
;
6499 static void niu_reset_task(struct work_struct
*work
)
6501 struct niu
*np
= container_of(work
, struct niu
, reset_task
);
6502 unsigned long flags
;
6505 spin_lock_irqsave(&np
->lock
, flags
);
6506 if (!netif_running(np
->dev
)) {
6507 spin_unlock_irqrestore(&np
->lock
, flags
);
6511 spin_unlock_irqrestore(&np
->lock
, flags
);
6513 del_timer_sync(&np
->timer
);
6517 spin_lock_irqsave(&np
->lock
, flags
);
6521 spin_unlock_irqrestore(&np
->lock
, flags
);
6523 niu_reset_buffers(np
);
6525 spin_lock_irqsave(&np
->lock
, flags
);
6527 err
= niu_init_hw(np
);
6529 np
->timer
.expires
= jiffies
+ HZ
;
6530 add_timer(&np
->timer
);
6531 niu_netif_start(np
);
6534 spin_unlock_irqrestore(&np
->lock
, flags
);
6537 static void niu_tx_timeout(struct net_device
*dev
)
6539 struct niu
*np
= netdev_priv(dev
);
6541 dev_err(np
->device
, PFX
"%s: Transmit timed out, resetting\n",
6544 schedule_work(&np
->reset_task
);
6547 static void niu_set_txd(struct tx_ring_info
*rp
, int index
,
6548 u64 mapping
, u64 len
, u64 mark
,
6551 __le64
*desc
= &rp
->descr
[index
];
6553 *desc
= cpu_to_le64(mark
|
6554 (n_frags
<< TX_DESC_NUM_PTR_SHIFT
) |
6555 (len
<< TX_DESC_TR_LEN_SHIFT
) |
6556 (mapping
& TX_DESC_SAD
));
6559 static u64
niu_compute_tx_flags(struct sk_buff
*skb
, struct ethhdr
*ehdr
,
6560 u64 pad_bytes
, u64 len
)
6562 u16 eth_proto
, eth_proto_inner
;
6563 u64 csum_bits
, l3off
, ihl
, ret
;
6567 eth_proto
= be16_to_cpu(ehdr
->h_proto
);
6568 eth_proto_inner
= eth_proto
;
6569 if (eth_proto
== ETH_P_8021Q
) {
6570 struct vlan_ethhdr
*vp
= (struct vlan_ethhdr
*) ehdr
;
6571 __be16 val
= vp
->h_vlan_encapsulated_proto
;
6573 eth_proto_inner
= be16_to_cpu(val
);
6577 switch (skb
->protocol
) {
6578 case cpu_to_be16(ETH_P_IP
):
6579 ip_proto
= ip_hdr(skb
)->protocol
;
6580 ihl
= ip_hdr(skb
)->ihl
;
6582 case cpu_to_be16(ETH_P_IPV6
):
6583 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
6592 csum_bits
= TXHDR_CSUM_NONE
;
6593 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6596 csum_bits
= (ip_proto
== IPPROTO_TCP
?
6598 (ip_proto
== IPPROTO_UDP
?
6599 TXHDR_CSUM_UDP
: TXHDR_CSUM_SCTP
));
6601 start
= skb_transport_offset(skb
) -
6602 (pad_bytes
+ sizeof(struct tx_pkt_hdr
));
6603 stuff
= start
+ skb
->csum_offset
;
6605 csum_bits
|= (start
/ 2) << TXHDR_L4START_SHIFT
;
6606 csum_bits
|= (stuff
/ 2) << TXHDR_L4STUFF_SHIFT
;
6609 l3off
= skb_network_offset(skb
) -
6610 (pad_bytes
+ sizeof(struct tx_pkt_hdr
));
6612 ret
= (((pad_bytes
/ 2) << TXHDR_PAD_SHIFT
) |
6613 (len
<< TXHDR_LEN_SHIFT
) |
6614 ((l3off
/ 2) << TXHDR_L3START_SHIFT
) |
6615 (ihl
<< TXHDR_IHL_SHIFT
) |
6616 ((eth_proto_inner
< 1536) ? TXHDR_LLC
: 0) |
6617 ((eth_proto
== ETH_P_8021Q
) ? TXHDR_VLAN
: 0) |
6618 (ipv6
? TXHDR_IP_VER
: 0) |
6624 static int niu_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
6626 struct niu
*np
= netdev_priv(dev
);
6627 unsigned long align
, headroom
;
6628 struct netdev_queue
*txq
;
6629 struct tx_ring_info
*rp
;
6630 struct tx_pkt_hdr
*tp
;
6631 unsigned int len
, nfg
;
6632 struct ethhdr
*ehdr
;
6636 i
= skb_get_queue_mapping(skb
);
6637 rp
= &np
->tx_rings
[i
];
6638 txq
= netdev_get_tx_queue(dev
, i
);
6640 if (niu_tx_avail(rp
) <= (skb_shinfo(skb
)->nr_frags
+ 1)) {
6641 netif_tx_stop_queue(txq
);
6642 dev_err(np
->device
, PFX
"%s: BUG! Tx ring full when "
6643 "queue awake!\n", dev
->name
);
6645 return NETDEV_TX_BUSY
;
6648 if (skb
->len
< ETH_ZLEN
) {
6649 unsigned int pad_bytes
= ETH_ZLEN
- skb
->len
;
6651 if (skb_pad(skb
, pad_bytes
))
6653 skb_put(skb
, pad_bytes
);
6656 len
= sizeof(struct tx_pkt_hdr
) + 15;
6657 if (skb_headroom(skb
) < len
) {
6658 struct sk_buff
*skb_new
;
6660 skb_new
= skb_realloc_headroom(skb
, len
);
6670 align
= ((unsigned long) skb
->data
& (16 - 1));
6671 headroom
= align
+ sizeof(struct tx_pkt_hdr
);
6673 ehdr
= (struct ethhdr
*) skb
->data
;
6674 tp
= (struct tx_pkt_hdr
*) skb_push(skb
, headroom
);
6676 len
= skb
->len
- sizeof(struct tx_pkt_hdr
);
6677 tp
->flags
= cpu_to_le64(niu_compute_tx_flags(skb
, ehdr
, align
, len
));
6680 len
= skb_headlen(skb
);
6681 mapping
= np
->ops
->map_single(np
->device
, skb
->data
,
6682 len
, DMA_TO_DEVICE
);
6686 rp
->tx_buffs
[prod
].skb
= skb
;
6687 rp
->tx_buffs
[prod
].mapping
= mapping
;
6690 if (++rp
->mark_counter
== rp
->mark_freq
) {
6691 rp
->mark_counter
= 0;
6692 mrk
|= TX_DESC_MARK
;
6697 nfg
= skb_shinfo(skb
)->nr_frags
;
6699 tlen
-= MAX_TX_DESC_LEN
;
6704 unsigned int this_len
= len
;
6706 if (this_len
> MAX_TX_DESC_LEN
)
6707 this_len
= MAX_TX_DESC_LEN
;
6709 niu_set_txd(rp
, prod
, mapping
, this_len
, mrk
, nfg
);
6712 prod
= NEXT_TX(rp
, prod
);
6713 mapping
+= this_len
;
6717 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
6718 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
6721 mapping
= np
->ops
->map_page(np
->device
, frag
->page
,
6722 frag
->page_offset
, len
,
6725 rp
->tx_buffs
[prod
].skb
= NULL
;
6726 rp
->tx_buffs
[prod
].mapping
= mapping
;
6728 niu_set_txd(rp
, prod
, mapping
, len
, 0, 0);
6730 prod
= NEXT_TX(rp
, prod
);
6733 if (prod
< rp
->prod
)
6734 rp
->wrap_bit
^= TX_RING_KICK_WRAP
;
6737 nw64(TX_RING_KICK(rp
->tx_channel
), rp
->wrap_bit
| (prod
<< 3));
6739 if (unlikely(niu_tx_avail(rp
) <= (MAX_SKB_FRAGS
+ 1))) {
6740 netif_tx_stop_queue(txq
);
6741 if (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
))
6742 netif_tx_wake_queue(txq
);
6745 dev
->trans_start
= jiffies
;
6748 return NETDEV_TX_OK
;
6756 static int niu_change_mtu(struct net_device
*dev
, int new_mtu
)
6758 struct niu
*np
= netdev_priv(dev
);
6759 int err
, orig_jumbo
, new_jumbo
;
6761 if (new_mtu
< 68 || new_mtu
> NIU_MAX_MTU
)
6764 orig_jumbo
= (dev
->mtu
> ETH_DATA_LEN
);
6765 new_jumbo
= (new_mtu
> ETH_DATA_LEN
);
6769 if (!netif_running(dev
) ||
6770 (orig_jumbo
== new_jumbo
))
6773 niu_full_shutdown(np
, dev
);
6775 niu_free_channels(np
);
6777 niu_enable_napi(np
);
6779 err
= niu_alloc_channels(np
);
6783 spin_lock_irq(&np
->lock
);
6785 err
= niu_init_hw(np
);
6787 init_timer(&np
->timer
);
6788 np
->timer
.expires
= jiffies
+ HZ
;
6789 np
->timer
.data
= (unsigned long) np
;
6790 np
->timer
.function
= niu_timer
;
6792 err
= niu_enable_interrupts(np
, 1);
6797 spin_unlock_irq(&np
->lock
);
6800 netif_tx_start_all_queues(dev
);
6801 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
6802 netif_carrier_on(dev
);
6804 add_timer(&np
->timer
);
6810 static void niu_get_drvinfo(struct net_device
*dev
,
6811 struct ethtool_drvinfo
*info
)
6813 struct niu
*np
= netdev_priv(dev
);
6814 struct niu_vpd
*vpd
= &np
->vpd
;
6816 strcpy(info
->driver
, DRV_MODULE_NAME
);
6817 strcpy(info
->version
, DRV_MODULE_VERSION
);
6818 sprintf(info
->fw_version
, "%d.%d",
6819 vpd
->fcode_major
, vpd
->fcode_minor
);
6820 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
)
6821 strcpy(info
->bus_info
, pci_name(np
->pdev
));
6824 static int niu_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6826 struct niu
*np
= netdev_priv(dev
);
6827 struct niu_link_config
*lp
;
6829 lp
= &np
->link_config
;
6831 memset(cmd
, 0, sizeof(*cmd
));
6832 cmd
->phy_address
= np
->phy_addr
;
6833 cmd
->supported
= lp
->supported
;
6834 cmd
->advertising
= lp
->active_advertising
;
6835 cmd
->autoneg
= lp
->active_autoneg
;
6836 cmd
->speed
= lp
->active_speed
;
6837 cmd
->duplex
= lp
->active_duplex
;
6838 cmd
->port
= (np
->flags
& NIU_FLAGS_FIBER
) ? PORT_FIBRE
: PORT_TP
;
6839 cmd
->transceiver
= (np
->flags
& NIU_FLAGS_XCVR_SERDES
) ?
6840 XCVR_EXTERNAL
: XCVR_INTERNAL
;
6845 static int niu_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6847 struct niu
*np
= netdev_priv(dev
);
6848 struct niu_link_config
*lp
= &np
->link_config
;
6850 lp
->advertising
= cmd
->advertising
;
6851 lp
->speed
= cmd
->speed
;
6852 lp
->duplex
= cmd
->duplex
;
6853 lp
->autoneg
= cmd
->autoneg
;
6854 return niu_init_link(np
);
6857 static u32
niu_get_msglevel(struct net_device
*dev
)
6859 struct niu
*np
= netdev_priv(dev
);
6860 return np
->msg_enable
;
6863 static void niu_set_msglevel(struct net_device
*dev
, u32 value
)
6865 struct niu
*np
= netdev_priv(dev
);
6866 np
->msg_enable
= value
;
6869 static int niu_nway_reset(struct net_device
*dev
)
6871 struct niu
*np
= netdev_priv(dev
);
6873 if (np
->link_config
.autoneg
)
6874 return niu_init_link(np
);
6879 static int niu_get_eeprom_len(struct net_device
*dev
)
6881 struct niu
*np
= netdev_priv(dev
);
6883 return np
->eeprom_len
;
6886 static int niu_get_eeprom(struct net_device
*dev
,
6887 struct ethtool_eeprom
*eeprom
, u8
*data
)
6889 struct niu
*np
= netdev_priv(dev
);
6890 u32 offset
, len
, val
;
6892 offset
= eeprom
->offset
;
6895 if (offset
+ len
< offset
)
6897 if (offset
>= np
->eeprom_len
)
6899 if (offset
+ len
> np
->eeprom_len
)
6900 len
= eeprom
->len
= np
->eeprom_len
- offset
;
6903 u32 b_offset
, b_count
;
6905 b_offset
= offset
& 3;
6906 b_count
= 4 - b_offset
;
6910 val
= nr64(ESPC_NCR((offset
- b_offset
) / 4));
6911 memcpy(data
, ((char *)&val
) + b_offset
, b_count
);
6917 val
= nr64(ESPC_NCR(offset
/ 4));
6918 memcpy(data
, &val
, 4);
6924 val
= nr64(ESPC_NCR(offset
/ 4));
6925 memcpy(data
, &val
, len
);
6930 static void niu_ethflow_to_l3proto(int flow_type
, u8
*pid
)
6932 switch (flow_type
) {
6943 *pid
= IPPROTO_SCTP
;
6959 static int niu_class_to_ethflow(u64
class, int *flow_type
)
6962 case CLASS_CODE_TCP_IPV4
:
6963 *flow_type
= TCP_V4_FLOW
;
6965 case CLASS_CODE_UDP_IPV4
:
6966 *flow_type
= UDP_V4_FLOW
;
6968 case CLASS_CODE_AH_ESP_IPV4
:
6969 *flow_type
= AH_V4_FLOW
;
6971 case CLASS_CODE_SCTP_IPV4
:
6972 *flow_type
= SCTP_V4_FLOW
;
6974 case CLASS_CODE_TCP_IPV6
:
6975 *flow_type
= TCP_V6_FLOW
;
6977 case CLASS_CODE_UDP_IPV6
:
6978 *flow_type
= UDP_V6_FLOW
;
6980 case CLASS_CODE_AH_ESP_IPV6
:
6981 *flow_type
= AH_V6_FLOW
;
6983 case CLASS_CODE_SCTP_IPV6
:
6984 *flow_type
= SCTP_V6_FLOW
;
6986 case CLASS_CODE_USER_PROG1
:
6987 case CLASS_CODE_USER_PROG2
:
6988 case CLASS_CODE_USER_PROG3
:
6989 case CLASS_CODE_USER_PROG4
:
6990 *flow_type
= IP_USER_FLOW
;
6999 static int niu_ethflow_to_class(int flow_type
, u64
*class)
7001 switch (flow_type
) {
7003 *class = CLASS_CODE_TCP_IPV4
;
7006 *class = CLASS_CODE_UDP_IPV4
;
7010 *class = CLASS_CODE_AH_ESP_IPV4
;
7013 *class = CLASS_CODE_SCTP_IPV4
;
7016 *class = CLASS_CODE_TCP_IPV6
;
7019 *class = CLASS_CODE_UDP_IPV6
;
7023 *class = CLASS_CODE_AH_ESP_IPV6
;
7026 *class = CLASS_CODE_SCTP_IPV6
;
7035 static u64
niu_flowkey_to_ethflow(u64 flow_key
)
7039 if (flow_key
& FLOW_KEY_L2DA
)
7040 ethflow
|= RXH_L2DA
;
7041 if (flow_key
& FLOW_KEY_VLAN
)
7042 ethflow
|= RXH_VLAN
;
7043 if (flow_key
& FLOW_KEY_IPSA
)
7044 ethflow
|= RXH_IP_SRC
;
7045 if (flow_key
& FLOW_KEY_IPDA
)
7046 ethflow
|= RXH_IP_DST
;
7047 if (flow_key
& FLOW_KEY_PROTO
)
7048 ethflow
|= RXH_L3_PROTO
;
7049 if (flow_key
& (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_0_SHIFT
))
7050 ethflow
|= RXH_L4_B_0_1
;
7051 if (flow_key
& (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_1_SHIFT
))
7052 ethflow
|= RXH_L4_B_2_3
;
7058 static int niu_ethflow_to_flowkey(u64 ethflow
, u64
*flow_key
)
7062 if (ethflow
& RXH_L2DA
)
7063 key
|= FLOW_KEY_L2DA
;
7064 if (ethflow
& RXH_VLAN
)
7065 key
|= FLOW_KEY_VLAN
;
7066 if (ethflow
& RXH_IP_SRC
)
7067 key
|= FLOW_KEY_IPSA
;
7068 if (ethflow
& RXH_IP_DST
)
7069 key
|= FLOW_KEY_IPDA
;
7070 if (ethflow
& RXH_L3_PROTO
)
7071 key
|= FLOW_KEY_PROTO
;
7072 if (ethflow
& RXH_L4_B_0_1
)
7073 key
|= (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_0_SHIFT
);
7074 if (ethflow
& RXH_L4_B_2_3
)
7075 key
|= (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_1_SHIFT
);
7083 static int niu_get_hash_opts(struct niu
*np
, struct ethtool_rxnfc
*nfc
)
7089 if (!niu_ethflow_to_class(nfc
->flow_type
, &class))
7092 if (np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] &
7094 nfc
->data
= RXH_DISCARD
;
7096 nfc
->data
= niu_flowkey_to_ethflow(np
->parent
->flow_key
[class -
7097 CLASS_CODE_USER_PROG1
]);
7101 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry
*tp
,
7102 struct ethtool_rx_flow_spec
*fsp
)
7105 fsp
->h_u
.tcp_ip4_spec
.ip4src
= (tp
->key
[3] & TCAM_V4KEY3_SADDR
) >>
7106 TCAM_V4KEY3_SADDR_SHIFT
;
7107 fsp
->h_u
.tcp_ip4_spec
.ip4dst
= (tp
->key
[3] & TCAM_V4KEY3_DADDR
) >>
7108 TCAM_V4KEY3_DADDR_SHIFT
;
7109 fsp
->m_u
.tcp_ip4_spec
.ip4src
= (tp
->key_mask
[3] & TCAM_V4KEY3_SADDR
) >>
7110 TCAM_V4KEY3_SADDR_SHIFT
;
7111 fsp
->m_u
.tcp_ip4_spec
.ip4dst
= (tp
->key_mask
[3] & TCAM_V4KEY3_DADDR
) >>
7112 TCAM_V4KEY3_DADDR_SHIFT
;
7114 fsp
->h_u
.tcp_ip4_spec
.ip4src
=
7115 cpu_to_be32(fsp
->h_u
.tcp_ip4_spec
.ip4src
);
7116 fsp
->m_u
.tcp_ip4_spec
.ip4src
=
7117 cpu_to_be32(fsp
->m_u
.tcp_ip4_spec
.ip4src
);
7118 fsp
->h_u
.tcp_ip4_spec
.ip4dst
=
7119 cpu_to_be32(fsp
->h_u
.tcp_ip4_spec
.ip4dst
);
7120 fsp
->m_u
.tcp_ip4_spec
.ip4dst
=
7121 cpu_to_be32(fsp
->m_u
.tcp_ip4_spec
.ip4dst
);
7123 fsp
->h_u
.tcp_ip4_spec
.tos
= (tp
->key
[2] & TCAM_V4KEY2_TOS
) >>
7124 TCAM_V4KEY2_TOS_SHIFT
;
7125 fsp
->m_u
.tcp_ip4_spec
.tos
= (tp
->key_mask
[2] & TCAM_V4KEY2_TOS
) >>
7126 TCAM_V4KEY2_TOS_SHIFT
;
7128 switch (fsp
->flow_type
) {
7132 fsp
->h_u
.tcp_ip4_spec
.psrc
=
7133 ((tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7134 TCAM_V4KEY2_PORT_SPI_SHIFT
) >> 16;
7135 fsp
->h_u
.tcp_ip4_spec
.pdst
=
7136 ((tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7137 TCAM_V4KEY2_PORT_SPI_SHIFT
) & 0xffff;
7138 fsp
->m_u
.tcp_ip4_spec
.psrc
=
7139 ((tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7140 TCAM_V4KEY2_PORT_SPI_SHIFT
) >> 16;
7141 fsp
->m_u
.tcp_ip4_spec
.pdst
=
7142 ((tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7143 TCAM_V4KEY2_PORT_SPI_SHIFT
) & 0xffff;
7145 fsp
->h_u
.tcp_ip4_spec
.psrc
=
7146 cpu_to_be16(fsp
->h_u
.tcp_ip4_spec
.psrc
);
7147 fsp
->h_u
.tcp_ip4_spec
.pdst
=
7148 cpu_to_be16(fsp
->h_u
.tcp_ip4_spec
.pdst
);
7149 fsp
->m_u
.tcp_ip4_spec
.psrc
=
7150 cpu_to_be16(fsp
->m_u
.tcp_ip4_spec
.psrc
);
7151 fsp
->m_u
.tcp_ip4_spec
.pdst
=
7152 cpu_to_be16(fsp
->m_u
.tcp_ip4_spec
.pdst
);
7156 fsp
->h_u
.ah_ip4_spec
.spi
=
7157 (tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7158 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7159 fsp
->m_u
.ah_ip4_spec
.spi
=
7160 (tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7161 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7163 fsp
->h_u
.ah_ip4_spec
.spi
=
7164 cpu_to_be32(fsp
->h_u
.ah_ip4_spec
.spi
);
7165 fsp
->m_u
.ah_ip4_spec
.spi
=
7166 cpu_to_be32(fsp
->m_u
.ah_ip4_spec
.spi
);
7169 fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
=
7170 (tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7171 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7172 fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
=
7173 (tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7174 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7176 fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
=
7177 cpu_to_be32(fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
);
7178 fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
=
7179 cpu_to_be32(fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
);
7181 fsp
->h_u
.usr_ip4_spec
.proto
=
7182 (tp
->key
[2] & TCAM_V4KEY2_PROTO
) >>
7183 TCAM_V4KEY2_PROTO_SHIFT
;
7184 fsp
->m_u
.usr_ip4_spec
.proto
=
7185 (tp
->key_mask
[2] & TCAM_V4KEY2_PROTO
) >>
7186 TCAM_V4KEY2_PROTO_SHIFT
;
7188 fsp
->h_u
.usr_ip4_spec
.ip_ver
= ETH_RX_NFC_IP4
;
7195 static int niu_get_ethtool_tcam_entry(struct niu
*np
,
7196 struct ethtool_rxnfc
*nfc
)
7198 struct niu_parent
*parent
= np
->parent
;
7199 struct niu_tcam_entry
*tp
;
7200 struct ethtool_rx_flow_spec
*fsp
= &nfc
->fs
;
7205 idx
= tcam_get_index(np
, (u16
)nfc
->fs
.location
);
7207 tp
= &parent
->tcam
[idx
];
7209 pr_info(PFX
"niu%d: %s entry [%d] invalid for idx[%d]\n",
7210 parent
->index
, np
->dev
->name
, (u16
)nfc
->fs
.location
, idx
);
7214 /* fill the flow spec entry */
7215 class = (tp
->key
[0] & TCAM_V4KEY0_CLASS_CODE
) >>
7216 TCAM_V4KEY0_CLASS_CODE_SHIFT
;
7217 ret
= niu_class_to_ethflow(class, &fsp
->flow_type
);
7220 pr_info(PFX
"niu%d: %s niu_class_to_ethflow failed\n",
7221 parent
->index
, np
->dev
->name
);
7226 if (fsp
->flow_type
== AH_V4_FLOW
|| fsp
->flow_type
== AH_V6_FLOW
) {
7227 u32 proto
= (tp
->key
[2] & TCAM_V4KEY2_PROTO
) >>
7228 TCAM_V4KEY2_PROTO_SHIFT
;
7229 if (proto
== IPPROTO_ESP
) {
7230 if (fsp
->flow_type
== AH_V4_FLOW
)
7231 fsp
->flow_type
= ESP_V4_FLOW
;
7233 fsp
->flow_type
= ESP_V6_FLOW
;
7237 switch (fsp
->flow_type
) {
7243 niu_get_ip4fs_from_tcam_key(tp
, fsp
);
7250 /* Not yet implemented */
7254 niu_get_ip4fs_from_tcam_key(tp
, fsp
);
7264 if (tp
->assoc_data
& TCAM_ASSOCDATA_DISC
)
7265 fsp
->ring_cookie
= RX_CLS_FLOW_DISC
;
7267 fsp
->ring_cookie
= (tp
->assoc_data
& TCAM_ASSOCDATA_OFFSET
) >>
7268 TCAM_ASSOCDATA_OFFSET_SHIFT
;
7270 /* put the tcam size here */
7271 nfc
->data
= tcam_get_size(np
);
7276 static int niu_get_ethtool_tcam_all(struct niu
*np
,
7277 struct ethtool_rxnfc
*nfc
,
7280 struct niu_parent
*parent
= np
->parent
;
7281 struct niu_tcam_entry
*tp
;
7284 unsigned long flags
;
7287 /* put the tcam size here */
7288 nfc
->data
= tcam_get_size(np
);
7290 niu_lock_parent(np
, flags
);
7291 n_entries
= nfc
->rule_cnt
;
7292 for (cnt
= 0, i
= 0; i
< nfc
->data
; i
++) {
7293 idx
= tcam_get_index(np
, i
);
7294 tp
= &parent
->tcam
[idx
];
7300 niu_unlock_parent(np
, flags
);
7302 if (n_entries
!= cnt
) {
7303 /* print warning, this should not happen */
7304 pr_info(PFX
"niu%d: %s In niu_get_ethtool_tcam_all, "
7305 "n_entries[%d] != cnt[%d]!!!\n\n",
7306 np
->parent
->index
, np
->dev
->name
, n_entries
, cnt
);
7312 static int niu_get_nfc(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
,
7315 struct niu
*np
= netdev_priv(dev
);
7320 ret
= niu_get_hash_opts(np
, cmd
);
7322 case ETHTOOL_GRXRINGS
:
7323 cmd
->data
= np
->num_rx_rings
;
7325 case ETHTOOL_GRXCLSRLCNT
:
7326 cmd
->rule_cnt
= tcam_get_valid_entry_cnt(np
);
7328 case ETHTOOL_GRXCLSRULE
:
7329 ret
= niu_get_ethtool_tcam_entry(np
, cmd
);
7331 case ETHTOOL_GRXCLSRLALL
:
7332 ret
= niu_get_ethtool_tcam_all(np
, cmd
, (u32
*)rule_locs
);
7342 static int niu_set_hash_opts(struct niu
*np
, struct ethtool_rxnfc
*nfc
)
7346 unsigned long flags
;
7348 if (!niu_ethflow_to_class(nfc
->flow_type
, &class))
7351 if (class < CLASS_CODE_USER_PROG1
||
7352 class > CLASS_CODE_SCTP_IPV6
)
7355 if (nfc
->data
& RXH_DISCARD
) {
7356 niu_lock_parent(np
, flags
);
7357 flow_key
= np
->parent
->tcam_key
[class -
7358 CLASS_CODE_USER_PROG1
];
7359 flow_key
|= TCAM_KEY_DISC
;
7360 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1
), flow_key
);
7361 np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] = flow_key
;
7362 niu_unlock_parent(np
, flags
);
7365 /* Discard was set before, but is not set now */
7366 if (np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] &
7368 niu_lock_parent(np
, flags
);
7369 flow_key
= np
->parent
->tcam_key
[class -
7370 CLASS_CODE_USER_PROG1
];
7371 flow_key
&= ~TCAM_KEY_DISC
;
7372 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1
),
7374 np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] =
7376 niu_unlock_parent(np
, flags
);
7380 if (!niu_ethflow_to_flowkey(nfc
->data
, &flow_key
))
7383 niu_lock_parent(np
, flags
);
7384 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1
), flow_key
);
7385 np
->parent
->flow_key
[class - CLASS_CODE_USER_PROG1
] = flow_key
;
7386 niu_unlock_parent(np
, flags
);
7391 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec
*fsp
,
7392 struct niu_tcam_entry
*tp
,
7393 int l2_rdc_tab
, u64
class)
7396 u32 sip
, dip
, sipm
, dipm
, spi
, spim
;
7397 u16 sport
, dport
, spm
, dpm
;
7399 sip
= be32_to_cpu(fsp
->h_u
.tcp_ip4_spec
.ip4src
);
7400 sipm
= be32_to_cpu(fsp
->m_u
.tcp_ip4_spec
.ip4src
);
7401 dip
= be32_to_cpu(fsp
->h_u
.tcp_ip4_spec
.ip4dst
);
7402 dipm
= be32_to_cpu(fsp
->m_u
.tcp_ip4_spec
.ip4dst
);
7404 tp
->key
[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT
;
7405 tp
->key_mask
[0] = TCAM_V4KEY0_CLASS_CODE
;
7406 tp
->key
[1] = (u64
)l2_rdc_tab
<< TCAM_V4KEY1_L2RDCNUM_SHIFT
;
7407 tp
->key_mask
[1] = TCAM_V4KEY1_L2RDCNUM
;
7409 tp
->key
[3] = (u64
)sip
<< TCAM_V4KEY3_SADDR_SHIFT
;
7412 tp
->key_mask
[3] = (u64
)sipm
<< TCAM_V4KEY3_SADDR_SHIFT
;
7413 tp
->key_mask
[3] |= dipm
;
7415 tp
->key
[2] |= ((u64
)fsp
->h_u
.tcp_ip4_spec
.tos
<<
7416 TCAM_V4KEY2_TOS_SHIFT
);
7417 tp
->key_mask
[2] |= ((u64
)fsp
->m_u
.tcp_ip4_spec
.tos
<<
7418 TCAM_V4KEY2_TOS_SHIFT
);
7419 switch (fsp
->flow_type
) {
7423 sport
= be16_to_cpu(fsp
->h_u
.tcp_ip4_spec
.psrc
);
7424 spm
= be16_to_cpu(fsp
->m_u
.tcp_ip4_spec
.psrc
);
7425 dport
= be16_to_cpu(fsp
->h_u
.tcp_ip4_spec
.pdst
);
7426 dpm
= be16_to_cpu(fsp
->m_u
.tcp_ip4_spec
.pdst
);
7428 tp
->key
[2] |= (((u64
)sport
<< 16) | dport
);
7429 tp
->key_mask
[2] |= (((u64
)spm
<< 16) | dpm
);
7430 niu_ethflow_to_l3proto(fsp
->flow_type
, &pid
);
7434 spi
= be32_to_cpu(fsp
->h_u
.ah_ip4_spec
.spi
);
7435 spim
= be32_to_cpu(fsp
->m_u
.ah_ip4_spec
.spi
);
7438 tp
->key_mask
[2] |= spim
;
7439 niu_ethflow_to_l3proto(fsp
->flow_type
, &pid
);
7442 spi
= be32_to_cpu(fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
);
7443 spim
= be32_to_cpu(fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
);
7446 tp
->key_mask
[2] |= spim
;
7447 pid
= fsp
->h_u
.usr_ip4_spec
.proto
;
7453 tp
->key
[2] |= ((u64
)pid
<< TCAM_V4KEY2_PROTO_SHIFT
);
7455 tp
->key_mask
[2] |= TCAM_V4KEY2_PROTO
;
7459 static int niu_add_ethtool_tcam_entry(struct niu
*np
,
7460 struct ethtool_rxnfc
*nfc
)
7462 struct niu_parent
*parent
= np
->parent
;
7463 struct niu_tcam_entry
*tp
;
7464 struct ethtool_rx_flow_spec
*fsp
= &nfc
->fs
;
7465 struct niu_rdc_tables
*rdc_table
= &parent
->rdc_group_cfg
[np
->port
];
7466 int l2_rdc_table
= rdc_table
->first_table_num
;
7469 unsigned long flags
;
7474 idx
= nfc
->fs
.location
;
7475 if (idx
>= tcam_get_size(np
))
7478 if (fsp
->flow_type
== IP_USER_FLOW
) {
7480 int add_usr_cls
= 0;
7482 struct ethtool_usrip4_spec
*uspec
= &fsp
->h_u
.usr_ip4_spec
;
7483 struct ethtool_usrip4_spec
*umask
= &fsp
->m_u
.usr_ip4_spec
;
7485 niu_lock_parent(np
, flags
);
7487 for (i
= 0; i
< NIU_L3_PROG_CLS
; i
++) {
7488 if (parent
->l3_cls
[i
]) {
7489 if (uspec
->proto
== parent
->l3_cls_pid
[i
]) {
7490 class = parent
->l3_cls
[i
];
7491 parent
->l3_cls_refcnt
[i
]++;
7496 /* Program new user IP class */
7499 class = CLASS_CODE_USER_PROG1
;
7502 class = CLASS_CODE_USER_PROG2
;
7505 class = CLASS_CODE_USER_PROG3
;
7508 class = CLASS_CODE_USER_PROG4
;
7513 if (uspec
->ip_ver
== ETH_RX_NFC_IP6
)
7515 ret
= tcam_user_ip_class_set(np
, class, ipv6
,
7522 ret
= tcam_user_ip_class_enable(np
, class, 1);
7525 parent
->l3_cls
[i
] = class;
7526 parent
->l3_cls_pid
[i
] = uspec
->proto
;
7527 parent
->l3_cls_refcnt
[i
]++;
7533 pr_info(PFX
"niu%d: %s niu_add_ethtool_tcam_entry: "
7534 "Could not find/insert class for pid %d\n",
7535 parent
->index
, np
->dev
->name
, uspec
->proto
);
7539 niu_unlock_parent(np
, flags
);
7541 if (!niu_ethflow_to_class(fsp
->flow_type
, &class)) {
7546 niu_lock_parent(np
, flags
);
7548 idx
= tcam_get_index(np
, idx
);
7549 tp
= &parent
->tcam
[idx
];
7551 memset(tp
, 0, sizeof(*tp
));
7553 /* fill in the tcam key and mask */
7554 switch (fsp
->flow_type
) {
7560 niu_get_tcamkey_from_ip4fs(fsp
, tp
, l2_rdc_table
, class);
7567 /* Not yet implemented */
7568 pr_info(PFX
"niu%d: %s In niu_add_ethtool_tcam_entry: "
7569 "flow %d for IPv6 not implemented\n\n",
7570 parent
->index
, np
->dev
->name
, fsp
->flow_type
);
7574 if (fsp
->h_u
.usr_ip4_spec
.ip_ver
== ETH_RX_NFC_IP4
) {
7575 niu_get_tcamkey_from_ip4fs(fsp
, tp
, l2_rdc_table
,
7578 /* Not yet implemented */
7579 pr_info(PFX
"niu%d: %s In niu_add_ethtool_tcam_entry: "
7580 "usr flow for IPv6 not implemented\n\n",
7581 parent
->index
, np
->dev
->name
);
7587 pr_info(PFX
"niu%d: %s In niu_add_ethtool_tcam_entry: "
7588 "Unknown flow type %d\n\n",
7589 parent
->index
, np
->dev
->name
, fsp
->flow_type
);
7594 /* fill in the assoc data */
7595 if (fsp
->ring_cookie
== RX_CLS_FLOW_DISC
) {
7596 tp
->assoc_data
= TCAM_ASSOCDATA_DISC
;
7598 if (fsp
->ring_cookie
>= np
->num_rx_rings
) {
7599 pr_info(PFX
"niu%d: %s In niu_add_ethtool_tcam_entry: "
7600 "Invalid RX ring %lld\n\n",
7601 parent
->index
, np
->dev
->name
,
7602 (long long) fsp
->ring_cookie
);
7606 tp
->assoc_data
= (TCAM_ASSOCDATA_TRES_USE_OFFSET
|
7607 (fsp
->ring_cookie
<<
7608 TCAM_ASSOCDATA_OFFSET_SHIFT
));
7611 err
= tcam_write(np
, idx
, tp
->key
, tp
->key_mask
);
7616 err
= tcam_assoc_write(np
, idx
, tp
->assoc_data
);
7622 /* validate the entry */
7624 np
->clas
.tcam_valid_entries
++;
7626 niu_unlock_parent(np
, flags
);
7631 static int niu_del_ethtool_tcam_entry(struct niu
*np
, u32 loc
)
7633 struct niu_parent
*parent
= np
->parent
;
7634 struct niu_tcam_entry
*tp
;
7636 unsigned long flags
;
7640 if (loc
>= tcam_get_size(np
))
7643 niu_lock_parent(np
, flags
);
7645 idx
= tcam_get_index(np
, loc
);
7646 tp
= &parent
->tcam
[idx
];
7648 /* if the entry is of a user defined class, then update*/
7649 class = (tp
->key
[0] & TCAM_V4KEY0_CLASS_CODE
) >>
7650 TCAM_V4KEY0_CLASS_CODE_SHIFT
;
7652 if (class >= CLASS_CODE_USER_PROG1
&& class <= CLASS_CODE_USER_PROG4
) {
7654 for (i
= 0; i
< NIU_L3_PROG_CLS
; i
++) {
7655 if (parent
->l3_cls
[i
] == class) {
7656 parent
->l3_cls_refcnt
[i
]--;
7657 if (!parent
->l3_cls_refcnt
[i
]) {
7659 ret
= tcam_user_ip_class_enable(np
,
7664 parent
->l3_cls
[i
] = 0;
7665 parent
->l3_cls_pid
[i
] = 0;
7670 if (i
== NIU_L3_PROG_CLS
) {
7671 pr_info(PFX
"niu%d: %s In niu_del_ethtool_tcam_entry,"
7672 "Usr class 0x%llx not found \n",
7673 parent
->index
, np
->dev
->name
,
7674 (unsigned long long) class);
7680 ret
= tcam_flush(np
, idx
);
7684 /* invalidate the entry */
7686 np
->clas
.tcam_valid_entries
--;
7688 niu_unlock_parent(np
, flags
);
7693 static int niu_set_nfc(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
)
7695 struct niu
*np
= netdev_priv(dev
);
7700 ret
= niu_set_hash_opts(np
, cmd
);
7702 case ETHTOOL_SRXCLSRLINS
:
7703 ret
= niu_add_ethtool_tcam_entry(np
, cmd
);
7705 case ETHTOOL_SRXCLSRLDEL
:
7706 ret
= niu_del_ethtool_tcam_entry(np
, cmd
->fs
.location
);
7716 static const struct {
7717 const char string
[ETH_GSTRING_LEN
];
7718 } niu_xmac_stat_keys
[] = {
7721 { "tx_fifo_errors" },
7722 { "tx_overflow_errors" },
7723 { "tx_max_pkt_size_errors" },
7724 { "tx_underflow_errors" },
7725 { "rx_local_faults" },
7726 { "rx_remote_faults" },
7727 { "rx_link_faults" },
7728 { "rx_align_errors" },
7740 { "rx_code_violations" },
7741 { "rx_len_errors" },
7742 { "rx_crc_errors" },
7743 { "rx_underflows" },
7745 { "pause_off_state" },
7746 { "pause_on_state" },
7747 { "pause_received" },
7750 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7752 static const struct {
7753 const char string
[ETH_GSTRING_LEN
];
7754 } niu_bmac_stat_keys
[] = {
7755 { "tx_underflow_errors" },
7756 { "tx_max_pkt_size_errors" },
7761 { "rx_align_errors" },
7762 { "rx_crc_errors" },
7763 { "rx_len_errors" },
7764 { "pause_off_state" },
7765 { "pause_on_state" },
7766 { "pause_received" },
7769 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7771 static const struct {
7772 const char string
[ETH_GSTRING_LEN
];
7773 } niu_rxchan_stat_keys
[] = {
7781 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7783 static const struct {
7784 const char string
[ETH_GSTRING_LEN
];
7785 } niu_txchan_stat_keys
[] = {
7792 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7794 static void niu_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
7796 struct niu
*np
= netdev_priv(dev
);
7799 if (stringset
!= ETH_SS_STATS
)
7802 if (np
->flags
& NIU_FLAGS_XMAC
) {
7803 memcpy(data
, niu_xmac_stat_keys
,
7804 sizeof(niu_xmac_stat_keys
));
7805 data
+= sizeof(niu_xmac_stat_keys
);
7807 memcpy(data
, niu_bmac_stat_keys
,
7808 sizeof(niu_bmac_stat_keys
));
7809 data
+= sizeof(niu_bmac_stat_keys
);
7811 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
7812 memcpy(data
, niu_rxchan_stat_keys
,
7813 sizeof(niu_rxchan_stat_keys
));
7814 data
+= sizeof(niu_rxchan_stat_keys
);
7816 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
7817 memcpy(data
, niu_txchan_stat_keys
,
7818 sizeof(niu_txchan_stat_keys
));
7819 data
+= sizeof(niu_txchan_stat_keys
);
7823 static int niu_get_stats_count(struct net_device
*dev
)
7825 struct niu
*np
= netdev_priv(dev
);
7827 return ((np
->flags
& NIU_FLAGS_XMAC
?
7828 NUM_XMAC_STAT_KEYS
:
7829 NUM_BMAC_STAT_KEYS
) +
7830 (np
->num_rx_rings
* NUM_RXCHAN_STAT_KEYS
) +
7831 (np
->num_tx_rings
* NUM_TXCHAN_STAT_KEYS
));
7834 static void niu_get_ethtool_stats(struct net_device
*dev
,
7835 struct ethtool_stats
*stats
, u64
*data
)
7837 struct niu
*np
= netdev_priv(dev
);
7840 niu_sync_mac_stats(np
);
7841 if (np
->flags
& NIU_FLAGS_XMAC
) {
7842 memcpy(data
, &np
->mac_stats
.xmac
,
7843 sizeof(struct niu_xmac_stats
));
7844 data
+= (sizeof(struct niu_xmac_stats
) / sizeof(u64
));
7846 memcpy(data
, &np
->mac_stats
.bmac
,
7847 sizeof(struct niu_bmac_stats
));
7848 data
+= (sizeof(struct niu_bmac_stats
) / sizeof(u64
));
7850 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
7851 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
7853 niu_sync_rx_discard_stats(np
, rp
, 0);
7855 data
[0] = rp
->rx_channel
;
7856 data
[1] = rp
->rx_packets
;
7857 data
[2] = rp
->rx_bytes
;
7858 data
[3] = rp
->rx_dropped
;
7859 data
[4] = rp
->rx_errors
;
7862 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
7863 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
7865 data
[0] = rp
->tx_channel
;
7866 data
[1] = rp
->tx_packets
;
7867 data
[2] = rp
->tx_bytes
;
7868 data
[3] = rp
->tx_errors
;
7873 static u64
niu_led_state_save(struct niu
*np
)
7875 if (np
->flags
& NIU_FLAGS_XMAC
)
7876 return nr64_mac(XMAC_CONFIG
);
7878 return nr64_mac(BMAC_XIF_CONFIG
);
7881 static void niu_led_state_restore(struct niu
*np
, u64 val
)
7883 if (np
->flags
& NIU_FLAGS_XMAC
)
7884 nw64_mac(XMAC_CONFIG
, val
);
7886 nw64_mac(BMAC_XIF_CONFIG
, val
);
7889 static void niu_force_led(struct niu
*np
, int on
)
7893 if (np
->flags
& NIU_FLAGS_XMAC
) {
7895 bit
= XMAC_CONFIG_FORCE_LED_ON
;
7897 reg
= BMAC_XIF_CONFIG
;
7898 bit
= BMAC_XIF_CONFIG_LINK_LED
;
7901 val
= nr64_mac(reg
);
7909 static int niu_phys_id(struct net_device
*dev
, u32 data
)
7911 struct niu
*np
= netdev_priv(dev
);
7915 if (!netif_running(dev
))
7921 orig_led_state
= niu_led_state_save(np
);
7922 for (i
= 0; i
< (data
* 2); i
++) {
7923 int on
= ((i
% 2) == 0);
7925 niu_force_led(np
, on
);
7927 if (msleep_interruptible(500))
7930 niu_led_state_restore(np
, orig_led_state
);
7935 static const struct ethtool_ops niu_ethtool_ops
= {
7936 .get_drvinfo
= niu_get_drvinfo
,
7937 .get_link
= ethtool_op_get_link
,
7938 .get_msglevel
= niu_get_msglevel
,
7939 .set_msglevel
= niu_set_msglevel
,
7940 .nway_reset
= niu_nway_reset
,
7941 .get_eeprom_len
= niu_get_eeprom_len
,
7942 .get_eeprom
= niu_get_eeprom
,
7943 .get_settings
= niu_get_settings
,
7944 .set_settings
= niu_set_settings
,
7945 .get_strings
= niu_get_strings
,
7946 .get_stats_count
= niu_get_stats_count
,
7947 .get_ethtool_stats
= niu_get_ethtool_stats
,
7948 .phys_id
= niu_phys_id
,
7949 .get_rxnfc
= niu_get_nfc
,
7950 .set_rxnfc
= niu_set_nfc
,
7953 static int niu_ldg_assign_ldn(struct niu
*np
, struct niu_parent
*parent
,
7956 if (ldg
< NIU_LDG_MIN
|| ldg
> NIU_LDG_MAX
)
7958 if (ldn
< 0 || ldn
> LDN_MAX
)
7961 parent
->ldg_map
[ldn
] = ldg
;
7963 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
) {
7964 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7965 * the firmware, and we're not supposed to change them.
7966 * Validate the mapping, because if it's wrong we probably
7967 * won't get any interrupts and that's painful to debug.
7969 if (nr64(LDG_NUM(ldn
)) != ldg
) {
7970 dev_err(np
->device
, PFX
"Port %u, mis-matched "
7972 "for ldn %d, should be %d is %llu\n",
7974 (unsigned long long) nr64(LDG_NUM(ldn
)));
7978 nw64(LDG_NUM(ldn
), ldg
);
7983 static int niu_set_ldg_timer_res(struct niu
*np
, int res
)
7985 if (res
< 0 || res
> LDG_TIMER_RES_VAL
)
7989 nw64(LDG_TIMER_RES
, res
);
7994 static int niu_set_ldg_sid(struct niu
*np
, int ldg
, int func
, int vector
)
7996 if ((ldg
< NIU_LDG_MIN
|| ldg
> NIU_LDG_MAX
) ||
7997 (func
< 0 || func
> 3) ||
7998 (vector
< 0 || vector
> 0x1f))
8001 nw64(SID(ldg
), (func
<< SID_FUNC_SHIFT
) | vector
);
8006 static int __devinit
niu_pci_eeprom_read(struct niu
*np
, u32 addr
)
8008 u64 frame
, frame_base
= (ESPC_PIO_STAT_READ_START
|
8009 (addr
<< ESPC_PIO_STAT_ADDR_SHIFT
));
8012 if (addr
> (ESPC_PIO_STAT_ADDR
>> ESPC_PIO_STAT_ADDR_SHIFT
))
8016 nw64(ESPC_PIO_STAT
, frame
);
8020 frame
= nr64(ESPC_PIO_STAT
);
8021 if (frame
& ESPC_PIO_STAT_READ_END
)
8024 if (!(frame
& ESPC_PIO_STAT_READ_END
)) {
8025 dev_err(np
->device
, PFX
"EEPROM read timeout frame[%llx]\n",
8026 (unsigned long long) frame
);
8031 nw64(ESPC_PIO_STAT
, frame
);
8035 frame
= nr64(ESPC_PIO_STAT
);
8036 if (frame
& ESPC_PIO_STAT_READ_END
)
8039 if (!(frame
& ESPC_PIO_STAT_READ_END
)) {
8040 dev_err(np
->device
, PFX
"EEPROM read timeout frame[%llx]\n",
8041 (unsigned long long) frame
);
8045 frame
= nr64(ESPC_PIO_STAT
);
8046 return (frame
& ESPC_PIO_STAT_DATA
) >> ESPC_PIO_STAT_DATA_SHIFT
;
8049 static int __devinit
niu_pci_eeprom_read16(struct niu
*np
, u32 off
)
8051 int err
= niu_pci_eeprom_read(np
, off
);
8057 err
= niu_pci_eeprom_read(np
, off
+ 1);
8060 val
|= (err
& 0xff);
8065 static int __devinit
niu_pci_eeprom_read16_swp(struct niu
*np
, u32 off
)
8067 int err
= niu_pci_eeprom_read(np
, off
);
8074 err
= niu_pci_eeprom_read(np
, off
+ 1);
8078 val
|= (err
& 0xff) << 8;
8083 static int __devinit
niu_pci_vpd_get_propname(struct niu
*np
,
8090 for (i
= 0; i
< namebuf_len
; i
++) {
8091 int err
= niu_pci_eeprom_read(np
, off
+ i
);
8098 if (i
>= namebuf_len
)
8104 static void __devinit
niu_vpd_parse_version(struct niu
*np
)
8106 struct niu_vpd
*vpd
= &np
->vpd
;
8107 int len
= strlen(vpd
->version
) + 1;
8108 const char *s
= vpd
->version
;
8111 for (i
= 0; i
< len
- 5; i
++) {
8112 if (!strncmp(s
+ i
, "FCode ", 5))
8119 sscanf(s
, "%d.%d", &vpd
->fcode_major
, &vpd
->fcode_minor
);
8121 niudbg(PROBE
, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8122 vpd
->fcode_major
, vpd
->fcode_minor
);
8123 if (vpd
->fcode_major
> NIU_VPD_MIN_MAJOR
||
8124 (vpd
->fcode_major
== NIU_VPD_MIN_MAJOR
&&
8125 vpd
->fcode_minor
>= NIU_VPD_MIN_MINOR
))
8126 np
->flags
|= NIU_FLAGS_VPD_VALID
;
8129 /* ESPC_PIO_EN_ENABLE must be set */
8130 static int __devinit
niu_pci_vpd_scan_props(struct niu
*np
,
8133 unsigned int found_mask
= 0;
8134 #define FOUND_MASK_MODEL 0x00000001
8135 #define FOUND_MASK_BMODEL 0x00000002
8136 #define FOUND_MASK_VERS 0x00000004
8137 #define FOUND_MASK_MAC 0x00000008
8138 #define FOUND_MASK_NMAC 0x00000010
8139 #define FOUND_MASK_PHY 0x00000020
8140 #define FOUND_MASK_ALL 0x0000003f
8142 niudbg(PROBE
, "VPD_SCAN: start[%x] end[%x]\n",
8144 while (start
< end
) {
8145 int len
, err
, instance
, type
, prop_len
;
8150 if (found_mask
== FOUND_MASK_ALL
) {
8151 niu_vpd_parse_version(np
);
8155 err
= niu_pci_eeprom_read(np
, start
+ 2);
8161 instance
= niu_pci_eeprom_read(np
, start
);
8162 type
= niu_pci_eeprom_read(np
, start
+ 3);
8163 prop_len
= niu_pci_eeprom_read(np
, start
+ 4);
8164 err
= niu_pci_vpd_get_propname(np
, start
+ 5, namebuf
, 64);
8170 if (!strcmp(namebuf
, "model")) {
8171 prop_buf
= np
->vpd
.model
;
8172 max_len
= NIU_VPD_MODEL_MAX
;
8173 found_mask
|= FOUND_MASK_MODEL
;
8174 } else if (!strcmp(namebuf
, "board-model")) {
8175 prop_buf
= np
->vpd
.board_model
;
8176 max_len
= NIU_VPD_BD_MODEL_MAX
;
8177 found_mask
|= FOUND_MASK_BMODEL
;
8178 } else if (!strcmp(namebuf
, "version")) {
8179 prop_buf
= np
->vpd
.version
;
8180 max_len
= NIU_VPD_VERSION_MAX
;
8181 found_mask
|= FOUND_MASK_VERS
;
8182 } else if (!strcmp(namebuf
, "local-mac-address")) {
8183 prop_buf
= np
->vpd
.local_mac
;
8185 found_mask
|= FOUND_MASK_MAC
;
8186 } else if (!strcmp(namebuf
, "num-mac-addresses")) {
8187 prop_buf
= &np
->vpd
.mac_num
;
8189 found_mask
|= FOUND_MASK_NMAC
;
8190 } else if (!strcmp(namebuf
, "phy-type")) {
8191 prop_buf
= np
->vpd
.phy_type
;
8192 max_len
= NIU_VPD_PHY_TYPE_MAX
;
8193 found_mask
|= FOUND_MASK_PHY
;
8196 if (max_len
&& prop_len
> max_len
) {
8197 dev_err(np
->device
, PFX
"Property '%s' length (%d) is "
8198 "too long.\n", namebuf
, prop_len
);
8203 u32 off
= start
+ 5 + err
;
8206 niudbg(PROBE
, "VPD_SCAN: Reading in property [%s] "
8207 "len[%d]\n", namebuf
, prop_len
);
8208 for (i
= 0; i
< prop_len
; i
++)
8209 *prop_buf
++ = niu_pci_eeprom_read(np
, off
+ i
);
8218 /* ESPC_PIO_EN_ENABLE must be set */
8219 static void __devinit
niu_pci_vpd_fetch(struct niu
*np
, u32 start
)
8224 err
= niu_pci_eeprom_read16_swp(np
, start
+ 1);
8230 while (start
+ offset
< ESPC_EEPROM_SIZE
) {
8231 u32 here
= start
+ offset
;
8234 err
= niu_pci_eeprom_read(np
, here
);
8238 err
= niu_pci_eeprom_read16_swp(np
, here
+ 1);
8242 here
= start
+ offset
+ 3;
8243 end
= start
+ offset
+ err
;
8247 err
= niu_pci_vpd_scan_props(np
, here
, end
);
8248 if (err
< 0 || err
== 1)
8253 /* ESPC_PIO_EN_ENABLE must be set */
8254 static u32 __devinit
niu_pci_vpd_offset(struct niu
*np
)
8256 u32 start
= 0, end
= ESPC_EEPROM_SIZE
, ret
;
8259 while (start
< end
) {
8262 /* ROM header signature? */
8263 err
= niu_pci_eeprom_read16(np
, start
+ 0);
8267 /* Apply offset to PCI data structure. */
8268 err
= niu_pci_eeprom_read16(np
, start
+ 23);
8273 /* Check for "PCIR" signature. */
8274 err
= niu_pci_eeprom_read16(np
, start
+ 0);
8277 err
= niu_pci_eeprom_read16(np
, start
+ 2);
8281 /* Check for OBP image type. */
8282 err
= niu_pci_eeprom_read(np
, start
+ 20);
8286 err
= niu_pci_eeprom_read(np
, ret
+ 2);
8290 start
= ret
+ (err
* 512);
8294 err
= niu_pci_eeprom_read16_swp(np
, start
+ 8);
8299 err
= niu_pci_eeprom_read(np
, ret
+ 0);
8309 static int __devinit
niu_phy_type_prop_decode(struct niu
*np
,
8310 const char *phy_prop
)
8312 if (!strcmp(phy_prop
, "mif")) {
8313 /* 1G copper, MII */
8314 np
->flags
&= ~(NIU_FLAGS_FIBER
|
8316 np
->mac_xcvr
= MAC_XCVR_MII
;
8317 } else if (!strcmp(phy_prop
, "xgf")) {
8318 /* 10G fiber, XPCS */
8319 np
->flags
|= (NIU_FLAGS_10G
|
8321 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8322 } else if (!strcmp(phy_prop
, "pcs")) {
8324 np
->flags
&= ~NIU_FLAGS_10G
;
8325 np
->flags
|= NIU_FLAGS_FIBER
;
8326 np
->mac_xcvr
= MAC_XCVR_PCS
;
8327 } else if (!strcmp(phy_prop
, "xgc")) {
8328 /* 10G copper, XPCS */
8329 np
->flags
|= NIU_FLAGS_10G
;
8330 np
->flags
&= ~NIU_FLAGS_FIBER
;
8331 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8332 } else if (!strcmp(phy_prop
, "xgsd") || !strcmp(phy_prop
, "gsd")) {
8333 /* 10G Serdes or 1G Serdes, default to 10G */
8334 np
->flags
|= NIU_FLAGS_10G
;
8335 np
->flags
&= ~NIU_FLAGS_FIBER
;
8336 np
->flags
|= NIU_FLAGS_XCVR_SERDES
;
8337 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8344 static int niu_pci_vpd_get_nports(struct niu
*np
)
8348 if ((!strcmp(np
->vpd
.model
, NIU_QGC_LP_MDL_STR
)) ||
8349 (!strcmp(np
->vpd
.model
, NIU_QGC_PEM_MDL_STR
)) ||
8350 (!strcmp(np
->vpd
.model
, NIU_MARAMBA_MDL_STR
)) ||
8351 (!strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) ||
8352 (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
))) {
8354 } else if ((!strcmp(np
->vpd
.model
, NIU_2XGF_LP_MDL_STR
)) ||
8355 (!strcmp(np
->vpd
.model
, NIU_2XGF_PEM_MDL_STR
)) ||
8356 (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) ||
8357 (!strcmp(np
->vpd
.model
, NIU_2XGF_MRVL_MDL_STR
))) {
8364 static void __devinit
niu_pci_vpd_validate(struct niu
*np
)
8366 struct net_device
*dev
= np
->dev
;
8367 struct niu_vpd
*vpd
= &np
->vpd
;
8370 if (!is_valid_ether_addr(&vpd
->local_mac
[0])) {
8371 dev_err(np
->device
, PFX
"VPD MAC invalid, "
8372 "falling back to SPROM.\n");
8374 np
->flags
&= ~NIU_FLAGS_VPD_VALID
;
8378 if (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
) ||
8379 !strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) {
8380 np
->flags
|= NIU_FLAGS_10G
;
8381 np
->flags
&= ~NIU_FLAGS_FIBER
;
8382 np
->flags
|= NIU_FLAGS_XCVR_SERDES
;
8383 np
->mac_xcvr
= MAC_XCVR_PCS
;
8385 np
->flags
|= NIU_FLAGS_FIBER
;
8386 np
->flags
&= ~NIU_FLAGS_10G
;
8388 if (np
->flags
& NIU_FLAGS_10G
)
8389 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8390 } else if (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) {
8391 np
->flags
|= (NIU_FLAGS_10G
| NIU_FLAGS_FIBER
|
8392 NIU_FLAGS_HOTPLUG_PHY
);
8393 } else if (niu_phy_type_prop_decode(np
, np
->vpd
.phy_type
)) {
8394 dev_err(np
->device
, PFX
"Illegal phy string [%s].\n",
8396 dev_err(np
->device
, PFX
"Falling back to SPROM.\n");
8397 np
->flags
&= ~NIU_FLAGS_VPD_VALID
;
8401 memcpy(dev
->perm_addr
, vpd
->local_mac
, ETH_ALEN
);
8403 val8
= dev
->perm_addr
[5];
8404 dev
->perm_addr
[5] += np
->port
;
8405 if (dev
->perm_addr
[5] < val8
)
8406 dev
->perm_addr
[4]++;
8408 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
8411 static int __devinit
niu_pci_probe_sprom(struct niu
*np
)
8413 struct net_device
*dev
= np
->dev
;
8418 val
= (nr64(ESPC_VER_IMGSZ
) & ESPC_VER_IMGSZ_IMGSZ
);
8419 val
>>= ESPC_VER_IMGSZ_IMGSZ_SHIFT
;
8422 np
->eeprom_len
= len
;
8424 niudbg(PROBE
, "SPROM: Image size %llu\n", (unsigned long long) val
);
8427 for (i
= 0; i
< len
; i
++) {
8428 val
= nr64(ESPC_NCR(i
));
8429 sum
+= (val
>> 0) & 0xff;
8430 sum
+= (val
>> 8) & 0xff;
8431 sum
+= (val
>> 16) & 0xff;
8432 sum
+= (val
>> 24) & 0xff;
8434 niudbg(PROBE
, "SPROM: Checksum %x\n", (int)(sum
& 0xff));
8435 if ((sum
& 0xff) != 0xab) {
8436 dev_err(np
->device
, PFX
"Bad SPROM checksum "
8437 "(%x, should be 0xab)\n", (int) (sum
& 0xff));
8441 val
= nr64(ESPC_PHY_TYPE
);
8444 val8
= (val
& ESPC_PHY_TYPE_PORT0
) >>
8445 ESPC_PHY_TYPE_PORT0_SHIFT
;
8448 val8
= (val
& ESPC_PHY_TYPE_PORT1
) >>
8449 ESPC_PHY_TYPE_PORT1_SHIFT
;
8452 val8
= (val
& ESPC_PHY_TYPE_PORT2
) >>
8453 ESPC_PHY_TYPE_PORT2_SHIFT
;
8456 val8
= (val
& ESPC_PHY_TYPE_PORT3
) >>
8457 ESPC_PHY_TYPE_PORT3_SHIFT
;
8460 dev_err(np
->device
, PFX
"Bogus port number %u\n",
8464 niudbg(PROBE
, "SPROM: PHY type %x\n", val8
);
8467 case ESPC_PHY_TYPE_1G_COPPER
:
8468 /* 1G copper, MII */
8469 np
->flags
&= ~(NIU_FLAGS_FIBER
|
8471 np
->mac_xcvr
= MAC_XCVR_MII
;
8474 case ESPC_PHY_TYPE_1G_FIBER
:
8476 np
->flags
&= ~NIU_FLAGS_10G
;
8477 np
->flags
|= NIU_FLAGS_FIBER
;
8478 np
->mac_xcvr
= MAC_XCVR_PCS
;
8481 case ESPC_PHY_TYPE_10G_COPPER
:
8482 /* 10G copper, XPCS */
8483 np
->flags
|= NIU_FLAGS_10G
;
8484 np
->flags
&= ~NIU_FLAGS_FIBER
;
8485 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8488 case ESPC_PHY_TYPE_10G_FIBER
:
8489 /* 10G fiber, XPCS */
8490 np
->flags
|= (NIU_FLAGS_10G
|
8492 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8496 dev_err(np
->device
, PFX
"Bogus SPROM phy type %u\n", val8
);
8500 val
= nr64(ESPC_MAC_ADDR0
);
8501 niudbg(PROBE
, "SPROM: MAC_ADDR0[%08llx]\n",
8502 (unsigned long long) val
);
8503 dev
->perm_addr
[0] = (val
>> 0) & 0xff;
8504 dev
->perm_addr
[1] = (val
>> 8) & 0xff;
8505 dev
->perm_addr
[2] = (val
>> 16) & 0xff;
8506 dev
->perm_addr
[3] = (val
>> 24) & 0xff;
8508 val
= nr64(ESPC_MAC_ADDR1
);
8509 niudbg(PROBE
, "SPROM: MAC_ADDR1[%08llx]\n",
8510 (unsigned long long) val
);
8511 dev
->perm_addr
[4] = (val
>> 0) & 0xff;
8512 dev
->perm_addr
[5] = (val
>> 8) & 0xff;
8514 if (!is_valid_ether_addr(&dev
->perm_addr
[0])) {
8515 dev_err(np
->device
, PFX
"SPROM MAC address invalid\n");
8516 dev_err(np
->device
, PFX
"[ \n");
8517 for (i
= 0; i
< 6; i
++)
8518 printk("%02x ", dev
->perm_addr
[i
]);
8523 val8
= dev
->perm_addr
[5];
8524 dev
->perm_addr
[5] += np
->port
;
8525 if (dev
->perm_addr
[5] < val8
)
8526 dev
->perm_addr
[4]++;
8528 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
8530 val
= nr64(ESPC_MOD_STR_LEN
);
8531 niudbg(PROBE
, "SPROM: MOD_STR_LEN[%llu]\n",
8532 (unsigned long long) val
);
8536 for (i
= 0; i
< val
; i
+= 4) {
8537 u64 tmp
= nr64(ESPC_NCR(5 + (i
/ 4)));
8539 np
->vpd
.model
[i
+ 3] = (tmp
>> 0) & 0xff;
8540 np
->vpd
.model
[i
+ 2] = (tmp
>> 8) & 0xff;
8541 np
->vpd
.model
[i
+ 1] = (tmp
>> 16) & 0xff;
8542 np
->vpd
.model
[i
+ 0] = (tmp
>> 24) & 0xff;
8544 np
->vpd
.model
[val
] = '\0';
8546 val
= nr64(ESPC_BD_MOD_STR_LEN
);
8547 niudbg(PROBE
, "SPROM: BD_MOD_STR_LEN[%llu]\n",
8548 (unsigned long long) val
);
8552 for (i
= 0; i
< val
; i
+= 4) {
8553 u64 tmp
= nr64(ESPC_NCR(14 + (i
/ 4)));
8555 np
->vpd
.board_model
[i
+ 3] = (tmp
>> 0) & 0xff;
8556 np
->vpd
.board_model
[i
+ 2] = (tmp
>> 8) & 0xff;
8557 np
->vpd
.board_model
[i
+ 1] = (tmp
>> 16) & 0xff;
8558 np
->vpd
.board_model
[i
+ 0] = (tmp
>> 24) & 0xff;
8560 np
->vpd
.board_model
[val
] = '\0';
8563 nr64(ESPC_NUM_PORTS_MACS
) & ESPC_NUM_PORTS_MACS_VAL
;
8564 niudbg(PROBE
, "SPROM: NUM_PORTS_MACS[%d]\n",
8570 static int __devinit
niu_get_and_validate_port(struct niu
*np
)
8572 struct niu_parent
*parent
= np
->parent
;
8575 np
->flags
|= NIU_FLAGS_XMAC
;
8577 if (!parent
->num_ports
) {
8578 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
8579 parent
->num_ports
= 2;
8581 parent
->num_ports
= niu_pci_vpd_get_nports(np
);
8582 if (!parent
->num_ports
) {
8583 /* Fall back to SPROM as last resort.
8584 * This will fail on most cards.
8586 parent
->num_ports
= nr64(ESPC_NUM_PORTS_MACS
) &
8587 ESPC_NUM_PORTS_MACS_VAL
;
8589 /* All of the current probing methods fail on
8590 * Maramba on-board parts.
8592 if (!parent
->num_ports
)
8593 parent
->num_ports
= 4;
8598 niudbg(PROBE
, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
8599 np
->port
, parent
->num_ports
);
8600 if (np
->port
>= parent
->num_ports
)
8606 static int __devinit
phy_record(struct niu_parent
*parent
,
8607 struct phy_probe_info
*p
,
8608 int dev_id_1
, int dev_id_2
, u8 phy_port
,
8611 u32 id
= (dev_id_1
<< 16) | dev_id_2
;
8614 if (dev_id_1
< 0 || dev_id_2
< 0)
8616 if (type
== PHY_TYPE_PMA_PMD
|| type
== PHY_TYPE_PCS
) {
8617 if (((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM8704
) &&
8618 ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_MRVL88X2011
) &&
8619 ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM8706
))
8622 if ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM5464R
)
8626 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8628 (type
== PHY_TYPE_PMA_PMD
?
8630 (type
== PHY_TYPE_PCS
?
8634 if (p
->cur
[type
] >= NIU_MAX_PORTS
) {
8635 printk(KERN_ERR PFX
"Too many PHY ports.\n");
8639 p
->phy_id
[type
][idx
] = id
;
8640 p
->phy_port
[type
][idx
] = phy_port
;
8641 p
->cur
[type
] = idx
+ 1;
8645 static int __devinit
port_has_10g(struct phy_probe_info
*p
, int port
)
8649 for (i
= 0; i
< p
->cur
[PHY_TYPE_PMA_PMD
]; i
++) {
8650 if (p
->phy_port
[PHY_TYPE_PMA_PMD
][i
] == port
)
8653 for (i
= 0; i
< p
->cur
[PHY_TYPE_PCS
]; i
++) {
8654 if (p
->phy_port
[PHY_TYPE_PCS
][i
] == port
)
8661 static int __devinit
count_10g_ports(struct phy_probe_info
*p
, int *lowest
)
8667 for (port
= 8; port
< 32; port
++) {
8668 if (port_has_10g(p
, port
)) {
8678 static int __devinit
count_1g_ports(struct phy_probe_info
*p
, int *lowest
)
8681 if (p
->cur
[PHY_TYPE_MII
])
8682 *lowest
= p
->phy_port
[PHY_TYPE_MII
][0];
8684 return p
->cur
[PHY_TYPE_MII
];
8687 static void __devinit
niu_n2_divide_channels(struct niu_parent
*parent
)
8689 int num_ports
= parent
->num_ports
;
8692 for (i
= 0; i
< num_ports
; i
++) {
8693 parent
->rxchan_per_port
[i
] = (16 / num_ports
);
8694 parent
->txchan_per_port
[i
] = (16 / num_ports
);
8696 pr_info(PFX
"niu%d: Port %u [%u RX chans] "
8699 parent
->rxchan_per_port
[i
],
8700 parent
->txchan_per_port
[i
]);
8704 static void __devinit
niu_divide_channels(struct niu_parent
*parent
,
8705 int num_10g
, int num_1g
)
8707 int num_ports
= parent
->num_ports
;
8708 int rx_chans_per_10g
, rx_chans_per_1g
;
8709 int tx_chans_per_10g
, tx_chans_per_1g
;
8710 int i
, tot_rx
, tot_tx
;
8712 if (!num_10g
|| !num_1g
) {
8713 rx_chans_per_10g
= rx_chans_per_1g
=
8714 (NIU_NUM_RXCHAN
/ num_ports
);
8715 tx_chans_per_10g
= tx_chans_per_1g
=
8716 (NIU_NUM_TXCHAN
/ num_ports
);
8718 rx_chans_per_1g
= NIU_NUM_RXCHAN
/ 8;
8719 rx_chans_per_10g
= (NIU_NUM_RXCHAN
-
8720 (rx_chans_per_1g
* num_1g
)) /
8723 tx_chans_per_1g
= NIU_NUM_TXCHAN
/ 6;
8724 tx_chans_per_10g
= (NIU_NUM_TXCHAN
-
8725 (tx_chans_per_1g
* num_1g
)) /
8729 tot_rx
= tot_tx
= 0;
8730 for (i
= 0; i
< num_ports
; i
++) {
8731 int type
= phy_decode(parent
->port_phy
, i
);
8733 if (type
== PORT_TYPE_10G
) {
8734 parent
->rxchan_per_port
[i
] = rx_chans_per_10g
;
8735 parent
->txchan_per_port
[i
] = tx_chans_per_10g
;
8737 parent
->rxchan_per_port
[i
] = rx_chans_per_1g
;
8738 parent
->txchan_per_port
[i
] = tx_chans_per_1g
;
8740 pr_info(PFX
"niu%d: Port %u [%u RX chans] "
8743 parent
->rxchan_per_port
[i
],
8744 parent
->txchan_per_port
[i
]);
8745 tot_rx
+= parent
->rxchan_per_port
[i
];
8746 tot_tx
+= parent
->txchan_per_port
[i
];
8749 if (tot_rx
> NIU_NUM_RXCHAN
) {
8750 printk(KERN_ERR PFX
"niu%d: Too many RX channels (%d), "
8751 "resetting to one per port.\n",
8752 parent
->index
, tot_rx
);
8753 for (i
= 0; i
< num_ports
; i
++)
8754 parent
->rxchan_per_port
[i
] = 1;
8756 if (tot_tx
> NIU_NUM_TXCHAN
) {
8757 printk(KERN_ERR PFX
"niu%d: Too many TX channels (%d), "
8758 "resetting to one per port.\n",
8759 parent
->index
, tot_tx
);
8760 for (i
= 0; i
< num_ports
; i
++)
8761 parent
->txchan_per_port
[i
] = 1;
8763 if (tot_rx
< NIU_NUM_RXCHAN
|| tot_tx
< NIU_NUM_TXCHAN
) {
8764 printk(KERN_WARNING PFX
"niu%d: Driver bug, wasted channels, "
8766 parent
->index
, tot_rx
, tot_tx
);
8770 static void __devinit
niu_divide_rdc_groups(struct niu_parent
*parent
,
8771 int num_10g
, int num_1g
)
8773 int i
, num_ports
= parent
->num_ports
;
8774 int rdc_group
, rdc_groups_per_port
;
8775 int rdc_channel_base
;
8778 rdc_groups_per_port
= NIU_NUM_RDC_TABLES
/ num_ports
;
8780 rdc_channel_base
= 0;
8782 for (i
= 0; i
< num_ports
; i
++) {
8783 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[i
];
8784 int grp
, num_channels
= parent
->rxchan_per_port
[i
];
8785 int this_channel_offset
;
8787 tp
->first_table_num
= rdc_group
;
8788 tp
->num_tables
= rdc_groups_per_port
;
8789 this_channel_offset
= 0;
8790 for (grp
= 0; grp
< tp
->num_tables
; grp
++) {
8791 struct rdc_table
*rt
= &tp
->tables
[grp
];
8794 pr_info(PFX
"niu%d: Port %d RDC tbl(%d) [ ",
8795 parent
->index
, i
, tp
->first_table_num
+ grp
);
8796 for (slot
= 0; slot
< NIU_RDC_TABLE_SLOTS
; slot
++) {
8797 rt
->rxdma_channel
[slot
] =
8798 rdc_channel_base
+ this_channel_offset
;
8800 printk("%d ", rt
->rxdma_channel
[slot
]);
8802 if (++this_channel_offset
== num_channels
)
8803 this_channel_offset
= 0;
8808 parent
->rdc_default
[i
] = rdc_channel_base
;
8810 rdc_channel_base
+= num_channels
;
8811 rdc_group
+= rdc_groups_per_port
;
8815 static int __devinit
fill_phy_probe_info(struct niu
*np
,
8816 struct niu_parent
*parent
,
8817 struct phy_probe_info
*info
)
8819 unsigned long flags
;
8822 memset(info
, 0, sizeof(*info
));
8824 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8825 niu_lock_parent(np
, flags
);
8827 for (port
= 8; port
< 32; port
++) {
8828 int dev_id_1
, dev_id_2
;
8830 dev_id_1
= mdio_read(np
, port
,
8831 NIU_PMA_PMD_DEV_ADDR
, MII_PHYSID1
);
8832 dev_id_2
= mdio_read(np
, port
,
8833 NIU_PMA_PMD_DEV_ADDR
, MII_PHYSID2
);
8834 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
8838 dev_id_1
= mdio_read(np
, port
,
8839 NIU_PCS_DEV_ADDR
, MII_PHYSID1
);
8840 dev_id_2
= mdio_read(np
, port
,
8841 NIU_PCS_DEV_ADDR
, MII_PHYSID2
);
8842 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
8846 dev_id_1
= mii_read(np
, port
, MII_PHYSID1
);
8847 dev_id_2
= mii_read(np
, port
, MII_PHYSID2
);
8848 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
8853 niu_unlock_parent(np
, flags
);
8858 static int __devinit
walk_phys(struct niu
*np
, struct niu_parent
*parent
)
8860 struct phy_probe_info
*info
= &parent
->phy_probe_info
;
8861 int lowest_10g
, lowest_1g
;
8862 int num_10g
, num_1g
;
8866 num_10g
= num_1g
= 0;
8868 if (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
) ||
8869 !strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) {
8872 parent
->plat_type
= PLAT_TYPE_ATCA_CP3220
;
8873 parent
->num_ports
= 4;
8874 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8875 phy_encode(PORT_TYPE_1G
, 1) |
8876 phy_encode(PORT_TYPE_1G
, 2) |
8877 phy_encode(PORT_TYPE_1G
, 3));
8878 } else if (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) {
8881 parent
->num_ports
= 2;
8882 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8883 phy_encode(PORT_TYPE_10G
, 1));
8884 } else if ((np
->flags
& NIU_FLAGS_XCVR_SERDES
) &&
8885 (parent
->plat_type
== PLAT_TYPE_NIU
)) {
8886 /* this is the Monza case */
8887 if (np
->flags
& NIU_FLAGS_10G
) {
8888 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8889 phy_encode(PORT_TYPE_10G
, 1));
8891 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8892 phy_encode(PORT_TYPE_1G
, 1));
8895 err
= fill_phy_probe_info(np
, parent
, info
);
8899 num_10g
= count_10g_ports(info
, &lowest_10g
);
8900 num_1g
= count_1g_ports(info
, &lowest_1g
);
8902 switch ((num_10g
<< 4) | num_1g
) {
8904 if (lowest_1g
== 10)
8905 parent
->plat_type
= PLAT_TYPE_VF_P0
;
8906 else if (lowest_1g
== 26)
8907 parent
->plat_type
= PLAT_TYPE_VF_P1
;
8909 goto unknown_vg_1g_port
;
8913 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8914 phy_encode(PORT_TYPE_10G
, 1) |
8915 phy_encode(PORT_TYPE_1G
, 2) |
8916 phy_encode(PORT_TYPE_1G
, 3));
8920 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8921 phy_encode(PORT_TYPE_10G
, 1));
8925 val
= phy_encode(PORT_TYPE_10G
, np
->port
);
8929 if (lowest_1g
== 10)
8930 parent
->plat_type
= PLAT_TYPE_VF_P0
;
8931 else if (lowest_1g
== 26)
8932 parent
->plat_type
= PLAT_TYPE_VF_P1
;
8934 goto unknown_vg_1g_port
;
8938 if ((lowest_10g
& 0x7) == 0)
8939 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8940 phy_encode(PORT_TYPE_1G
, 1) |
8941 phy_encode(PORT_TYPE_1G
, 2) |
8942 phy_encode(PORT_TYPE_1G
, 3));
8944 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8945 phy_encode(PORT_TYPE_10G
, 1) |
8946 phy_encode(PORT_TYPE_1G
, 2) |
8947 phy_encode(PORT_TYPE_1G
, 3));
8951 if (lowest_1g
== 10)
8952 parent
->plat_type
= PLAT_TYPE_VF_P0
;
8953 else if (lowest_1g
== 26)
8954 parent
->plat_type
= PLAT_TYPE_VF_P1
;
8956 goto unknown_vg_1g_port
;
8958 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8959 phy_encode(PORT_TYPE_1G
, 1) |
8960 phy_encode(PORT_TYPE_1G
, 2) |
8961 phy_encode(PORT_TYPE_1G
, 3));
8965 printk(KERN_ERR PFX
"Unsupported port config "
8972 parent
->port_phy
= val
;
8974 if (parent
->plat_type
== PLAT_TYPE_NIU
)
8975 niu_n2_divide_channels(parent
);
8977 niu_divide_channels(parent
, num_10g
, num_1g
);
8979 niu_divide_rdc_groups(parent
, num_10g
, num_1g
);
8984 printk(KERN_ERR PFX
"Cannot identify platform type, 1gport=%d\n",
8989 static int __devinit
niu_probe_ports(struct niu
*np
)
8991 struct niu_parent
*parent
= np
->parent
;
8994 niudbg(PROBE
, "niu_probe_ports(): port_phy[%08x]\n",
8997 if (parent
->port_phy
== PORT_PHY_UNKNOWN
) {
8998 err
= walk_phys(np
, parent
);
9002 niu_set_ldg_timer_res(np
, 2);
9003 for (i
= 0; i
<= LDN_MAX
; i
++)
9004 niu_ldn_irq_enable(np
, i
, 0);
9007 if (parent
->port_phy
== PORT_PHY_INVALID
)
9013 static int __devinit
niu_classifier_swstate_init(struct niu
*np
)
9015 struct niu_classifier
*cp
= &np
->clas
;
9017 niudbg(PROBE
, "niu_classifier_swstate_init: num_tcam(%d)\n",
9018 np
->parent
->tcam_num_entries
);
9020 cp
->tcam_top
= (u16
) np
->port
;
9021 cp
->tcam_sz
= np
->parent
->tcam_num_entries
/ np
->parent
->num_ports
;
9022 cp
->h1_init
= 0xffffffff;
9023 cp
->h2_init
= 0xffff;
9025 return fflp_early_init(np
);
9028 static void __devinit
niu_link_config_init(struct niu
*np
)
9030 struct niu_link_config
*lp
= &np
->link_config
;
9032 lp
->advertising
= (ADVERTISED_10baseT_Half
|
9033 ADVERTISED_10baseT_Full
|
9034 ADVERTISED_100baseT_Half
|
9035 ADVERTISED_100baseT_Full
|
9036 ADVERTISED_1000baseT_Half
|
9037 ADVERTISED_1000baseT_Full
|
9038 ADVERTISED_10000baseT_Full
|
9039 ADVERTISED_Autoneg
);
9040 lp
->speed
= lp
->active_speed
= SPEED_INVALID
;
9041 lp
->duplex
= DUPLEX_FULL
;
9042 lp
->active_duplex
= DUPLEX_INVALID
;
9045 lp
->loopback_mode
= LOOPBACK_MAC
;
9046 lp
->active_speed
= SPEED_10000
;
9047 lp
->active_duplex
= DUPLEX_FULL
;
9049 lp
->loopback_mode
= LOOPBACK_DISABLED
;
9053 static int __devinit
niu_init_mac_ipp_pcs_base(struct niu
*np
)
9057 np
->mac_regs
= np
->regs
+ XMAC_PORT0_OFF
;
9058 np
->ipp_off
= 0x00000;
9059 np
->pcs_off
= 0x04000;
9060 np
->xpcs_off
= 0x02000;
9064 np
->mac_regs
= np
->regs
+ XMAC_PORT1_OFF
;
9065 np
->ipp_off
= 0x08000;
9066 np
->pcs_off
= 0x0a000;
9067 np
->xpcs_off
= 0x08000;
9071 np
->mac_regs
= np
->regs
+ BMAC_PORT2_OFF
;
9072 np
->ipp_off
= 0x04000;
9073 np
->pcs_off
= 0x0e000;
9074 np
->xpcs_off
= ~0UL;
9078 np
->mac_regs
= np
->regs
+ BMAC_PORT3_OFF
;
9079 np
->ipp_off
= 0x0c000;
9080 np
->pcs_off
= 0x12000;
9081 np
->xpcs_off
= ~0UL;
9085 dev_err(np
->device
, PFX
"Port %u is invalid, cannot "
9086 "compute MAC block offset.\n", np
->port
);
9093 static void __devinit
niu_try_msix(struct niu
*np
, u8
*ldg_num_map
)
9095 struct msix_entry msi_vec
[NIU_NUM_LDG
];
9096 struct niu_parent
*parent
= np
->parent
;
9097 struct pci_dev
*pdev
= np
->pdev
;
9098 int i
, num_irqs
, err
;
9101 first_ldg
= (NIU_NUM_LDG
/ parent
->num_ports
) * np
->port
;
9102 for (i
= 0; i
< (NIU_NUM_LDG
/ parent
->num_ports
); i
++)
9103 ldg_num_map
[i
] = first_ldg
+ i
;
9105 num_irqs
= (parent
->rxchan_per_port
[np
->port
] +
9106 parent
->txchan_per_port
[np
->port
] +
9107 (np
->port
== 0 ? 3 : 1));
9108 BUG_ON(num_irqs
> (NIU_NUM_LDG
/ parent
->num_ports
));
9111 for (i
= 0; i
< num_irqs
; i
++) {
9112 msi_vec
[i
].vector
= 0;
9113 msi_vec
[i
].entry
= i
;
9116 err
= pci_enable_msix(pdev
, msi_vec
, num_irqs
);
9118 np
->flags
&= ~NIU_FLAGS_MSIX
;
9126 np
->flags
|= NIU_FLAGS_MSIX
;
9127 for (i
= 0; i
< num_irqs
; i
++)
9128 np
->ldg
[i
].irq
= msi_vec
[i
].vector
;
9129 np
->num_ldg
= num_irqs
;
9132 static int __devinit
niu_n2_irq_init(struct niu
*np
, u8
*ldg_num_map
)
9134 #ifdef CONFIG_SPARC64
9135 struct of_device
*op
= np
->op
;
9136 const u32
*int_prop
;
9139 int_prop
= of_get_property(op
->node
, "interrupts", NULL
);
9143 for (i
= 0; i
< op
->num_irqs
; i
++) {
9144 ldg_num_map
[i
] = int_prop
[i
];
9145 np
->ldg
[i
].irq
= op
->irqs
[i
];
9148 np
->num_ldg
= op
->num_irqs
;
9156 static int __devinit
niu_ldg_init(struct niu
*np
)
9158 struct niu_parent
*parent
= np
->parent
;
9159 u8 ldg_num_map
[NIU_NUM_LDG
];
9160 int first_chan
, num_chan
;
9161 int i
, err
, ldg_rotor
;
9165 np
->ldg
[0].irq
= np
->dev
->irq
;
9166 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
9167 err
= niu_n2_irq_init(np
, ldg_num_map
);
9171 niu_try_msix(np
, ldg_num_map
);
9174 for (i
= 0; i
< np
->num_ldg
; i
++) {
9175 struct niu_ldg
*lp
= &np
->ldg
[i
];
9177 netif_napi_add(np
->dev
, &lp
->napi
, niu_poll
, 64);
9180 lp
->ldg_num
= ldg_num_map
[i
];
9181 lp
->timer
= 2; /* XXX */
9183 /* On N2 NIU the firmware has setup the SID mappings so they go
9184 * to the correct values that will route the LDG to the proper
9185 * interrupt in the NCU interrupt table.
9187 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
9188 err
= niu_set_ldg_sid(np
, lp
->ldg_num
, port
, i
);
9194 /* We adopt the LDG assignment ordering used by the N2 NIU
9195 * 'interrupt' properties because that simplifies a lot of
9196 * things. This ordering is:
9199 * MIF (if port zero)
9200 * SYSERR (if port zero)
9207 err
= niu_ldg_assign_ldn(np
, parent
, ldg_num_map
[ldg_rotor
],
9213 if (ldg_rotor
== np
->num_ldg
)
9217 err
= niu_ldg_assign_ldn(np
, parent
,
9218 ldg_num_map
[ldg_rotor
],
9224 if (ldg_rotor
== np
->num_ldg
)
9227 err
= niu_ldg_assign_ldn(np
, parent
,
9228 ldg_num_map
[ldg_rotor
],
9234 if (ldg_rotor
== np
->num_ldg
)
9240 for (i
= 0; i
< port
; i
++)
9241 first_chan
+= parent
->rxchan_per_port
[port
];
9242 num_chan
= parent
->rxchan_per_port
[port
];
9244 for (i
= first_chan
; i
< (first_chan
+ num_chan
); i
++) {
9245 err
= niu_ldg_assign_ldn(np
, parent
,
9246 ldg_num_map
[ldg_rotor
],
9251 if (ldg_rotor
== np
->num_ldg
)
9256 for (i
= 0; i
< port
; i
++)
9257 first_chan
+= parent
->txchan_per_port
[port
];
9258 num_chan
= parent
->txchan_per_port
[port
];
9259 for (i
= first_chan
; i
< (first_chan
+ num_chan
); i
++) {
9260 err
= niu_ldg_assign_ldn(np
, parent
,
9261 ldg_num_map
[ldg_rotor
],
9266 if (ldg_rotor
== np
->num_ldg
)
9273 static void __devexit
niu_ldg_free(struct niu
*np
)
9275 if (np
->flags
& NIU_FLAGS_MSIX
)
9276 pci_disable_msix(np
->pdev
);
9279 static int __devinit
niu_get_of_props(struct niu
*np
)
9281 #ifdef CONFIG_SPARC64
9282 struct net_device
*dev
= np
->dev
;
9283 struct device_node
*dp
;
9284 const char *phy_type
;
9289 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
)
9292 dp
= pci_device_to_OF_node(np
->pdev
);
9294 phy_type
= of_get_property(dp
, "phy-type", &prop_len
);
9296 dev_err(np
->device
, PFX
"%s: OF node lacks "
9297 "phy-type property\n",
9302 if (!strcmp(phy_type
, "none"))
9305 strcpy(np
->vpd
.phy_type
, phy_type
);
9307 if (niu_phy_type_prop_decode(np
, np
->vpd
.phy_type
)) {
9308 dev_err(np
->device
, PFX
"%s: Illegal phy string [%s].\n",
9309 dp
->full_name
, np
->vpd
.phy_type
);
9313 mac_addr
= of_get_property(dp
, "local-mac-address", &prop_len
);
9315 dev_err(np
->device
, PFX
"%s: OF node lacks "
9316 "local-mac-address property\n",
9320 if (prop_len
!= dev
->addr_len
) {
9321 dev_err(np
->device
, PFX
"%s: OF MAC address prop len (%d) "
9323 dp
->full_name
, prop_len
);
9325 memcpy(dev
->perm_addr
, mac_addr
, dev
->addr_len
);
9326 if (!is_valid_ether_addr(&dev
->perm_addr
[0])) {
9329 dev_err(np
->device
, PFX
"%s: OF MAC address is invalid\n",
9331 dev_err(np
->device
, PFX
"%s: [ \n",
9333 for (i
= 0; i
< 6; i
++)
9334 printk("%02x ", dev
->perm_addr
[i
]);
9339 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
9341 model
= of_get_property(dp
, "model", &prop_len
);
9344 strcpy(np
->vpd
.model
, model
);
9352 static int __devinit
niu_get_invariants(struct niu
*np
)
9354 int err
, have_props
;
9357 err
= niu_get_of_props(np
);
9363 err
= niu_init_mac_ipp_pcs_base(np
);
9368 err
= niu_get_and_validate_port(np
);
9373 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
)
9376 nw64(ESPC_PIO_EN
, ESPC_PIO_EN_ENABLE
);
9377 offset
= niu_pci_vpd_offset(np
);
9378 niudbg(PROBE
, "niu_get_invariants: VPD offset [%08x]\n",
9381 niu_pci_vpd_fetch(np
, offset
);
9382 nw64(ESPC_PIO_EN
, 0);
9384 if (np
->flags
& NIU_FLAGS_VPD_VALID
) {
9385 niu_pci_vpd_validate(np
);
9386 err
= niu_get_and_validate_port(np
);
9391 if (!(np
->flags
& NIU_FLAGS_VPD_VALID
)) {
9392 err
= niu_get_and_validate_port(np
);
9395 err
= niu_pci_probe_sprom(np
);
9401 err
= niu_probe_ports(np
);
9407 niu_classifier_swstate_init(np
);
9408 niu_link_config_init(np
);
9410 err
= niu_determine_phy_disposition(np
);
9412 err
= niu_init_link(np
);
9417 static LIST_HEAD(niu_parent_list
);
9418 static DEFINE_MUTEX(niu_parent_lock
);
9419 static int niu_parent_index
;
9421 static ssize_t
show_port_phy(struct device
*dev
,
9422 struct device_attribute
*attr
, char *buf
)
9424 struct platform_device
*plat_dev
= to_platform_device(dev
);
9425 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9426 u32 port_phy
= p
->port_phy
;
9427 char *orig_buf
= buf
;
9430 if (port_phy
== PORT_PHY_UNKNOWN
||
9431 port_phy
== PORT_PHY_INVALID
)
9434 for (i
= 0; i
< p
->num_ports
; i
++) {
9435 const char *type_str
;
9438 type
= phy_decode(port_phy
, i
);
9439 if (type
== PORT_TYPE_10G
)
9444 (i
== 0) ? "%s" : " %s",
9447 buf
+= sprintf(buf
, "\n");
9448 return buf
- orig_buf
;
9451 static ssize_t
show_plat_type(struct device
*dev
,
9452 struct device_attribute
*attr
, char *buf
)
9454 struct platform_device
*plat_dev
= to_platform_device(dev
);
9455 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9456 const char *type_str
;
9458 switch (p
->plat_type
) {
9459 case PLAT_TYPE_ATLAS
:
9465 case PLAT_TYPE_VF_P0
:
9468 case PLAT_TYPE_VF_P1
:
9472 type_str
= "unknown";
9476 return sprintf(buf
, "%s\n", type_str
);
9479 static ssize_t
__show_chan_per_port(struct device
*dev
,
9480 struct device_attribute
*attr
, char *buf
,
9483 struct platform_device
*plat_dev
= to_platform_device(dev
);
9484 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9485 char *orig_buf
= buf
;
9489 arr
= (rx
? p
->rxchan_per_port
: p
->txchan_per_port
);
9491 for (i
= 0; i
< p
->num_ports
; i
++) {
9493 (i
== 0) ? "%d" : " %d",
9496 buf
+= sprintf(buf
, "\n");
9498 return buf
- orig_buf
;
9501 static ssize_t
show_rxchan_per_port(struct device
*dev
,
9502 struct device_attribute
*attr
, char *buf
)
9504 return __show_chan_per_port(dev
, attr
, buf
, 1);
9507 static ssize_t
show_txchan_per_port(struct device
*dev
,
9508 struct device_attribute
*attr
, char *buf
)
9510 return __show_chan_per_port(dev
, attr
, buf
, 1);
9513 static ssize_t
show_num_ports(struct device
*dev
,
9514 struct device_attribute
*attr
, char *buf
)
9516 struct platform_device
*plat_dev
= to_platform_device(dev
);
9517 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9519 return sprintf(buf
, "%d\n", p
->num_ports
);
9522 static struct device_attribute niu_parent_attributes
[] = {
9523 __ATTR(port_phy
, S_IRUGO
, show_port_phy
, NULL
),
9524 __ATTR(plat_type
, S_IRUGO
, show_plat_type
, NULL
),
9525 __ATTR(rxchan_per_port
, S_IRUGO
, show_rxchan_per_port
, NULL
),
9526 __ATTR(txchan_per_port
, S_IRUGO
, show_txchan_per_port
, NULL
),
9527 __ATTR(num_ports
, S_IRUGO
, show_num_ports
, NULL
),
9531 static struct niu_parent
* __devinit
niu_new_parent(struct niu
*np
,
9532 union niu_parent_id
*id
,
9535 struct platform_device
*plat_dev
;
9536 struct niu_parent
*p
;
9539 niudbg(PROBE
, "niu_new_parent: Creating new parent.\n");
9541 plat_dev
= platform_device_register_simple("niu", niu_parent_index
,
9546 for (i
= 0; attr_name(niu_parent_attributes
[i
]); i
++) {
9547 int err
= device_create_file(&plat_dev
->dev
,
9548 &niu_parent_attributes
[i
]);
9550 goto fail_unregister
;
9553 p
= kzalloc(sizeof(*p
), GFP_KERNEL
);
9555 goto fail_unregister
;
9557 p
->index
= niu_parent_index
++;
9559 plat_dev
->dev
.platform_data
= p
;
9560 p
->plat_dev
= plat_dev
;
9562 memcpy(&p
->id
, id
, sizeof(*id
));
9563 p
->plat_type
= ptype
;
9564 INIT_LIST_HEAD(&p
->list
);
9565 atomic_set(&p
->refcnt
, 0);
9566 list_add(&p
->list
, &niu_parent_list
);
9567 spin_lock_init(&p
->lock
);
9569 p
->rxdma_clock_divider
= 7500;
9571 p
->tcam_num_entries
= NIU_PCI_TCAM_ENTRIES
;
9572 if (p
->plat_type
== PLAT_TYPE_NIU
)
9573 p
->tcam_num_entries
= NIU_NONPCI_TCAM_ENTRIES
;
9575 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_SCTP_IPV6
; i
++) {
9576 int index
= i
- CLASS_CODE_USER_PROG1
;
9578 p
->tcam_key
[index
] = TCAM_KEY_TSEL
;
9579 p
->flow_key
[index
] = (FLOW_KEY_IPSA
|
9582 (FLOW_KEY_L4_BYTE12
<<
9583 FLOW_KEY_L4_0_SHIFT
) |
9584 (FLOW_KEY_L4_BYTE12
<<
9585 FLOW_KEY_L4_1_SHIFT
));
9588 for (i
= 0; i
< LDN_MAX
+ 1; i
++)
9589 p
->ldg_map
[i
] = LDG_INVALID
;
9594 platform_device_unregister(plat_dev
);
9598 static struct niu_parent
* __devinit
niu_get_parent(struct niu
*np
,
9599 union niu_parent_id
*id
,
9602 struct niu_parent
*p
, *tmp
;
9603 int port
= np
->port
;
9605 niudbg(PROBE
, "niu_get_parent: platform_type[%u] port[%u]\n",
9608 mutex_lock(&niu_parent_lock
);
9610 list_for_each_entry(tmp
, &niu_parent_list
, list
) {
9611 if (!memcmp(id
, &tmp
->id
, sizeof(*id
))) {
9617 p
= niu_new_parent(np
, id
, ptype
);
9623 sprintf(port_name
, "port%d", port
);
9624 err
= sysfs_create_link(&p
->plat_dev
->dev
.kobj
,
9628 p
->ports
[port
] = np
;
9629 atomic_inc(&p
->refcnt
);
9632 mutex_unlock(&niu_parent_lock
);
9637 static void niu_put_parent(struct niu
*np
)
9639 struct niu_parent
*p
= np
->parent
;
9643 BUG_ON(!p
|| p
->ports
[port
] != np
);
9645 niudbg(PROBE
, "niu_put_parent: port[%u]\n", port
);
9647 sprintf(port_name
, "port%d", port
);
9649 mutex_lock(&niu_parent_lock
);
9651 sysfs_remove_link(&p
->plat_dev
->dev
.kobj
, port_name
);
9653 p
->ports
[port
] = NULL
;
9656 if (atomic_dec_and_test(&p
->refcnt
)) {
9658 platform_device_unregister(p
->plat_dev
);
9661 mutex_unlock(&niu_parent_lock
);
9664 static void *niu_pci_alloc_coherent(struct device
*dev
, size_t size
,
9665 u64
*handle
, gfp_t flag
)
9670 ret
= dma_alloc_coherent(dev
, size
, &dh
, flag
);
9676 static void niu_pci_free_coherent(struct device
*dev
, size_t size
,
9677 void *cpu_addr
, u64 handle
)
9679 dma_free_coherent(dev
, size
, cpu_addr
, handle
);
9682 static u64
niu_pci_map_page(struct device
*dev
, struct page
*page
,
9683 unsigned long offset
, size_t size
,
9684 enum dma_data_direction direction
)
9686 return dma_map_page(dev
, page
, offset
, size
, direction
);
9689 static void niu_pci_unmap_page(struct device
*dev
, u64 dma_address
,
9690 size_t size
, enum dma_data_direction direction
)
9692 dma_unmap_page(dev
, dma_address
, size
, direction
);
9695 static u64
niu_pci_map_single(struct device
*dev
, void *cpu_addr
,
9697 enum dma_data_direction direction
)
9699 return dma_map_single(dev
, cpu_addr
, size
, direction
);
9702 static void niu_pci_unmap_single(struct device
*dev
, u64 dma_address
,
9704 enum dma_data_direction direction
)
9706 dma_unmap_single(dev
, dma_address
, size
, direction
);
9709 static const struct niu_ops niu_pci_ops
= {
9710 .alloc_coherent
= niu_pci_alloc_coherent
,
9711 .free_coherent
= niu_pci_free_coherent
,
9712 .map_page
= niu_pci_map_page
,
9713 .unmap_page
= niu_pci_unmap_page
,
9714 .map_single
= niu_pci_map_single
,
9715 .unmap_single
= niu_pci_unmap_single
,
9718 static void __devinit
niu_driver_version(void)
9720 static int niu_version_printed
;
9722 if (niu_version_printed
++ == 0)
9723 pr_info("%s", version
);
9726 static struct net_device
* __devinit
niu_alloc_and_init(
9727 struct device
*gen_dev
, struct pci_dev
*pdev
,
9728 struct of_device
*op
, const struct niu_ops
*ops
,
9731 struct net_device
*dev
;
9734 dev
= alloc_etherdev_mq(sizeof(struct niu
), NIU_NUM_TXCHAN
);
9736 dev_err(gen_dev
, PFX
"Etherdev alloc failed, aborting.\n");
9740 SET_NETDEV_DEV(dev
, gen_dev
);
9742 np
= netdev_priv(dev
);
9746 np
->device
= gen_dev
;
9749 np
->msg_enable
= niu_debug
;
9751 spin_lock_init(&np
->lock
);
9752 INIT_WORK(&np
->reset_task
, niu_reset_task
);
9759 static const struct net_device_ops niu_netdev_ops
= {
9760 .ndo_open
= niu_open
,
9761 .ndo_stop
= niu_close
,
9762 .ndo_start_xmit
= niu_start_xmit
,
9763 .ndo_get_stats
= niu_get_stats
,
9764 .ndo_set_multicast_list
= niu_set_rx_mode
,
9765 .ndo_validate_addr
= eth_validate_addr
,
9766 .ndo_set_mac_address
= niu_set_mac_addr
,
9767 .ndo_do_ioctl
= niu_ioctl
,
9768 .ndo_tx_timeout
= niu_tx_timeout
,
9769 .ndo_change_mtu
= niu_change_mtu
,
9772 static void __devinit
niu_assign_netdev_ops(struct net_device
*dev
)
9774 dev
->netdev_ops
= &niu_netdev_ops
;
9775 dev
->ethtool_ops
= &niu_ethtool_ops
;
9776 dev
->watchdog_timeo
= NIU_TX_TIMEOUT
;
9779 static void __devinit
niu_device_announce(struct niu
*np
)
9781 struct net_device
*dev
= np
->dev
;
9783 pr_info("%s: NIU Ethernet %pM\n", dev
->name
, dev
->dev_addr
);
9785 if (np
->parent
->plat_type
== PLAT_TYPE_ATCA_CP3220
) {
9786 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9788 (np
->flags
& NIU_FLAGS_XMAC
? "XMAC" : "BMAC"),
9789 (np
->flags
& NIU_FLAGS_10G
? "10G" : "1G"),
9790 (np
->flags
& NIU_FLAGS_FIBER
? "RGMII FIBER" : "SERDES"),
9791 (np
->mac_xcvr
== MAC_XCVR_MII
? "MII" :
9792 (np
->mac_xcvr
== MAC_XCVR_PCS
? "PCS" : "XPCS")),
9795 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9797 (np
->flags
& NIU_FLAGS_XMAC
? "XMAC" : "BMAC"),
9798 (np
->flags
& NIU_FLAGS_10G
? "10G" : "1G"),
9799 (np
->flags
& NIU_FLAGS_FIBER
? "FIBER" :
9800 (np
->flags
& NIU_FLAGS_XCVR_SERDES
? "SERDES" :
9802 (np
->mac_xcvr
== MAC_XCVR_MII
? "MII" :
9803 (np
->mac_xcvr
== MAC_XCVR_PCS
? "PCS" : "XPCS")),
9808 static int __devinit
niu_pci_init_one(struct pci_dev
*pdev
,
9809 const struct pci_device_id
*ent
)
9811 union niu_parent_id parent_id
;
9812 struct net_device
*dev
;
9818 niu_driver_version();
9820 err
= pci_enable_device(pdev
);
9822 dev_err(&pdev
->dev
, PFX
"Cannot enable PCI device, "
9827 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
) ||
9828 !(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
9829 dev_err(&pdev
->dev
, PFX
"Cannot find proper PCI device "
9830 "base addresses, aborting.\n");
9832 goto err_out_disable_pdev
;
9835 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
9837 dev_err(&pdev
->dev
, PFX
"Cannot obtain PCI resources, "
9839 goto err_out_disable_pdev
;
9842 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
9844 dev_err(&pdev
->dev
, PFX
"Cannot find PCI Express capability, "
9846 goto err_out_free_res
;
9849 dev
= niu_alloc_and_init(&pdev
->dev
, pdev
, NULL
,
9850 &niu_pci_ops
, PCI_FUNC(pdev
->devfn
));
9853 goto err_out_free_res
;
9855 np
= netdev_priv(dev
);
9857 memset(&parent_id
, 0, sizeof(parent_id
));
9858 parent_id
.pci
.domain
= pci_domain_nr(pdev
->bus
);
9859 parent_id
.pci
.bus
= pdev
->bus
->number
;
9860 parent_id
.pci
.device
= PCI_SLOT(pdev
->devfn
);
9862 np
->parent
= niu_get_parent(np
, &parent_id
,
9866 goto err_out_free_dev
;
9869 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, &val16
);
9870 val16
&= ~PCI_EXP_DEVCTL_NOSNOOP_EN
;
9871 val16
|= (PCI_EXP_DEVCTL_CERE
|
9872 PCI_EXP_DEVCTL_NFERE
|
9873 PCI_EXP_DEVCTL_FERE
|
9874 PCI_EXP_DEVCTL_URRE
|
9875 PCI_EXP_DEVCTL_RELAX_EN
);
9876 pci_write_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, val16
);
9878 dma_mask
= DMA_44BIT_MASK
;
9879 err
= pci_set_dma_mask(pdev
, dma_mask
);
9881 dev
->features
|= NETIF_F_HIGHDMA
;
9882 err
= pci_set_consistent_dma_mask(pdev
, dma_mask
);
9884 dev_err(&pdev
->dev
, PFX
"Unable to obtain 44 bit "
9885 "DMA for consistent allocations, "
9887 goto err_out_release_parent
;
9890 if (err
|| dma_mask
== DMA_32BIT_MASK
) {
9891 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
9893 dev_err(&pdev
->dev
, PFX
"No usable DMA configuration, "
9895 goto err_out_release_parent
;
9899 dev
->features
|= (NETIF_F_SG
| NETIF_F_HW_CSUM
);
9901 np
->regs
= pci_ioremap_bar(pdev
, 0);
9903 dev_err(&pdev
->dev
, PFX
"Cannot map device registers, "
9906 goto err_out_release_parent
;
9909 pci_set_master(pdev
);
9910 pci_save_state(pdev
);
9912 dev
->irq
= pdev
->irq
;
9914 niu_assign_netdev_ops(dev
);
9916 err
= niu_get_invariants(np
);
9919 dev_err(&pdev
->dev
, PFX
"Problem fetching invariants "
9920 "of chip, aborting.\n");
9921 goto err_out_iounmap
;
9924 err
= register_netdev(dev
);
9926 dev_err(&pdev
->dev
, PFX
"Cannot register net device, "
9928 goto err_out_iounmap
;
9931 pci_set_drvdata(pdev
, dev
);
9933 niu_device_announce(np
);
9943 err_out_release_parent
:
9950 pci_release_regions(pdev
);
9952 err_out_disable_pdev
:
9953 pci_disable_device(pdev
);
9954 pci_set_drvdata(pdev
, NULL
);
9959 static void __devexit
niu_pci_remove_one(struct pci_dev
*pdev
)
9961 struct net_device
*dev
= pci_get_drvdata(pdev
);
9964 struct niu
*np
= netdev_priv(dev
);
9966 unregister_netdev(dev
);
9977 pci_release_regions(pdev
);
9978 pci_disable_device(pdev
);
9979 pci_set_drvdata(pdev
, NULL
);
9983 static int niu_suspend(struct pci_dev
*pdev
, pm_message_t state
)
9985 struct net_device
*dev
= pci_get_drvdata(pdev
);
9986 struct niu
*np
= netdev_priv(dev
);
9987 unsigned long flags
;
9989 if (!netif_running(dev
))
9992 flush_scheduled_work();
9995 del_timer_sync(&np
->timer
);
9997 spin_lock_irqsave(&np
->lock
, flags
);
9998 niu_enable_interrupts(np
, 0);
9999 spin_unlock_irqrestore(&np
->lock
, flags
);
10001 netif_device_detach(dev
);
10003 spin_lock_irqsave(&np
->lock
, flags
);
10005 spin_unlock_irqrestore(&np
->lock
, flags
);
10007 pci_save_state(pdev
);
10012 static int niu_resume(struct pci_dev
*pdev
)
10014 struct net_device
*dev
= pci_get_drvdata(pdev
);
10015 struct niu
*np
= netdev_priv(dev
);
10016 unsigned long flags
;
10019 if (!netif_running(dev
))
10022 pci_restore_state(pdev
);
10024 netif_device_attach(dev
);
10026 spin_lock_irqsave(&np
->lock
, flags
);
10028 err
= niu_init_hw(np
);
10030 np
->timer
.expires
= jiffies
+ HZ
;
10031 add_timer(&np
->timer
);
10032 niu_netif_start(np
);
10035 spin_unlock_irqrestore(&np
->lock
, flags
);
10040 static struct pci_driver niu_pci_driver
= {
10041 .name
= DRV_MODULE_NAME
,
10042 .id_table
= niu_pci_tbl
,
10043 .probe
= niu_pci_init_one
,
10044 .remove
= __devexit_p(niu_pci_remove_one
),
10045 .suspend
= niu_suspend
,
10046 .resume
= niu_resume
,
10049 #ifdef CONFIG_SPARC64
10050 static void *niu_phys_alloc_coherent(struct device
*dev
, size_t size
,
10051 u64
*dma_addr
, gfp_t flag
)
10053 unsigned long order
= get_order(size
);
10054 unsigned long page
= __get_free_pages(flag
, order
);
10058 memset((char *)page
, 0, PAGE_SIZE
<< order
);
10059 *dma_addr
= __pa(page
);
10061 return (void *) page
;
10064 static void niu_phys_free_coherent(struct device
*dev
, size_t size
,
10065 void *cpu_addr
, u64 handle
)
10067 unsigned long order
= get_order(size
);
10069 free_pages((unsigned long) cpu_addr
, order
);
10072 static u64
niu_phys_map_page(struct device
*dev
, struct page
*page
,
10073 unsigned long offset
, size_t size
,
10074 enum dma_data_direction direction
)
10076 return page_to_phys(page
) + offset
;
10079 static void niu_phys_unmap_page(struct device
*dev
, u64 dma_address
,
10080 size_t size
, enum dma_data_direction direction
)
10082 /* Nothing to do. */
10085 static u64
niu_phys_map_single(struct device
*dev
, void *cpu_addr
,
10087 enum dma_data_direction direction
)
10089 return __pa(cpu_addr
);
10092 static void niu_phys_unmap_single(struct device
*dev
, u64 dma_address
,
10094 enum dma_data_direction direction
)
10096 /* Nothing to do. */
10099 static const struct niu_ops niu_phys_ops
= {
10100 .alloc_coherent
= niu_phys_alloc_coherent
,
10101 .free_coherent
= niu_phys_free_coherent
,
10102 .map_page
= niu_phys_map_page
,
10103 .unmap_page
= niu_phys_unmap_page
,
10104 .map_single
= niu_phys_map_single
,
10105 .unmap_single
= niu_phys_unmap_single
,
10108 static unsigned long res_size(struct resource
*r
)
10110 return r
->end
- r
->start
+ 1UL;
10113 static int __devinit
niu_of_probe(struct of_device
*op
,
10114 const struct of_device_id
*match
)
10116 union niu_parent_id parent_id
;
10117 struct net_device
*dev
;
10122 niu_driver_version();
10124 reg
= of_get_property(op
->node
, "reg", NULL
);
10126 dev_err(&op
->dev
, PFX
"%s: No 'reg' property, aborting.\n",
10127 op
->node
->full_name
);
10131 dev
= niu_alloc_and_init(&op
->dev
, NULL
, op
,
10132 &niu_phys_ops
, reg
[0] & 0x1);
10137 np
= netdev_priv(dev
);
10139 memset(&parent_id
, 0, sizeof(parent_id
));
10140 parent_id
.of
= of_get_parent(op
->node
);
10142 np
->parent
= niu_get_parent(np
, &parent_id
,
10146 goto err_out_free_dev
;
10149 dev
->features
|= (NETIF_F_SG
| NETIF_F_HW_CSUM
);
10151 np
->regs
= of_ioremap(&op
->resource
[1], 0,
10152 res_size(&op
->resource
[1]),
10155 dev_err(&op
->dev
, PFX
"Cannot map device registers, "
10158 goto err_out_release_parent
;
10161 np
->vir_regs_1
= of_ioremap(&op
->resource
[2], 0,
10162 res_size(&op
->resource
[2]),
10164 if (!np
->vir_regs_1
) {
10165 dev_err(&op
->dev
, PFX
"Cannot map device vir registers 1, "
10168 goto err_out_iounmap
;
10171 np
->vir_regs_2
= of_ioremap(&op
->resource
[3], 0,
10172 res_size(&op
->resource
[3]),
10174 if (!np
->vir_regs_2
) {
10175 dev_err(&op
->dev
, PFX
"Cannot map device vir registers 2, "
10178 goto err_out_iounmap
;
10181 niu_assign_netdev_ops(dev
);
10183 err
= niu_get_invariants(np
);
10185 if (err
!= -ENODEV
)
10186 dev_err(&op
->dev
, PFX
"Problem fetching invariants "
10187 "of chip, aborting.\n");
10188 goto err_out_iounmap
;
10191 err
= register_netdev(dev
);
10193 dev_err(&op
->dev
, PFX
"Cannot register net device, "
10195 goto err_out_iounmap
;
10198 dev_set_drvdata(&op
->dev
, dev
);
10200 niu_device_announce(np
);
10205 if (np
->vir_regs_1
) {
10206 of_iounmap(&op
->resource
[2], np
->vir_regs_1
,
10207 res_size(&op
->resource
[2]));
10208 np
->vir_regs_1
= NULL
;
10211 if (np
->vir_regs_2
) {
10212 of_iounmap(&op
->resource
[3], np
->vir_regs_2
,
10213 res_size(&op
->resource
[3]));
10214 np
->vir_regs_2
= NULL
;
10218 of_iounmap(&op
->resource
[1], np
->regs
,
10219 res_size(&op
->resource
[1]));
10223 err_out_release_parent
:
10224 niu_put_parent(np
);
10233 static int __devexit
niu_of_remove(struct of_device
*op
)
10235 struct net_device
*dev
= dev_get_drvdata(&op
->dev
);
10238 struct niu
*np
= netdev_priv(dev
);
10240 unregister_netdev(dev
);
10242 if (np
->vir_regs_1
) {
10243 of_iounmap(&op
->resource
[2], np
->vir_regs_1
,
10244 res_size(&op
->resource
[2]));
10245 np
->vir_regs_1
= NULL
;
10248 if (np
->vir_regs_2
) {
10249 of_iounmap(&op
->resource
[3], np
->vir_regs_2
,
10250 res_size(&op
->resource
[3]));
10251 np
->vir_regs_2
= NULL
;
10255 of_iounmap(&op
->resource
[1], np
->regs
,
10256 res_size(&op
->resource
[1]));
10262 niu_put_parent(np
);
10265 dev_set_drvdata(&op
->dev
, NULL
);
10270 static const struct of_device_id niu_match
[] = {
10273 .compatible
= "SUNW,niusl",
10277 MODULE_DEVICE_TABLE(of
, niu_match
);
10279 static struct of_platform_driver niu_of_driver
= {
10281 .match_table
= niu_match
,
10282 .probe
= niu_of_probe
,
10283 .remove
= __devexit_p(niu_of_remove
),
10286 #endif /* CONFIG_SPARC64 */
10288 static int __init
niu_init(void)
10292 BUILD_BUG_ON(PAGE_SIZE
< 4 * 1024);
10294 niu_debug
= netif_msg_init(debug
, NIU_MSG_DEFAULT
);
10296 #ifdef CONFIG_SPARC64
10297 err
= of_register_driver(&niu_of_driver
, &of_bus_type
);
10301 err
= pci_register_driver(&niu_pci_driver
);
10302 #ifdef CONFIG_SPARC64
10304 of_unregister_driver(&niu_of_driver
);
10311 static void __exit
niu_exit(void)
10313 pci_unregister_driver(&niu_pci_driver
);
10314 #ifdef CONFIG_SPARC64
10315 of_unregister_driver(&niu_of_driver
);
10319 module_init(niu_init
);
10320 module_exit(niu_exit
);