drm/nouveau: Add DRM driver for NVIDIA GPUs
[linux-2.6/linux-2.6-openrd.git] / include / drm / i2c / ch7006.h
blob8390b437a1f8e2178ac6f71bf9377f9194ea7bd7
1 /*
2 * Copyright (C) 2009 Francisco Jerez.
3 * All Rights Reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #ifndef __DRM_I2C_CH7006_H__
28 #define __DRM_I2C_CH7006_H__
30 /**
31 * struct ch7006_encoder_params
33 * Describes how the ch7006 is wired up with the GPU. It should be
34 * used as the @params parameter of its @set_config method.
36 * See "http://www.chrontel.com/pdf/7006.pdf" for their precise
37 * meaning.
39 struct ch7006_encoder_params {
40 enum {
41 CH7006_FORMAT_RGB16 = 0,
42 CH7006_FORMAT_YCrCb24m16,
43 CH7006_FORMAT_RGB24m16,
44 CH7006_FORMAT_RGB15,
45 CH7006_FORMAT_RGB24m12C,
46 CH7006_FORMAT_RGB24m12I,
47 CH7006_FORMAT_RGB24m8,
48 CH7006_FORMAT_RGB16m8,
49 CH7006_FORMAT_RGB15m8,
50 CH7006_FORMAT_YCrCb24m8,
51 } input_format;
53 enum {
54 CH7006_CLOCK_SLAVE = 0,
55 CH7006_CLOCK_MASTER,
56 } clock_mode;
58 enum {
59 CH7006_CLOCK_EDGE_NEG = 0,
60 CH7006_CLOCK_EDGE_POS,
61 } clock_edge;
63 int xcm, pcm;
65 enum {
66 CH7006_SYNC_SLAVE = 0,
67 CH7006_SYNC_MASTER,
68 } sync_direction;
70 enum {
71 CH7006_SYNC_SEPARATED = 0,
72 CH7006_SYNC_EMBEDDED,
73 } sync_encoding;
75 enum {
76 CH7006_POUT_1_8V = 0,
77 CH7006_POUT_3_3V,
78 } pout_level;
80 enum {
81 CH7006_ACTIVE_HSYNC = 0,
82 CH7006_ACTIVE_DSTART,
83 } active_detect;
86 #endif