2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #define NV_DEBUG_NOTRACE
27 #include "nouveau_drv.h"
28 #include "nouveau_hw.h"
30 /* these defines are made up */
31 #define NV_CIO_CRE_44_HEADA 0x0
32 #define NV_CIO_CRE_44_HEADB 0x3
33 #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
34 #define LEGACY_I2C_CRT 0x80
35 #define LEGACY_I2C_PANEL 0x81
36 #define LEGACY_I2C_TV 0x82
40 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
41 #define LOG_OLD_VALUE(x)
43 #define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
44 #define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
51 static bool nv_cksum(const uint8_t *data
, unsigned int length
)
54 * There's a few checksums in the BIOS, so here's a generic checking
60 for (i
= 0; i
< length
; i
++)
70 score_vbios(struct drm_device
*dev
, const uint8_t *data
, const bool writeable
)
72 if (!(data
[0] == 0x55 && data
[1] == 0xAA)) {
73 NV_TRACEWARN(dev
, "... BIOS signature not found\n");
77 if (nv_cksum(data
, data
[2] * 512)) {
78 NV_TRACEWARN(dev
, "... BIOS checksum invalid\n");
79 /* if a ro image is somewhat bad, it's probably all rubbish */
80 return writeable
? 2 : 1;
82 NV_TRACE(dev
, "... appears to be valid\n");
87 static void load_vbios_prom(struct drm_device
*dev
, uint8_t *data
)
89 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
90 uint32_t pci_nv_20
, save_pci_nv_20
;
94 if (dev_priv
->card_type
>= NV_50
)
97 pci_nv_20
= NV_PBUS_PCI_NV_20
;
99 /* enable ROM access */
100 save_pci_nv_20
= nvReadMC(dev
, pci_nv_20
);
101 nvWriteMC(dev
, pci_nv_20
,
102 save_pci_nv_20
& ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED
);
104 /* bail if no rom signature */
105 if (nv_rd08(dev
, NV_PROM_OFFSET
) != 0x55 ||
106 nv_rd08(dev
, NV_PROM_OFFSET
+ 1) != 0xaa)
109 /* additional check (see note below) - read PCI record header */
110 pcir_ptr
= nv_rd08(dev
, NV_PROM_OFFSET
+ 0x18) |
111 nv_rd08(dev
, NV_PROM_OFFSET
+ 0x19) << 8;
112 if (nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
) != 'P' ||
113 nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
+ 1) != 'C' ||
114 nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
+ 2) != 'I' ||
115 nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
+ 3) != 'R')
118 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
119 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
120 * each byte. we'll hope pramin has something usable instead
122 for (i
= 0; i
< NV_PROM_SIZE
; i
++)
123 data
[i
] = nv_rd08(dev
, NV_PROM_OFFSET
+ i
);
126 /* disable ROM access */
127 nvWriteMC(dev
, pci_nv_20
,
128 save_pci_nv_20
| NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED
);
131 static void load_vbios_pramin(struct drm_device
*dev
, uint8_t *data
)
133 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
134 uint32_t old_bar0_pramin
= 0;
137 if (dev_priv
->card_type
>= NV_50
) {
138 uint32_t vbios_vram
= (nv_rd32(dev
, 0x619f04) & ~0xff) << 8;
141 vbios_vram
= (nv_rd32(dev
, 0x1700) << 16) + 0xf0000;
143 old_bar0_pramin
= nv_rd32(dev
, 0x1700);
144 nv_wr32(dev
, 0x1700, vbios_vram
>> 16);
147 /* bail if no rom signature */
148 if (nv_rd08(dev
, NV_PRAMIN_OFFSET
) != 0x55 ||
149 nv_rd08(dev
, NV_PRAMIN_OFFSET
+ 1) != 0xaa)
152 for (i
= 0; i
< NV_PROM_SIZE
; i
++)
153 data
[i
] = nv_rd08(dev
, NV_PRAMIN_OFFSET
+ i
);
156 if (dev_priv
->card_type
>= NV_50
)
157 nv_wr32(dev
, 0x1700, old_bar0_pramin
);
160 static void load_vbios_pci(struct drm_device
*dev
, uint8_t *data
)
162 void __iomem
*rom
= NULL
;
166 ret
= pci_enable_rom(dev
->pdev
);
170 rom
= pci_map_rom(dev
->pdev
, &rom_len
);
173 memcpy_fromio(data
, rom
, rom_len
);
174 pci_unmap_rom(dev
->pdev
, rom
);
177 pci_disable_rom(dev
->pdev
);
182 void (*loadbios
)(struct drm_device
*, uint8_t *);
187 static struct methods nv04_methods
[] = {
188 { "PROM", load_vbios_prom
, false },
189 { "PRAMIN", load_vbios_pramin
, true },
190 { "PCIROM", load_vbios_pci
, true },
194 static struct methods nv50_methods
[] = {
195 { "PRAMIN", load_vbios_pramin
, true },
196 { "PROM", load_vbios_prom
, false },
197 { "PCIROM", load_vbios_pci
, true },
201 static bool NVShadowVBIOS(struct drm_device
*dev
, uint8_t *data
)
203 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
204 struct methods
*methods
, *method
;
208 method
= nv04_methods
;
209 while (method
->loadbios
) {
210 if (!strcasecmp(nouveau_vbios
, method
->desc
))
215 if (method
->loadbios
) {
216 NV_INFO(dev
, "Attempting to use BIOS image from %s\n",
219 method
->loadbios(dev
, data
);
220 if (score_vbios(dev
, data
, method
->rw
))
224 NV_ERROR(dev
, "VBIOS source \'%s\' invalid\n", nouveau_vbios
);
227 if (dev_priv
->card_type
< NV_50
)
228 methods
= nv04_methods
;
230 methods
= nv50_methods
;
233 while (method
->loadbios
) {
234 NV_TRACE(dev
, "Attempting to load BIOS image from %s\n",
236 data
[0] = data
[1] = 0; /* avoid reuse of previous image */
237 method
->loadbios(dev
, data
);
238 method
->score
= score_vbios(dev
, data
, method
->rw
);
239 if (method
->score
== testscore
)
244 while (--testscore
> 0) {
246 while (method
->loadbios
) {
247 if (method
->score
== testscore
) {
248 NV_TRACE(dev
, "Using BIOS image from %s\n",
250 method
->loadbios(dev
, data
);
257 NV_ERROR(dev
, "No valid BIOS image found\n");
261 struct init_tbl_entry
{
266 int length_multiplier
;
267 bool (*handler
)(struct nvbios
*, uint16_t, struct init_exec
*);
276 static int parse_init_table(struct nvbios
*, unsigned int, struct init_exec
*);
278 #define MACRO_INDEX_SIZE 2
280 #define CONDITION_SIZE 12
281 #define IO_FLAG_CONDITION_SIZE 9
282 #define IO_CONDITION_SIZE 5
283 #define MEM_INIT_SIZE 66
285 static void still_alive(void)
294 munge_reg(struct nvbios
*bios
, uint32_t reg
)
296 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
297 struct dcb_entry
*dcbent
= bios
->display
.output
;
299 if (dev_priv
->card_type
< NV_50
)
302 if (reg
& 0x40000000) {
305 reg
+= (ffs(dcbent
->or) - 1) * 0x800;
306 if ((reg
& 0x20000000) && !(dcbent
->sorconf
.link
& 1))
315 valid_reg(struct nvbios
*bios
, uint32_t reg
)
317 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
318 struct drm_device
*dev
= bios
->dev
;
320 /* C51 has misaligned regs on purpose. Marvellous */
321 if (reg
& 0x2 || (reg
& 0x1 && dev_priv
->VBIOS
.pub
.chip_version
!= 0x51)) {
322 NV_ERROR(dev
, "========== misaligned reg 0x%08X ==========\n",
327 * Warn on C51 regs that have not been verified accessible in
330 if (reg
& 0x1 && dev_priv
->VBIOS
.pub
.chip_version
== 0x51 &&
331 reg
!= 0x130d && reg
!= 0x1311 && reg
!= 0x60081d)
332 NV_WARN(dev
, "=== C51 misaligned reg 0x%08X not verified ===\n",
335 /* Trust the init scripts on G80 */
336 if (dev_priv
->card_type
>= NV_50
)
339 #define WITHIN(x, y, z) ((x >= y) && (x < y + z))
340 if (WITHIN(reg
, NV_PMC_OFFSET
, NV_PMC_SIZE
))
342 if (WITHIN(reg
, NV_PBUS_OFFSET
, NV_PBUS_SIZE
))
344 if (WITHIN(reg
, NV_PFIFO_OFFSET
, NV_PFIFO_SIZE
))
346 if (dev_priv
->VBIOS
.pub
.chip_version
>= 0x30 &&
347 (WITHIN(reg
, 0x4000, 0x600) || reg
== 0x00004600))
349 if (dev_priv
->VBIOS
.pub
.chip_version
>= 0x40 &&
350 WITHIN(reg
, 0xc000, 0x48))
352 if (dev_priv
->VBIOS
.pub
.chip_version
>= 0x17 && reg
== 0x0000d204)
354 if (dev_priv
->VBIOS
.pub
.chip_version
>= 0x40) {
355 if (reg
== 0x00011014 || reg
== 0x00020328)
357 if (WITHIN(reg
, 0x88000, NV_PBUS_SIZE
)) /* new PBUS */
360 if (WITHIN(reg
, NV_PFB_OFFSET
, NV_PFB_SIZE
))
362 if (WITHIN(reg
, NV_PEXTDEV_OFFSET
, NV_PEXTDEV_SIZE
))
364 if (WITHIN(reg
, NV_PCRTC0_OFFSET
, NV_PCRTC0_SIZE
* 2))
366 if (WITHIN(reg
, NV_PRAMDAC0_OFFSET
, NV_PRAMDAC0_SIZE
* 2))
368 if (dev_priv
->VBIOS
.pub
.chip_version
>= 0x17 && reg
== 0x0070fff0)
370 if (dev_priv
->VBIOS
.pub
.chip_version
== 0x51 &&
371 WITHIN(reg
, NV_PRAMIN_OFFSET
, NV_PRAMIN_SIZE
))
375 NV_ERROR(dev
, "========== unknown reg 0x%08X ==========\n", reg
);
381 valid_idx_port(struct nvbios
*bios
, uint16_t port
)
383 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
384 struct drm_device
*dev
= bios
->dev
;
387 * If adding more ports here, the read/write functions below will need
388 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
389 * used for the port in question
391 if (dev_priv
->card_type
< NV_50
) {
392 if (port
== NV_CIO_CRX__COLOR
)
394 if (port
== NV_VIO_SRX
)
397 if (port
== NV_CIO_CRX__COLOR
)
401 NV_ERROR(dev
, "========== unknown indexed io port 0x%04X ==========\n",
408 valid_port(struct nvbios
*bios
, uint16_t port
)
410 struct drm_device
*dev
= bios
->dev
;
413 * If adding more ports here, the read/write functions below will need
414 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
415 * used for the port in question
417 if (port
== NV_VIO_VSE2
)
420 NV_ERROR(dev
, "========== unknown io port 0x%04X ==========\n", port
);
426 bios_rd32(struct nvbios
*bios
, uint32_t reg
)
430 reg
= munge_reg(bios
, reg
);
431 if (!valid_reg(bios
, reg
))
435 * C51 sometimes uses regs with bit0 set in the address. For these
436 * cases there should exist a translation in a BIOS table to an IO
437 * port address which the BIOS uses for accessing the reg
439 * These only seem to appear for the power control regs to a flat panel,
440 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
441 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
442 * suspend-resume mmio trace from a C51 will be required to see if this
443 * is true for the power microcode in 0x14.., or whether the direct IO
444 * port access method is needed
449 data
= nv_rd32(bios
->dev
, reg
);
451 BIOSLOG(bios
, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg
, data
);
457 bios_wr32(struct nvbios
*bios
, uint32_t reg
, uint32_t data
)
459 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
461 reg
= munge_reg(bios
, reg
);
462 if (!valid_reg(bios
, reg
))
465 /* see note in bios_rd32 */
469 LOG_OLD_VALUE(bios_rd32(bios
, reg
));
470 BIOSLOG(bios
, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg
, data
);
472 if (dev_priv
->VBIOS
.execute
) {
474 nv_wr32(bios
->dev
, reg
, data
);
479 bios_idxprt_rd(struct nvbios
*bios
, uint16_t port
, uint8_t index
)
481 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
482 struct drm_device
*dev
= bios
->dev
;
485 if (!valid_idx_port(bios
, port
))
488 if (dev_priv
->card_type
< NV_50
) {
489 if (port
== NV_VIO_SRX
)
490 data
= NVReadVgaSeq(dev
, bios
->state
.crtchead
, index
);
491 else /* assume NV_CIO_CRX__COLOR */
492 data
= NVReadVgaCrtc(dev
, bios
->state
.crtchead
, index
);
496 data32
= bios_rd32(bios
, NV50_PDISPLAY_VGACRTC(index
& ~3));
497 data
= (data32
>> ((index
& 3) << 3)) & 0xff;
500 BIOSLOG(bios
, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
501 "Head: 0x%02X, Data: 0x%02X\n",
502 port
, index
, bios
->state
.crtchead
, data
);
507 bios_idxprt_wr(struct nvbios
*bios
, uint16_t port
, uint8_t index
, uint8_t data
)
509 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
510 struct drm_device
*dev
= bios
->dev
;
512 if (!valid_idx_port(bios
, port
))
516 * The current head is maintained in the nvbios member state.crtchead.
517 * We trap changes to CR44 and update the head variable and hence the
518 * register set written.
519 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
520 * of the write, and to head1 after the write
522 if (port
== NV_CIO_CRX__COLOR
&& index
== NV_CIO_CRE_44
&&
523 data
!= NV_CIO_CRE_44_HEADB
)
524 bios
->state
.crtchead
= 0;
526 LOG_OLD_VALUE(bios_idxprt_rd(bios
, port
, index
));
527 BIOSLOG(bios
, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
528 "Head: 0x%02X, Data: 0x%02X\n",
529 port
, index
, bios
->state
.crtchead
, data
);
531 if (bios
->execute
&& dev_priv
->card_type
< NV_50
) {
533 if (port
== NV_VIO_SRX
)
534 NVWriteVgaSeq(dev
, bios
->state
.crtchead
, index
, data
);
535 else /* assume NV_CIO_CRX__COLOR */
536 NVWriteVgaCrtc(dev
, bios
->state
.crtchead
, index
, data
);
539 uint32_t data32
, shift
= (index
& 3) << 3;
543 data32
= bios_rd32(bios
, NV50_PDISPLAY_VGACRTC(index
& ~3));
544 data32
&= ~(0xff << shift
);
545 data32
|= (data
<< shift
);
546 bios_wr32(bios
, NV50_PDISPLAY_VGACRTC(index
& ~3), data32
);
549 if (port
== NV_CIO_CRX__COLOR
&&
550 index
== NV_CIO_CRE_44
&& data
== NV_CIO_CRE_44_HEADB
)
551 bios
->state
.crtchead
= 1;
555 bios_port_rd(struct nvbios
*bios
, uint16_t port
)
557 uint8_t data
, head
= bios
->state
.crtchead
;
559 if (!valid_port(bios
, port
))
562 data
= NVReadPRMVIO(bios
->dev
, head
, NV_PRMVIO0_OFFSET
+ port
);
564 BIOSLOG(bios
, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
571 bios_port_wr(struct nvbios
*bios
, uint16_t port
, uint8_t data
)
573 int head
= bios
->state
.crtchead
;
575 if (!valid_port(bios
, port
))
578 LOG_OLD_VALUE(bios_port_rd(bios
, port
));
579 BIOSLOG(bios
, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
586 NVWritePRMVIO(bios
->dev
, head
, NV_PRMVIO0_OFFSET
+ port
, data
);
590 io_flag_condition_met(struct nvbios
*bios
, uint16_t offset
, uint8_t cond
)
593 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
594 * for the CRTC index; 1 byte for the mask to apply to the value
595 * retrieved from the CRTC; 1 byte for the shift right to apply to the
596 * masked CRTC value; 2 bytes for the offset to the flag array, to
597 * which the shifted value is added; 1 byte for the mask applied to the
598 * value read from the flag array; and 1 byte for the value to compare
599 * against the masked byte from the flag table.
602 uint16_t condptr
= bios
->io_flag_condition_tbl_ptr
+ cond
* IO_FLAG_CONDITION_SIZE
;
603 uint16_t crtcport
= ROM16(bios
->data
[condptr
]);
604 uint8_t crtcindex
= bios
->data
[condptr
+ 2];
605 uint8_t mask
= bios
->data
[condptr
+ 3];
606 uint8_t shift
= bios
->data
[condptr
+ 4];
607 uint16_t flagarray
= ROM16(bios
->data
[condptr
+ 5]);
608 uint8_t flagarraymask
= bios
->data
[condptr
+ 7];
609 uint8_t cmpval
= bios
->data
[condptr
+ 8];
612 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
613 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
615 offset
, crtcport
, crtcindex
, mask
, shift
, flagarray
, flagarraymask
, cmpval
);
617 data
= bios_idxprt_rd(bios
, crtcport
, crtcindex
);
619 data
= bios
->data
[flagarray
+ ((data
& mask
) >> shift
)];
620 data
&= flagarraymask
;
622 BIOSLOG(bios
, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
623 offset
, data
, cmpval
);
625 return (data
== cmpval
);
629 bios_condition_met(struct nvbios
*bios
, uint16_t offset
, uint8_t cond
)
632 * The condition table entry has 4 bytes for the address of the
633 * register to check, 4 bytes for a mask to apply to the register and
634 * 4 for a test comparison value
637 uint16_t condptr
= bios
->condition_tbl_ptr
+ cond
* CONDITION_SIZE
;
638 uint32_t reg
= ROM32(bios
->data
[condptr
]);
639 uint32_t mask
= ROM32(bios
->data
[condptr
+ 4]);
640 uint32_t cmpval
= ROM32(bios
->data
[condptr
+ 8]);
643 BIOSLOG(bios
, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
644 offset
, cond
, reg
, mask
);
646 data
= bios_rd32(bios
, reg
) & mask
;
648 BIOSLOG(bios
, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
649 offset
, data
, cmpval
);
651 return (data
== cmpval
);
655 io_condition_met(struct nvbios
*bios
, uint16_t offset
, uint8_t cond
)
658 * The IO condition entry has 2 bytes for the IO port address; 1 byte
659 * for the index to write to io_port; 1 byte for the mask to apply to
660 * the byte read from io_port+1; and 1 byte for the value to compare
661 * against the masked byte.
664 uint16_t condptr
= bios
->io_condition_tbl_ptr
+ cond
* IO_CONDITION_SIZE
;
665 uint16_t io_port
= ROM16(bios
->data
[condptr
]);
666 uint8_t port_index
= bios
->data
[condptr
+ 2];
667 uint8_t mask
= bios
->data
[condptr
+ 3];
668 uint8_t cmpval
= bios
->data
[condptr
+ 4];
670 uint8_t data
= bios_idxprt_rd(bios
, io_port
, port_index
) & mask
;
672 BIOSLOG(bios
, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
673 offset
, data
, cmpval
);
675 return (data
== cmpval
);
679 nv50_pll_set(struct drm_device
*dev
, uint32_t reg
, uint32_t clk
)
681 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
682 uint32_t reg0
= nv_rd32(dev
, reg
+ 0);
683 uint32_t reg1
= nv_rd32(dev
, reg
+ 4);
684 struct nouveau_pll_vals pll
;
685 struct pll_lims pll_limits
;
688 ret
= get_pll_limits(dev
, reg
, &pll_limits
);
692 clk
= nouveau_calc_pll_mnp(dev
, &pll_limits
, clk
, &pll
);
696 reg0
= (reg0
& 0xfff8ffff) | (pll
.log2P
<< 16);
697 reg1
= (reg1
& 0xffff0000) | (pll
.N1
<< 8) | pll
.M1
;
699 if (dev_priv
->VBIOS
.execute
) {
701 nv_wr32(dev
, reg
+ 4, reg1
);
702 nv_wr32(dev
, reg
+ 0, reg0
);
709 setPLL(struct nvbios
*bios
, uint32_t reg
, uint32_t clk
)
711 struct drm_device
*dev
= bios
->dev
;
712 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
714 struct pll_lims pll_lim
;
715 struct nouveau_pll_vals pllvals
;
718 if (dev_priv
->card_type
>= NV_50
)
719 return nv50_pll_set(dev
, reg
, clk
);
721 /* high regs (such as in the mac g5 table) are not -= 4 */
722 ret
= get_pll_limits(dev
, reg
> 0x405c ? reg
: reg
- 4, &pll_lim
);
726 clk
= nouveau_calc_pll_mnp(dev
, &pll_lim
, clk
, &pllvals
);
732 nouveau_hw_setpll(dev
, reg
, &pllvals
);
738 static int dcb_entry_idx_from_crtchead(struct drm_device
*dev
)
740 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
741 struct nvbios
*bios
= &dev_priv
->VBIOS
;
744 * For the results of this function to be correct, CR44 must have been
745 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
746 * and the DCB table parsed, before the script calling the function is
747 * run. run_digital_op_script is example of how to do such setup
750 uint8_t dcb_entry
= NVReadVgaCrtc5758(dev
, bios
->state
.crtchead
, 0);
752 if (dcb_entry
> bios
->bdcb
.dcb
.entries
) {
753 NV_ERROR(dev
, "CR58 doesn't have a valid DCB entry currently "
754 "(%02X)\n", dcb_entry
);
755 dcb_entry
= 0x7f; /* unused / invalid marker */
761 static struct nouveau_i2c_chan
*
762 init_i2c_device_find(struct drm_device
*dev
, int i2c_index
)
764 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
765 struct bios_parsed_dcb
*bdcb
= &dev_priv
->VBIOS
.bdcb
;
767 if (i2c_index
== 0xff) {
768 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
769 int idx
= dcb_entry_idx_from_crtchead(dev
), shift
= 0;
770 int default_indices
= bdcb
->i2c_default_indices
;
772 if (idx
!= 0x7f && bdcb
->dcb
.entry
[idx
].i2c_upper_default
)
775 i2c_index
= (default_indices
>> shift
) & 0xf;
777 if (i2c_index
== 0x80) /* g80+ */
778 i2c_index
= bdcb
->i2c_default_indices
& 0xf;
780 return nouveau_i2c_find(dev
, i2c_index
);
783 static uint32_t get_tmds_index_reg(struct drm_device
*dev
, uint8_t mlv
)
786 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
787 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
788 * CR58 for CR57 = 0 to index a table of offsets to the basic
790 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
791 * CR58 for CR57 = 0 to index a table of offsets to the basic
792 * 0x6808b0 address, and then flip the offset by 8.
795 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
796 const int pramdac_offset
[13] = {
797 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
798 const uint32_t pramdac_table
[4] = {
799 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
802 int dcb_entry
, dacoffset
;
804 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
805 dcb_entry
= dcb_entry_idx_from_crtchead(dev
);
806 if (dcb_entry
== 0x7f)
808 dacoffset
= pramdac_offset
[
809 dev_priv
->VBIOS
.bdcb
.dcb
.entry
[dcb_entry
].or];
812 return 0x6808b0 + dacoffset
;
814 if (mlv
> ARRAY_SIZE(pramdac_table
)) {
815 NV_ERROR(dev
, "Magic Lookup Value too big (%02X)\n",
819 return pramdac_table
[mlv
];
824 init_io_restrict_prog(struct nvbios
*bios
, uint16_t offset
,
825 struct init_exec
*iexec
)
828 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
830 * offset (8 bit): opcode
831 * offset + 1 (16 bit): CRTC port
832 * offset + 3 (8 bit): CRTC index
833 * offset + 4 (8 bit): mask
834 * offset + 5 (8 bit): shift
835 * offset + 6 (8 bit): count
836 * offset + 7 (32 bit): register
837 * offset + 11 (32 bit): configuration 1
840 * Starting at offset + 11 there are "count" 32 bit values.
841 * To find out which value to use read index "CRTC index" on "CRTC
842 * port", AND this value with "mask" and then bit shift right "shift"
843 * bits. Read the appropriate value using this index and write to
847 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
848 uint8_t crtcindex
= bios
->data
[offset
+ 3];
849 uint8_t mask
= bios
->data
[offset
+ 4];
850 uint8_t shift
= bios
->data
[offset
+ 5];
851 uint8_t count
= bios
->data
[offset
+ 6];
852 uint32_t reg
= ROM32(bios
->data
[offset
+ 7]);
859 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
860 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
861 offset
, crtcport
, crtcindex
, mask
, shift
, count
, reg
);
863 config
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) >> shift
;
864 if (config
> count
) {
866 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
867 offset
, config
, count
);
871 configval
= ROM32(bios
->data
[offset
+ 11 + config
* 4]);
873 BIOSLOG(bios
, "0x%04X: Writing config %02X\n", offset
, config
);
875 bios_wr32(bios
, reg
, configval
);
881 init_repeat(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
884 * INIT_REPEAT opcode: 0x33 ('3')
886 * offset (8 bit): opcode
887 * offset + 1 (8 bit): count
889 * Execute script following this opcode up to INIT_REPEAT_END
893 uint8_t count
= bios
->data
[offset
+ 1];
896 /* no iexec->execute check by design */
898 BIOSLOG(bios
, "0x%04X: Repeating following segment %d times\n",
901 iexec
->repeat
= true;
904 * count - 1, as the script block will execute once when we leave this
905 * opcode -- this is compatible with bios behaviour as:
906 * a) the block is always executed at least once, even if count == 0
907 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
910 for (i
= 0; i
< count
- 1; i
++)
911 parse_init_table(bios
, offset
+ 2, iexec
);
913 iexec
->repeat
= false;
919 init_io_restrict_pll(struct nvbios
*bios
, uint16_t offset
,
920 struct init_exec
*iexec
)
923 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
925 * offset (8 bit): opcode
926 * offset + 1 (16 bit): CRTC port
927 * offset + 3 (8 bit): CRTC index
928 * offset + 4 (8 bit): mask
929 * offset + 5 (8 bit): shift
930 * offset + 6 (8 bit): IO flag condition index
931 * offset + 7 (8 bit): count
932 * offset + 8 (32 bit): register
933 * offset + 12 (16 bit): frequency 1
936 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
937 * Set PLL register "register" to coefficients for frequency n,
938 * selected by reading index "CRTC index" of "CRTC port" ANDed with
939 * "mask" and shifted right by "shift".
941 * If "IO flag condition index" > 0, and condition met, double
942 * frequency before setting it.
945 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
946 uint8_t crtcindex
= bios
->data
[offset
+ 3];
947 uint8_t mask
= bios
->data
[offset
+ 4];
948 uint8_t shift
= bios
->data
[offset
+ 5];
949 int8_t io_flag_condition_idx
= bios
->data
[offset
+ 6];
950 uint8_t count
= bios
->data
[offset
+ 7];
951 uint32_t reg
= ROM32(bios
->data
[offset
+ 8]);
958 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
959 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
960 "Count: 0x%02X, Reg: 0x%08X\n",
961 offset
, crtcport
, crtcindex
, mask
, shift
,
962 io_flag_condition_idx
, count
, reg
);
964 config
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) >> shift
;
965 if (config
> count
) {
967 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
968 offset
, config
, count
);
972 freq
= ROM16(bios
->data
[offset
+ 12 + config
* 2]);
974 if (io_flag_condition_idx
> 0) {
975 if (io_flag_condition_met(bios
, offset
, io_flag_condition_idx
)) {
976 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- "
977 "frequency doubled\n", offset
);
980 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- "
981 "frequency unchanged\n", offset
);
984 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
985 offset
, reg
, config
, freq
);
987 setPLL(bios
, reg
, freq
* 10);
993 init_end_repeat(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
996 * INIT_END_REPEAT opcode: 0x36 ('6')
998 * offset (8 bit): opcode
1000 * Marks the end of the block for INIT_REPEAT to repeat
1003 /* no iexec->execute check by design */
1006 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1007 * we're not in repeat mode
1016 init_copy(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1019 * INIT_COPY opcode: 0x37 ('7')
1021 * offset (8 bit): opcode
1022 * offset + 1 (32 bit): register
1023 * offset + 5 (8 bit): shift
1024 * offset + 6 (8 bit): srcmask
1025 * offset + 7 (16 bit): CRTC port
1026 * offset + 9 (8 bit): CRTC index
1027 * offset + 10 (8 bit): mask
1029 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1030 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1034 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
1035 uint8_t shift
= bios
->data
[offset
+ 5];
1036 uint8_t srcmask
= bios
->data
[offset
+ 6];
1037 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 7]);
1038 uint8_t crtcindex
= bios
->data
[offset
+ 9];
1039 uint8_t mask
= bios
->data
[offset
+ 10];
1043 if (!iexec
->execute
)
1046 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1047 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1048 offset
, reg
, shift
, srcmask
, crtcport
, crtcindex
, mask
);
1050 data
= bios_rd32(bios
, reg
);
1055 data
<<= (0x100 - shift
);
1059 crtcdata
= bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
;
1060 crtcdata
|= (uint8_t)data
;
1061 bios_idxprt_wr(bios
, crtcport
, crtcindex
, crtcdata
);
1067 init_not(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1070 * INIT_NOT opcode: 0x38 ('8')
1072 * offset (8 bit): opcode
1074 * Invert the current execute / no-execute condition (i.e. "else")
1077 BIOSLOG(bios
, "0x%04X: ------ Skipping following commands ------\n", offset
);
1079 BIOSLOG(bios
, "0x%04X: ------ Executing following commands ------\n", offset
);
1081 iexec
->execute
= !iexec
->execute
;
1086 init_io_flag_condition(struct nvbios
*bios
, uint16_t offset
,
1087 struct init_exec
*iexec
)
1090 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1092 * offset (8 bit): opcode
1093 * offset + 1 (8 bit): condition number
1095 * Check condition "condition number" in the IO flag condition table.
1096 * If condition not met skip subsequent opcodes until condition is
1097 * inverted (INIT_NOT), or we hit INIT_RESUME
1100 uint8_t cond
= bios
->data
[offset
+ 1];
1102 if (!iexec
->execute
)
1105 if (io_flag_condition_met(bios
, offset
, cond
))
1106 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
1108 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
1109 iexec
->execute
= false;
1116 init_idx_addr_latched(struct nvbios
*bios
, uint16_t offset
,
1117 struct init_exec
*iexec
)
1120 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1122 * offset (8 bit): opcode
1123 * offset + 1 (32 bit): control register
1124 * offset + 5 (32 bit): data register
1125 * offset + 9 (32 bit): mask
1126 * offset + 13 (32 bit): data
1127 * offset + 17 (8 bit): count
1128 * offset + 18 (8 bit): address 1
1129 * offset + 19 (8 bit): data 1
1132 * For each of "count" address and data pairs, write "data n" to
1133 * "data register", read the current value of "control register",
1134 * and write it back once ANDed with "mask", ORed with "data",
1135 * and ORed with "address n"
1138 uint32_t controlreg
= ROM32(bios
->data
[offset
+ 1]);
1139 uint32_t datareg
= ROM32(bios
->data
[offset
+ 5]);
1140 uint32_t mask
= ROM32(bios
->data
[offset
+ 9]);
1141 uint32_t data
= ROM32(bios
->data
[offset
+ 13]);
1142 uint8_t count
= bios
->data
[offset
+ 17];
1146 if (!iexec
->execute
)
1149 BIOSLOG(bios
, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1150 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1151 offset
, controlreg
, datareg
, mask
, data
, count
);
1153 for (i
= 0; i
< count
; i
++) {
1154 uint8_t instaddress
= bios
->data
[offset
+ 18 + i
* 2];
1155 uint8_t instdata
= bios
->data
[offset
+ 19 + i
* 2];
1157 BIOSLOG(bios
, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1158 offset
, instaddress
, instdata
);
1160 bios_wr32(bios
, datareg
, instdata
);
1161 value
= bios_rd32(bios
, controlreg
) & mask
;
1163 value
|= instaddress
;
1164 bios_wr32(bios
, controlreg
, value
);
1171 init_io_restrict_pll2(struct nvbios
*bios
, uint16_t offset
,
1172 struct init_exec
*iexec
)
1175 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1177 * offset (8 bit): opcode
1178 * offset + 1 (16 bit): CRTC port
1179 * offset + 3 (8 bit): CRTC index
1180 * offset + 4 (8 bit): mask
1181 * offset + 5 (8 bit): shift
1182 * offset + 6 (8 bit): count
1183 * offset + 7 (32 bit): register
1184 * offset + 11 (32 bit): frequency 1
1187 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1188 * Set PLL register "register" to coefficients for frequency n,
1189 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1190 * "mask" and shifted right by "shift".
1193 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
1194 uint8_t crtcindex
= bios
->data
[offset
+ 3];
1195 uint8_t mask
= bios
->data
[offset
+ 4];
1196 uint8_t shift
= bios
->data
[offset
+ 5];
1197 uint8_t count
= bios
->data
[offset
+ 6];
1198 uint32_t reg
= ROM32(bios
->data
[offset
+ 7]);
1202 if (!iexec
->execute
)
1205 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1206 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1207 offset
, crtcport
, crtcindex
, mask
, shift
, count
, reg
);
1212 config
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) >> shift
;
1213 if (config
> count
) {
1215 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1216 offset
, config
, count
);
1220 freq
= ROM32(bios
->data
[offset
+ 11 + config
* 4]);
1222 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1223 offset
, reg
, config
, freq
);
1225 setPLL(bios
, reg
, freq
);
1231 init_pll2(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1234 * INIT_PLL2 opcode: 0x4B ('K')
1236 * offset (8 bit): opcode
1237 * offset + 1 (32 bit): register
1238 * offset + 5 (32 bit): freq
1240 * Set PLL register "register" to coefficients for frequency "freq"
1243 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
1244 uint32_t freq
= ROM32(bios
->data
[offset
+ 5]);
1246 if (!iexec
->execute
)
1249 BIOSLOG(bios
, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1252 setPLL(bios
, reg
, freq
);
1257 init_i2c_byte(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1260 * INIT_I2C_BYTE opcode: 0x4C ('L')
1262 * offset (8 bit): opcode
1263 * offset + 1 (8 bit): DCB I2C table entry index
1264 * offset + 2 (8 bit): I2C slave address
1265 * offset + 3 (8 bit): count
1266 * offset + 4 (8 bit): I2C register 1
1267 * offset + 5 (8 bit): mask 1
1268 * offset + 6 (8 bit): data 1
1271 * For each of "count" registers given by "I2C register n" on the device
1272 * addressed by "I2C slave address" on the I2C bus given by
1273 * "DCB I2C table entry index", read the register, AND the result with
1274 * "mask n" and OR it with "data n" before writing it back to the device
1277 uint8_t i2c_index
= bios
->data
[offset
+ 1];
1278 uint8_t i2c_address
= bios
->data
[offset
+ 2];
1279 uint8_t count
= bios
->data
[offset
+ 3];
1280 struct nouveau_i2c_chan
*chan
;
1284 if (!iexec
->execute
)
1287 BIOSLOG(bios
, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1289 offset
, i2c_index
, i2c_address
, count
);
1291 chan
= init_i2c_device_find(bios
->dev
, i2c_index
);
1295 for (i
= 0; i
< count
; i
++) {
1296 uint8_t i2c_reg
= bios
->data
[offset
+ 4 + i
* 3];
1297 uint8_t mask
= bios
->data
[offset
+ 5 + i
* 3];
1298 uint8_t data
= bios
->data
[offset
+ 6 + i
* 3];
1301 msg
.addr
= i2c_address
;
1302 msg
.flags
= I2C_M_RD
;
1305 if (i2c_transfer(&chan
->adapter
, &msg
, 1) != 1)
1308 BIOSLOG(bios
, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1309 "Mask: 0x%02X, Data: 0x%02X\n",
1310 offset
, i2c_reg
, value
, mask
, data
);
1312 value
= (value
& mask
) | data
;
1314 if (bios
->execute
) {
1315 msg
.addr
= i2c_address
;
1319 if (i2c_transfer(&chan
->adapter
, &msg
, 1) != 1)
1328 init_zm_i2c_byte(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1331 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1333 * offset (8 bit): opcode
1334 * offset + 1 (8 bit): DCB I2C table entry index
1335 * offset + 2 (8 bit): I2C slave address
1336 * offset + 3 (8 bit): count
1337 * offset + 4 (8 bit): I2C register 1
1338 * offset + 5 (8 bit): data 1
1341 * For each of "count" registers given by "I2C register n" on the device
1342 * addressed by "I2C slave address" on the I2C bus given by
1343 * "DCB I2C table entry index", set the register to "data n"
1346 uint8_t i2c_index
= bios
->data
[offset
+ 1];
1347 uint8_t i2c_address
= bios
->data
[offset
+ 2];
1348 uint8_t count
= bios
->data
[offset
+ 3];
1349 struct nouveau_i2c_chan
*chan
;
1353 if (!iexec
->execute
)
1356 BIOSLOG(bios
, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1358 offset
, i2c_index
, i2c_address
, count
);
1360 chan
= init_i2c_device_find(bios
->dev
, i2c_index
);
1364 for (i
= 0; i
< count
; i
++) {
1365 uint8_t i2c_reg
= bios
->data
[offset
+ 4 + i
* 2];
1366 uint8_t data
= bios
->data
[offset
+ 5 + i
* 2];
1368 BIOSLOG(bios
, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1369 offset
, i2c_reg
, data
);
1371 if (bios
->execute
) {
1372 msg
.addr
= i2c_address
;
1376 if (i2c_transfer(&chan
->adapter
, &msg
, 1) != 1)
1385 init_zm_i2c(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1388 * INIT_ZM_I2C opcode: 0x4E ('N')
1390 * offset (8 bit): opcode
1391 * offset + 1 (8 bit): DCB I2C table entry index
1392 * offset + 2 (8 bit): I2C slave address
1393 * offset + 3 (8 bit): count
1394 * offset + 4 (8 bit): data 1
1397 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1398 * address" on the I2C bus given by "DCB I2C table entry index"
1401 uint8_t i2c_index
= bios
->data
[offset
+ 1];
1402 uint8_t i2c_address
= bios
->data
[offset
+ 2];
1403 uint8_t count
= bios
->data
[offset
+ 3];
1404 struct nouveau_i2c_chan
*chan
;
1409 if (!iexec
->execute
)
1412 BIOSLOG(bios
, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1414 offset
, i2c_index
, i2c_address
, count
);
1416 chan
= init_i2c_device_find(bios
->dev
, i2c_index
);
1420 for (i
= 0; i
< count
; i
++) {
1421 data
[i
] = bios
->data
[offset
+ 4 + i
];
1423 BIOSLOG(bios
, "0x%04X: Data: 0x%02X\n", offset
, data
[i
]);
1426 if (bios
->execute
) {
1427 msg
.addr
= i2c_address
;
1431 if (i2c_transfer(&chan
->adapter
, &msg
, 1) != 1)
1439 init_tmds(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1442 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1444 * offset (8 bit): opcode
1445 * offset + 1 (8 bit): magic lookup value
1446 * offset + 2 (8 bit): TMDS address
1447 * offset + 3 (8 bit): mask
1448 * offset + 4 (8 bit): data
1450 * Read the data reg for TMDS address "TMDS address", AND it with mask
1451 * and OR it with data, then write it back
1452 * "magic lookup value" determines which TMDS base address register is
1453 * used -- see get_tmds_index_reg()
1456 uint8_t mlv
= bios
->data
[offset
+ 1];
1457 uint32_t tmdsaddr
= bios
->data
[offset
+ 2];
1458 uint8_t mask
= bios
->data
[offset
+ 3];
1459 uint8_t data
= bios
->data
[offset
+ 4];
1460 uint32_t reg
, value
;
1462 if (!iexec
->execute
)
1465 BIOSLOG(bios
, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1466 "Mask: 0x%02X, Data: 0x%02X\n",
1467 offset
, mlv
, tmdsaddr
, mask
, data
);
1469 reg
= get_tmds_index_reg(bios
->dev
, mlv
);
1473 bios_wr32(bios
, reg
,
1474 tmdsaddr
| NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE
);
1475 value
= (bios_rd32(bios
, reg
+ 4) & mask
) | data
;
1476 bios_wr32(bios
, reg
+ 4, value
);
1477 bios_wr32(bios
, reg
, tmdsaddr
);
1483 init_zm_tmds_group(struct nvbios
*bios
, uint16_t offset
,
1484 struct init_exec
*iexec
)
1487 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1489 * offset (8 bit): opcode
1490 * offset + 1 (8 bit): magic lookup value
1491 * offset + 2 (8 bit): count
1492 * offset + 3 (8 bit): addr 1
1493 * offset + 4 (8 bit): data 1
1496 * For each of "count" TMDS address and data pairs write "data n" to
1497 * "addr n". "magic lookup value" determines which TMDS base address
1498 * register is used -- see get_tmds_index_reg()
1501 uint8_t mlv
= bios
->data
[offset
+ 1];
1502 uint8_t count
= bios
->data
[offset
+ 2];
1506 if (!iexec
->execute
)
1509 BIOSLOG(bios
, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1510 offset
, mlv
, count
);
1512 reg
= get_tmds_index_reg(bios
->dev
, mlv
);
1516 for (i
= 0; i
< count
; i
++) {
1517 uint8_t tmdsaddr
= bios
->data
[offset
+ 3 + i
* 2];
1518 uint8_t tmdsdata
= bios
->data
[offset
+ 4 + i
* 2];
1520 bios_wr32(bios
, reg
+ 4, tmdsdata
);
1521 bios_wr32(bios
, reg
, tmdsaddr
);
1528 init_cr_idx_adr_latch(struct nvbios
*bios
, uint16_t offset
,
1529 struct init_exec
*iexec
)
1532 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1534 * offset (8 bit): opcode
1535 * offset + 1 (8 bit): CRTC index1
1536 * offset + 2 (8 bit): CRTC index2
1537 * offset + 3 (8 bit): baseaddr
1538 * offset + 4 (8 bit): count
1539 * offset + 5 (8 bit): data 1
1542 * For each of "count" address and data pairs, write "baseaddr + n" to
1543 * "CRTC index1" and "data n" to "CRTC index2"
1544 * Once complete, restore initial value read from "CRTC index1"
1546 uint8_t crtcindex1
= bios
->data
[offset
+ 1];
1547 uint8_t crtcindex2
= bios
->data
[offset
+ 2];
1548 uint8_t baseaddr
= bios
->data
[offset
+ 3];
1549 uint8_t count
= bios
->data
[offset
+ 4];
1550 uint8_t oldaddr
, data
;
1553 if (!iexec
->execute
)
1556 BIOSLOG(bios
, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1557 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1558 offset
, crtcindex1
, crtcindex2
, baseaddr
, count
);
1560 oldaddr
= bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, crtcindex1
);
1562 for (i
= 0; i
< count
; i
++) {
1563 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex1
,
1565 data
= bios
->data
[offset
+ 5 + i
];
1566 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex2
, data
);
1569 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex1
, oldaddr
);
1575 init_cr(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1578 * INIT_CR opcode: 0x52 ('R')
1580 * offset (8 bit): opcode
1581 * offset + 1 (8 bit): CRTC index
1582 * offset + 2 (8 bit): mask
1583 * offset + 3 (8 bit): data
1585 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1586 * data back to "CRTC index"
1589 uint8_t crtcindex
= bios
->data
[offset
+ 1];
1590 uint8_t mask
= bios
->data
[offset
+ 2];
1591 uint8_t data
= bios
->data
[offset
+ 3];
1594 if (!iexec
->execute
)
1597 BIOSLOG(bios
, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1598 offset
, crtcindex
, mask
, data
);
1600 value
= bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, crtcindex
) & mask
;
1602 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex
, value
);
1608 init_zm_cr(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1611 * INIT_ZM_CR opcode: 0x53 ('S')
1613 * offset (8 bit): opcode
1614 * offset + 1 (8 bit): CRTC index
1615 * offset + 2 (8 bit): value
1617 * Assign "value" to CRTC register with index "CRTC index".
1620 uint8_t crtcindex
= ROM32(bios
->data
[offset
+ 1]);
1621 uint8_t data
= bios
->data
[offset
+ 2];
1623 if (!iexec
->execute
)
1626 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex
, data
);
1632 init_zm_cr_group(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1635 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1637 * offset (8 bit): opcode
1638 * offset + 1 (8 bit): count
1639 * offset + 2 (8 bit): CRTC index 1
1640 * offset + 3 (8 bit): value 1
1643 * For "count", assign "value n" to CRTC register with index
1647 uint8_t count
= bios
->data
[offset
+ 1];
1650 if (!iexec
->execute
)
1653 for (i
= 0; i
< count
; i
++)
1654 init_zm_cr(bios
, offset
+ 2 + 2 * i
- 1, iexec
);
1660 init_condition_time(struct nvbios
*bios
, uint16_t offset
,
1661 struct init_exec
*iexec
)
1664 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1666 * offset (8 bit): opcode
1667 * offset + 1 (8 bit): condition number
1668 * offset + 2 (8 bit): retries / 50
1670 * Check condition "condition number" in the condition table.
1671 * Bios code then sleeps for 2ms if the condition is not met, and
1672 * repeats up to "retries" times, but on one C51 this has proved
1673 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1674 * this, and bail after "retries" times, or 2s, whichever is less.
1675 * If still not met after retries, clear execution flag for this table.
1678 uint8_t cond
= bios
->data
[offset
+ 1];
1679 uint16_t retries
= bios
->data
[offset
+ 2] * 50;
1682 if (!iexec
->execute
)
1688 BIOSLOG(bios
, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1689 offset
, cond
, retries
);
1691 if (!bios
->execute
) /* avoid 2s delays when "faking" execution */
1694 for (cnt
= 0; cnt
< retries
; cnt
++) {
1695 if (bios_condition_met(bios
, offset
, cond
)) {
1696 BIOSLOG(bios
, "0x%04X: Condition met, continuing\n",
1700 BIOSLOG(bios
, "0x%04X: "
1701 "Condition not met, sleeping for 20ms\n",
1707 if (!bios_condition_met(bios
, offset
, cond
)) {
1709 "0x%04X: Condition still not met after %dms, "
1710 "skipping following opcodes\n", offset
, 20 * retries
);
1711 iexec
->execute
= false;
1718 init_zm_reg_sequence(struct nvbios
*bios
, uint16_t offset
,
1719 struct init_exec
*iexec
)
1722 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1724 * offset (8 bit): opcode
1725 * offset + 1 (32 bit): base register
1726 * offset + 5 (8 bit): count
1727 * offset + 6 (32 bit): value 1
1730 * Starting at offset + 6 there are "count" 32 bit values.
1731 * For "count" iterations set "base register" + 4 * current_iteration
1732 * to "value current_iteration"
1735 uint32_t basereg
= ROM32(bios
->data
[offset
+ 1]);
1736 uint32_t count
= bios
->data
[offset
+ 5];
1739 if (!iexec
->execute
)
1742 BIOSLOG(bios
, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1743 offset
, basereg
, count
);
1745 for (i
= 0; i
< count
; i
++) {
1746 uint32_t reg
= basereg
+ i
* 4;
1747 uint32_t data
= ROM32(bios
->data
[offset
+ 6 + i
* 4]);
1749 bios_wr32(bios
, reg
, data
);
1756 init_sub_direct(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1759 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1761 * offset (8 bit): opcode
1762 * offset + 1 (16 bit): subroutine offset (in bios)
1764 * Calls a subroutine that will execute commands until INIT_DONE
1768 uint16_t sub_offset
= ROM16(bios
->data
[offset
+ 1]);
1770 if (!iexec
->execute
)
1773 BIOSLOG(bios
, "0x%04X: Executing subroutine at 0x%04X\n",
1774 offset
, sub_offset
);
1776 parse_init_table(bios
, sub_offset
, iexec
);
1778 BIOSLOG(bios
, "0x%04X: End of 0x%04X subroutine\n", offset
, sub_offset
);
1784 init_copy_nv_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1787 * INIT_COPY_NV_REG opcode: 0x5F ('_')
1789 * offset (8 bit): opcode
1790 * offset + 1 (32 bit): src reg
1791 * offset + 5 (8 bit): shift
1792 * offset + 6 (32 bit): src mask
1793 * offset + 10 (32 bit): xor
1794 * offset + 14 (32 bit): dst reg
1795 * offset + 18 (32 bit): dst mask
1797 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1798 * "src mask", then XOR with "xor". Write this OR'd with
1799 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1802 uint32_t srcreg
= *((uint32_t *)(&bios
->data
[offset
+ 1]));
1803 uint8_t shift
= bios
->data
[offset
+ 5];
1804 uint32_t srcmask
= *((uint32_t *)(&bios
->data
[offset
+ 6]));
1805 uint32_t xor = *((uint32_t *)(&bios
->data
[offset
+ 10]));
1806 uint32_t dstreg
= *((uint32_t *)(&bios
->data
[offset
+ 14]));
1807 uint32_t dstmask
= *((uint32_t *)(&bios
->data
[offset
+ 18]));
1808 uint32_t srcvalue
, dstvalue
;
1810 if (!iexec
->execute
)
1813 BIOSLOG(bios
, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1814 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1815 offset
, srcreg
, shift
, srcmask
, xor, dstreg
, dstmask
);
1817 srcvalue
= bios_rd32(bios
, srcreg
);
1822 srcvalue
<<= (0x100 - shift
);
1824 srcvalue
= (srcvalue
& srcmask
) ^ xor;
1826 dstvalue
= bios_rd32(bios
, dstreg
) & dstmask
;
1828 bios_wr32(bios
, dstreg
, dstvalue
| srcvalue
);
1834 init_zm_index_io(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1837 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1839 * offset (8 bit): opcode
1840 * offset + 1 (16 bit): CRTC port
1841 * offset + 3 (8 bit): CRTC index
1842 * offset + 4 (8 bit): data
1844 * Write "data" to index "CRTC index" of "CRTC port"
1846 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
1847 uint8_t crtcindex
= bios
->data
[offset
+ 3];
1848 uint8_t data
= bios
->data
[offset
+ 4];
1850 if (!iexec
->execute
)
1853 bios_idxprt_wr(bios
, crtcport
, crtcindex
, data
);
1859 init_compute_mem(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1862 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
1864 * offset (8 bit): opcode
1866 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1867 * that the hardware can correctly calculate how much VRAM it has
1868 * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C))
1870 * The implementation of this opcode in general consists of two parts:
1871 * 1) determination of the memory bus width
1872 * 2) determination of how many of the card's RAM pads have ICs attached
1874 * 1) is done by a cunning combination of writes to offsets 0x1c and
1875 * 0x3c in the framebuffer, and seeing whether the written values are
1876 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1878 * 2) is done by a cunning combination of writes to an offset slightly
1879 * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing
1880 * if the test pattern can be read back. This then affects bits 12-15 of
1883 * In this context a "cunning combination" may include multiple reads
1884 * and writes to varying locations, often alternating the test pattern
1885 * and 0, doubtless to make sure buffers are filled, residual charges
1886 * on tracks are removed etc.
1888 * Unfortunately, the "cunning combination"s mentioned above, and the
1889 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1892 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1893 * we started was correct, and use that instead
1896 /* no iexec->execute check by design */
1899 * This appears to be a NOP on G8x chipsets, both io logs of the VBIOS
1900 * and kmmio traces of the binary driver POSTing the card show nothing
1901 * being done for this opcode. why is it still listed in the table?!
1904 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
1906 if (dev_priv
->card_type
>= NV_50
)
1910 * On every card I've seen, this step gets done for us earlier in
1912 uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01);
1913 bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20);
1917 * This also has probably been done in the scripts, but an mmio trace of
1918 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write)
1920 bios_wr32(bios
, NV_PFB_REFCTRL
, NV_PFB_REFCTRL_VALID_1
);
1922 /* write back the saved configuration value */
1923 bios_wr32(bios
, NV_PFB_CFG0
, bios
->state
.saved_nv_pfb_cfg0
);
1929 init_reset(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1932 * INIT_RESET opcode: 0x65 ('e')
1934 * offset (8 bit): opcode
1935 * offset + 1 (32 bit): register
1936 * offset + 5 (32 bit): value1
1937 * offset + 9 (32 bit): value2
1939 * Assign "value1" to "register", then assign "value2" to "register"
1942 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
1943 uint32_t value1
= ROM32(bios
->data
[offset
+ 5]);
1944 uint32_t value2
= ROM32(bios
->data
[offset
+ 9]);
1945 uint32_t pci_nv_19
, pci_nv_20
;
1947 /* no iexec->execute check by design */
1949 pci_nv_19
= bios_rd32(bios
, NV_PBUS_PCI_NV_19
);
1950 bios_wr32(bios
, NV_PBUS_PCI_NV_19
, 0);
1951 bios_wr32(bios
, reg
, value1
);
1955 bios_wr32(bios
, reg
, value2
);
1956 bios_wr32(bios
, NV_PBUS_PCI_NV_19
, pci_nv_19
);
1958 pci_nv_20
= bios_rd32(bios
, NV_PBUS_PCI_NV_20
);
1959 pci_nv_20
&= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED
; /* 0xfffffffe */
1960 bios_wr32(bios
, NV_PBUS_PCI_NV_20
, pci_nv_20
);
1966 init_configure_mem(struct nvbios
*bios
, uint16_t offset
,
1967 struct init_exec
*iexec
)
1970 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
1972 * offset (8 bit): opcode
1974 * Equivalent to INIT_DONE on bios version 3 or greater.
1975 * For early bios versions, sets up the memory registers, using values
1976 * taken from the memory init table
1979 /* no iexec->execute check by design */
1981 uint16_t meminitoffs
= bios
->legacy
.mem_init_tbl_ptr
+ MEM_INIT_SIZE
* (bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_SCRATCH4__INDEX
) >> 4);
1982 uint16_t seqtbloffs
= bios
->legacy
.sdr_seq_tbl_ptr
, meminitdata
= meminitoffs
+ 6;
1985 if (bios
->major_version
> 2)
1988 bios_idxprt_wr(bios
, NV_VIO_SRX
, NV_VIO_SR_CLOCK_INDEX
, bios_idxprt_rd(
1989 bios
, NV_VIO_SRX
, NV_VIO_SR_CLOCK_INDEX
) | 0x20);
1991 if (bios
->data
[meminitoffs
] & 1)
1992 seqtbloffs
= bios
->legacy
.ddr_seq_tbl_ptr
;
1994 for (reg
= ROM32(bios
->data
[seqtbloffs
]);
1996 reg
= ROM32(bios
->data
[seqtbloffs
+= 4])) {
2000 data
= NV_PFB_PRE_CMD_PRECHARGE
;
2003 data
= NV_PFB_PAD_CKE_NORMAL
;
2006 data
= NV_PFB_REF_CMD_REFRESH
;
2009 data
= ROM32(bios
->data
[meminitdata
]);
2011 if (data
== 0xffffffff)
2015 bios_wr32(bios
, reg
, data
);
2022 init_configure_clk(struct nvbios
*bios
, uint16_t offset
,
2023 struct init_exec
*iexec
)
2026 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2028 * offset (8 bit): opcode
2030 * Equivalent to INIT_DONE on bios version 3 or greater.
2031 * For early bios versions, sets up the NVClk and MClk PLLs, using
2032 * values taken from the memory init table
2035 /* no iexec->execute check by design */
2037 uint16_t meminitoffs
= bios
->legacy
.mem_init_tbl_ptr
+ MEM_INIT_SIZE
* (bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_SCRATCH4__INDEX
) >> 4);
2040 if (bios
->major_version
> 2)
2043 clock
= ROM16(bios
->data
[meminitoffs
+ 4]) * 10;
2044 setPLL(bios
, NV_PRAMDAC_NVPLL_COEFF
, clock
);
2046 clock
= ROM16(bios
->data
[meminitoffs
+ 2]) * 10;
2047 if (bios
->data
[meminitoffs
] & 1) /* DDR */
2049 setPLL(bios
, NV_PRAMDAC_MPLL_COEFF
, clock
);
2055 init_configure_preinit(struct nvbios
*bios
, uint16_t offset
,
2056 struct init_exec
*iexec
)
2059 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2061 * offset (8 bit): opcode
2063 * Equivalent to INIT_DONE on bios version 3 or greater.
2064 * For early bios versions, does early init, loading ram and crystal
2065 * configuration from straps into CR3C
2068 /* no iexec->execute check by design */
2070 uint32_t straps
= bios_rd32(bios
, NV_PEXTDEV_BOOT_0
);
2071 uint8_t cr3c
= ((straps
<< 2) & 0xf0) | (straps
& (1 << 6));
2073 if (bios
->major_version
> 2)
2076 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
,
2077 NV_CIO_CRE_SCRATCH4__INDEX
, cr3c
);
2083 init_io(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2086 * INIT_IO opcode: 0x69 ('i')
2088 * offset (8 bit): opcode
2089 * offset + 1 (16 bit): CRTC port
2090 * offset + 3 (8 bit): mask
2091 * offset + 4 (8 bit): data
2093 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2096 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
2097 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
2098 uint8_t mask
= bios
->data
[offset
+ 3];
2099 uint8_t data
= bios
->data
[offset
+ 4];
2101 if (!iexec
->execute
)
2104 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2105 offset
, crtcport
, mask
, data
);
2108 * I have no idea what this does, but NVIDIA do this magic sequence
2109 * in the places where this INIT_IO happens..
2111 if (dev_priv
->card_type
>= NV_50
&& crtcport
== 0x3c3 && data
== 1) {
2114 bios_wr32(bios
, 0x614100, (bios_rd32(
2115 bios
, 0x614100) & 0x0fffffff) | 0x00800000);
2117 bios_wr32(bios
, 0x00e18c, bios_rd32(
2118 bios
, 0x00e18c) | 0x00020000);
2120 bios_wr32(bios
, 0x614900, (bios_rd32(
2121 bios
, 0x614900) & 0x0fffffff) | 0x00800000);
2123 bios_wr32(bios
, 0x000200, bios_rd32(
2124 bios
, 0x000200) & ~0x40000000);
2128 bios_wr32(bios
, 0x00e18c, bios_rd32(
2129 bios
, 0x00e18c) & ~0x00020000);
2131 bios_wr32(bios
, 0x000200, bios_rd32(
2132 bios
, 0x000200) | 0x40000000);
2134 bios_wr32(bios
, 0x614100, 0x00800018);
2135 bios_wr32(bios
, 0x614900, 0x00800018);
2139 bios_wr32(bios
, 0x614100, 0x10000018);
2140 bios_wr32(bios
, 0x614900, 0x10000018);
2142 for (i
= 0; i
< 3; i
++)
2143 bios_wr32(bios
, 0x614280 + (i
*0x800), bios_rd32(
2144 bios
, 0x614280 + (i
*0x800)) & 0xf0f0f0f0);
2146 for (i
= 0; i
< 2; i
++)
2147 bios_wr32(bios
, 0x614300 + (i
*0x800), bios_rd32(
2148 bios
, 0x614300 + (i
*0x800)) & 0xfffff0f0);
2150 for (i
= 0; i
< 3; i
++)
2151 bios_wr32(bios
, 0x614380 + (i
*0x800), bios_rd32(
2152 bios
, 0x614380 + (i
*0x800)) & 0xfffff0f0);
2154 for (i
= 0; i
< 2; i
++)
2155 bios_wr32(bios
, 0x614200 + (i
*0x800), bios_rd32(
2156 bios
, 0x614200 + (i
*0x800)) & 0xfffffff0);
2158 for (i
= 0; i
< 2; i
++)
2159 bios_wr32(bios
, 0x614108 + (i
*0x800), bios_rd32(
2160 bios
, 0x614108 + (i
*0x800)) & 0x0fffffff);
2164 bios_port_wr(bios
, crtcport
, (bios_port_rd(bios
, crtcport
) & mask
) |
2170 init_sub(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2173 * INIT_SUB opcode: 0x6B ('k')
2175 * offset (8 bit): opcode
2176 * offset + 1 (8 bit): script number
2178 * Execute script number "script number", as a subroutine
2181 uint8_t sub
= bios
->data
[offset
+ 1];
2183 if (!iexec
->execute
)
2186 BIOSLOG(bios
, "0x%04X: Calling script %d\n", offset
, sub
);
2188 parse_init_table(bios
,
2189 ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ sub
* 2]),
2192 BIOSLOG(bios
, "0x%04X: End of script %d\n", offset
, sub
);
2198 init_ram_condition(struct nvbios
*bios
, uint16_t offset
,
2199 struct init_exec
*iexec
)
2202 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2204 * offset (8 bit): opcode
2205 * offset + 1 (8 bit): mask
2206 * offset + 2 (8 bit): cmpval
2208 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".
2209 * If condition not met skip subsequent opcodes until condition is
2210 * inverted (INIT_NOT), or we hit INIT_RESUME
2213 uint8_t mask
= bios
->data
[offset
+ 1];
2214 uint8_t cmpval
= bios
->data
[offset
+ 2];
2217 if (!iexec
->execute
)
2220 data
= bios_rd32(bios
, NV_PFB_BOOT_0
) & mask
;
2222 BIOSLOG(bios
, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2223 offset
, data
, cmpval
);
2226 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
2228 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
2229 iexec
->execute
= false;
2236 init_nv_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2239 * INIT_NV_REG opcode: 0x6E ('n')
2241 * offset (8 bit): opcode
2242 * offset + 1 (32 bit): register
2243 * offset + 5 (32 bit): mask
2244 * offset + 9 (32 bit): data
2246 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2249 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2250 uint32_t mask
= ROM32(bios
->data
[offset
+ 5]);
2251 uint32_t data
= ROM32(bios
->data
[offset
+ 9]);
2253 if (!iexec
->execute
)
2256 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2257 offset
, reg
, mask
, data
);
2259 bios_wr32(bios
, reg
, (bios_rd32(bios
, reg
) & mask
) | data
);
2265 init_macro(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2268 * INIT_MACRO opcode: 0x6F ('o')
2270 * offset (8 bit): opcode
2271 * offset + 1 (8 bit): macro number
2273 * Look up macro index "macro number" in the macro index table.
2274 * The macro index table entry has 1 byte for the index in the macro
2275 * table, and 1 byte for the number of times to repeat the macro.
2276 * The macro table entry has 4 bytes for the register address and
2277 * 4 bytes for the value to write to that register
2280 uint8_t macro_index_tbl_idx
= bios
->data
[offset
+ 1];
2281 uint16_t tmp
= bios
->macro_index_tbl_ptr
+ (macro_index_tbl_idx
* MACRO_INDEX_SIZE
);
2282 uint8_t macro_tbl_idx
= bios
->data
[tmp
];
2283 uint8_t count
= bios
->data
[tmp
+ 1];
2287 if (!iexec
->execute
)
2290 BIOSLOG(bios
, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2292 offset
, macro_index_tbl_idx
, macro_tbl_idx
, count
);
2294 for (i
= 0; i
< count
; i
++) {
2295 uint16_t macroentryptr
= bios
->macro_tbl_ptr
+ (macro_tbl_idx
+ i
) * MACRO_SIZE
;
2297 reg
= ROM32(bios
->data
[macroentryptr
]);
2298 data
= ROM32(bios
->data
[macroentryptr
+ 4]);
2300 bios_wr32(bios
, reg
, data
);
2307 init_done(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2310 * INIT_DONE opcode: 0x71 ('q')
2312 * offset (8 bit): opcode
2314 * End the current script
2317 /* mild retval abuse to stop parsing this table */
2322 init_resume(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2325 * INIT_RESUME opcode: 0x72 ('r')
2327 * offset (8 bit): opcode
2329 * End the current execute / no-execute condition
2335 iexec
->execute
= true;
2336 BIOSLOG(bios
, "0x%04X: ---- Executing following commands ----\n", offset
);
2342 init_time(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2345 * INIT_TIME opcode: 0x74 ('t')
2347 * offset (8 bit): opcode
2348 * offset + 1 (16 bit): time
2350 * Sleep for "time" microseconds.
2353 unsigned time
= ROM16(bios
->data
[offset
+ 1]);
2355 if (!iexec
->execute
)
2358 BIOSLOG(bios
, "0x%04X: Sleeping for 0x%04X microseconds\n",
2364 msleep((time
+ 900) / 1000);
2370 init_condition(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2373 * INIT_CONDITION opcode: 0x75 ('u')
2375 * offset (8 bit): opcode
2376 * offset + 1 (8 bit): condition number
2378 * Check condition "condition number" in the condition table.
2379 * If condition not met skip subsequent opcodes until condition is
2380 * inverted (INIT_NOT), or we hit INIT_RESUME
2383 uint8_t cond
= bios
->data
[offset
+ 1];
2385 if (!iexec
->execute
)
2388 BIOSLOG(bios
, "0x%04X: Condition: 0x%02X\n", offset
, cond
);
2390 if (bios_condition_met(bios
, offset
, cond
))
2391 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
2393 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
2394 iexec
->execute
= false;
2401 init_io_condition(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2404 * INIT_IO_CONDITION opcode: 0x76
2406 * offset (8 bit): opcode
2407 * offset + 1 (8 bit): condition number
2409 * Check condition "condition number" in the io condition table.
2410 * If condition not met skip subsequent opcodes until condition is
2411 * inverted (INIT_NOT), or we hit INIT_RESUME
2414 uint8_t cond
= bios
->data
[offset
+ 1];
2416 if (!iexec
->execute
)
2419 BIOSLOG(bios
, "0x%04X: IO condition: 0x%02X\n", offset
, cond
);
2421 if (io_condition_met(bios
, offset
, cond
))
2422 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
2424 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
2425 iexec
->execute
= false;
2432 init_index_io(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2435 * INIT_INDEX_IO opcode: 0x78 ('x')
2437 * offset (8 bit): opcode
2438 * offset + 1 (16 bit): CRTC port
2439 * offset + 3 (8 bit): CRTC index
2440 * offset + 4 (8 bit): mask
2441 * offset + 5 (8 bit): data
2443 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2444 * OR with "data", write-back
2447 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
2448 uint8_t crtcindex
= bios
->data
[offset
+ 3];
2449 uint8_t mask
= bios
->data
[offset
+ 4];
2450 uint8_t data
= bios
->data
[offset
+ 5];
2453 if (!iexec
->execute
)
2456 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2458 offset
, crtcport
, crtcindex
, mask
, data
);
2460 value
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) | data
;
2461 bios_idxprt_wr(bios
, crtcport
, crtcindex
, value
);
2467 init_pll(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2470 * INIT_PLL opcode: 0x79 ('y')
2472 * offset (8 bit): opcode
2473 * offset + 1 (32 bit): register
2474 * offset + 5 (16 bit): freq
2476 * Set PLL register "register" to coefficients for frequency (10kHz)
2480 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2481 uint16_t freq
= ROM16(bios
->data
[offset
+ 5]);
2483 if (!iexec
->execute
)
2486 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset
, reg
, freq
);
2488 setPLL(bios
, reg
, freq
* 10);
2494 init_zm_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2497 * INIT_ZM_REG opcode: 0x7A ('z')
2499 * offset (8 bit): opcode
2500 * offset + 1 (32 bit): register
2501 * offset + 5 (32 bit): value
2503 * Assign "value" to "register"
2506 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2507 uint32_t value
= ROM32(bios
->data
[offset
+ 5]);
2509 if (!iexec
->execute
)
2512 if (reg
== 0x000200)
2515 bios_wr32(bios
, reg
, value
);
2521 init_ram_restrict_pll(struct nvbios
*bios
, uint16_t offset
,
2522 struct init_exec
*iexec
)
2525 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
2527 * offset (8 bit): opcode
2528 * offset + 1 (8 bit): PLL type
2529 * offset + 2 (32 bit): frequency 0
2531 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2532 * ram_restrict_table_ptr. The value read from there is used to select
2533 * a frequency from the table starting at 'frequency 0' to be
2534 * programmed into the PLL corresponding to 'type'.
2536 * The PLL limits table on cards using this opcode has a mapping of
2537 * 'type' to the relevant registers.
2540 struct drm_device
*dev
= bios
->dev
;
2541 uint32_t strap
= (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) & 0x0000003c) >> 2;
2542 uint8_t index
= bios
->data
[bios
->ram_restrict_tbl_ptr
+ strap
];
2543 uint8_t type
= bios
->data
[offset
+ 1];
2544 uint32_t freq
= ROM32(bios
->data
[offset
+ 2 + (index
* 4)]);
2545 uint8_t *pll_limits
= &bios
->data
[bios
->pll_limit_tbl_ptr
], *entry
;
2548 if (!iexec
->execute
)
2551 if (!bios
->pll_limit_tbl_ptr
|| (pll_limits
[0] & 0xf0) != 0x30) {
2552 NV_ERROR(dev
, "PLL limits table not version 3.x\n");
2553 return true; /* deliberate, allow default clocks to remain */
2556 entry
= pll_limits
+ pll_limits
[1];
2557 for (i
= 0; i
< pll_limits
[3]; i
++, entry
+= pll_limits
[2]) {
2558 if (entry
[0] == type
) {
2559 uint32_t reg
= ROM32(entry
[3]);
2561 BIOSLOG(bios
, "0x%04X: "
2562 "Type %02x Reg 0x%08x Freq %dKHz\n",
2563 offset
, type
, reg
, freq
);
2565 setPLL(bios
, reg
, freq
);
2570 NV_ERROR(dev
, "PLL type 0x%02x not found in PLL limits table", type
);
2575 init_8c(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2578 * INIT_8C opcode: 0x8C ('')
2588 init_8d(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2591 * INIT_8D opcode: 0x8D ('')
2601 init_gpio(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2604 * INIT_GPIO opcode: 0x8E ('')
2606 * offset (8 bit): opcode
2608 * Loop over all entries in the DCB GPIO table, and initialise
2609 * each GPIO according to various values listed in each entry
2612 const uint32_t nv50_gpio_reg
[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
2613 const uint32_t nv50_gpio_ctl
[2] = { 0xe100, 0xe28c };
2614 const uint8_t *gpio_table
= &bios
->data
[bios
->bdcb
.gpio_table_ptr
];
2615 const uint8_t *gpio_entry
;
2618 if (bios
->bdcb
.version
!= 0x40) {
2619 NV_ERROR(bios
->dev
, "DCB table not version 4.0\n");
2623 if (!bios
->bdcb
.gpio_table_ptr
) {
2624 NV_WARN(bios
->dev
, "Invalid pointer to INIT_8E table\n");
2628 gpio_entry
= gpio_table
+ gpio_table
[1];
2629 for (i
= 0; i
< gpio_table
[2]; i
++, gpio_entry
+= gpio_table
[3]) {
2630 uint32_t entry
= ROM32(gpio_entry
[0]), r
, s
, v
;
2631 int line
= (entry
& 0x0000001f);
2633 BIOSLOG(bios
, "0x%04X: Entry: 0x%08X\n", offset
, entry
);
2635 if ((entry
& 0x0000ff00) == 0x0000ff00)
2638 r
= nv50_gpio_reg
[line
>> 3];
2639 s
= (line
& 0x07) << 2;
2640 v
= bios_rd32(bios
, r
) & ~(0x00000003 << s
);
2641 if (entry
& 0x01000000)
2642 v
|= (((entry
& 0x60000000) >> 29) ^ 2) << s
;
2644 v
|= (((entry
& 0x18000000) >> 27) ^ 2) << s
;
2645 bios_wr32(bios
, r
, v
);
2647 r
= nv50_gpio_ctl
[line
>> 4];
2649 v
= bios_rd32(bios
, r
) & ~(0x00010001 << s
);
2650 switch ((entry
& 0x06000000) >> 25) {
2652 v
|= (0x00000001 << s
);
2655 v
|= (0x00010000 << s
);
2660 bios_wr32(bios
, r
, v
);
2666 /* hack to avoid moving the itbl_entry array before this function */
2667 int init_ram_restrict_zm_reg_group_blocklen
;
2670 init_ram_restrict_zm_reg_group(struct nvbios
*bios
, uint16_t offset
,
2671 struct init_exec
*iexec
)
2674 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2676 * offset (8 bit): opcode
2677 * offset + 1 (32 bit): reg
2678 * offset + 5 (8 bit): regincrement
2679 * offset + 6 (8 bit): count
2680 * offset + 7 (32 bit): value 1,1
2683 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2684 * ram_restrict_table_ptr. The value read from here is 'n', and
2685 * "value 1,n" gets written to "reg". This repeats "count" times and on
2686 * each iteration 'm', "reg" increases by "regincrement" and
2687 * "value m,n" is used. The extent of n is limited by a number read
2688 * from the 'M' BIT table, herein called "blocklen"
2691 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2692 uint8_t regincrement
= bios
->data
[offset
+ 5];
2693 uint8_t count
= bios
->data
[offset
+ 6];
2694 uint32_t strap_ramcfg
, data
;
2699 /* previously set by 'M' BIT table */
2700 blocklen
= init_ram_restrict_zm_reg_group_blocklen
;
2702 if (!iexec
->execute
)
2707 "0x%04X: Zero block length - has the M table "
2708 "been parsed?\n", offset
);
2712 strap_ramcfg
= (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) >> 2) & 0xf;
2713 index
= bios
->data
[bios
->ram_restrict_tbl_ptr
+ strap_ramcfg
];
2715 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
2716 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2717 offset
, reg
, regincrement
, count
, strap_ramcfg
, index
);
2719 for (i
= 0; i
< count
; i
++) {
2720 data
= ROM32(bios
->data
[offset
+ 7 + index
* 4 + blocklen
* i
]);
2722 bios_wr32(bios
, reg
, data
);
2724 reg
+= regincrement
;
2731 init_copy_zm_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2734 * INIT_COPY_ZM_REG opcode: 0x90 ('')
2736 * offset (8 bit): opcode
2737 * offset + 1 (32 bit): src reg
2738 * offset + 5 (32 bit): dst reg
2740 * Put contents of "src reg" into "dst reg"
2743 uint32_t srcreg
= ROM32(bios
->data
[offset
+ 1]);
2744 uint32_t dstreg
= ROM32(bios
->data
[offset
+ 5]);
2746 if (!iexec
->execute
)
2749 bios_wr32(bios
, dstreg
, bios_rd32(bios
, srcreg
));
2755 init_zm_reg_group_addr_latched(struct nvbios
*bios
, uint16_t offset
,
2756 struct init_exec
*iexec
)
2759 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2761 * offset (8 bit): opcode
2762 * offset + 1 (32 bit): dst reg
2763 * offset + 5 (8 bit): count
2764 * offset + 6 (32 bit): data 1
2767 * For each of "count" values write "data n" to "dst reg"
2770 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2771 uint8_t count
= bios
->data
[offset
+ 5];
2774 if (!iexec
->execute
)
2777 for (i
= 0; i
< count
; i
++) {
2778 uint32_t data
= ROM32(bios
->data
[offset
+ 6 + 4 * i
]);
2779 bios_wr32(bios
, reg
, data
);
2786 init_reserved(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2789 * INIT_RESERVED opcode: 0x92 ('')
2791 * offset (8 bit): opcode
2793 * Seemingly does nothing
2800 init_96(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2803 * INIT_96 opcode: 0x96 ('')
2805 * offset (8 bit): opcode
2806 * offset + 1 (32 bit): sreg
2807 * offset + 5 (8 bit): sshift
2808 * offset + 6 (8 bit): smask
2809 * offset + 7 (8 bit): index
2810 * offset + 8 (32 bit): reg
2811 * offset + 12 (32 bit): mask
2812 * offset + 16 (8 bit): shift
2816 uint16_t xlatptr
= bios
->init96_tbl_ptr
+ (bios
->data
[offset
+ 7] * 2);
2817 uint32_t reg
= ROM32(bios
->data
[offset
+ 8]);
2818 uint32_t mask
= ROM32(bios
->data
[offset
+ 12]);
2821 val
= bios_rd32(bios
, ROM32(bios
->data
[offset
+ 1]));
2822 if (bios
->data
[offset
+ 5] < 0x80)
2823 val
>>= bios
->data
[offset
+ 5];
2825 val
<<= (0x100 - bios
->data
[offset
+ 5]);
2826 val
&= bios
->data
[offset
+ 6];
2828 val
= bios
->data
[ROM16(bios
->data
[xlatptr
]) + val
];
2829 val
<<= bios
->data
[offset
+ 16];
2831 if (!iexec
->execute
)
2834 bios_wr32(bios
, reg
, (bios_rd32(bios
, reg
) & mask
) | val
);
2839 init_97(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2842 * INIT_97 opcode: 0x97 ('')
2844 * offset (8 bit): opcode
2845 * offset + 1 (32 bit): register
2846 * offset + 5 (32 bit): mask
2847 * offset + 9 (32 bit): value
2849 * Adds "value" to "register" preserving the fields specified
2853 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2854 uint32_t mask
= ROM32(bios
->data
[offset
+ 5]);
2855 uint32_t add
= ROM32(bios
->data
[offset
+ 9]);
2858 val
= bios_rd32(bios
, reg
);
2859 val
= (val
& mask
) | ((val
+ add
) & ~mask
);
2861 if (!iexec
->execute
)
2864 bios_wr32(bios
, reg
, val
);
2869 init_auxch(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2872 * INIT_AUXCH opcode: 0x98 ('')
2874 * offset (8 bit): opcode
2875 * offset + 1 (32 bit): address
2876 * offset + 5 (8 bit): count
2877 * offset + 6 (8 bit): mask 0
2878 * offset + 7 (8 bit): data 0
2883 struct drm_device
*dev
= bios
->dev
;
2884 struct nouveau_i2c_chan
*auxch
;
2885 uint32_t addr
= ROM32(bios
->data
[offset
+ 1]);
2886 uint8_t len
= bios
->data
[offset
+ 5];
2889 if (!bios
->display
.output
) {
2890 NV_ERROR(dev
, "INIT_AUXCH: no active output\n");
2894 auxch
= init_i2c_device_find(dev
, bios
->display
.output
->i2c_index
);
2896 NV_ERROR(dev
, "INIT_AUXCH: couldn't get auxch %d\n",
2897 bios
->display
.output
->i2c_index
);
2901 if (!iexec
->execute
)
2905 for (i
= 0; i
< len
; i
++, offset
+= 2) {
2908 ret
= nouveau_dp_auxch(auxch
, 9, addr
, &data
, 1);
2910 NV_ERROR(dev
, "INIT_AUXCH: rd auxch fail %d\n", ret
);
2914 data
&= bios
->data
[offset
+ 0];
2915 data
|= bios
->data
[offset
+ 1];
2917 ret
= nouveau_dp_auxch(auxch
, 8, addr
, &data
, 1);
2919 NV_ERROR(dev
, "INIT_AUXCH: wr auxch fail %d\n", ret
);
2928 init_zm_auxch(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2931 * INIT_ZM_AUXCH opcode: 0x99 ('')
2933 * offset (8 bit): opcode
2934 * offset + 1 (32 bit): address
2935 * offset + 5 (8 bit): count
2936 * offset + 6 (8 bit): data 0
2941 struct drm_device
*dev
= bios
->dev
;
2942 struct nouveau_i2c_chan
*auxch
;
2943 uint32_t addr
= ROM32(bios
->data
[offset
+ 1]);
2944 uint8_t len
= bios
->data
[offset
+ 5];
2947 if (!bios
->display
.output
) {
2948 NV_ERROR(dev
, "INIT_ZM_AUXCH: no active output\n");
2952 auxch
= init_i2c_device_find(dev
, bios
->display
.output
->i2c_index
);
2954 NV_ERROR(dev
, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
2955 bios
->display
.output
->i2c_index
);
2959 if (!iexec
->execute
)
2963 for (i
= 0; i
< len
; i
++, offset
++) {
2964 ret
= nouveau_dp_auxch(auxch
, 8, addr
, &bios
->data
[offset
], 1);
2966 NV_ERROR(dev
, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret
);
2974 static struct init_tbl_entry itbl_entry
[] = {
2975 /* command name , id , length , offset , mult , command handler */
2976 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
2977 { "INIT_IO_RESTRICT_PROG" , 0x32, 11 , 6 , 4 , init_io_restrict_prog
},
2978 { "INIT_REPEAT" , 0x33, 2 , 0 , 0 , init_repeat
},
2979 { "INIT_IO_RESTRICT_PLL" , 0x34, 12 , 7 , 2 , init_io_restrict_pll
},
2980 { "INIT_END_REPEAT" , 0x36, 1 , 0 , 0 , init_end_repeat
},
2981 { "INIT_COPY" , 0x37, 11 , 0 , 0 , init_copy
},
2982 { "INIT_NOT" , 0x38, 1 , 0 , 0 , init_not
},
2983 { "INIT_IO_FLAG_CONDITION" , 0x39, 2 , 0 , 0 , init_io_flag_condition
},
2984 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, 18 , 17 , 2 , init_idx_addr_latched
},
2985 { "INIT_IO_RESTRICT_PLL2" , 0x4A, 11 , 6 , 4 , init_io_restrict_pll2
},
2986 { "INIT_PLL2" , 0x4B, 9 , 0 , 0 , init_pll2
},
2987 { "INIT_I2C_BYTE" , 0x4C, 4 , 3 , 3 , init_i2c_byte
},
2988 { "INIT_ZM_I2C_BYTE" , 0x4D, 4 , 3 , 2 , init_zm_i2c_byte
},
2989 { "INIT_ZM_I2C" , 0x4E, 4 , 3 , 1 , init_zm_i2c
},
2990 { "INIT_TMDS" , 0x4F, 5 , 0 , 0 , init_tmds
},
2991 { "INIT_ZM_TMDS_GROUP" , 0x50, 3 , 2 , 2 , init_zm_tmds_group
},
2992 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, 5 , 4 , 1 , init_cr_idx_adr_latch
},
2993 { "INIT_CR" , 0x52, 4 , 0 , 0 , init_cr
},
2994 { "INIT_ZM_CR" , 0x53, 3 , 0 , 0 , init_zm_cr
},
2995 { "INIT_ZM_CR_GROUP" , 0x54, 2 , 1 , 2 , init_zm_cr_group
},
2996 { "INIT_CONDITION_TIME" , 0x56, 3 , 0 , 0 , init_condition_time
},
2997 { "INIT_ZM_REG_SEQUENCE" , 0x58, 6 , 5 , 4 , init_zm_reg_sequence
},
2998 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
2999 { "INIT_SUB_DIRECT" , 0x5B, 3 , 0 , 0 , init_sub_direct
},
3000 { "INIT_COPY_NV_REG" , 0x5F, 22 , 0 , 0 , init_copy_nv_reg
},
3001 { "INIT_ZM_INDEX_IO" , 0x62, 5 , 0 , 0 , init_zm_index_io
},
3002 { "INIT_COMPUTE_MEM" , 0x63, 1 , 0 , 0 , init_compute_mem
},
3003 { "INIT_RESET" , 0x65, 13 , 0 , 0 , init_reset
},
3004 { "INIT_CONFIGURE_MEM" , 0x66, 1 , 0 , 0 , init_configure_mem
},
3005 { "INIT_CONFIGURE_CLK" , 0x67, 1 , 0 , 0 , init_configure_clk
},
3006 { "INIT_CONFIGURE_PREINIT" , 0x68, 1 , 0 , 0 , init_configure_preinit
},
3007 { "INIT_IO" , 0x69, 5 , 0 , 0 , init_io
},
3008 { "INIT_SUB" , 0x6B, 2 , 0 , 0 , init_sub
},
3009 { "INIT_RAM_CONDITION" , 0x6D, 3 , 0 , 0 , init_ram_condition
},
3010 { "INIT_NV_REG" , 0x6E, 13 , 0 , 0 , init_nv_reg
},
3011 { "INIT_MACRO" , 0x6F, 2 , 0 , 0 , init_macro
},
3012 { "INIT_DONE" , 0x71, 1 , 0 , 0 , init_done
},
3013 { "INIT_RESUME" , 0x72, 1 , 0 , 0 , init_resume
},
3014 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
3015 { "INIT_TIME" , 0x74, 3 , 0 , 0 , init_time
},
3016 { "INIT_CONDITION" , 0x75, 2 , 0 , 0 , init_condition
},
3017 { "INIT_IO_CONDITION" , 0x76, 2 , 0 , 0 , init_io_condition
},
3018 { "INIT_INDEX_IO" , 0x78, 6 , 0 , 0 , init_index_io
},
3019 { "INIT_PLL" , 0x79, 7 , 0 , 0 , init_pll
},
3020 { "INIT_ZM_REG" , 0x7A, 9 , 0 , 0 , init_zm_reg
},
3021 /* INIT_RAM_RESTRICT_PLL's length is adjusted by the BIT M table */
3022 { "INIT_RAM_RESTRICT_PLL" , 0x87, 2 , 0 , 0 , init_ram_restrict_pll
},
3023 { "INIT_8C" , 0x8C, 1 , 0 , 0 , init_8c
},
3024 { "INIT_8D" , 0x8D, 1 , 0 , 0 , init_8d
},
3025 { "INIT_GPIO" , 0x8E, 1 , 0 , 0 , init_gpio
},
3026 /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */
3027 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, 7 , 6 , 0 , init_ram_restrict_zm_reg_group
},
3028 { "INIT_COPY_ZM_REG" , 0x90, 9 , 0 , 0 , init_copy_zm_reg
},
3029 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, 6 , 5 , 4 , init_zm_reg_group_addr_latched
},
3030 { "INIT_RESERVED" , 0x92, 1 , 0 , 0 , init_reserved
},
3031 { "INIT_96" , 0x96, 17 , 0 , 0 , init_96
},
3032 { "INIT_97" , 0x97, 13 , 0 , 0 , init_97
},
3033 { "INIT_AUXCH" , 0x98, 6 , 5 , 2 , init_auxch
},
3034 { "INIT_ZM_AUXCH" , 0x99, 6 , 5 , 1 , init_zm_auxch
},
3035 { NULL
, 0 , 0 , 0 , 0 , NULL
}
3038 static unsigned int get_init_table_entry_length(struct nvbios
*bios
, unsigned int offset
, int i
)
3040 /* Calculates the length of a given init table entry. */
3041 return itbl_entry
[i
].length
+ bios
->data
[offset
+ itbl_entry
[i
].length_offset
]*itbl_entry
[i
].length_multiplier
;
3044 #define MAX_TABLE_OPS 1000
3047 parse_init_table(struct nvbios
*bios
, unsigned int offset
,
3048 struct init_exec
*iexec
)
3051 * Parses all commands in an init table.
3053 * We start out executing all commands found in the init table. Some
3054 * opcodes may change the status of iexec->execute to SKIP, which will
3055 * cause the following opcodes to perform no operation until the value
3056 * is changed back to EXECUTE.
3063 * Loop until INIT_DONE causes us to break out of the loop
3064 * (or until offset > bios length just in case... )
3065 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3067 while ((offset
< bios
->length
) && (count
++ < MAX_TABLE_OPS
)) {
3068 id
= bios
->data
[offset
];
3070 /* Find matching id in itbl_entry */
3071 for (i
= 0; itbl_entry
[i
].name
&& (itbl_entry
[i
].id
!= id
); i
++)
3074 if (itbl_entry
[i
].name
) {
3075 BIOSLOG(bios
, "0x%04X: [ (0x%02X) - %s ]\n",
3076 offset
, itbl_entry
[i
].id
, itbl_entry
[i
].name
);
3078 /* execute eventual command handler */
3079 if (itbl_entry
[i
].handler
)
3080 if (!(*itbl_entry
[i
].handler
)(bios
, offset
, iexec
))
3084 "0x%04X: Init table command not found: "
3085 "0x%02X\n", offset
, id
);
3090 * Add the offset of the current command including all data
3091 * of that command. The offset will then be pointing on the
3094 offset
+= get_init_table_entry_length(bios
, offset
, i
);
3097 if (offset
>= bios
->length
)
3099 "Offset 0x%04X greater than known bios image length. "
3100 "Corrupt image?\n", offset
);
3101 if (count
>= MAX_TABLE_OPS
)
3103 "More than %d opcodes to a table is unlikely, "
3104 "is the bios image corrupt?\n", MAX_TABLE_OPS
);
3110 parse_init_tables(struct nvbios
*bios
)
3112 /* Loops and calls parse_init_table() for each present table. */
3116 struct init_exec iexec
= {true, false};
3118 if (bios
->old_style_init
) {
3119 if (bios
->init_script_tbls_ptr
)
3120 parse_init_table(bios
, bios
->init_script_tbls_ptr
, &iexec
);
3121 if (bios
->extra_init_script_tbl_ptr
)
3122 parse_init_table(bios
, bios
->extra_init_script_tbl_ptr
, &iexec
);
3127 while ((table
= ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ i
]))) {
3129 "Parsing VBIOS init table %d at offset 0x%04X\n",
3131 BIOSLOG(bios
, "0x%04X: ------ Executing following commands ------\n", table
);
3133 parse_init_table(bios
, table
, &iexec
);
3138 static uint16_t clkcmptable(struct nvbios
*bios
, uint16_t clktable
, int pxclk
)
3140 int compare_record_len
, i
= 0;
3141 uint16_t compareclk
, scriptptr
= 0;
3143 if (bios
->major_version
< 5) /* pre BIT */
3144 compare_record_len
= 3;
3146 compare_record_len
= 4;
3149 compareclk
= ROM16(bios
->data
[clktable
+ compare_record_len
* i
]);
3150 if (pxclk
>= compareclk
* 10) {
3151 if (bios
->major_version
< 5) {
3152 uint8_t tmdssub
= bios
->data
[clktable
+ 2 + compare_record_len
* i
];
3153 scriptptr
= ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ tmdssub
* 2]);
3155 scriptptr
= ROM16(bios
->data
[clktable
+ 2 + compare_record_len
* i
]);
3159 } while (compareclk
);
3165 run_digital_op_script(struct drm_device
*dev
, uint16_t scriptptr
,
3166 struct dcb_entry
*dcbent
, int head
, bool dl
)
3168 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3169 struct nvbios
*bios
= &dev_priv
->VBIOS
;
3170 struct init_exec iexec
= {true, false};
3172 NV_TRACE(dev
, "0x%04X: Parsing digital output script table\n",
3174 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_44
,
3175 head
? NV_CIO_CRE_44_HEADB
: NV_CIO_CRE_44_HEADA
);
3176 /* note: if dcb entries have been merged, index may be misleading */
3177 NVWriteVgaCrtc5758(dev
, head
, 0, dcbent
->index
);
3178 parse_init_table(bios
, scriptptr
, &iexec
);
3180 nv04_dfp_bind_head(dev
, dcbent
, head
, dl
);
3183 static int call_lvds_manufacturer_script(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, enum LVDS_script script
)
3185 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3186 struct nvbios
*bios
= &dev_priv
->VBIOS
;
3187 uint8_t sub
= bios
->data
[bios
->fp
.xlated_entry
+ script
] + (bios
->fp
.link_c_increment
&& dcbent
->or & OUTPUT_C
? 1 : 0);
3188 uint16_t scriptofs
= ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ sub
* 2]);
3190 if (!bios
->fp
.xlated_entry
|| !sub
|| !scriptofs
)
3193 run_digital_op_script(dev
, scriptofs
, dcbent
, head
, bios
->fp
.dual_link
);
3195 if (script
== LVDS_PANEL_OFF
) {
3196 /* off-on delay in ms */
3197 msleep(ROM16(bios
->data
[bios
->fp
.xlated_entry
+ 7]));
3200 /* Powerbook specific quirks */
3201 if (script
== LVDS_RESET
&& ((dev
->pci_device
& 0xffff) == 0x0179 || (dev
->pci_device
& 0xffff) == 0x0329))
3202 nv_write_tmds(dev
, dcbent
->or, 0, 0x02, 0x72);
3203 if ((dev
->pci_device
& 0xffff) == 0x0179 || (dev
->pci_device
& 0xffff) == 0x0189 || (dev
->pci_device
& 0xffff) == 0x0329) {
3204 if (script
== LVDS_PANEL_ON
) {
3205 bios_wr32(bios
, NV_PBUS_DEBUG_DUALHEAD_CTL
, bios_rd32(bios
, NV_PBUS_DEBUG_DUALHEAD_CTL
) | (1 << 31));
3206 bios_wr32(bios
, NV_PCRTC_GPIO_EXT
, bios_rd32(bios
, NV_PCRTC_GPIO_EXT
) | 1);
3208 if (script
== LVDS_PANEL_OFF
) {
3209 bios_wr32(bios
, NV_PBUS_DEBUG_DUALHEAD_CTL
, bios_rd32(bios
, NV_PBUS_DEBUG_DUALHEAD_CTL
) & ~(1 << 31));
3210 bios_wr32(bios
, NV_PCRTC_GPIO_EXT
, bios_rd32(bios
, NV_PCRTC_GPIO_EXT
) & ~3);
3218 static int run_lvds_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, enum LVDS_script script
, int pxclk
)
3221 * The BIT LVDS table's header has the information to setup the
3222 * necessary registers. Following the standard 4 byte header are:
3223 * A bitmask byte and a dual-link transition pxclk value for use in
3224 * selecting the init script when not using straps; 4 script pointers
3225 * for panel power, selected by output and on/off; and 8 table pointers
3226 * for panel init, the needed one determined by output, and bits in the
3227 * conf byte. These tables are similar to the TMDS tables, consisting
3228 * of a list of pxclks and script pointers.
3230 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3231 struct nvbios
*bios
= &dev_priv
->VBIOS
;
3232 unsigned int outputset
= (dcbent
->or == 4) ? 1 : 0;
3233 uint16_t scriptptr
= 0, clktable
;
3234 uint8_t clktableptr
= 0;
3237 * For now we assume version 3.0 table - g80 support will need some
3244 case LVDS_BACKLIGHT_ON
:
3246 scriptptr
= ROM16(bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 7 + outputset
* 2]);
3248 case LVDS_BACKLIGHT_OFF
:
3249 case LVDS_PANEL_OFF
:
3250 scriptptr
= ROM16(bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 11 + outputset
* 2]);
3253 if (dcbent
->lvdsconf
.use_straps_for_mode
) {
3254 if (bios
->fp
.dual_link
)
3256 if (bios
->fp
.BITbit1
)
3260 uint8_t fallback
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 4];
3261 int fallbackcmpval
= (dcbent
->or == 4) ? 4 : 1;
3263 if (bios
->fp
.dual_link
) {
3265 fallbackcmpval
*= 2;
3267 if (fallbackcmpval
& fallback
)
3271 /* adding outputset * 8 may not be correct */
3272 clktable
= ROM16(bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 15 + clktableptr
* 2 + outputset
* 8]);
3274 NV_ERROR(dev
, "Pixel clock comparison table not found\n");
3277 scriptptr
= clkcmptable(bios
, clktable
, pxclk
);
3281 NV_ERROR(dev
, "LVDS output init script not found\n");
3284 run_digital_op_script(dev
, scriptptr
, dcbent
, head
, bios
->fp
.dual_link
);
3289 int call_lvds_script(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, enum LVDS_script script
, int pxclk
)
3292 * LVDS operations are multiplexed in an effort to present a single API
3293 * which works with two vastly differing underlying structures.
3294 * This acts as the demux
3297 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3298 struct nvbios
*bios
= &dev_priv
->VBIOS
;
3299 uint8_t lvds_ver
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
];
3300 uint32_t sel_clk_binding
, sel_clk
;
3303 if (bios
->fp
.last_script_invoc
== (script
<< 1 | head
) || !lvds_ver
||
3304 (lvds_ver
>= 0x30 && script
== LVDS_INIT
))
3307 if (!bios
->fp
.lvds_init_run
) {
3308 bios
->fp
.lvds_init_run
= true;
3309 call_lvds_script(dev
, dcbent
, head
, LVDS_INIT
, pxclk
);
3312 if (script
== LVDS_PANEL_ON
&& bios
->fp
.reset_after_pclk_change
)
3313 call_lvds_script(dev
, dcbent
, head
, LVDS_RESET
, pxclk
);
3314 if (script
== LVDS_RESET
&& bios
->fp
.power_off_for_reset
)
3315 call_lvds_script(dev
, dcbent
, head
, LVDS_PANEL_OFF
, pxclk
);
3317 NV_TRACE(dev
, "Calling LVDS script %d:\n", script
);
3319 /* don't let script change pll->head binding */
3320 sel_clk_binding
= bios_rd32(bios
, NV_PRAMDAC_SEL_CLK
) & 0x50000;
3322 if (lvds_ver
< 0x30)
3323 ret
= call_lvds_manufacturer_script(dev
, dcbent
, head
, script
);
3325 ret
= run_lvds_table(dev
, dcbent
, head
, script
, pxclk
);
3327 bios
->fp
.last_script_invoc
= (script
<< 1 | head
);
3329 sel_clk
= NVReadRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
) & ~0x50000;
3330 NVWriteRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
, sel_clk
| sel_clk_binding
);
3331 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3332 nvWriteMC(dev
, NV_PBUS_POWERCTRL_2
, 0);
3337 struct lvdstableheader
{
3338 uint8_t lvds_ver
, headerlen
, recordlen
;
3341 static int parse_lvds_manufacturer_table_header(struct drm_device
*dev
, struct nvbios
*bios
, struct lvdstableheader
*lth
)
3344 * BMP version (0xa) LVDS table has a simple header of version and
3345 * record length. The BIT LVDS table has the typical BIT table header:
3346 * version byte, header length byte, record length byte, and a byte for
3347 * the maximum number of records that can be held in the table.
3350 uint8_t lvds_ver
, headerlen
, recordlen
;
3352 memset(lth
, 0, sizeof(struct lvdstableheader
));
3354 if (bios
->fp
.lvdsmanufacturerpointer
== 0x0) {
3355 NV_ERROR(dev
, "Pointer to LVDS manufacturer table invalid\n");
3359 lvds_ver
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
];
3362 case 0x0a: /* pre NV40 */
3364 recordlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 1];
3366 case 0x30: /* NV4x */
3367 headerlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 1];
3368 if (headerlen
< 0x1f) {
3369 NV_ERROR(dev
, "LVDS table header not understood\n");
3372 recordlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 2];
3374 case 0x40: /* G80/G90 */
3375 headerlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 1];
3376 if (headerlen
< 0x7) {
3377 NV_ERROR(dev
, "LVDS table header not understood\n");
3380 recordlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 2];
3384 "LVDS table revision %d.%d not currently supported\n",
3385 lvds_ver
>> 4, lvds_ver
& 0xf);
3389 lth
->lvds_ver
= lvds_ver
;
3390 lth
->headerlen
= headerlen
;
3391 lth
->recordlen
= recordlen
;
3397 get_fp_strap(struct drm_device
*dev
, struct nvbios
*bios
)
3399 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3402 * The fp strap is normally dictated by the "User Strap" in
3403 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3404 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3405 * by the PCI subsystem ID during POST, but not before the previous user
3406 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3407 * read and used instead
3410 if (bios
->major_version
< 5 && bios
->data
[0x48] & 0x4)
3411 return NVReadVgaCrtc5758(dev
, 0, 0xf) & 0xf;
3413 if (dev_priv
->card_type
>= NV_50
)
3414 return (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) >> 24) & 0xf;
3416 return (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) >> 16) & 0xf;
3419 static int parse_fp_mode_table(struct drm_device
*dev
, struct nvbios
*bios
)
3422 uint8_t fptable_ver
, headerlen
= 0, recordlen
, fpentries
= 0xf, fpindex
;
3423 int ret
, ofs
, fpstrapping
;
3424 struct lvdstableheader lth
;
3426 if (bios
->fp
.fptablepointer
== 0x0) {
3427 /* Apple cards don't have the fp table; the laptops use DDC */
3428 /* The table is also missing on some x86 IGPs */
3430 NV_ERROR(dev
, "Pointer to flat panel table invalid\n");
3432 bios
->pub
.digital_min_front_porch
= 0x4b;
3436 fptable
= &bios
->data
[bios
->fp
.fptablepointer
];
3437 fptable_ver
= fptable
[0];
3439 switch (fptable_ver
) {
3441 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
3442 * version field, and miss one of the spread spectrum/PWM bytes.
3443 * This could affect early GF2Go parts (not seen any appropriate ROMs
3444 * though). Here we assume that a version of 0x05 matches this case
3445 * (combining with a BMP version check would be better), as the
3446 * common case for the panel type field is 0x0005, and that is in
3447 * fact what we are reading the first byte of.
3449 case 0x05: /* some NV10, 11, 15, 16 */
3453 case 0x10: /* some NV15/16, and NV11+ */
3457 case 0x20: /* NV40+ */
3458 headerlen
= fptable
[1];
3459 recordlen
= fptable
[2];
3460 fpentries
= fptable
[3];
3462 * fptable[4] is the minimum
3463 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
3465 bios
->pub
.digital_min_front_porch
= fptable
[4];
3470 "FP table revision %d.%d not currently supported\n",
3471 fptable_ver
>> 4, fptable_ver
& 0xf);
3475 if (!bios
->is_mobile
) /* !mobile only needs digital_min_front_porch */
3478 ret
= parse_lvds_manufacturer_table_header(dev
, bios
, <h
);
3482 if (lth
.lvds_ver
== 0x30 || lth
.lvds_ver
== 0x40) {
3483 bios
->fp
.fpxlatetableptr
= bios
->fp
.lvdsmanufacturerpointer
+
3485 bios
->fp
.xlatwidth
= lth
.recordlen
;
3487 if (bios
->fp
.fpxlatetableptr
== 0x0) {
3488 NV_ERROR(dev
, "Pointer to flat panel xlat table invalid\n");
3492 fpstrapping
= get_fp_strap(dev
, bios
);
3494 fpindex
= bios
->data
[bios
->fp
.fpxlatetableptr
+
3495 fpstrapping
* bios
->fp
.xlatwidth
];
3497 if (fpindex
> fpentries
) {
3498 NV_ERROR(dev
, "Bad flat panel table index\n");
3502 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
3503 if (lth
.lvds_ver
> 0x10)
3504 bios
->pub
.fp_no_ddc
= fpstrapping
!= 0xf || fpindex
!= 0xf;
3507 * If either the strap or xlated fpindex value are 0xf there is no
3508 * panel using a strap-derived bios mode present. this condition
3509 * includes, but is different from, the DDC panel indicator above
3511 if (fpstrapping
== 0xf || fpindex
== 0xf)
3514 bios
->fp
.mode_ptr
= bios
->fp
.fptablepointer
+ headerlen
+
3515 recordlen
* fpindex
+ ofs
;
3517 NV_TRACE(dev
, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
3518 ROM16(bios
->data
[bios
->fp
.mode_ptr
+ 11]) + 1,
3519 ROM16(bios
->data
[bios
->fp
.mode_ptr
+ 25]) + 1,
3520 ROM16(bios
->data
[bios
->fp
.mode_ptr
+ 7]) * 10);
3525 bool nouveau_bios_fp_mode(struct drm_device
*dev
, struct drm_display_mode
*mode
)
3527 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3528 struct nvbios
*bios
= &dev_priv
->VBIOS
;
3529 uint8_t *mode_entry
= &bios
->data
[bios
->fp
.mode_ptr
];
3531 if (!mode
) /* just checking whether we can produce a mode */
3532 return bios
->fp
.mode_ptr
;
3534 memset(mode
, 0, sizeof(struct drm_display_mode
));
3536 * For version 1.0 (version in byte 0):
3537 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
3538 * single/dual link, and type (TFT etc.)
3539 * bytes 3-6 are bits per colour in RGBX
3541 mode
->clock
= ROM16(mode_entry
[7]) * 10;
3542 /* bytes 9-10 is HActive */
3543 mode
->hdisplay
= ROM16(mode_entry
[11]) + 1;
3545 * bytes 13-14 is HValid Start
3546 * bytes 15-16 is HValid End
3548 mode
->hsync_start
= ROM16(mode_entry
[17]) + 1;
3549 mode
->hsync_end
= ROM16(mode_entry
[19]) + 1;
3550 mode
->htotal
= ROM16(mode_entry
[21]) + 1;
3551 /* bytes 23-24, 27-30 similarly, but vertical */
3552 mode
->vdisplay
= ROM16(mode_entry
[25]) + 1;
3553 mode
->vsync_start
= ROM16(mode_entry
[31]) + 1;
3554 mode
->vsync_end
= ROM16(mode_entry
[33]) + 1;
3555 mode
->vtotal
= ROM16(mode_entry
[35]) + 1;
3556 mode
->flags
|= (mode_entry
[37] & 0x10) ?
3557 DRM_MODE_FLAG_PHSYNC
: DRM_MODE_FLAG_NHSYNC
;
3558 mode
->flags
|= (mode_entry
[37] & 0x1) ?
3559 DRM_MODE_FLAG_PVSYNC
: DRM_MODE_FLAG_NVSYNC
;
3561 * bytes 38-39 relate to spread spectrum settings
3562 * bytes 40-43 are something to do with PWM
3565 mode
->status
= MODE_OK
;
3566 mode
->type
= DRM_MODE_TYPE_DRIVER
| DRM_MODE_TYPE_PREFERRED
;
3567 drm_mode_set_name(mode
);
3568 return bios
->fp
.mode_ptr
;
3571 int nouveau_bios_parse_lvds_table(struct drm_device
*dev
, int pxclk
, bool *dl
, bool *if_is_24bit
)
3574 * The LVDS table header is (mostly) described in
3575 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3576 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3577 * straps are not being used for the panel, this specifies the frequency
3578 * at which modes should be set up in the dual link style.
3580 * Following the header, the BMP (ver 0xa) table has several records,
3581 * indexed by a seperate xlat table, indexed in turn by the fp strap in
3582 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3583 * numbers for use by INIT_SUB which controlled panel init and power,
3584 * and finally a dword of ms to sleep between power off and on
3587 * In the BIT versions, the table following the header serves as an
3588 * integrated config and xlat table: the records in the table are
3589 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3590 * two bytes - the first as a config byte, the second for indexing the
3591 * fp mode table pointed to by the BIT 'D' table
3593 * DDC is not used until after card init, so selecting the correct table
3594 * entry and setting the dual link flag for EDID equipped panels,
3595 * requiring tests against the native-mode pixel clock, cannot be done
3596 * until later, when this function should be called with non-zero pxclk
3598 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3599 struct nvbios
*bios
= &dev_priv
->VBIOS
;
3600 int fpstrapping
= get_fp_strap(dev
, bios
), lvdsmanufacturerindex
= 0;
3601 struct lvdstableheader lth
;
3603 int ret
, chip_version
= bios
->pub
.chip_version
;
3605 ret
= parse_lvds_manufacturer_table_header(dev
, bios
, <h
);
3609 switch (lth
.lvds_ver
) {
3610 case 0x0a: /* pre NV40 */
3611 lvdsmanufacturerindex
= bios
->data
[
3612 bios
->fp
.fpxlatemanufacturertableptr
+
3615 /* we're done if this isn't the EDID panel case */
3619 if (chip_version
< 0x25) {
3622 * It seems the old style lvds script pointer is reused
3623 * to select 18/24 bit colour depth for EDID panels.
3625 lvdsmanufacturerindex
=
3626 (bios
->legacy
.lvds_single_a_script_ptr
& 1) ?
3628 if (pxclk
>= bios
->fp
.duallink_transition_clk
)
3629 lvdsmanufacturerindex
++;
3630 } else if (chip_version
< 0x30) {
3631 /* nv28 behaviour (off-chip encoder)
3633 * nv28 does a complex dance of first using byte 121 of
3634 * the EDID to choose the lvdsmanufacturerindex, then
3635 * later attempting to match the EDID manufacturer and
3636 * product IDs in a table (signature 'pidt' (panel id
3637 * table?)), setting an lvdsmanufacturerindex of 0 and
3638 * an fp strap of the match index (or 0xf if none)
3640 lvdsmanufacturerindex
= 0;
3642 /* nv31, nv34 behaviour */
3643 lvdsmanufacturerindex
= 0;
3644 if (pxclk
>= bios
->fp
.duallink_transition_clk
)
3645 lvdsmanufacturerindex
= 2;
3646 if (pxclk
>= 140000)
3647 lvdsmanufacturerindex
= 3;
3651 * nvidia set the high nibble of (cr57=f, cr58) to
3652 * lvdsmanufacturerindex in this case; we don't
3655 case 0x30: /* NV4x */
3656 case 0x40: /* G80/G90 */
3657 lvdsmanufacturerindex
= fpstrapping
;
3660 NV_ERROR(dev
, "LVDS table revision not currently supported\n");
3664 lvdsofs
= bios
->fp
.xlated_entry
= bios
->fp
.lvdsmanufacturerpointer
+ lth
.headerlen
+ lth
.recordlen
* lvdsmanufacturerindex
;
3665 switch (lth
.lvds_ver
) {
3667 bios
->fp
.power_off_for_reset
= bios
->data
[lvdsofs
] & 1;
3668 bios
->fp
.reset_after_pclk_change
= bios
->data
[lvdsofs
] & 2;
3669 bios
->fp
.dual_link
= bios
->data
[lvdsofs
] & 4;
3670 bios
->fp
.link_c_increment
= bios
->data
[lvdsofs
] & 8;
3671 *if_is_24bit
= bios
->data
[lvdsofs
] & 16;
3675 * My money would be on there being a 24 bit interface bit in
3676 * this table, but I have no example of a laptop bios with a
3677 * 24 bit panel to confirm that. Hence we shout loudly if any
3678 * bit other than bit 0 is set (I've not even seen bit 1)
3680 if (bios
->data
[lvdsofs
] > 1)
3682 "You have a very unusual laptop display; please report it\n");
3684 * No sign of the "power off for reset" or "reset for panel
3685 * on" bits, but it's safer to assume we should
3687 bios
->fp
.power_off_for_reset
= true;
3688 bios
->fp
.reset_after_pclk_change
= true;
3690 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
3691 * over-written, and BITbit1 isn't used
3693 bios
->fp
.dual_link
= bios
->data
[lvdsofs
] & 1;
3694 bios
->fp
.BITbit1
= bios
->data
[lvdsofs
] & 2;
3695 bios
->fp
.duallink_transition_clk
= ROM16(bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 5]) * 10;
3698 bios
->fp
.dual_link
= bios
->data
[lvdsofs
] & 1;
3699 bios
->fp
.if_is_24bit
= bios
->data
[lvdsofs
] & 2;
3700 bios
->fp
.strapless_is_24bit
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 4];
3701 bios
->fp
.duallink_transition_clk
= ROM16(bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 5]) * 10;
3705 /* set dual_link flag for EDID case */
3706 if (pxclk
&& (chip_version
< 0x25 || chip_version
> 0x28))
3707 bios
->fp
.dual_link
= (pxclk
>= bios
->fp
.duallink_transition_clk
);
3709 *dl
= bios
->fp
.dual_link
;
3715 bios_output_config_match(struct drm_device
*dev
, struct dcb_entry
*dcbent
,
3716 uint16_t record
, int record_len
, int record_nr
)
3718 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3719 struct nvbios
*bios
= &dev_priv
->VBIOS
;
3724 for (i
= 0; i
< record_nr
; i
++, record
+= record_len
) {
3725 table
= ROM16(bios
->data
[record
]);
3728 entry
= ROM32(bios
->data
[table
]);
3730 v
= (entry
& 0x000f0000) >> 16;
3731 if (!(v
& dcbent
->or))
3734 v
= (entry
& 0x000000f0) >> 4;
3735 if (v
!= dcbent
->location
)
3738 v
= (entry
& 0x0000000f);
3739 if (v
!= dcbent
->type
)
3742 return &bios
->data
[table
];
3749 nouveau_bios_dp_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
,
3752 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3753 struct nvbios
*bios
= &dev_priv
->VBIOS
;
3756 if (!bios
->display
.dp_table_ptr
) {
3757 NV_ERROR(dev
, "No pointer to DisplayPort table\n");
3760 table
= &bios
->data
[bios
->display
.dp_table_ptr
];
3762 if (table
[0] != 0x21) {
3763 NV_ERROR(dev
, "DisplayPort table version 0x%02x unknown\n",
3769 return bios_output_config_match(dev
, dcbent
,
3770 bios
->display
.dp_table_ptr
+ table
[1],
3771 table
[2], table
[3]);
3775 nouveau_bios_run_display_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
,
3776 uint32_t sub
, int pxclk
)
3779 * The display script table is located by the BIT 'U' table.
3781 * It contains an array of pointers to various tables describing
3782 * a particular output type. The first 32-bits of the output
3783 * tables contains similar information to a DCB entry, and is
3784 * used to decide whether that particular table is suitable for
3785 * the output you want to access.
3787 * The "record header length" field here seems to indicate the
3788 * offset of the first configuration entry in the output tables.
3789 * This is 10 on most cards I've seen, but 12 has been witnessed
3790 * on DP cards, and there's another script pointer within the
3793 * offset + 0 ( 8 bits): version
3794 * offset + 1 ( 8 bits): header length
3795 * offset + 2 ( 8 bits): record length
3796 * offset + 3 ( 8 bits): number of records
3797 * offset + 4 ( 8 bits): record header length
3798 * offset + 5 (16 bits): pointer to first output script table
3801 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3802 struct init_exec iexec
= {true, false};
3803 struct nvbios
*bios
= &dev_priv
->VBIOS
;
3804 uint8_t *table
= &bios
->data
[bios
->display
.script_table_ptr
];
3805 uint8_t *otable
= NULL
;
3809 if (!bios
->display
.script_table_ptr
) {
3810 NV_ERROR(dev
, "No pointer to output script table\n");
3815 * Nothing useful has been in any of the pre-2.0 tables I've seen,
3816 * so until they are, we really don't need to care.
3818 if (table
[0] < 0x20)
3821 if (table
[0] != 0x20 && table
[0] != 0x21) {
3822 NV_ERROR(dev
, "Output script table version 0x%02x unknown\n",
3828 * The output script tables describing a particular output type
3831 * offset + 0 (32 bits): output this table matches (hash of DCB)
3832 * offset + 4 ( 8 bits): unknown
3833 * offset + 5 ( 8 bits): number of configurations
3834 * offset + 6 (16 bits): pointer to some script
3835 * offset + 8 (16 bits): pointer to some script
3838 * offset + 10 : configuration 0
3841 * offset + 10 : pointer to some script
3842 * offset + 12 : configuration 0
3844 * Each config entry is as follows:
3846 * offset + 0 (16 bits): unknown, assumed to be a match value
3847 * offset + 2 (16 bits): pointer to script table (clock set?)
3848 * offset + 4 (16 bits): pointer to script table (reset?)
3850 * There doesn't appear to be a count value to say how many
3851 * entries exist in each script table, instead, a 0 value in
3852 * the first 16-bit word seems to indicate both the end of the
3853 * list and the default entry. The second 16-bit word in the
3854 * script tables is a pointer to the script to execute.
3857 NV_DEBUG(dev
, "Searching for output entry for %d %d %d\n",
3858 dcbent
->type
, dcbent
->location
, dcbent
->or);
3859 otable
= bios_output_config_match(dev
, dcbent
, table
[1] +
3860 bios
->display
.script_table_ptr
,
3861 table
[2], table
[3]);
3863 NV_ERROR(dev
, "Couldn't find matching output script table\n");
3867 if (pxclk
< -2 || pxclk
> 0) {
3868 /* Try to find matching script table entry */
3869 for (i
= 0; i
< otable
[5]; i
++) {
3870 if (ROM16(otable
[table
[4] + i
*6]) == sub
)
3874 if (i
== otable
[5]) {
3875 NV_ERROR(dev
, "Table 0x%04x not found for %d/%d, "
3877 sub
, dcbent
->type
, dcbent
->or);
3882 bios
->display
.output
= dcbent
;
3885 script
= ROM16(otable
[6]);
3887 NV_DEBUG(dev
, "output script 0 not found\n");
3891 NV_TRACE(dev
, "0x%04X: parsing output script 0\n", script
);
3892 parse_init_table(bios
, script
, &iexec
);
3895 script
= ROM16(otable
[8]);
3897 NV_DEBUG(dev
, "output script 1 not found\n");
3901 NV_TRACE(dev
, "0x%04X: parsing output script 1\n", script
);
3902 parse_init_table(bios
, script
, &iexec
);
3906 script
= ROM16(otable
[10]);
3910 NV_DEBUG(dev
, "output script 2 not found\n");
3914 NV_TRACE(dev
, "0x%04X: parsing output script 2\n", script
);
3915 parse_init_table(bios
, script
, &iexec
);
3918 script
= ROM16(otable
[table
[4] + i
*6 + 2]);
3920 script
= clkcmptable(bios
, script
, pxclk
);
3922 NV_ERROR(dev
, "clock script 0 not found\n");
3926 NV_TRACE(dev
, "0x%04X: parsing clock script 0\n", script
);
3927 parse_init_table(bios
, script
, &iexec
);
3930 script
= ROM16(otable
[table
[4] + i
*6 + 4]);
3932 script
= clkcmptable(bios
, script
, -pxclk
);
3934 NV_DEBUG(dev
, "clock script 1 not found\n");
3938 NV_TRACE(dev
, "0x%04X: parsing clock script 1\n", script
);
3939 parse_init_table(bios
, script
, &iexec
);
3946 int run_tmds_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, int pxclk
)
3949 * the pxclk parameter is in kHz
3951 * This runs the TMDS regs setting code found on BIT bios cards
3953 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
3954 * ffs(or) == 3, use the second.
3957 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3958 struct nvbios
*bios
= &dev_priv
->VBIOS
;
3959 int cv
= bios
->pub
.chip_version
;
3960 uint16_t clktable
= 0, scriptptr
;
3961 uint32_t sel_clk_binding
, sel_clk
;
3963 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
3964 if (cv
>= 0x17 && cv
!= 0x1a && cv
!= 0x20 &&
3965 dcbent
->location
!= DCB_LOC_ON_CHIP
)
3968 switch (ffs(dcbent
->or)) {
3970 clktable
= bios
->tmds
.output0_script_ptr
;
3974 clktable
= bios
->tmds
.output1_script_ptr
;
3979 NV_ERROR(dev
, "Pixel clock comparison table not found\n");
3983 scriptptr
= clkcmptable(bios
, clktable
, pxclk
);
3986 NV_ERROR(dev
, "TMDS output init script not found\n");
3990 /* don't let script change pll->head binding */
3991 sel_clk_binding
= bios_rd32(bios
, NV_PRAMDAC_SEL_CLK
) & 0x50000;
3992 run_digital_op_script(dev
, scriptptr
, dcbent
, head
, pxclk
>= 165000);
3993 sel_clk
= NVReadRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
) & ~0x50000;
3994 NVWriteRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
, sel_clk
| sel_clk_binding
);
3999 int get_pll_limits(struct drm_device
*dev
, uint32_t limit_match
, struct pll_lims
*pll_lim
)
4004 * Version 0x10: NV30, NV31
4005 * One byte header (version), one record of 24 bytes
4006 * Version 0x11: NV36 - Not implemented
4007 * Seems to have same record style as 0x10, but 3 records rather than 1
4008 * Version 0x20: Found on Geforce 6 cards
4009 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4010 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4011 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4012 * length in general, some (integrated) have an extra configuration byte
4013 * Version 0x30: Found on Geforce 8, separates the register mapping
4014 * from the limits tables.
4017 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4018 struct nvbios
*bios
= &dev_priv
->VBIOS
;
4019 int cv
= bios
->pub
.chip_version
, pllindex
= 0;
4020 uint8_t pll_lim_ver
= 0, headerlen
= 0, recordlen
= 0, entries
= 0;
4021 uint32_t crystal_strap_mask
, crystal_straps
;
4023 if (!bios
->pll_limit_tbl_ptr
) {
4024 if (cv
== 0x30 || cv
== 0x31 || cv
== 0x35 || cv
== 0x36 ||
4026 NV_ERROR(dev
, "Pointer to PLL limits table invalid\n");
4030 pll_lim_ver
= bios
->data
[bios
->pll_limit_tbl_ptr
];
4032 crystal_strap_mask
= 1 << 6;
4033 /* open coded dev->twoHeads test */
4034 if (cv
> 0x10 && cv
!= 0x15 && cv
!= 0x1a && cv
!= 0x20)
4035 crystal_strap_mask
|= 1 << 22;
4036 crystal_straps
= nvReadEXTDEV(dev
, NV_PEXTDEV_BOOT_0
) &
4039 switch (pll_lim_ver
) {
4041 * We use version 0 to indicate a pre limit table bios (single stage
4042 * pll) and load the hard coded limits instead.
4049 * Strictly v0x11 has 3 entries, but the last two don't seem
4061 headerlen
= bios
->data
[bios
->pll_limit_tbl_ptr
+ 1];
4062 recordlen
= bios
->data
[bios
->pll_limit_tbl_ptr
+ 2];
4063 entries
= bios
->data
[bios
->pll_limit_tbl_ptr
+ 3];
4066 NV_ERROR(dev
, "PLL limits table revision 0x%X not currently "
4067 "supported\n", pll_lim_ver
);
4071 /* initialize all members to zero */
4072 memset(pll_lim
, 0, sizeof(struct pll_lims
));
4074 if (pll_lim_ver
== 0x10 || pll_lim_ver
== 0x11) {
4075 uint8_t *pll_rec
= &bios
->data
[bios
->pll_limit_tbl_ptr
+ headerlen
+ recordlen
* pllindex
];
4077 pll_lim
->vco1
.minfreq
= ROM32(pll_rec
[0]);
4078 pll_lim
->vco1
.maxfreq
= ROM32(pll_rec
[4]);
4079 pll_lim
->vco2
.minfreq
= ROM32(pll_rec
[8]);
4080 pll_lim
->vco2
.maxfreq
= ROM32(pll_rec
[12]);
4081 pll_lim
->vco1
.min_inputfreq
= ROM32(pll_rec
[16]);
4082 pll_lim
->vco2
.min_inputfreq
= ROM32(pll_rec
[20]);
4083 pll_lim
->vco1
.max_inputfreq
= pll_lim
->vco2
.max_inputfreq
= INT_MAX
;
4085 /* these values taken from nv30/31/36 */
4086 pll_lim
->vco1
.min_n
= 0x1;
4088 pll_lim
->vco1
.min_n
= 0x5;
4089 pll_lim
->vco1
.max_n
= 0xff;
4090 pll_lim
->vco1
.min_m
= 0x1;
4091 pll_lim
->vco1
.max_m
= 0xd;
4092 pll_lim
->vco2
.min_n
= 0x4;
4094 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4095 * table version (apart from nv35)), N2 is compared to
4096 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4099 pll_lim
->vco2
.max_n
= 0x28;
4100 if (cv
== 0x30 || cv
== 0x35)
4101 /* only 5 bits available for N2 on nv30/35 */
4102 pll_lim
->vco2
.max_n
= 0x1f;
4103 pll_lim
->vco2
.min_m
= 0x1;
4104 pll_lim
->vco2
.max_m
= 0x4;
4105 pll_lim
->max_log2p
= 0x7;
4106 pll_lim
->max_usable_log2p
= 0x6;
4107 } else if (pll_lim_ver
== 0x20 || pll_lim_ver
== 0x21) {
4108 uint16_t plloffs
= bios
->pll_limit_tbl_ptr
+ headerlen
;
4109 uint32_t reg
= 0; /* default match */
4114 * First entry is default match, if nothing better. warn if
4117 if (ROM32(bios
->data
[plloffs
]))
4118 NV_WARN(dev
, "Default PLL limit entry has non-zero "
4119 "register field\n");
4121 if (limit_match
> MAX_PLL_TYPES
)
4122 /* we've been passed a reg as the match */
4124 else /* limit match is a pll type */
4125 for (i
= 1; i
< entries
&& !reg
; i
++) {
4126 uint32_t cmpreg
= ROM32(bios
->data
[plloffs
+ recordlen
* i
]);
4128 if (limit_match
== NVPLL
&&
4129 (cmpreg
== NV_PRAMDAC_NVPLL_COEFF
|| cmpreg
== 0x4000))
4131 if (limit_match
== MPLL
&&
4132 (cmpreg
== NV_PRAMDAC_MPLL_COEFF
|| cmpreg
== 0x4020))
4134 if (limit_match
== VPLL1
&&
4135 (cmpreg
== NV_PRAMDAC_VPLL_COEFF
|| cmpreg
== 0x4010))
4137 if (limit_match
== VPLL2
&&
4138 (cmpreg
== NV_RAMDAC_VPLL2
|| cmpreg
== 0x4018))
4142 for (i
= 1; i
< entries
; i
++)
4143 if (ROM32(bios
->data
[plloffs
+ recordlen
* i
]) == reg
) {
4148 pll_rec
= &bios
->data
[plloffs
+ recordlen
* pllindex
];
4150 BIOSLOG(bios
, "Loading PLL limits for reg 0x%08x\n",
4151 pllindex
? reg
: 0);
4154 * Frequencies are stored in tables in MHz, kHz are more
4155 * useful, so we convert.
4158 /* What output frequencies can each VCO generate? */
4159 pll_lim
->vco1
.minfreq
= ROM16(pll_rec
[4]) * 1000;
4160 pll_lim
->vco1
.maxfreq
= ROM16(pll_rec
[6]) * 1000;
4161 pll_lim
->vco2
.minfreq
= ROM16(pll_rec
[8]) * 1000;
4162 pll_lim
->vco2
.maxfreq
= ROM16(pll_rec
[10]) * 1000;
4164 /* What input frequencies they accept (past the m-divider)? */
4165 pll_lim
->vco1
.min_inputfreq
= ROM16(pll_rec
[12]) * 1000;
4166 pll_lim
->vco2
.min_inputfreq
= ROM16(pll_rec
[14]) * 1000;
4167 pll_lim
->vco1
.max_inputfreq
= ROM16(pll_rec
[16]) * 1000;
4168 pll_lim
->vco2
.max_inputfreq
= ROM16(pll_rec
[18]) * 1000;
4170 /* What values are accepted as multiplier and divider? */
4171 pll_lim
->vco1
.min_n
= pll_rec
[20];
4172 pll_lim
->vco1
.max_n
= pll_rec
[21];
4173 pll_lim
->vco1
.min_m
= pll_rec
[22];
4174 pll_lim
->vco1
.max_m
= pll_rec
[23];
4175 pll_lim
->vco2
.min_n
= pll_rec
[24];
4176 pll_lim
->vco2
.max_n
= pll_rec
[25];
4177 pll_lim
->vco2
.min_m
= pll_rec
[26];
4178 pll_lim
->vco2
.max_m
= pll_rec
[27];
4180 pll_lim
->max_usable_log2p
= pll_lim
->max_log2p
= pll_rec
[29];
4181 if (pll_lim
->max_log2p
> 0x7)
4182 /* pll decoding in nv_hw.c assumes never > 7 */
4183 NV_WARN(dev
, "Max log2 P value greater than 7 (%d)\n",
4184 pll_lim
->max_log2p
);
4186 pll_lim
->max_usable_log2p
= 0x6;
4187 pll_lim
->log2p_bias
= pll_rec
[30];
4189 if (recordlen
> 0x22)
4190 pll_lim
->refclk
= ROM32(pll_rec
[31]);
4192 if (recordlen
> 0x23 && pll_rec
[35])
4194 "Bits set in PLL configuration byte (%x)\n",
4197 /* C51 special not seen elsewhere */
4198 if (cv
== 0x51 && !pll_lim
->refclk
) {
4199 uint32_t sel_clk
= bios_rd32(bios
, NV_PRAMDAC_SEL_CLK
);
4201 if (((limit_match
== NV_PRAMDAC_VPLL_COEFF
|| limit_match
== VPLL1
) && sel_clk
& 0x20) ||
4202 ((limit_match
== NV_RAMDAC_VPLL2
|| limit_match
== VPLL2
) && sel_clk
& 0x80)) {
4203 if (bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_CHIP_ID_INDEX
) < 0xa3)
4204 pll_lim
->refclk
= 200000;
4206 pll_lim
->refclk
= 25000;
4209 } else if (pll_lim_ver
== 0x30) { /* ver 0x30 */
4210 uint8_t *entry
= &bios
->data
[bios
->pll_limit_tbl_ptr
+ headerlen
];
4211 uint8_t *record
= NULL
;
4214 BIOSLOG(bios
, "Loading PLL limits for register 0x%08x\n",
4217 for (i
= 0; i
< entries
; i
++, entry
+= recordlen
) {
4218 if (ROM32(entry
[3]) == limit_match
) {
4219 record
= &bios
->data
[ROM16(entry
[1])];
4225 NV_ERROR(dev
, "Register 0x%08x not found in PLL "
4226 "limits table", limit_match
);
4230 pll_lim
->vco1
.minfreq
= ROM16(record
[0]) * 1000;
4231 pll_lim
->vco1
.maxfreq
= ROM16(record
[2]) * 1000;
4232 pll_lim
->vco2
.minfreq
= ROM16(record
[4]) * 1000;
4233 pll_lim
->vco2
.maxfreq
= ROM16(record
[6]) * 1000;
4234 pll_lim
->vco1
.min_inputfreq
= ROM16(record
[8]) * 1000;
4235 pll_lim
->vco2
.min_inputfreq
= ROM16(record
[10]) * 1000;
4236 pll_lim
->vco1
.max_inputfreq
= ROM16(record
[12]) * 1000;
4237 pll_lim
->vco2
.max_inputfreq
= ROM16(record
[14]) * 1000;
4238 pll_lim
->vco1
.min_n
= record
[16];
4239 pll_lim
->vco1
.max_n
= record
[17];
4240 pll_lim
->vco1
.min_m
= record
[18];
4241 pll_lim
->vco1
.max_m
= record
[19];
4242 pll_lim
->vco2
.min_n
= record
[20];
4243 pll_lim
->vco2
.max_n
= record
[21];
4244 pll_lim
->vco2
.min_m
= record
[22];
4245 pll_lim
->vco2
.max_m
= record
[23];
4246 pll_lim
->max_usable_log2p
= pll_lim
->max_log2p
= record
[25];
4247 pll_lim
->log2p_bias
= record
[27];
4248 pll_lim
->refclk
= ROM32(record
[28]);
4249 } else if (pll_lim_ver
) { /* ver 0x40 */
4250 uint8_t *entry
= &bios
->data
[bios
->pll_limit_tbl_ptr
+ headerlen
];
4251 uint8_t *record
= NULL
;
4254 BIOSLOG(bios
, "Loading PLL limits for register 0x%08x\n",
4257 for (i
= 0; i
< entries
; i
++, entry
+= recordlen
) {
4258 if (ROM32(entry
[3]) == limit_match
) {
4259 record
= &bios
->data
[ROM16(entry
[1])];
4265 NV_ERROR(dev
, "Register 0x%08x not found in PLL "
4266 "limits table", limit_match
);
4270 pll_lim
->vco1
.minfreq
= ROM16(record
[0]) * 1000;
4271 pll_lim
->vco1
.maxfreq
= ROM16(record
[2]) * 1000;
4272 pll_lim
->vco1
.min_inputfreq
= ROM16(record
[4]) * 1000;
4273 pll_lim
->vco1
.max_inputfreq
= ROM16(record
[6]) * 1000;
4274 pll_lim
->vco1
.min_m
= record
[8];
4275 pll_lim
->vco1
.max_m
= record
[9];
4276 pll_lim
->vco1
.min_n
= record
[10];
4277 pll_lim
->vco1
.max_n
= record
[11];
4278 pll_lim
->min_p
= record
[12];
4279 pll_lim
->max_p
= record
[13];
4280 /* where did this go to?? */
4281 if (limit_match
== 0x00614100 || limit_match
== 0x00614900)
4282 pll_lim
->refclk
= 27000;
4284 pll_lim
->refclk
= 100000;
4288 * By now any valid limit table ought to have set a max frequency for
4289 * vco1, so if it's zero it's either a pre limit table bios, or one
4290 * with an empty limit table (seen on nv18)
4292 if (!pll_lim
->vco1
.maxfreq
) {
4293 pll_lim
->vco1
.minfreq
= bios
->fminvco
;
4294 pll_lim
->vco1
.maxfreq
= bios
->fmaxvco
;
4295 pll_lim
->vco1
.min_inputfreq
= 0;
4296 pll_lim
->vco1
.max_inputfreq
= INT_MAX
;
4297 pll_lim
->vco1
.min_n
= 0x1;
4298 pll_lim
->vco1
.max_n
= 0xff;
4299 pll_lim
->vco1
.min_m
= 0x1;
4300 if (crystal_straps
== 0) {
4301 /* nv05 does this, nv11 doesn't, nv10 unknown */
4303 pll_lim
->vco1
.min_m
= 0x7;
4304 pll_lim
->vco1
.max_m
= 0xd;
4307 pll_lim
->vco1
.min_m
= 0x8;
4308 pll_lim
->vco1
.max_m
= 0xe;
4310 if (cv
< 0x17 || cv
== 0x1a || cv
== 0x20)
4311 pll_lim
->max_log2p
= 4;
4313 pll_lim
->max_log2p
= 5;
4314 pll_lim
->max_usable_log2p
= pll_lim
->max_log2p
;
4317 if (!pll_lim
->refclk
)
4318 switch (crystal_straps
) {
4320 pll_lim
->refclk
= 13500;
4323 pll_lim
->refclk
= 14318;
4326 pll_lim
->refclk
= 27000;
4328 case (1 << 22 | 1 << 6):
4329 pll_lim
->refclk
= 25000;
4333 #if 0 /* for easy debugging */
4334 ErrorF("pll.vco1.minfreq: %d\n", pll_lim
->vco1
.minfreq
);
4335 ErrorF("pll.vco1.maxfreq: %d\n", pll_lim
->vco1
.maxfreq
);
4336 ErrorF("pll.vco2.minfreq: %d\n", pll_lim
->vco2
.minfreq
);
4337 ErrorF("pll.vco2.maxfreq: %d\n", pll_lim
->vco2
.maxfreq
);
4339 ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim
->vco1
.min_inputfreq
);
4340 ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim
->vco1
.max_inputfreq
);
4341 ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim
->vco2
.min_inputfreq
);
4342 ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim
->vco2
.max_inputfreq
);
4344 ErrorF("pll.vco1.min_n: %d\n", pll_lim
->vco1
.min_n
);
4345 ErrorF("pll.vco1.max_n: %d\n", pll_lim
->vco1
.max_n
);
4346 ErrorF("pll.vco1.min_m: %d\n", pll_lim
->vco1
.min_m
);
4347 ErrorF("pll.vco1.max_m: %d\n", pll_lim
->vco1
.max_m
);
4348 ErrorF("pll.vco2.min_n: %d\n", pll_lim
->vco2
.min_n
);
4349 ErrorF("pll.vco2.max_n: %d\n", pll_lim
->vco2
.max_n
);
4350 ErrorF("pll.vco2.min_m: %d\n", pll_lim
->vco2
.min_m
);
4351 ErrorF("pll.vco2.max_m: %d\n", pll_lim
->vco2
.max_m
);
4353 ErrorF("pll.max_log2p: %d\n", pll_lim
->max_log2p
);
4354 ErrorF("pll.log2p_bias: %d\n", pll_lim
->log2p_bias
);
4356 ErrorF("pll.refclk: %d\n", pll_lim
->refclk
);
4362 static void parse_bios_version(struct drm_device
*dev
, struct nvbios
*bios
, uint16_t offset
)
4365 * offset + 0 (8 bits): Micro version
4366 * offset + 1 (8 bits): Minor version
4367 * offset + 2 (8 bits): Chip version
4368 * offset + 3 (8 bits): Major version
4371 bios
->major_version
= bios
->data
[offset
+ 3];
4372 bios
->pub
.chip_version
= bios
->data
[offset
+ 2];
4373 NV_TRACE(dev
, "Bios version %02x.%02x.%02x.%02x\n",
4374 bios
->data
[offset
+ 3], bios
->data
[offset
+ 2],
4375 bios
->data
[offset
+ 1], bios
->data
[offset
]);
4378 static void parse_script_table_pointers(struct nvbios
*bios
, uint16_t offset
)
4381 * Parses the init table segment for pointers used in script execution.
4383 * offset + 0 (16 bits): init script tables pointer
4384 * offset + 2 (16 bits): macro index table pointer
4385 * offset + 4 (16 bits): macro table pointer
4386 * offset + 6 (16 bits): condition table pointer
4387 * offset + 8 (16 bits): io condition table pointer
4388 * offset + 10 (16 bits): io flag condition table pointer
4389 * offset + 12 (16 bits): init function table pointer
4392 bios
->init_script_tbls_ptr
= ROM16(bios
->data
[offset
]);
4393 bios
->macro_index_tbl_ptr
= ROM16(bios
->data
[offset
+ 2]);
4394 bios
->macro_tbl_ptr
= ROM16(bios
->data
[offset
+ 4]);
4395 bios
->condition_tbl_ptr
= ROM16(bios
->data
[offset
+ 6]);
4396 bios
->io_condition_tbl_ptr
= ROM16(bios
->data
[offset
+ 8]);
4397 bios
->io_flag_condition_tbl_ptr
= ROM16(bios
->data
[offset
+ 10]);
4398 bios
->init_function_tbl_ptr
= ROM16(bios
->data
[offset
+ 12]);
4401 static int parse_bit_A_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
4404 * Parses the load detect values for g80 cards.
4406 * offset + 0 (16 bits): loadval table pointer
4409 uint16_t load_table_ptr
;
4410 uint8_t version
, headerlen
, entrylen
, num_entries
;
4412 if (bitentry
->length
!= 3) {
4413 NV_ERROR(dev
, "Do not understand BIT A table\n");
4417 load_table_ptr
= ROM16(bios
->data
[bitentry
->offset
]);
4419 if (load_table_ptr
== 0x0) {
4420 NV_ERROR(dev
, "Pointer to BIT loadval table invalid\n");
4424 version
= bios
->data
[load_table_ptr
];
4426 if (version
!= 0x10) {
4427 NV_ERROR(dev
, "BIT loadval table version %d.%d not supported\n",
4428 version
>> 4, version
& 0xF);
4432 headerlen
= bios
->data
[load_table_ptr
+ 1];
4433 entrylen
= bios
->data
[load_table_ptr
+ 2];
4434 num_entries
= bios
->data
[load_table_ptr
+ 3];
4436 if (headerlen
!= 4 || entrylen
!= 4 || num_entries
!= 2) {
4437 NV_ERROR(dev
, "Do not understand BIT loadval table\n");
4441 /* First entry is normal dac, 2nd tv-out perhaps? */
4442 bios
->pub
.dactestval
= ROM32(bios
->data
[load_table_ptr
+ headerlen
]) & 0x3ff;
4447 static int parse_bit_C_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
4450 * offset + 8 (16 bits): PLL limits table pointer
4452 * There's more in here, but that's unknown.
4455 if (bitentry
->length
< 10) {
4456 NV_ERROR(dev
, "Do not understand BIT C table\n");
4460 bios
->pll_limit_tbl_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 8]);
4465 static int parse_bit_display_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
4468 * Parses the flat panel table segment that the bit entry points to.
4469 * Starting at bitentry->offset:
4471 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
4472 * records beginning with a freq.
4473 * offset + 2 (16 bits): mode table pointer
4476 if (bitentry
->length
!= 4) {
4477 NV_ERROR(dev
, "Do not understand BIT display table\n");
4481 bios
->fp
.fptablepointer
= ROM16(bios
->data
[bitentry
->offset
+ 2]);
4486 static int parse_bit_init_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
4489 * Parses the init table segment that the bit entry points to.
4491 * See parse_script_table_pointers for layout
4494 if (bitentry
->length
< 14) {
4495 NV_ERROR(dev
, "Do not understand init table\n");
4499 parse_script_table_pointers(bios
, bitentry
->offset
);
4501 if (bitentry
->length
>= 16)
4502 bios
->some_script_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 14]);
4503 if (bitentry
->length
>= 18)
4504 bios
->init96_tbl_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 16]);
4509 static int parse_bit_i_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
4512 * BIT 'i' (info?) table
4514 * offset + 0 (32 bits): BIOS version dword (as in B table)
4515 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
4516 * offset + 13 (16 bits): pointer to table containing DAC load
4517 * detection comparison values
4519 * There's other things in the table, purpose unknown
4522 uint16_t daccmpoffset
;
4523 uint8_t dacver
, dacheaderlen
;
4525 if (bitentry
->length
< 6) {
4526 NV_ERROR(dev
, "BIT i table too short for needed information\n");
4530 parse_bios_version(dev
, bios
, bitentry
->offset
);
4533 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
4534 * Quadro identity crisis), other bits possibly as for BMP feature byte
4536 bios
->feature_byte
= bios
->data
[bitentry
->offset
+ 5];
4537 bios
->is_mobile
= bios
->feature_byte
& FEATURE_MOBILE
;
4539 if (bitentry
->length
< 15) {
4540 NV_WARN(dev
, "BIT i table not long enough for DAC load "
4541 "detection comparison table\n");
4545 daccmpoffset
= ROM16(bios
->data
[bitentry
->offset
+ 13]);
4547 /* doesn't exist on g80 */
4552 * The first value in the table, following the header, is the
4553 * comparison value, the second entry is a comparison value for
4554 * TV load detection.
4557 dacver
= bios
->data
[daccmpoffset
];
4558 dacheaderlen
= bios
->data
[daccmpoffset
+ 1];
4560 if (dacver
!= 0x00 && dacver
!= 0x10) {
4561 NV_WARN(dev
, "DAC load detection comparison table version "
4562 "%d.%d not known\n", dacver
>> 4, dacver
& 0xf);
4566 bios
->pub
.dactestval
= ROM32(bios
->data
[daccmpoffset
+ dacheaderlen
]);
4567 bios
->pub
.tvdactestval
= ROM32(bios
->data
[daccmpoffset
+ dacheaderlen
+ 4]);
4572 static int parse_bit_lvds_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
4575 * Parses the LVDS table segment that the bit entry points to.
4576 * Starting at bitentry->offset:
4578 * offset + 0 (16 bits): LVDS strap xlate table pointer
4581 if (bitentry
->length
!= 2) {
4582 NV_ERROR(dev
, "Do not understand BIT LVDS table\n");
4587 * No idea if it's still called the LVDS manufacturer table, but
4588 * the concept's close enough.
4590 bios
->fp
.lvdsmanufacturerpointer
= ROM16(bios
->data
[bitentry
->offset
]);
4596 parse_bit_M_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
,
4597 struct bit_entry
*bitentry
)
4600 * offset + 2 (8 bits): number of options in an
4601 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
4602 * offset + 3 (16 bits): pointer to strap xlate table for RAM
4603 * restrict option selection
4605 * There's a bunch of bits in this table other than the RAM restrict
4606 * stuff that we don't use - their use currently unknown
4609 uint16_t rr_strap_xlat
;
4610 uint8_t rr_group_count
;
4614 * Older bios versions don't have a sufficiently long table for
4617 if (bitentry
->length
< 0x5)
4620 if (bitentry
->id
[1] < 2) {
4621 rr_group_count
= bios
->data
[bitentry
->offset
+ 2];
4622 rr_strap_xlat
= ROM16(bios
->data
[bitentry
->offset
+ 3]);
4624 rr_group_count
= bios
->data
[bitentry
->offset
+ 0];
4625 rr_strap_xlat
= ROM16(bios
->data
[bitentry
->offset
+ 1]);
4628 /* adjust length of INIT_87 */
4629 for (i
= 0; itbl_entry
[i
].name
&& (itbl_entry
[i
].id
!= 0x87); i
++);
4630 itbl_entry
[i
].length
+= rr_group_count
* 4;
4632 /* set up multiplier for INIT_RAM_RESTRICT_ZM_REG_GROUP */
4633 for (; itbl_entry
[i
].name
&& (itbl_entry
[i
].id
!= 0x8f); i
++);
4634 itbl_entry
[i
].length_multiplier
= rr_group_count
* 4;
4636 init_ram_restrict_zm_reg_group_blocklen
= itbl_entry
[i
].length_multiplier
;
4637 bios
->ram_restrict_tbl_ptr
= rr_strap_xlat
;
4642 static int parse_bit_tmds_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
4645 * Parses the pointer to the TMDS table
4647 * Starting at bitentry->offset:
4649 * offset + 0 (16 bits): TMDS table pointer
4651 * The TMDS table is typically found just before the DCB table, with a
4652 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
4655 * At offset +7 is a pointer to a script, which I don't know how to
4657 * At offset +9 is a pointer to another script, likewise
4658 * Offset +11 has a pointer to a table where the first word is a pxclk
4659 * frequency and the second word a pointer to a script, which should be
4660 * run if the comparison pxclk frequency is less than the pxclk desired.
4661 * This repeats for decreasing comparison frequencies
4662 * Offset +13 has a pointer to a similar table
4663 * The selection of table (and possibly +7/+9 script) is dictated by
4664 * "or" from the DCB.
4667 uint16_t tmdstableptr
, script1
, script2
;
4669 if (bitentry
->length
!= 2) {
4670 NV_ERROR(dev
, "Do not understand BIT TMDS table\n");
4674 tmdstableptr
= ROM16(bios
->data
[bitentry
->offset
]);
4676 if (tmdstableptr
== 0x0) {
4677 NV_ERROR(dev
, "Pointer to TMDS table invalid\n");
4681 /* nv50+ has v2.0, but we don't parse it atm */
4682 if (bios
->data
[tmdstableptr
] != 0x11) {
4684 "TMDS table revision %d.%d not currently supported\n",
4685 bios
->data
[tmdstableptr
] >> 4, bios
->data
[tmdstableptr
] & 0xf);
4690 * These two scripts are odd: they don't seem to get run even when
4691 * they are not stubbed.
4693 script1
= ROM16(bios
->data
[tmdstableptr
+ 7]);
4694 script2
= ROM16(bios
->data
[tmdstableptr
+ 9]);
4695 if (bios
->data
[script1
] != 'q' || bios
->data
[script2
] != 'q')
4696 NV_WARN(dev
, "TMDS table script pointers not stubbed\n");
4698 bios
->tmds
.output0_script_ptr
= ROM16(bios
->data
[tmdstableptr
+ 11]);
4699 bios
->tmds
.output1_script_ptr
= ROM16(bios
->data
[tmdstableptr
+ 13]);
4705 parse_bit_U_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
,
4706 struct bit_entry
*bitentry
)
4709 * Parses the pointer to the G80 output script tables
4711 * Starting at bitentry->offset:
4713 * offset + 0 (16 bits): output script table pointer
4716 uint16_t outputscripttableptr
;
4718 if (bitentry
->length
!= 3) {
4719 NV_ERROR(dev
, "Do not understand BIT U table\n");
4723 outputscripttableptr
= ROM16(bios
->data
[bitentry
->offset
]);
4724 bios
->display
.script_table_ptr
= outputscripttableptr
;
4729 parse_bit_displayport_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
,
4730 struct bit_entry
*bitentry
)
4732 bios
->display
.dp_table_ptr
= ROM16(bios
->data
[bitentry
->offset
]);
4738 int (* const parse_fn
)(struct drm_device
*, struct nvbios
*, struct bit_entry
*);
4741 #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
4744 parse_bit_table(struct nvbios
*bios
, const uint16_t bitoffset
,
4745 struct bit_table
*table
)
4747 struct drm_device
*dev
= bios
->dev
;
4748 uint8_t maxentries
= bios
->data
[bitoffset
+ 4];
4750 struct bit_entry bitentry
;
4752 for (i
= 0, offset
= bitoffset
+ 6; i
< maxentries
; i
++, offset
+= 6) {
4753 bitentry
.id
[0] = bios
->data
[offset
];
4755 if (bitentry
.id
[0] != table
->id
)
4758 bitentry
.id
[1] = bios
->data
[offset
+ 1];
4759 bitentry
.length
= ROM16(bios
->data
[offset
+ 2]);
4760 bitentry
.offset
= ROM16(bios
->data
[offset
+ 4]);
4762 return table
->parse_fn(dev
, bios
, &bitentry
);
4765 NV_INFO(dev
, "BIT table '%c' not found\n", table
->id
);
4770 parse_bit_structure(struct nvbios
*bios
, const uint16_t bitoffset
)
4775 * The only restriction on parsing order currently is having 'i' first
4776 * for use of bios->*_version or bios->feature_byte while parsing;
4777 * functions shouldn't be actually *doing* anything apart from pulling
4778 * data from the image into the bios struct, thus no interdependencies
4780 ret
= parse_bit_table(bios
, bitoffset
, &BIT_TABLE('i', i
));
4781 if (ret
) /* info? */
4783 if (bios
->major_version
>= 0x60) /* g80+ */
4784 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('A', A
));
4785 ret
= parse_bit_table(bios
, bitoffset
, &BIT_TABLE('C', C
));
4788 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('D', display
));
4789 ret
= parse_bit_table(bios
, bitoffset
, &BIT_TABLE('I', init
));
4792 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('M', M
)); /* memory? */
4793 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('L', lvds
));
4794 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('T', tmds
));
4795 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('U', U
));
4796 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('d', displayport
));
4801 static int parse_bmp_structure(struct drm_device
*dev
, struct nvbios
*bios
, unsigned int offset
)
4804 * Parses the BMP structure for useful things, but does not act on them
4806 * offset + 5: BMP major version
4807 * offset + 6: BMP minor version
4808 * offset + 9: BMP feature byte
4809 * offset + 10: BCD encoded BIOS version
4811 * offset + 18: init script table pointer (for bios versions < 5.10h)
4812 * offset + 20: extra init script table pointer (for bios
4815 * offset + 24: memory init table pointer (used on early bios versions)
4816 * offset + 26: SDR memory sequencing setup data table
4817 * offset + 28: DDR memory sequencing setup data table
4819 * offset + 54: index of I2C CRTC pair to use for CRT output
4820 * offset + 55: index of I2C CRTC pair to use for TV output
4821 * offset + 56: index of I2C CRTC pair to use for flat panel output
4822 * offset + 58: write CRTC index for I2C pair 0
4823 * offset + 59: read CRTC index for I2C pair 0
4824 * offset + 60: write CRTC index for I2C pair 1
4825 * offset + 61: read CRTC index for I2C pair 1
4827 * offset + 67: maximum internal PLL frequency (single stage PLL)
4828 * offset + 71: minimum internal PLL frequency (single stage PLL)
4830 * offset + 75: script table pointers, as described in
4831 * parse_script_table_pointers
4833 * offset + 89: TMDS single link output A table pointer
4834 * offset + 91: TMDS single link output B table pointer
4835 * offset + 95: LVDS single link output A table pointer
4836 * offset + 105: flat panel timings table pointer
4837 * offset + 107: flat panel strapping translation table pointer
4838 * offset + 117: LVDS manufacturer panel config table pointer
4839 * offset + 119: LVDS manufacturer strapping translation table pointer
4841 * offset + 142: PLL limits table pointer
4843 * offset + 156: minimum pixel clock for LVDS dual link
4846 uint8_t *bmp
= &bios
->data
[offset
], bmp_version_major
, bmp_version_minor
;
4848 uint16_t legacy_scripts_offset
, legacy_i2c_offset
;
4850 /* load needed defaults in case we can't parse this info */
4851 bios
->bdcb
.dcb
.i2c
[0].write
= NV_CIO_CRE_DDC_WR__INDEX
;
4852 bios
->bdcb
.dcb
.i2c
[0].read
= NV_CIO_CRE_DDC_STATUS__INDEX
;
4853 bios
->bdcb
.dcb
.i2c
[1].write
= NV_CIO_CRE_DDC0_WR__INDEX
;
4854 bios
->bdcb
.dcb
.i2c
[1].read
= NV_CIO_CRE_DDC0_STATUS__INDEX
;
4855 bios
->pub
.digital_min_front_porch
= 0x4b;
4856 bios
->fmaxvco
= 256000;
4857 bios
->fminvco
= 128000;
4858 bios
->fp
.duallink_transition_clk
= 90000;
4860 bmp_version_major
= bmp
[5];
4861 bmp_version_minor
= bmp
[6];
4863 NV_TRACE(dev
, "BMP version %d.%d\n",
4864 bmp_version_major
, bmp_version_minor
);
4867 * Make sure that 0x36 is blank and can't be mistaken for a DCB
4868 * pointer on early versions
4870 if (bmp_version_major
< 5)
4871 *(uint16_t *)&bios
->data
[0x36] = 0;
4874 * Seems that the minor version was 1 for all major versions prior
4875 * to 5. Version 6 could theoretically exist, but I suspect BIT
4878 if ((bmp_version_major
< 5 && bmp_version_minor
!= 1) || bmp_version_major
> 5) {
4879 NV_ERROR(dev
, "You have an unsupported BMP version. "
4880 "Please send in your bios\n");
4884 if (bmp_version_major
== 0)
4885 /* nothing that's currently useful in this version */
4887 else if (bmp_version_major
== 1)
4888 bmplength
= 44; /* exact for 1.01 */
4889 else if (bmp_version_major
== 2)
4890 bmplength
= 48; /* exact for 2.01 */
4891 else if (bmp_version_major
== 3)
4893 /* guessed - mem init tables added in this version */
4894 else if (bmp_version_major
== 4 || bmp_version_minor
< 0x1)
4895 /* don't know if 5.0 exists... */
4897 /* guessed - BMP I2C indices added in version 4*/
4898 else if (bmp_version_minor
< 0x6)
4899 bmplength
= 67; /* exact for 5.01 */
4900 else if (bmp_version_minor
< 0x10)
4901 bmplength
= 75; /* exact for 5.06 */
4902 else if (bmp_version_minor
== 0x10)
4903 bmplength
= 89; /* exact for 5.10h */
4904 else if (bmp_version_minor
< 0x14)
4905 bmplength
= 118; /* exact for 5.11h */
4906 else if (bmp_version_minor
< 0x24)
4908 * Not sure of version where pll limits came in;
4909 * certainly exist by 0x24 though.
4911 /* length not exact: this is long enough to get lvds members */
4913 else if (bmp_version_minor
< 0x27)
4915 * Length not exact: this is long enough to get pll limit
4921 * Length not exact: this is long enough to get dual link
4927 if (nv_cksum(bmp
, 8)) {
4928 NV_ERROR(dev
, "Bad BMP checksum\n");
4933 * Bit 4 seems to indicate either a mobile bios or a quadro card --
4934 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
4935 * (not nv10gl), bit 5 that the flat panel tables are present, and
4938 bios
->feature_byte
= bmp
[9];
4940 parse_bios_version(dev
, bios
, offset
+ 10);
4942 if (bmp_version_major
< 5 || bmp_version_minor
< 0x10)
4943 bios
->old_style_init
= true;
4944 legacy_scripts_offset
= 18;
4945 if (bmp_version_major
< 2)
4946 legacy_scripts_offset
-= 4;
4947 bios
->init_script_tbls_ptr
= ROM16(bmp
[legacy_scripts_offset
]);
4948 bios
->extra_init_script_tbl_ptr
= ROM16(bmp
[legacy_scripts_offset
+ 2]);
4950 if (bmp_version_major
> 2) { /* appears in BMP 3 */
4951 bios
->legacy
.mem_init_tbl_ptr
= ROM16(bmp
[24]);
4952 bios
->legacy
.sdr_seq_tbl_ptr
= ROM16(bmp
[26]);
4953 bios
->legacy
.ddr_seq_tbl_ptr
= ROM16(bmp
[28]);
4956 legacy_i2c_offset
= 0x48; /* BMP version 2 & 3 */
4958 legacy_i2c_offset
= offset
+ 54;
4959 bios
->legacy
.i2c_indices
.crt
= bios
->data
[legacy_i2c_offset
];
4960 bios
->legacy
.i2c_indices
.tv
= bios
->data
[legacy_i2c_offset
+ 1];
4961 bios
->legacy
.i2c_indices
.panel
= bios
->data
[legacy_i2c_offset
+ 2];
4962 bios
->bdcb
.dcb
.i2c
[0].write
= bios
->data
[legacy_i2c_offset
+ 4];
4963 bios
->bdcb
.dcb
.i2c
[0].read
= bios
->data
[legacy_i2c_offset
+ 5];
4964 bios
->bdcb
.dcb
.i2c
[1].write
= bios
->data
[legacy_i2c_offset
+ 6];
4965 bios
->bdcb
.dcb
.i2c
[1].read
= bios
->data
[legacy_i2c_offset
+ 7];
4967 if (bmplength
> 74) {
4968 bios
->fmaxvco
= ROM32(bmp
[67]);
4969 bios
->fminvco
= ROM32(bmp
[71]);
4972 parse_script_table_pointers(bios
, offset
+ 75);
4973 if (bmplength
> 94) {
4974 bios
->tmds
.output0_script_ptr
= ROM16(bmp
[89]);
4975 bios
->tmds
.output1_script_ptr
= ROM16(bmp
[91]);
4977 * Never observed in use with lvds scripts, but is reused for
4978 * 18/24 bit panel interface default for EDID equipped panels
4979 * (if_is_24bit not set directly to avoid any oscillation).
4981 bios
->legacy
.lvds_single_a_script_ptr
= ROM16(bmp
[95]);
4983 if (bmplength
> 108) {
4984 bios
->fp
.fptablepointer
= ROM16(bmp
[105]);
4985 bios
->fp
.fpxlatetableptr
= ROM16(bmp
[107]);
4986 bios
->fp
.xlatwidth
= 1;
4988 if (bmplength
> 120) {
4989 bios
->fp
.lvdsmanufacturerpointer
= ROM16(bmp
[117]);
4990 bios
->fp
.fpxlatemanufacturertableptr
= ROM16(bmp
[119]);
4992 if (bmplength
> 143)
4993 bios
->pll_limit_tbl_ptr
= ROM16(bmp
[142]);
4995 if (bmplength
> 157)
4996 bios
->fp
.duallink_transition_clk
= ROM16(bmp
[156]) * 10;
5001 static uint16_t findstr(uint8_t *data
, int n
, const uint8_t *str
, int len
)
5005 for (i
= 0; i
<= (n
- len
); i
++) {
5006 for (j
= 0; j
< len
; j
++)
5007 if (data
[i
+ j
] != str
[j
])
5017 read_dcb_i2c_entry(struct drm_device
*dev
, int dcb_version
, uint8_t *i2ctable
, int index
, struct dcb_i2c_entry
*i2c
)
5019 uint8_t dcb_i2c_ver
= dcb_version
, headerlen
= 0, entry_len
= 4;
5020 int i2c_entries
= DCB_MAX_NUM_I2C_ENTRIES
;
5021 int recordoffset
= 0, rdofs
= 1, wrofs
= 0;
5022 uint8_t port_type
= 0;
5027 if (dcb_version
>= 0x30) {
5028 if (i2ctable
[0] != dcb_version
) /* necessary? */
5030 "DCB I2C table version mismatch (%02X vs %02X)\n",
5031 i2ctable
[0], dcb_version
);
5032 dcb_i2c_ver
= i2ctable
[0];
5033 headerlen
= i2ctable
[1];
5034 if (i2ctable
[2] <= DCB_MAX_NUM_I2C_ENTRIES
)
5035 i2c_entries
= i2ctable
[2];
5038 "DCB I2C table has more entries than indexable "
5039 "(%d entries, max index 15)\n", i2ctable
[2]);
5040 entry_len
= i2ctable
[3];
5041 /* [4] is i2c_default_indices, read in parse_dcb_table() */
5044 * It's your own fault if you call this function on a DCB 1.1 BIOS --
5045 * the test below is for DCB 1.2
5047 if (dcb_version
< 0x14) {
5055 if (index
> i2c_entries
) {
5056 NV_ERROR(dev
, "DCB I2C index too big (%d > %d)\n",
5057 index
, i2ctable
[2]);
5060 if (i2ctable
[headerlen
+ entry_len
* index
+ 3] == 0xff) {
5061 NV_ERROR(dev
, "DCB I2C entry invalid\n");
5065 if (dcb_i2c_ver
>= 0x30) {
5066 port_type
= i2ctable
[headerlen
+ recordoffset
+ 3 + entry_len
* index
];
5069 * Fixup for chips using same address offset for read and
5072 if (port_type
== 4) /* seen on C51 */
5074 if (port_type
>= 5) /* G80+ */
5078 if (dcb_i2c_ver
>= 0x40 && port_type
!= 5 && port_type
!= 6)
5079 NV_WARN(dev
, "DCB I2C table has port type %d\n", port_type
);
5081 i2c
->port_type
= port_type
;
5082 i2c
->read
= i2ctable
[headerlen
+ recordoffset
+ rdofs
+ entry_len
* index
];
5083 i2c
->write
= i2ctable
[headerlen
+ recordoffset
+ wrofs
+ entry_len
* index
];
5088 static struct dcb_gpio_entry
*
5089 new_gpio_entry(struct nvbios
*bios
)
5091 struct parsed_dcb_gpio
*gpio
= &bios
->bdcb
.gpio
;
5093 return &gpio
->entry
[gpio
->entries
++];
5096 struct dcb_gpio_entry
*
5097 nouveau_bios_gpio_entry(struct drm_device
*dev
, enum dcb_gpio_tag tag
)
5099 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5100 struct nvbios
*bios
= &dev_priv
->VBIOS
;
5103 for (i
= 0; i
< bios
->bdcb
.gpio
.entries
; i
++) {
5104 if (bios
->bdcb
.gpio
.entry
[i
].tag
!= tag
)
5107 return &bios
->bdcb
.gpio
.entry
[i
];
5114 parse_dcb30_gpio_entry(struct nvbios
*bios
, uint16_t offset
)
5116 struct dcb_gpio_entry
*gpio
;
5117 uint16_t ent
= ROM16(bios
->data
[offset
]);
5118 uint8_t line
= ent
& 0x1f,
5119 tag
= ent
>> 5 & 0x3f,
5120 flags
= ent
>> 11 & 0x1f;
5125 gpio
= new_gpio_entry(bios
);
5129 gpio
->invert
= flags
!= 4;
5133 parse_dcb40_gpio_entry(struct nvbios
*bios
, uint16_t offset
)
5135 struct dcb_gpio_entry
*gpio
;
5136 uint32_t ent
= ROM32(bios
->data
[offset
]);
5137 uint8_t line
= ent
& 0x1f,
5138 tag
= ent
>> 8 & 0xff;
5143 gpio
= new_gpio_entry(bios
);
5145 /* Currently unused, we may need more fields parsed at some
5152 parse_dcb_gpio_table(struct nvbios
*bios
)
5154 struct drm_device
*dev
= bios
->dev
;
5155 uint16_t gpio_table_ptr
= bios
->bdcb
.gpio_table_ptr
;
5156 uint8_t *gpio_table
= &bios
->data
[gpio_table_ptr
];
5157 int header_len
= gpio_table
[1],
5158 entries
= gpio_table
[2],
5159 entry_len
= gpio_table
[3];
5160 void (*parse_entry
)(struct nvbios
*, uint16_t) = NULL
;
5163 if (bios
->bdcb
.version
>= 0x40) {
5164 if (gpio_table_ptr
&& entry_len
!= 4) {
5165 NV_WARN(dev
, "Invalid DCB GPIO table entry length.\n");
5169 parse_entry
= parse_dcb40_gpio_entry
;
5171 } else if (bios
->bdcb
.version
>= 0x30) {
5172 if (gpio_table_ptr
&& entry_len
!= 2) {
5173 NV_WARN(dev
, "Invalid DCB GPIO table entry length.\n");
5177 parse_entry
= parse_dcb30_gpio_entry
;
5179 } else if (bios
->bdcb
.version
>= 0x22) {
5181 * DCBs older than v3.0 don't really have a GPIO
5182 * table, instead they keep some GPIO info at fixed
5185 uint16_t dcbptr
= ROM16(bios
->data
[0x36]);
5186 uint8_t *tvdac_gpio
= &bios
->data
[dcbptr
- 5];
5188 if (tvdac_gpio
[0] & 1) {
5189 struct dcb_gpio_entry
*gpio
= new_gpio_entry(bios
);
5191 gpio
->tag
= DCB_GPIO_TVDAC0
;
5192 gpio
->line
= tvdac_gpio
[1] >> 4;
5193 gpio
->invert
= tvdac_gpio
[0] & 2;
5197 if (!gpio_table_ptr
)
5200 if (entries
> DCB_MAX_NUM_GPIO_ENTRIES
) {
5201 NV_WARN(dev
, "Too many entries in the DCB GPIO table.\n");
5202 entries
= DCB_MAX_NUM_GPIO_ENTRIES
;
5205 for (i
= 0; i
< entries
; i
++)
5206 parse_entry(bios
, gpio_table_ptr
+ header_len
+ entry_len
* i
);
5209 struct dcb_connector_table_entry
*
5210 nouveau_bios_connector_entry(struct drm_device
*dev
, int index
)
5212 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5213 struct nvbios
*bios
= &dev_priv
->VBIOS
;
5214 struct dcb_connector_table_entry
*cte
;
5216 if (index
>= bios
->bdcb
.connector
.entries
)
5219 cte
= &bios
->bdcb
.connector
.entry
[index
];
5220 if (cte
->type
== 0xff)
5227 parse_dcb_connector_table(struct nvbios
*bios
)
5229 struct drm_device
*dev
= bios
->dev
;
5230 struct dcb_connector_table
*ct
= &bios
->bdcb
.connector
;
5231 struct dcb_connector_table_entry
*cte
;
5232 uint8_t *conntab
= &bios
->data
[bios
->bdcb
.connector_table_ptr
];
5236 if (!bios
->bdcb
.connector_table_ptr
) {
5237 NV_DEBUG(dev
, "No DCB connector table present\n");
5241 NV_INFO(dev
, "DCB connector table: VHER 0x%02x %d %d %d\n",
5242 conntab
[0], conntab
[1], conntab
[2], conntab
[3]);
5243 if ((conntab
[0] != 0x30 && conntab
[0] != 0x40) ||
5244 (conntab
[3] != 2 && conntab
[3] != 4)) {
5245 NV_ERROR(dev
, " Unknown! Please report.\n");
5249 ct
->entries
= conntab
[2];
5251 entry
= conntab
+ conntab
[1];
5252 cte
= &ct
->entry
[0];
5253 for (i
= 0; i
< conntab
[2]; i
++, entry
+= conntab
[3], cte
++) {
5254 if (conntab
[3] == 2)
5255 cte
->entry
= ROM16(entry
[0]);
5257 cte
->entry
= ROM32(entry
[0]);
5258 cte
->type
= (cte
->entry
& 0x000000ff) >> 0;
5259 cte
->index
= (cte
->entry
& 0x00000f00) >> 8;
5260 switch (cte
->entry
& 0x00033000) {
5262 cte
->gpio_tag
= 0x07;
5265 cte
->gpio_tag
= 0x08;
5268 cte
->gpio_tag
= 0x51;
5271 cte
->gpio_tag
= 0x52;
5274 cte
->gpio_tag
= 0xff;
5278 if (cte
->type
== 0xff)
5281 NV_INFO(dev
, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5282 i
, cte
->entry
, cte
->type
, cte
->index
, cte
->gpio_tag
);
5286 static struct dcb_entry
*new_dcb_entry(struct parsed_dcb
*dcb
)
5288 struct dcb_entry
*entry
= &dcb
->entry
[dcb
->entries
];
5290 memset(entry
, 0, sizeof(struct dcb_entry
));
5291 entry
->index
= dcb
->entries
++;
5296 static void fabricate_vga_output(struct parsed_dcb
*dcb
, int i2c
, int heads
)
5298 struct dcb_entry
*entry
= new_dcb_entry(dcb
);
5301 entry
->i2c_index
= i2c
;
5302 entry
->heads
= heads
;
5303 entry
->location
= DCB_LOC_ON_CHIP
;
5304 /* "or" mostly unused in early gen crt modesetting, 0 is fine */
5307 static void fabricate_dvi_i_output(struct parsed_dcb
*dcb
, bool twoHeads
)
5309 struct dcb_entry
*entry
= new_dcb_entry(dcb
);
5312 entry
->i2c_index
= LEGACY_I2C_PANEL
;
5313 entry
->heads
= twoHeads
? 3 : 1;
5314 entry
->location
= !DCB_LOC_ON_CHIP
; /* ie OFF CHIP */
5315 entry
->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */
5316 entry
->duallink_possible
= false; /* SiI164 and co. are single link */
5320 * For dvi-a either crtc probably works, but my card appears to only
5321 * support dvi-d. "nvidia" still attempts to program it for dvi-a,
5322 * doing the full fp output setup (program 0x6808.. fp dimension regs,
5323 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880);
5324 * the monitor picks up the mode res ok and lights up, but no pixel
5325 * data appears, so the board manufacturer probably connected up the
5326 * sync lines, but missed the video traces / components
5328 * with this introduction, dvi-a left as an exercise for the reader.
5330 fabricate_vga_output(dcb
, LEGACY_I2C_PANEL
, entry
->heads
);
5334 static void fabricate_tv_output(struct parsed_dcb
*dcb
, bool twoHeads
)
5336 struct dcb_entry
*entry
= new_dcb_entry(dcb
);
5339 entry
->i2c_index
= LEGACY_I2C_TV
;
5340 entry
->heads
= twoHeads
? 3 : 1;
5341 entry
->location
= !DCB_LOC_ON_CHIP
; /* ie OFF CHIP */
5345 parse_dcb20_entry(struct drm_device
*dev
, struct bios_parsed_dcb
*bdcb
,
5346 uint32_t conn
, uint32_t conf
, struct dcb_entry
*entry
)
5348 entry
->type
= conn
& 0xf;
5349 entry
->i2c_index
= (conn
>> 4) & 0xf;
5350 entry
->heads
= (conn
>> 8) & 0xf;
5351 if (bdcb
->version
>= 0x40)
5352 entry
->connector
= (conn
>> 12) & 0xf;
5353 entry
->bus
= (conn
>> 16) & 0xf;
5354 entry
->location
= (conn
>> 20) & 0x3;
5355 entry
->or = (conn
>> 24) & 0xf;
5357 * Normal entries consist of a single bit, but dual link has the
5358 * next most significant bit set too
5360 entry
->duallink_possible
=
5361 ((1 << (ffs(entry
->or) - 1)) * 3 == entry
->or);
5363 switch (entry
->type
) {
5366 * Although the rest of a CRT conf dword is usually
5367 * zeros, mac biosen have stuff there so we must mask
5369 entry
->crtconf
.maxfreq
= (bdcb
->version
< 0x30) ?
5370 (conf
& 0xffff) * 10 :
5371 (conf
& 0xff) * 10000;
5377 entry
->lvdsconf
.use_straps_for_mode
= true;
5378 if (bdcb
->version
< 0x22) {
5381 * The laptop in bug 14567 lies and claims to not use
5382 * straps when it does, so assume all DCB 2.0 laptops
5383 * use straps, until a broken EDID using one is produced
5385 entry
->lvdsconf
.use_straps_for_mode
= true;
5387 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5388 * mean the same thing (probably wrong, but might work)
5390 if (conf
& 0x4 || conf
& 0x8)
5391 entry
->lvdsconf
.use_power_scripts
= true;
5395 entry
->lvdsconf
.use_power_scripts
= true;
5399 * Until we even try to use these on G8x, it's
5400 * useless reporting unknown bits. They all are.
5402 if (bdcb
->version
>= 0x40)
5405 NV_ERROR(dev
, "Unknown LVDS configuration bits, "
5412 if (bdcb
->version
>= 0x30)
5413 entry
->tvconf
.has_component_output
= conf
& (0x8 << 4);
5415 entry
->tvconf
.has_component_output
= false;
5420 entry
->dpconf
.sor
.link
= (conf
& 0x00000030) >> 4;
5421 entry
->dpconf
.link_bw
= (conf
& 0x00e00000) >> 21;
5422 switch ((conf
& 0x0f000000) >> 24) {
5424 entry
->dpconf
.link_nr
= 4;
5427 entry
->dpconf
.link_nr
= 2;
5430 entry
->dpconf
.link_nr
= 1;
5435 entry
->tmdsconf
.sor
.link
= (conf
& 0x00000030) >> 4;
5438 /* weird g80 mobile type that "nv" treats as a terminator */
5439 bdcb
->dcb
.entries
--;
5443 /* unsure what DCB version introduces this, 3.0? */
5444 if (conf
& 0x100000)
5445 entry
->i2c_upper_default
= true;
5451 parse_dcb15_entry(struct drm_device
*dev
, struct parsed_dcb
*dcb
,
5452 uint32_t conn
, uint32_t conf
, struct dcb_entry
*entry
)
5454 if (conn
!= 0xf0003f00 && conn
!= 0xf2247f10 && conn
!= 0xf2204001 &&
5455 conn
!= 0xf2204301 && conn
!= 0xf2204311 && conn
!= 0xf2208001 &&
5456 conn
!= 0xf2244001 && conn
!= 0xf2244301 && conn
!= 0xf2244311 &&
5457 conn
!= 0xf4204011 && conn
!= 0xf4208011 && conn
!= 0xf4248011 &&
5458 conn
!= 0xf2045ff2 && conn
!= 0xf2045f14 && conn
!= 0xf207df14 &&
5459 conn
!= 0xf2205004 && conn
!= 0xf2209004) {
5460 NV_ERROR(dev
, "Unknown DCB 1.5 entry, please report\n");
5462 /* cause output setting to fail for !TV, so message is seen */
5463 if ((conn
& 0xf) != 0x1)
5468 /* most of the below is a "best guess" atm */
5469 entry
->type
= conn
& 0xf;
5470 if (entry
->type
== 2)
5471 /* another way of specifying straps based lvds... */
5472 entry
->type
= OUTPUT_LVDS
;
5473 if (entry
->type
== 4) { /* digital */
5475 entry
->type
= OUTPUT_LVDS
;
5477 entry
->type
= OUTPUT_TMDS
;
5479 /* what's in bits 5-13? could be some encoder maker thing, in tv case */
5480 entry
->i2c_index
= (conn
>> 14) & 0xf;
5481 /* raw heads field is in range 0-1, so move to 1-2 */
5482 entry
->heads
= ((conn
>> 18) & 0x7) + 1;
5483 entry
->location
= (conn
>> 21) & 0xf;
5484 /* unused: entry->bus = (conn >> 25) & 0x7; */
5485 /* set or to be same as heads -- hopefully safe enough */
5486 entry
->or = entry
->heads
;
5487 entry
->duallink_possible
= false;
5489 switch (entry
->type
) {
5491 entry
->crtconf
.maxfreq
= (conf
& 0xffff) * 10;
5495 * This is probably buried in conn's unknown bits.
5496 * This will upset EDID-ful models, if they exist
5498 entry
->lvdsconf
.use_straps_for_mode
= true;
5499 entry
->lvdsconf
.use_power_scripts
= true;
5503 * Invent a DVI-A output, by copying the fields of the DVI-D
5504 * output; reported to work by math_b on an NV20(!).
5506 fabricate_vga_output(dcb
, entry
->i2c_index
, entry
->heads
);
5509 entry
->tvconf
.has_component_output
= false;
5516 static bool parse_dcb_entry(struct drm_device
*dev
, struct bios_parsed_dcb
*bdcb
,
5517 uint32_t conn
, uint32_t conf
)
5519 struct dcb_entry
*entry
= new_dcb_entry(&bdcb
->dcb
);
5522 if (bdcb
->version
>= 0x20)
5523 ret
= parse_dcb20_entry(dev
, bdcb
, conn
, conf
, entry
);
5525 ret
= parse_dcb15_entry(dev
, &bdcb
->dcb
, conn
, conf
, entry
);
5529 read_dcb_i2c_entry(dev
, bdcb
->version
, bdcb
->i2c_table
,
5530 entry
->i2c_index
, &bdcb
->dcb
.i2c
[entry
->i2c_index
]);
5536 void merge_like_dcb_entries(struct drm_device
*dev
, struct parsed_dcb
*dcb
)
5539 * DCB v2.0 lists each output combination separately.
5540 * Here we merge compatible entries to have fewer outputs, with
5544 int i
, newentries
= 0;
5546 for (i
= 0; i
< dcb
->entries
; i
++) {
5547 struct dcb_entry
*ient
= &dcb
->entry
[i
];
5550 for (j
= i
+ 1; j
< dcb
->entries
; j
++) {
5551 struct dcb_entry
*jent
= &dcb
->entry
[j
];
5553 if (jent
->type
== 100) /* already merged entry */
5556 /* merge heads field when all other fields the same */
5557 if (jent
->i2c_index
== ient
->i2c_index
&&
5558 jent
->type
== ient
->type
&&
5559 jent
->location
== ient
->location
&&
5560 jent
->or == ient
->or) {
5561 NV_TRACE(dev
, "Merging DCB entries %d and %d\n",
5563 ient
->heads
|= jent
->heads
;
5564 jent
->type
= 100; /* dummy value */
5569 /* Compact entries merged into others out of dcb */
5570 for (i
= 0; i
< dcb
->entries
; i
++) {
5571 if (dcb
->entry
[i
].type
== 100)
5574 if (newentries
!= i
) {
5575 dcb
->entry
[newentries
] = dcb
->entry
[i
];
5576 dcb
->entry
[newentries
].index
= newentries
;
5581 dcb
->entries
= newentries
;
5584 static int parse_dcb_table(struct drm_device
*dev
, struct nvbios
*bios
, bool twoHeads
)
5586 struct bios_parsed_dcb
*bdcb
= &bios
->bdcb
;
5587 struct parsed_dcb
*dcb
;
5588 uint16_t dcbptr
, i2ctabptr
= 0;
5590 uint8_t headerlen
= 0x4, entries
= DCB_MAX_NUM_ENTRIES
;
5591 bool configblock
= true;
5592 int recordlength
= 8, confofs
= 4;
5595 dcb
= bios
->pub
.dcb
= &bdcb
->dcb
;
5598 /* get the offset from 0x36 */
5599 dcbptr
= ROM16(bios
->data
[0x36]);
5601 if (dcbptr
== 0x0) {
5602 NV_WARN(dev
, "No output data (DCB) found in BIOS, "
5603 "assuming a CRT output exists\n");
5604 /* this situation likely means a really old card, pre DCB */
5605 fabricate_vga_output(dcb
, LEGACY_I2C_CRT
, 1);
5607 if (nv04_tv_identify(dev
,
5608 bios
->legacy
.i2c_indices
.tv
) >= 0)
5609 fabricate_tv_output(dcb
, twoHeads
);
5614 dcbtable
= &bios
->data
[dcbptr
];
5616 /* get DCB version */
5617 bdcb
->version
= dcbtable
[0];
5618 NV_TRACE(dev
, "Found Display Configuration Block version %d.%d\n",
5619 bdcb
->version
>> 4, bdcb
->version
& 0xf);
5621 if (bdcb
->version
>= 0x20) { /* NV17+ */
5624 if (bdcb
->version
>= 0x30) { /* NV40+ */
5625 headerlen
= dcbtable
[1];
5626 entries
= dcbtable
[2];
5627 recordlength
= dcbtable
[3];
5628 i2ctabptr
= ROM16(dcbtable
[4]);
5629 sig
= ROM32(dcbtable
[6]);
5630 bdcb
->gpio_table_ptr
= ROM16(dcbtable
[10]);
5631 bdcb
->connector_table_ptr
= ROM16(dcbtable
[20]);
5633 i2ctabptr
= ROM16(dcbtable
[2]);
5634 sig
= ROM32(dcbtable
[4]);
5638 if (sig
!= 0x4edcbdcb) {
5639 NV_ERROR(dev
, "Bad Display Configuration Block "
5640 "signature (%08X)\n", sig
);
5643 } else if (bdcb
->version
>= 0x15) { /* some NV11 and NV20 */
5644 char sig
[8] = { 0 };
5646 strncpy(sig
, (char *)&dcbtable
[-7], 7);
5647 i2ctabptr
= ROM16(dcbtable
[2]);
5651 if (strcmp(sig
, "DEV_REC")) {
5652 NV_ERROR(dev
, "Bad Display Configuration Block "
5653 "signature (%s)\n", sig
);
5658 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
5659 * has the same single (crt) entry, even when tv-out present, so
5660 * the conclusion is this version cannot really be used.
5661 * v1.2 tables (some NV6/10, and NV15+) normally have the same
5662 * 5 entries, which are not specific to the card and so no use.
5663 * v1.2 does have an I2C table that read_dcb_i2c_table can
5664 * handle, but cards exist (nv11 in #14821) with a bad i2c table
5665 * pointer, so use the indices parsed in parse_bmp_structure.
5666 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5668 NV_TRACEWARN(dev
, "No useful information in BIOS output table; "
5669 "adding all possible outputs\n");
5670 fabricate_vga_output(dcb
, LEGACY_I2C_CRT
, 1);
5673 * Attempt to detect TV before DVI because the test
5674 * for the former is more accurate and it rules the
5677 if (nv04_tv_identify(dev
,
5678 bios
->legacy
.i2c_indices
.tv
) >= 0)
5679 fabricate_tv_output(dcb
, twoHeads
);
5681 else if (bios
->tmds
.output0_script_ptr
||
5682 bios
->tmds
.output1_script_ptr
)
5683 fabricate_dvi_i_output(dcb
, twoHeads
);
5689 NV_WARN(dev
, "No pointer to DCB I2C port table\n");
5691 bdcb
->i2c_table
= &bios
->data
[i2ctabptr
];
5692 if (bdcb
->version
>= 0x30)
5693 bdcb
->i2c_default_indices
= bdcb
->i2c_table
[4];
5696 parse_dcb_gpio_table(bios
);
5697 parse_dcb_connector_table(bios
);
5699 if (entries
> DCB_MAX_NUM_ENTRIES
)
5700 entries
= DCB_MAX_NUM_ENTRIES
;
5702 for (i
= 0; i
< entries
; i
++) {
5703 uint32_t connection
, config
= 0;
5705 connection
= ROM32(dcbtable
[headerlen
+ recordlength
* i
]);
5707 config
= ROM32(dcbtable
[headerlen
+ confofs
+ recordlength
* i
]);
5709 /* seen on an NV11 with DCB v1.5 */
5710 if (connection
== 0x00000000)
5713 /* seen on an NV17 with DCB v2.0 */
5714 if (connection
== 0xffffffff)
5717 if ((connection
& 0x0000000f) == 0x0000000f)
5720 NV_TRACEWARN(dev
, "Raw DCB entry %d: %08x %08x\n",
5721 dcb
->entries
, connection
, config
);
5723 if (!parse_dcb_entry(dev
, bdcb
, connection
, config
))
5728 * apart for v2.1+ not being known for requiring merging, this
5729 * guarantees dcbent->index is the index of the entry in the rom image
5731 if (bdcb
->version
< 0x21)
5732 merge_like_dcb_entries(dev
, dcb
);
5734 return dcb
->entries
? 0 : -ENXIO
;
5738 fixup_legacy_connector(struct nvbios
*bios
)
5740 struct bios_parsed_dcb
*bdcb
= &bios
->bdcb
;
5741 struct parsed_dcb
*dcb
= &bdcb
->dcb
;
5745 * DCB 3.0 also has the table in most cases, but there are some cards
5746 * where the table is filled with stub entries, and the DCB entriy
5747 * indices are all 0. We don't need the connector indices on pre-G80
5748 * chips (yet?) so limit the use to DCB 4.0 and above.
5750 if (bdcb
->version
>= 0x40)
5754 * No known connector info before v3.0, so make it up. the rule here
5755 * is: anything on the same i2c bus is considered to be on the same
5756 * connector. any output without an associated i2c bus is assigned
5757 * its own unique connector index.
5759 for (i
= 0; i
< dcb
->entries
; i
++) {
5760 if (dcb
->entry
[i
].i2c_index
== 0xf)
5764 * Ignore the I2C index for on-chip TV-out, as there
5765 * are cards with bogus values (nv31m in bug 23212),
5766 * and it's otherwise useless.
5768 if (dcb
->entry
[i
].type
== OUTPUT_TV
&&
5769 dcb
->entry
[i
].location
== DCB_LOC_ON_CHIP
) {
5770 dcb
->entry
[i
].i2c_index
= 0xf;
5774 dcb
->entry
[i
].connector
= dcb
->entry
[i
].i2c_index
;
5775 if (dcb
->entry
[i
].connector
> high
)
5776 high
= dcb
->entry
[i
].connector
;
5779 for (i
= 0; i
< dcb
->entries
; i
++) {
5780 if (dcb
->entry
[i
].i2c_index
!= 0xf)
5783 dcb
->entry
[i
].connector
= ++high
;
5788 fixup_legacy_i2c(struct nvbios
*bios
)
5790 struct parsed_dcb
*dcb
= &bios
->bdcb
.dcb
;
5793 for (i
= 0; i
< dcb
->entries
; i
++) {
5794 if (dcb
->entry
[i
].i2c_index
== LEGACY_I2C_CRT
)
5795 dcb
->entry
[i
].i2c_index
= bios
->legacy
.i2c_indices
.crt
;
5796 if (dcb
->entry
[i
].i2c_index
== LEGACY_I2C_PANEL
)
5797 dcb
->entry
[i
].i2c_index
= bios
->legacy
.i2c_indices
.panel
;
5798 if (dcb
->entry
[i
].i2c_index
== LEGACY_I2C_TV
)
5799 dcb
->entry
[i
].i2c_index
= bios
->legacy
.i2c_indices
.tv
;
5803 static int load_nv17_hwsq_ucode_entry(struct drm_device
*dev
, struct nvbios
*bios
, uint16_t hwsq_offset
, int entry
)
5806 * The header following the "HWSQ" signature has the number of entries,
5807 * and the entry size
5809 * An entry consists of a dword to write to the sequencer control reg
5810 * (0x00001304), followed by the ucode bytes, written sequentially,
5811 * starting at reg 0x00001400
5814 uint8_t bytes_to_write
;
5815 uint16_t hwsq_entry_offset
;
5818 if (bios
->data
[hwsq_offset
] <= entry
) {
5819 NV_ERROR(dev
, "Too few entries in HW sequencer table for "
5820 "requested entry\n");
5824 bytes_to_write
= bios
->data
[hwsq_offset
+ 1];
5826 if (bytes_to_write
!= 36) {
5827 NV_ERROR(dev
, "Unknown HW sequencer entry size\n");
5831 NV_TRACE(dev
, "Loading NV17 power sequencing microcode\n");
5833 hwsq_entry_offset
= hwsq_offset
+ 2 + entry
* bytes_to_write
;
5835 /* set sequencer control */
5836 bios_wr32(bios
, 0x00001304, ROM32(bios
->data
[hwsq_entry_offset
]));
5837 bytes_to_write
-= 4;
5840 for (i
= 0; i
< bytes_to_write
; i
+= 4)
5841 bios_wr32(bios
, 0x00001400 + i
, ROM32(bios
->data
[hwsq_entry_offset
+ i
+ 4]));
5843 /* twiddle NV_PBUS_DEBUG_4 */
5844 bios_wr32(bios
, NV_PBUS_DEBUG_4
, bios_rd32(bios
, NV_PBUS_DEBUG_4
) | 0x18);
5849 static int load_nv17_hw_sequencer_ucode(struct drm_device
*dev
,
5850 struct nvbios
*bios
)
5853 * BMP based cards, from NV17, need a microcode loading to correctly
5854 * control the GPIO etc for LVDS panels
5856 * BIT based cards seem to do this directly in the init scripts
5858 * The microcode entries are found by the "HWSQ" signature.
5861 const uint8_t hwsq_signature
[] = { 'H', 'W', 'S', 'Q' };
5862 const int sz
= sizeof(hwsq_signature
);
5865 hwsq_offset
= findstr(bios
->data
, bios
->length
, hwsq_signature
, sz
);
5869 /* always use entry 0? */
5870 return load_nv17_hwsq_ucode_entry(dev
, bios
, hwsq_offset
+ sz
, 0);
5873 uint8_t *nouveau_bios_embedded_edid(struct drm_device
*dev
)
5875 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5876 struct nvbios
*bios
= &dev_priv
->VBIOS
;
5877 const uint8_t edid_sig
[] = {
5878 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
5879 uint16_t offset
= 0;
5881 int searchlen
= NV_PROM_SIZE
;
5884 return bios
->fp
.edid
;
5887 newoffset
= findstr(&bios
->data
[offset
], searchlen
,
5891 offset
+= newoffset
;
5892 if (!nv_cksum(&bios
->data
[offset
], EDID1_LEN
))
5895 searchlen
-= offset
;
5899 NV_TRACE(dev
, "Found EDID in BIOS\n");
5901 return bios
->fp
.edid
= &bios
->data
[offset
];
5905 nouveau_bios_run_init_table(struct drm_device
*dev
, uint16_t table
,
5906 struct dcb_entry
*dcbent
)
5908 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5909 struct nvbios
*bios
= &dev_priv
->VBIOS
;
5910 struct init_exec iexec
= { true, false };
5912 bios
->display
.output
= dcbent
;
5913 parse_init_table(bios
, table
, &iexec
);
5914 bios
->display
.output
= NULL
;
5917 static bool NVInitVBIOS(struct drm_device
*dev
)
5919 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5920 struct nvbios
*bios
= &dev_priv
->VBIOS
;
5922 memset(bios
, 0, sizeof(struct nvbios
));
5925 if (!NVShadowVBIOS(dev
, bios
->data
))
5928 bios
->length
= NV_PROM_SIZE
;
5932 static int nouveau_parse_vbios_struct(struct drm_device
*dev
)
5934 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5935 struct nvbios
*bios
= &dev_priv
->VBIOS
;
5936 const uint8_t bit_signature
[] = { 0xff, 0xb8, 'B', 'I', 'T' };
5937 const uint8_t bmp_signature
[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
5940 offset
= findstr(bios
->data
, bios
->length
,
5941 bit_signature
, sizeof(bit_signature
));
5943 NV_TRACE(dev
, "BIT BIOS found\n");
5944 return parse_bit_structure(bios
, offset
+ 6);
5947 offset
= findstr(bios
->data
, bios
->length
,
5948 bmp_signature
, sizeof(bmp_signature
));
5950 NV_TRACE(dev
, "BMP BIOS found\n");
5951 return parse_bmp_structure(dev
, bios
, offset
);
5954 NV_ERROR(dev
, "No known BIOS signature found\n");
5959 nouveau_run_vbios_init(struct drm_device
*dev
)
5961 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5962 struct nvbios
*bios
= &dev_priv
->VBIOS
;
5965 NVLockVgaCrtcs(dev
, false);
5966 if (nv_two_heads(dev
))
5967 NVSetOwner(dev
, bios
->state
.crtchead
);
5969 if (bios
->major_version
< 5) /* BMP only */
5970 load_nv17_hw_sequencer_ucode(dev
, bios
);
5972 if (bios
->execute
) {
5973 bios
->fp
.last_script_invoc
= 0;
5974 bios
->fp
.lvds_init_run
= false;
5977 parse_init_tables(bios
);
5980 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
5981 * parser will run this right after the init tables, the binary
5982 * driver appears to run it at some point later.
5984 if (bios
->some_script_ptr
) {
5985 struct init_exec iexec
= {true, false};
5987 NV_INFO(dev
, "Parsing VBIOS init table at offset 0x%04X\n",
5988 bios
->some_script_ptr
);
5989 parse_init_table(bios
, bios
->some_script_ptr
, &iexec
);
5992 if (dev_priv
->card_type
>= NV_50
) {
5993 for (i
= 0; i
< bios
->bdcb
.dcb
.entries
; i
++) {
5994 nouveau_bios_run_display_table(dev
,
5995 &bios
->bdcb
.dcb
.entry
[i
],
6000 NVLockVgaCrtcs(dev
, true);
6006 nouveau_bios_i2c_devices_takedown(struct drm_device
*dev
)
6008 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6009 struct nvbios
*bios
= &dev_priv
->VBIOS
;
6010 struct dcb_i2c_entry
*entry
;
6013 entry
= &bios
->bdcb
.dcb
.i2c
[0];
6014 for (i
= 0; i
< DCB_MAX_NUM_I2C_ENTRIES
; i
++, entry
++)
6015 nouveau_i2c_fini(dev
, entry
);
6019 nouveau_bios_init(struct drm_device
*dev
)
6021 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6022 struct nvbios
*bios
= &dev_priv
->VBIOS
;
6023 uint32_t saved_nv_pextdev_boot_0
;
6027 dev_priv
->vbios
= &bios
->pub
;
6029 if (!NVInitVBIOS(dev
))
6032 ret
= nouveau_parse_vbios_struct(dev
);
6036 ret
= parse_dcb_table(dev
, bios
, nv_two_heads(dev
));
6040 fixup_legacy_i2c(bios
);
6041 fixup_legacy_connector(bios
);
6043 if (!bios
->major_version
) /* we don't run version 0 bios */
6046 /* these will need remembering across a suspend */
6047 saved_nv_pextdev_boot_0
= bios_rd32(bios
, NV_PEXTDEV_BOOT_0
);
6048 bios
->state
.saved_nv_pfb_cfg0
= bios_rd32(bios
, NV_PFB_CFG0
);
6050 /* init script execution disabled */
6051 bios
->execute
= false;
6053 /* ... unless card isn't POSTed already */
6054 if (dev_priv
->card_type
>= NV_10
&&
6055 NVReadVgaCrtc(dev
, 0, 0x00) == 0 &&
6056 NVReadVgaCrtc(dev
, 0, 0x1a) == 0) {
6057 NV_INFO(dev
, "Adaptor not initialised\n");
6058 if (dev_priv
->card_type
< NV_50
) {
6059 NV_ERROR(dev
, "Unable to POST this chipset\n");
6063 NV_INFO(dev
, "Running VBIOS init tables\n");
6064 bios
->execute
= true;
6067 bios_wr32(bios
, NV_PEXTDEV_BOOT_0
, saved_nv_pextdev_boot_0
);
6069 ret
= nouveau_run_vbios_init(dev
);
6071 dev_priv
->vbios
= NULL
;
6075 /* feature_byte on BMP is poor, but init always sets CR4B */
6076 was_locked
= NVLockVgaCrtcs(dev
, false);
6077 if (bios
->major_version
< 5)
6078 bios
->is_mobile
= NVReadVgaCrtc(dev
, 0, NV_CIO_CRE_4B
) & 0x40;
6080 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6081 if (bios
->is_mobile
|| bios
->major_version
>= 5)
6082 ret
= parse_fp_mode_table(dev
, bios
);
6083 NVLockVgaCrtcs(dev
, was_locked
);
6085 /* allow subsequent scripts to execute */
6086 bios
->execute
= true;
6092 nouveau_bios_takedown(struct drm_device
*dev
)
6094 nouveau_bios_i2c_devices_takedown(dev
);