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drm: radeon: Use surface for PCI GART table.
[linux-2.6/linux-2.6-openrd.git] / drivers / usb / gadget / m66592-udc.c
blob43dcf9e1af6b06bc46379ccfe1bcfb05aa25f524
1 /*
2 * M66592 UDC (USB gadget)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/io.h>
27 #include <linux/platform_device.h>
28
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31
32 #include "m66592-udc.h"
33
34
35 MODULE_DESCRIPTION("M66592 USB gadget driver");
36 MODULE_LICENSE("GPL");
37 MODULE_AUTHOR("Yoshihiro Shimoda");
38 MODULE_ALIAS("platform:m66592_udc");
39
40 #define DRIVER_VERSION "18 Oct 2007"
41
42 /* module parameters */
43 #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
44 static unsigned short endian = M66592_LITTLE;
45 module_param(endian, ushort, 0644);
46 MODULE_PARM_DESC(endian, "data endian: big=0, little=0 (default=0)");
47 #else
48 static unsigned short clock = M66592_XTAL24;
49 module_param(clock, ushort, 0644);
50 MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0 "
51 "(default=16384)");
52
53 static unsigned short vif = M66592_LDRV;
54 module_param(vif, ushort, 0644);
55 MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0 (default=32768)");
56
57 static unsigned short endian;
58 module_param(endian, ushort, 0644);
59 MODULE_PARM_DESC(endian, "data endian: big=256, little=0 (default=0)");
60
61 static unsigned short irq_sense = M66592_INTL;
62 module_param(irq_sense, ushort, 0644);
63 MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=2, falling edge=0 "
64 "(default=2)");
65 #endif
66
67 static const char udc_name[] = "m66592_udc";
68 static const char *m66592_ep_name[] = {
69 "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
70 };
71
72 static void disable_controller(struct m66592 *m66592);
73 static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
74 static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
75 static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
76 gfp_t gfp_flags);
77
78 static void transfer_complete(struct m66592_ep *ep,
79 struct m66592_request *req, int status);
80
81 /*-------------------------------------------------------------------------*/
82 static inline u16 get_usb_speed(struct m66592 *m66592)
83 {
84 return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
85 }
86
87 static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
88 unsigned long reg)
89 {
90 u16 tmp;
91
92 tmp = m66592_read(m66592, M66592_INTENB0);
93 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
94 M66592_INTENB0);
95 m66592_bset(m66592, (1 << pipenum), reg);
96 m66592_write(m66592, tmp, M66592_INTENB0);
97 }
98
99 static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
100 unsigned long reg)
101 {
102 u16 tmp;
103
104 tmp = m66592_read(m66592, M66592_INTENB0);
105 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
106 M66592_INTENB0);
107 m66592_bclr(m66592, (1 << pipenum), reg);
108 m66592_write(m66592, tmp, M66592_INTENB0);
109 }
110
111 static void m66592_usb_connect(struct m66592 *m66592)
112 {
113 m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
114 m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
115 M66592_INTENB0);
116 m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
117
118 m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
119 }
120
121 static void m66592_usb_disconnect(struct m66592 *m66592)
122 __releases(m66592->lock)
123 __acquires(m66592->lock)
124 {
125 m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
126 m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
127 M66592_INTENB0);
128 m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
129 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
130
131 m66592->gadget.speed = USB_SPEED_UNKNOWN;
132 spin_unlock(&m66592->lock);
133 m66592->driver->disconnect(&m66592->gadget);
134 spin_lock(&m66592->lock);
135
136 disable_controller(m66592);
137 INIT_LIST_HEAD(&m66592->ep[0].queue);
138 }
139
140 static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
141 {
142 u16 pid = 0;
143 unsigned long offset;
144
145 if (pipenum == 0)
146 pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
147 else if (pipenum < M66592_MAX_NUM_PIPE) {
148 offset = get_pipectr_addr(pipenum);
149 pid = m66592_read(m66592, offset) & M66592_PID;
150 } else
151 pr_err("unexpect pipe num (%d)\n", pipenum);
152
153 return pid;
154 }
155
156 static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
157 u16 pid)
158 {
159 unsigned long offset;
160
161 if (pipenum == 0)
162 m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
163 else if (pipenum < M66592_MAX_NUM_PIPE) {
164 offset = get_pipectr_addr(pipenum);
165 m66592_mdfy(m66592, pid, M66592_PID, offset);
166 } else
167 pr_err("unexpect pipe num (%d)\n", pipenum);
168 }
169
170 static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
171 {
172 control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
173 }
174
175 static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
176 {
177 control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
178 }
179
180 static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
181 {
182 control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
183 }
184
185 static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
186 {
187 u16 ret = 0;
188 unsigned long offset;
189
190 if (pipenum == 0)
191 ret = m66592_read(m66592, M66592_DCPCTR);
192 else if (pipenum < M66592_MAX_NUM_PIPE) {
193 offset = get_pipectr_addr(pipenum);
194 ret = m66592_read(m66592, offset);
195 } else
196 pr_err("unexpect pipe num (%d)\n", pipenum);
197
198 return ret;
199 }
200
201 static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
202 {
203 unsigned long offset;
204
205 pipe_stop(m66592, pipenum);
206
207 if (pipenum == 0)
208 m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
209 else if (pipenum < M66592_MAX_NUM_PIPE) {
210 offset = get_pipectr_addr(pipenum);
211 m66592_bset(m66592, M66592_SQCLR, offset);
212 } else
213 pr_err("unexpect pipe num(%d)\n", pipenum);
214 }
215
216 static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
217 {
218 u16 tmp;
219 int size;
220
221 if (pipenum == 0) {
222 tmp = m66592_read(m66592, M66592_DCPCFG);
223 if ((tmp & M66592_CNTMD) != 0)
224 size = 256;
225 else {
226 tmp = m66592_read(m66592, M66592_DCPMAXP);
227 size = tmp & M66592_MAXP;
228 }
229 } else {
230 m66592_write(m66592, pipenum, M66592_PIPESEL);
231 tmp = m66592_read(m66592, M66592_PIPECFG);
232 if ((tmp & M66592_CNTMD) != 0) {
233 tmp = m66592_read(m66592, M66592_PIPEBUF);
234 size = ((tmp >> 10) + 1) * 64;
235 } else {
236 tmp = m66592_read(m66592, M66592_PIPEMAXP);
237 size = tmp & M66592_MXPS;
238 }
239 }
240
241 return size;
242 }
243
244 static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
245 {
246 struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
247
248 if (ep->use_dma)
249 return;
250
251 m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
252
253 ndelay(450);
254
255 m66592_bset(m66592, M66592_MBW, ep->fifosel);
256 }
257
258 static int pipe_buffer_setting(struct m66592 *m66592,
259 struct m66592_pipe_info *info)
260 {
261 u16 bufnum = 0, buf_bsize = 0;
262 u16 pipecfg = 0;
263
264 if (info->pipe == 0)
265 return -EINVAL;
266
267 m66592_write(m66592, info->pipe, M66592_PIPESEL);
268
269 if (info->dir_in)
270 pipecfg |= M66592_DIR;
271 pipecfg |= info->type;
272 pipecfg |= info->epnum;
273 switch (info->type) {
274 case M66592_INT:
275 bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
276 buf_bsize = 0;
277 break;
278 case M66592_BULK:
279 bufnum = m66592->bi_bufnum +
280 (info->pipe - M66592_BASE_PIPENUM_BULK) * 16;
281 m66592->bi_bufnum += 16;
282 buf_bsize = 7;
283 pipecfg |= M66592_DBLB;
284 if (!info->dir_in)
285 pipecfg |= M66592_SHTNAK;
286 break;
287 case M66592_ISO:
288 bufnum = m66592->bi_bufnum +
289 (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
290 m66592->bi_bufnum += 16;
291 buf_bsize = 7;
292 break;
293 }
294 if (m66592->bi_bufnum > M66592_MAX_BUFNUM) {
295 pr_err("m66592 pipe memory is insufficient(%d)\n",
296 m66592->bi_bufnum);
297 return -ENOMEM;
298 }
299
300 m66592_write(m66592, pipecfg, M66592_PIPECFG);
301 m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
302 m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
303 if (info->interval)
304 info->interval--;
305 m66592_write(m66592, info->interval, M66592_PIPEPERI);
306
307 return 0;
308 }
309
310 static void pipe_buffer_release(struct m66592 *m66592,
311 struct m66592_pipe_info *info)
312 {
313 if (info->pipe == 0)
314 return;
315
316 switch (info->type) {
317 case M66592_BULK:
318 if (is_bulk_pipe(info->pipe))
319 m66592->bi_bufnum -= 16;
320 break;
321 case M66592_ISO:
322 if (is_isoc_pipe(info->pipe))
323 m66592->bi_bufnum -= 16;
324 break;
325 }
326
327 if (is_bulk_pipe(info->pipe)) {
328 m66592->bulk--;
329 } else if (is_interrupt_pipe(info->pipe))
330 m66592->interrupt--;
331 else if (is_isoc_pipe(info->pipe)) {
332 m66592->isochronous--;
333 if (info->type == M66592_BULK)
334 m66592->bulk--;
335 } else
336 pr_err("ep_release: unexpect pipenum (%d)\n",
337 info->pipe);
338 }
339
340 static void pipe_initialize(struct m66592_ep *ep)
341 {
342 struct m66592 *m66592 = ep->m66592;
343
344 m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
345
346 m66592_write(m66592, M66592_ACLRM, ep->pipectr);
347 m66592_write(m66592, 0, ep->pipectr);
348 m66592_write(m66592, M66592_SQCLR, ep->pipectr);
349 if (ep->use_dma) {
350 m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
351
352 ndelay(450);
353
354 m66592_bset(m66592, M66592_MBW, ep->fifosel);
355 }
356 }
357
358 static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
359 const struct usb_endpoint_descriptor *desc,
360 u16 pipenum, int dma)
361 {
362 if ((pipenum != 0) && dma) {
363 if (m66592->num_dma == 0) {
364 m66592->num_dma++;
365 ep->use_dma = 1;
366 ep->fifoaddr = M66592_D0FIFO;
367 ep->fifosel = M66592_D0FIFOSEL;
368 ep->fifoctr = M66592_D0FIFOCTR;
369 ep->fifotrn = M66592_D0FIFOTRN;
370 #if !defined(CONFIG_SUPERH_BUILT_IN_M66592)
371 } else if (m66592->num_dma == 1) {
372 m66592->num_dma++;
373 ep->use_dma = 1;
374 ep->fifoaddr = M66592_D1FIFO;
375 ep->fifosel = M66592_D1FIFOSEL;
376 ep->fifoctr = M66592_D1FIFOCTR;
377 ep->fifotrn = M66592_D1FIFOTRN;
378 #endif
379 } else {
380 ep->use_dma = 0;
381 ep->fifoaddr = M66592_CFIFO;
382 ep->fifosel = M66592_CFIFOSEL;
383 ep->fifoctr = M66592_CFIFOCTR;
384 ep->fifotrn = 0;
385 }
386 } else {
387 ep->use_dma = 0;
388 ep->fifoaddr = M66592_CFIFO;
389 ep->fifosel = M66592_CFIFOSEL;
390 ep->fifoctr = M66592_CFIFOCTR;
391 ep->fifotrn = 0;
392 }
393
394 ep->pipectr = get_pipectr_addr(pipenum);
395 ep->pipenum = pipenum;
396 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
397 m66592->pipenum2ep[pipenum] = ep;
398 m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
399 INIT_LIST_HEAD(&ep->queue);
400 }
401
402 static void m66592_ep_release(struct m66592_ep *ep)
403 {
404 struct m66592 *m66592 = ep->m66592;
405 u16 pipenum = ep->pipenum;
406
407 if (pipenum == 0)
408 return;
409
410 if (ep->use_dma)
411 m66592->num_dma--;
412 ep->pipenum = 0;
413 ep->busy = 0;
414 ep->use_dma = 0;
415 }
416
417 static int alloc_pipe_config(struct m66592_ep *ep,
418 const struct usb_endpoint_descriptor *desc)
419 {
420 struct m66592 *m66592 = ep->m66592;
421 struct m66592_pipe_info info;
422 int dma = 0;
423 int *counter;
424 int ret;
425
426 ep->desc = desc;
427
428 BUG_ON(ep->pipenum);
429
430 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
431 case USB_ENDPOINT_XFER_BULK:
432 if (m66592->bulk >= M66592_MAX_NUM_BULK) {
433 if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
434 pr_err("bulk pipe is insufficient\n");
435 return -ENODEV;
436 } else {
437 info.pipe = M66592_BASE_PIPENUM_ISOC
438 + m66592->isochronous;
439 counter = &m66592->isochronous;
440 }
441 } else {
442 info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
443 counter = &m66592->bulk;
444 }
445 info.type = M66592_BULK;
446 dma = 1;
447 break;
448 case USB_ENDPOINT_XFER_INT:
449 if (m66592->interrupt >= M66592_MAX_NUM_INT) {
450 pr_err("interrupt pipe is insufficient\n");
451 return -ENODEV;
452 }
453 info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
454 info.type = M66592_INT;
455 counter = &m66592->interrupt;
456 break;
457 case USB_ENDPOINT_XFER_ISOC:
458 if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
459 pr_err("isochronous pipe is insufficient\n");
460 return -ENODEV;
461 }
462 info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
463 info.type = M66592_ISO;
464 counter = &m66592->isochronous;
465 break;
466 default:
467 pr_err("unexpect xfer type\n");
468 return -EINVAL;
469 }
470 ep->type = info.type;
471
472 info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
473 info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
474 info.interval = desc->bInterval;
475 if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
476 info.dir_in = 1;
477 else
478 info.dir_in = 0;
479
480 ret = pipe_buffer_setting(m66592, &info);
481 if (ret < 0) {
482 pr_err("pipe_buffer_setting fail\n");
483 return ret;
484 }
485
486 (*counter)++;
487 if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
488 m66592->bulk++;
489
490 m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
491 pipe_initialize(ep);
492
493 return 0;
494 }
495
496 static int free_pipe_config(struct m66592_ep *ep)
497 {
498 struct m66592 *m66592 = ep->m66592;
499 struct m66592_pipe_info info;
500
501 info.pipe = ep->pipenum;
502 info.type = ep->type;
503 pipe_buffer_release(m66592, &info);
504 m66592_ep_release(ep);
505
506 return 0;
507 }
508
509 /*-------------------------------------------------------------------------*/
510 static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
511 {
512 enable_irq_ready(m66592, pipenum);
513 enable_irq_nrdy(m66592, pipenum);
514 }
515
516 static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
517 {
518 disable_irq_ready(m66592, pipenum);
519 disable_irq_nrdy(m66592, pipenum);
520 }
521
522 /* if complete is true, gadget driver complete function is not call */
523 static void control_end(struct m66592 *m66592, unsigned ccpl)
524 {
525 m66592->ep[0].internal_ccpl = ccpl;
526 pipe_start(m66592, 0);
527 m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
528 }
529
530 static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
531 {
532 struct m66592 *m66592 = ep->m66592;
533
534 pipe_change(m66592, ep->pipenum);
535 m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
536 (M66592_ISEL | M66592_CURPIPE),
537 M66592_CFIFOSEL);
538 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
539 if (req->req.length == 0) {
540 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
541 pipe_start(m66592, 0);
542 transfer_complete(ep, req, 0);
543 } else {
544 m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
545 irq_ep0_write(ep, req);
546 }
547 }
548
549 static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
550 {
551 struct m66592 *m66592 = ep->m66592;
552 u16 tmp;
553
554 pipe_change(m66592, ep->pipenum);
555 disable_irq_empty(m66592, ep->pipenum);
556 pipe_start(m66592, ep->pipenum);
557
558 tmp = m66592_read(m66592, ep->fifoctr);
559 if (unlikely((tmp & M66592_FRDY) == 0))
560 pipe_irq_enable(m66592, ep->pipenum);
561 else
562 irq_packet_write(ep, req);
563 }
564
565 static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
566 {
567 struct m66592 *m66592 = ep->m66592;
568 u16 pipenum = ep->pipenum;
569
570 if (ep->pipenum == 0) {
571 m66592_mdfy(m66592, M66592_PIPE0,
572 (M66592_ISEL | M66592_CURPIPE),
573 M66592_CFIFOSEL);
574 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
575 pipe_start(m66592, pipenum);
576 pipe_irq_enable(m66592, pipenum);
577 } else {
578 if (ep->use_dma) {
579 m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
580 pipe_change(m66592, pipenum);
581 m66592_bset(m66592, M66592_TRENB, ep->fifosel);
582 m66592_write(m66592,
583 (req->req.length + ep->ep.maxpacket - 1)
584 / ep->ep.maxpacket,
585 ep->fifotrn);
586 }
587 pipe_start(m66592, pipenum); /* trigger once */
588 pipe_irq_enable(m66592, pipenum);
589 }
590 }
591
592 static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
593 {
594 if (ep->desc->bEndpointAddress & USB_DIR_IN)
595 start_packet_write(ep, req);
596 else
597 start_packet_read(ep, req);
598 }
599
600 static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
601 {
602 u16 ctsq;
603
604 ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
605
606 switch (ctsq) {
607 case M66592_CS_RDDS:
608 start_ep0_write(ep, req);
609 break;
610 case M66592_CS_WRDS:
611 start_packet_read(ep, req);
612 break;
613
614 case M66592_CS_WRND:
615 control_end(ep->m66592, 0);
616 break;
617 default:
618 pr_err("start_ep0: unexpect ctsq(%x)\n", ctsq);
619 break;
620 }
621 }
622
623 #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
624 static void init_controller(struct m66592 *m66592)
625 {
626 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
627 m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
628 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
629 m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
630
631 /* This is a workaound for SH7722 2nd cut */
632 m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
633 m66592_bset(m66592, 0x1000, M66592_TESTMODE);
634 m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
635
636 m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
637
638 m66592_write(m66592, 0, M66592_CFBCFG);
639 m66592_write(m66592, 0, M66592_D0FBCFG);
640 m66592_bset(m66592, endian, M66592_CFBCFG);
641 m66592_bset(m66592, endian, M66592_D0FBCFG);
642 }
643 #else /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
644 static void init_controller(struct m66592 *m66592)
645 {
646 m66592_bset(m66592, (vif & M66592_LDRV) | (endian & M66592_BIGEND),
647 M66592_PINCFG);
648 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
649 m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL, M66592_SYSCFG);
650
651 m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
652 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
653 m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
654
655 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
656
657 msleep(3);
658
659 m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
660
661 msleep(1);
662
663 m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
664
665 m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
666 m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
667 M66592_DMA0CFG);
668 }
669 #endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
670
671 static void disable_controller(struct m66592 *m66592)
672 {
673 #if !defined(CONFIG_SUPERH_BUILT_IN_M66592)
674 m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
675 udelay(1);
676 m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
677 udelay(1);
678 m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
679 udelay(1);
680 m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
681 #endif
682 }
683
684 static void m66592_start_xclock(struct m66592 *m66592)
685 {
686 #if !defined(CONFIG_SUPERH_BUILT_IN_M66592)
687 u16 tmp;
688
689 tmp = m66592_read(m66592, M66592_SYSCFG);
690 if (!(tmp & M66592_XCKE))
691 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
692 #endif
693 }
694
695 /*-------------------------------------------------------------------------*/
696 static void transfer_complete(struct m66592_ep *ep,
697 struct m66592_request *req, int status)
698 __releases(m66592->lock)
699 __acquires(m66592->lock)
700 {
701 int restart = 0;
702
703 if (unlikely(ep->pipenum == 0)) {
704 if (ep->internal_ccpl) {
705 ep->internal_ccpl = 0;
706 return;
707 }
708 }
709
710 list_del_init(&req->queue);
711 if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
712 req->req.status = -ESHUTDOWN;
713 else
714 req->req.status = status;
715
716 if (!list_empty(&ep->queue))
717 restart = 1;
718
719 spin_unlock(&ep->m66592->lock);
720 req->req.complete(&ep->ep, &req->req);
721 spin_lock(&ep->m66592->lock);
722
723 if (restart) {
724 req = list_entry(ep->queue.next, struct m66592_request, queue);
725 if (ep->desc)
726 start_packet(ep, req);
727 }
728 }
729
730 static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
731 {
732 int i;
733 u16 tmp;
734 unsigned bufsize;
735 size_t size;
736 void *buf;
737 u16 pipenum = ep->pipenum;
738 struct m66592 *m66592 = ep->m66592;
739
740 pipe_change(m66592, pipenum);
741 m66592_bset(m66592, M66592_ISEL, ep->fifosel);
742
743 i = 0;
744 do {
745 tmp = m66592_read(m66592, ep->fifoctr);
746 if (i++ > 100000) {
747 pr_err("pipe0 is busy. maybe cpu i/o bus "
748 "conflict. please power off this controller.");
749 return;
750 }
751 ndelay(1);
752 } while ((tmp & M66592_FRDY) == 0);
753
754 /* prepare parameters */
755 bufsize = get_buffer_size(m66592, pipenum);
756 buf = req->req.buf + req->req.actual;
757 size = min(bufsize, req->req.length - req->req.actual);
758
759 /* write fifo */
760 if (req->req.buf) {
761 if (size > 0)
762 m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
763 if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
764 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
765 }
766
767 /* update parameters */
768 req->req.actual += size;
769
770 /* check transfer finish */
771 if ((!req->req.zero && (req->req.actual == req->req.length))
772 || (size % ep->ep.maxpacket)
773 || (size == 0)) {
774 disable_irq_ready(m66592, pipenum);
775 disable_irq_empty(m66592, pipenum);
776 } else {
777 disable_irq_ready(m66592, pipenum);
778 enable_irq_empty(m66592, pipenum);
779 }
780 pipe_start(m66592, pipenum);
781 }
782
783 static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
784 {
785 u16 tmp;
786 unsigned bufsize;
787 size_t size;
788 void *buf;
789 u16 pipenum = ep->pipenum;
790 struct m66592 *m66592 = ep->m66592;
791
792 pipe_change(m66592, pipenum);
793 tmp = m66592_read(m66592, ep->fifoctr);
794 if (unlikely((tmp & M66592_FRDY) == 0)) {
795 pipe_stop(m66592, pipenum);
796 pipe_irq_disable(m66592, pipenum);
797 pr_err("write fifo not ready. pipnum=%d\n", pipenum);
798 return;
799 }
800
801 /* prepare parameters */
802 bufsize = get_buffer_size(m66592, pipenum);
803 buf = req->req.buf + req->req.actual;
804 size = min(bufsize, req->req.length - req->req.actual);
805
806 /* write fifo */
807 if (req->req.buf) {
808 m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
809 if ((size == 0)
810 || ((size % ep->ep.maxpacket) != 0)
811 || ((bufsize != ep->ep.maxpacket)
812 && (bufsize > size)))
813 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
814 }
815
816 /* update parameters */
817 req->req.actual += size;
818 /* check transfer finish */
819 if ((!req->req.zero && (req->req.actual == req->req.length))
820 || (size % ep->ep.maxpacket)
821 || (size == 0)) {
822 disable_irq_ready(m66592, pipenum);
823 enable_irq_empty(m66592, pipenum);
824 } else {
825 disable_irq_empty(m66592, pipenum);
826 pipe_irq_enable(m66592, pipenum);
827 }
828 }
829
830 static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
831 {
832 u16 tmp;
833 int rcv_len, bufsize, req_len;
834 int size;
835 void *buf;
836 u16 pipenum = ep->pipenum;
837 struct m66592 *m66592 = ep->m66592;
838 int finish = 0;
839
840 pipe_change(m66592, pipenum);
841 tmp = m66592_read(m66592, ep->fifoctr);
842 if (unlikely((tmp & M66592_FRDY) == 0)) {
843 req->req.status = -EPIPE;
844 pipe_stop(m66592, pipenum);
845 pipe_irq_disable(m66592, pipenum);
846 pr_err("read fifo not ready");
847 return;
848 }
849
850 /* prepare parameters */
851 rcv_len = tmp & M66592_DTLN;
852 bufsize = get_buffer_size(m66592, pipenum);
853
854 buf = req->req.buf + req->req.actual;
855 req_len = req->req.length - req->req.actual;
856 if (rcv_len < bufsize)
857 size = min(rcv_len, req_len);
858 else
859 size = min(bufsize, req_len);
860
861 /* update parameters */
862 req->req.actual += size;
863
864 /* check transfer finish */
865 if ((!req->req.zero && (req->req.actual == req->req.length))
866 || (size % ep->ep.maxpacket)
867 || (size == 0)) {
868 pipe_stop(m66592, pipenum);
869 pipe_irq_disable(m66592, pipenum);
870 finish = 1;
871 }
872
873 /* read fifo */
874 if (req->req.buf) {
875 if (size == 0)
876 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
877 else
878 m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
879 }
880
881 if ((ep->pipenum != 0) && finish)
882 transfer_complete(ep, req, 0);
883 }
884
885 static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
886 {
887 u16 check;
888 u16 pipenum;
889 struct m66592_ep *ep;
890 struct m66592_request *req;
891
892 if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
893 m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
894 m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
895 M66592_CFIFOSEL);
896
897 ep = &m66592->ep[0];
898 req = list_entry(ep->queue.next, struct m66592_request, queue);
899 irq_packet_read(ep, req);
900 } else {
901 for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
902 check = 1 << pipenum;
903 if ((status & check) && (enb & check)) {
904 m66592_write(m66592, ~check, M66592_BRDYSTS);
905 ep = m66592->pipenum2ep[pipenum];
906 req = list_entry(ep->queue.next,
907 struct m66592_request, queue);
908 if (ep->desc->bEndpointAddress & USB_DIR_IN)
909 irq_packet_write(ep, req);
910 else
911 irq_packet_read(ep, req);
912 }
913 }
914 }
915 }
916
917 static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
918 {
919 u16 tmp;
920 u16 check;
921 u16 pipenum;
922 struct m66592_ep *ep;
923 struct m66592_request *req;
924
925 if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
926 m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
927
928 ep = &m66592->ep[0];
929 req = list_entry(ep->queue.next, struct m66592_request, queue);
930 irq_ep0_write(ep, req);
931 } else {
932 for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
933 check = 1 << pipenum;
934 if ((status & check) && (enb & check)) {
935 m66592_write(m66592, ~check, M66592_BEMPSTS);
936 tmp = control_reg_get(m66592, pipenum);
937 if ((tmp & M66592_INBUFM) == 0) {
938 disable_irq_empty(m66592, pipenum);
939 pipe_irq_disable(m66592, pipenum);
940 pipe_stop(m66592, pipenum);
941 ep = m66592->pipenum2ep[pipenum];
942 req = list_entry(ep->queue.next,
943 struct m66592_request,
944 queue);
945 if (!list_empty(&ep->queue))
946 transfer_complete(ep, req, 0);
947 }
948 }
949 }
950 }
951 }
952
953 static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
954 __releases(m66592->lock)
955 __acquires(m66592->lock)
956 {
957 struct m66592_ep *ep;
958 u16 pid;
959 u16 status = 0;
960 u16 w_index = le16_to_cpu(ctrl->wIndex);
961
962 switch (ctrl->bRequestType & USB_RECIP_MASK) {
963 case USB_RECIP_DEVICE:
964 status = 1 << USB_DEVICE_SELF_POWERED;
965 break;
966 case USB_RECIP_INTERFACE:
967 status = 0;
968 break;
969 case USB_RECIP_ENDPOINT:
970 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
971 pid = control_reg_get_pid(m66592, ep->pipenum);
972 if (pid == M66592_PID_STALL)
973 status = 1 << USB_ENDPOINT_HALT;
974 else
975 status = 0;
976 break;
977 default:
978 pipe_stall(m66592, 0);
979 return; /* exit */
980 }
981
982 m66592->ep0_data = cpu_to_le16(status);
983 m66592->ep0_req->buf = &m66592->ep0_data;
984 m66592->ep0_req->length = 2;
985 /* AV: what happens if we get called again before that gets through? */
986 spin_unlock(&m66592->lock);
987 m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
988 spin_lock(&m66592->lock);
989 }
990
991 static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
992 {
993 switch (ctrl->bRequestType & USB_RECIP_MASK) {
994 case USB_RECIP_DEVICE:
995 control_end(m66592, 1);
996 break;
997 case USB_RECIP_INTERFACE:
998 control_end(m66592, 1);
999 break;
1000 case USB_RECIP_ENDPOINT: {
1001 struct m66592_ep *ep;
1002 struct m66592_request *req;
1003 u16 w_index = le16_to_cpu(ctrl->wIndex);
1004
1005 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
1006 pipe_stop(m66592, ep->pipenum);
1007 control_reg_sqclr(m66592, ep->pipenum);
1008
1009 control_end(m66592, 1);
1010
1011 req = list_entry(ep->queue.next,
1012 struct m66592_request, queue);
1013 if (ep->busy) {
1014 ep->busy = 0;
1015 if (list_empty(&ep->queue))
1016 break;
1017 start_packet(ep, req);
1018 } else if (!list_empty(&ep->queue))
1019 pipe_start(m66592, ep->pipenum);
1020 }
1021 break;
1022 default:
1023 pipe_stall(m66592, 0);
1024 break;
1025 }
1026 }
1027
1028 static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1029 {
1030
1031 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1032 case USB_RECIP_DEVICE:
1033 control_end(m66592, 1);
1034 break;
1035 case USB_RECIP_INTERFACE:
1036 control_end(m66592, 1);
1037 break;
1038 case USB_RECIP_ENDPOINT: {
1039 struct m66592_ep *ep;
1040 u16 w_index = le16_to_cpu(ctrl->wIndex);
1041
1042 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
1043 pipe_stall(m66592, ep->pipenum);
1044
1045 control_end(m66592, 1);
1046 }
1047 break;
1048 default:
1049 pipe_stall(m66592, 0);
1050 break;
1051 }
1052 }
1053
1054 /* if return value is true, call class driver's setup() */
1055 static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1056 {
1057 u16 *p = (u16 *)ctrl;
1058 unsigned long offset = M66592_USBREQ;
1059 int i, ret = 0;
1060
1061 /* read fifo */
1062 m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
1063
1064 for (i = 0; i < 4; i++)
1065 p[i] = m66592_read(m66592, offset + i*2);
1066
1067 /* check request */
1068 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1069 switch (ctrl->bRequest) {
1070 case USB_REQ_GET_STATUS:
1071 get_status(m66592, ctrl);
1072 break;
1073 case USB_REQ_CLEAR_FEATURE:
1074 clear_feature(m66592, ctrl);
1075 break;
1076 case USB_REQ_SET_FEATURE:
1077 set_feature(m66592, ctrl);
1078 break;
1079 default:
1080 ret = 1;
1081 break;
1082 }
1083 } else
1084 ret = 1;
1085 return ret;
1086 }
1087
1088 static void m66592_update_usb_speed(struct m66592 *m66592)
1089 {
1090 u16 speed = get_usb_speed(m66592);
1091
1092 switch (speed) {
1093 case M66592_HSMODE:
1094 m66592->gadget.speed = USB_SPEED_HIGH;
1095 break;
1096 case M66592_FSMODE:
1097 m66592->gadget.speed = USB_SPEED_FULL;
1098 break;
1099 default:
1100 m66592->gadget.speed = USB_SPEED_UNKNOWN;
1101 pr_err("USB speed unknown\n");
1102 }
1103 }
1104
1105 static void irq_device_state(struct m66592 *m66592)
1106 {
1107 u16 dvsq;
1108
1109 dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
1110 m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
1111
1112 if (dvsq == M66592_DS_DFLT) { /* bus reset */
1113 m66592->driver->disconnect(&m66592->gadget);
1114 m66592_update_usb_speed(m66592);
1115 }
1116 if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
1117 m66592_update_usb_speed(m66592);
1118 if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
1119 && m66592->gadget.speed == USB_SPEED_UNKNOWN)
1120 m66592_update_usb_speed(m66592);
1121
1122 m66592->old_dvsq = dvsq;
1123 }
1124
1125 static void irq_control_stage(struct m66592 *m66592)
1126 __releases(m66592->lock)
1127 __acquires(m66592->lock)
1128 {
1129 struct usb_ctrlrequest ctrl;
1130 u16 ctsq;
1131
1132 ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
1133 m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
1134
1135 switch (ctsq) {
1136 case M66592_CS_IDST: {
1137 struct m66592_ep *ep;
1138 struct m66592_request *req;
1139 ep = &m66592->ep[0];
1140 req = list_entry(ep->queue.next, struct m66592_request, queue);
1141 transfer_complete(ep, req, 0);
1142 }
1143 break;
1144
1145 case M66592_CS_RDDS:
1146 case M66592_CS_WRDS:
1147 case M66592_CS_WRND:
1148 if (setup_packet(m66592, &ctrl)) {
1149 spin_unlock(&m66592->lock);
1150 if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
1151 pipe_stall(m66592, 0);
1152 spin_lock(&m66592->lock);
1153 }
1154 break;
1155 case M66592_CS_RDSS:
1156 case M66592_CS_WRSS:
1157 control_end(m66592, 0);
1158 break;
1159 default:
1160 pr_err("ctrl_stage: unexpect ctsq(%x)\n", ctsq);
1161 break;
1162 }
1163 }
1164
1165 static irqreturn_t m66592_irq(int irq, void *_m66592)
1166 {
1167 struct m66592 *m66592 = _m66592;
1168 u16 intsts0;
1169 u16 intenb0;
1170 u16 brdysts, nrdysts, bempsts;
1171 u16 brdyenb, nrdyenb, bempenb;
1172 u16 savepipe;
1173 u16 mask0;
1174
1175 spin_lock(&m66592->lock);
1176
1177 intsts0 = m66592_read(m66592, M66592_INTSTS0);
1178 intenb0 = m66592_read(m66592, M66592_INTENB0);
1179
1180 #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
1181 if (!intsts0 && !intenb0) {
1182 /*
1183 * When USB clock stops, it cannot read register. Even if a
1184 * clock stops, the interrupt occurs. So this driver turn on
1185 * a clock by this timing and do re-reading of register.
1186 */
1187 m66592_start_xclock(m66592);
1188 intsts0 = m66592_read(m66592, M66592_INTSTS0);
1189 intenb0 = m66592_read(m66592, M66592_INTENB0);
1190 }
1191 #endif
1192
1193 savepipe = m66592_read(m66592, M66592_CFIFOSEL);
1194
1195 mask0 = intsts0 & intenb0;
1196 if (mask0) {
1197 brdysts = m66592_read(m66592, M66592_BRDYSTS);
1198 nrdysts = m66592_read(m66592, M66592_NRDYSTS);
1199 bempsts = m66592_read(m66592, M66592_BEMPSTS);
1200 brdyenb = m66592_read(m66592, M66592_BRDYENB);
1201 nrdyenb = m66592_read(m66592, M66592_NRDYENB);
1202 bempenb = m66592_read(m66592, M66592_BEMPENB);
1203
1204 if (mask0 & M66592_VBINT) {
1205 m66592_write(m66592, 0xffff & ~M66592_VBINT,
1206 M66592_INTSTS0);
1207 m66592_start_xclock(m66592);
1208
1209 /* start vbus sampling */
1210 m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
1211 & M66592_VBSTS;
1212 m66592->scount = M66592_MAX_SAMPLING;
1213
1214 mod_timer(&m66592->timer,
1215 jiffies + msecs_to_jiffies(50));
1216 }
1217 if (intsts0 & M66592_DVSQ)
1218 irq_device_state(m66592);
1219
1220 if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
1221 && (brdysts & brdyenb)) {
1222 irq_pipe_ready(m66592, brdysts, brdyenb);
1223 }
1224 if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
1225 && (bempsts & bempenb)) {
1226 irq_pipe_empty(m66592, bempsts, bempenb);
1227 }
1228
1229 if (intsts0 & M66592_CTRT)
1230 irq_control_stage(m66592);
1231 }
1232
1233 m66592_write(m66592, savepipe, M66592_CFIFOSEL);
1234
1235 spin_unlock(&m66592->lock);
1236 return IRQ_HANDLED;
1237 }
1238
1239 static void m66592_timer(unsigned long _m66592)
1240 {
1241 struct m66592 *m66592 = (struct m66592 *)_m66592;
1242 unsigned long flags;
1243 u16 tmp;
1244
1245 spin_lock_irqsave(&m66592->lock, flags);
1246 tmp = m66592_read(m66592, M66592_SYSCFG);
1247 if (!(tmp & M66592_RCKE)) {
1248 m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
1249 udelay(10);
1250 m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
1251 }
1252 if (m66592->scount > 0) {
1253 tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
1254 if (tmp == m66592->old_vbus) {
1255 m66592->scount--;
1256 if (m66592->scount == 0) {
1257 if (tmp == M66592_VBSTS)
1258 m66592_usb_connect(m66592);
1259 else
1260 m66592_usb_disconnect(m66592);
1261 } else {
1262 mod_timer(&m66592->timer,
1263 jiffies + msecs_to_jiffies(50));
1264 }
1265 } else {
1266 m66592->scount = M66592_MAX_SAMPLING;
1267 m66592->old_vbus = tmp;
1268 mod_timer(&m66592->timer,
1269 jiffies + msecs_to_jiffies(50));
1270 }
1271 }
1272 spin_unlock_irqrestore(&m66592->lock, flags);
1273 }
1274
1275 /*-------------------------------------------------------------------------*/
1276 static int m66592_enable(struct usb_ep *_ep,
1277 const struct usb_endpoint_descriptor *desc)
1278 {
1279 struct m66592_ep *ep;
1280
1281 ep = container_of(_ep, struct m66592_ep, ep);
1282 return alloc_pipe_config(ep, desc);
1283 }
1284
1285 static int m66592_disable(struct usb_ep *_ep)
1286 {
1287 struct m66592_ep *ep;
1288 struct m66592_request *req;
1289 unsigned long flags;
1290
1291 ep = container_of(_ep, struct m66592_ep, ep);
1292 BUG_ON(!ep);
1293
1294 while (!list_empty(&ep->queue)) {
1295 req = list_entry(ep->queue.next, struct m66592_request, queue);
1296 spin_lock_irqsave(&ep->m66592->lock, flags);
1297 transfer_complete(ep, req, -ECONNRESET);
1298 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1299 }
1300
1301 pipe_irq_disable(ep->m66592, ep->pipenum);
1302 return free_pipe_config(ep);
1303 }
1304
1305 static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
1306 gfp_t gfp_flags)
1307 {
1308 struct m66592_request *req;
1309
1310 req = kzalloc(sizeof(struct m66592_request), gfp_flags);
1311 if (!req)
1312 return NULL;
1313
1314 INIT_LIST_HEAD(&req->queue);
1315
1316 return &req->req;
1317 }
1318
1319 static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
1320 {
1321 struct m66592_request *req;
1322
1323 req = container_of(_req, struct m66592_request, req);
1324 kfree(req);
1325 }
1326
1327 static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
1328 gfp_t gfp_flags)
1329 {
1330 struct m66592_ep *ep;
1331 struct m66592_request *req;
1332 unsigned long flags;
1333 int request = 0;
1334
1335 ep = container_of(_ep, struct m66592_ep, ep);
1336 req = container_of(_req, struct m66592_request, req);
1337
1338 if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
1339 return -ESHUTDOWN;
1340
1341 spin_lock_irqsave(&ep->m66592->lock, flags);
1342
1343 if (list_empty(&ep->queue))
1344 request = 1;
1345
1346 list_add_tail(&req->queue, &ep->queue);
1347 req->req.actual = 0;
1348 req->req.status = -EINPROGRESS;
1349
1350 if (ep->desc == NULL) /* control */
1351 start_ep0(ep, req);
1352 else {
1353 if (request && !ep->busy)
1354 start_packet(ep, req);
1355 }
1356
1357 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1358
1359 return 0;
1360 }
1361
1362 static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1363 {
1364 struct m66592_ep *ep;
1365 struct m66592_request *req;
1366 unsigned long flags;
1367
1368 ep = container_of(_ep, struct m66592_ep, ep);
1369 req = container_of(_req, struct m66592_request, req);
1370
1371 spin_lock_irqsave(&ep->m66592->lock, flags);
1372 if (!list_empty(&ep->queue))
1373 transfer_complete(ep, req, -ECONNRESET);
1374 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1375
1376 return 0;
1377 }
1378
1379 static int m66592_set_halt(struct usb_ep *_ep, int value)
1380 {
1381 struct m66592_ep *ep;
1382 struct m66592_request *req;
1383 unsigned long flags;
1384 int ret = 0;
1385
1386 ep = container_of(_ep, struct m66592_ep, ep);
1387 req = list_entry(ep->queue.next, struct m66592_request, queue);
1388
1389 spin_lock_irqsave(&ep->m66592->lock, flags);
1390 if (!list_empty(&ep->queue)) {
1391 ret = -EAGAIN;
1392 goto out;
1393 }
1394 if (value) {
1395 ep->busy = 1;
1396 pipe_stall(ep->m66592, ep->pipenum);
1397 } else {
1398 ep->busy = 0;
1399 pipe_stop(ep->m66592, ep->pipenum);
1400 }
1401
1402 out:
1403 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1404 return ret;
1405 }
1406
1407 static void m66592_fifo_flush(struct usb_ep *_ep)
1408 {
1409 struct m66592_ep *ep;
1410 unsigned long flags;
1411
1412 ep = container_of(_ep, struct m66592_ep, ep);
1413 spin_lock_irqsave(&ep->m66592->lock, flags);
1414 if (list_empty(&ep->queue) && !ep->busy) {
1415 pipe_stop(ep->m66592, ep->pipenum);
1416 m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
1417 }
1418 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1419 }
1420
1421 static struct usb_ep_ops m66592_ep_ops = {
1422 .enable = m66592_enable,
1423 .disable = m66592_disable,
1424
1425 .alloc_request = m66592_alloc_request,
1426 .free_request = m66592_free_request,
1427
1428 .queue = m66592_queue,
1429 .dequeue = m66592_dequeue,
1430
1431 .set_halt = m66592_set_halt,
1432 .fifo_flush = m66592_fifo_flush,
1433 };
1434
1435 /*-------------------------------------------------------------------------*/
1436 static struct m66592 *the_controller;
1437
1438 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1439 {
1440 struct m66592 *m66592 = the_controller;
1441 int retval;
1442
1443 if (!driver
1444 || driver->speed != USB_SPEED_HIGH
1445 || !driver->bind
1446 || !driver->setup)
1447 return -EINVAL;
1448 if (!m66592)
1449 return -ENODEV;
1450 if (m66592->driver)
1451 return -EBUSY;
1452
1453 /* hook up the driver */
1454 driver->driver.bus = NULL;
1455 m66592->driver = driver;
1456 m66592->gadget.dev.driver = &driver->driver;
1457
1458 retval = device_add(&m66592->gadget.dev);
1459 if (retval) {
1460 pr_err("device_add error (%d)\n", retval);
1461 goto error;
1462 }
1463
1464 retval = driver->bind (&m66592->gadget);
1465 if (retval) {
1466 pr_err("bind to driver error (%d)\n", retval);
1467 device_del(&m66592->gadget.dev);
1468 goto error;
1469 }
1470
1471 m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1472 if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
1473 m66592_start_xclock(m66592);
1474 /* start vbus sampling */
1475 m66592->old_vbus = m66592_read(m66592,
1476 M66592_INTSTS0) & M66592_VBSTS;
1477 m66592->scount = M66592_MAX_SAMPLING;
1478 mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
1479 }
1480
1481 return 0;
1482
1483 error:
1484 m66592->driver = NULL;
1485 m66592->gadget.dev.driver = NULL;
1486
1487 return retval;
1488 }
1489 EXPORT_SYMBOL(usb_gadget_register_driver);
1490
1491 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1492 {
1493 struct m66592 *m66592 = the_controller;
1494 unsigned long flags;
1495
1496 if (driver != m66592->driver || !driver->unbind)
1497 return -EINVAL;
1498
1499 spin_lock_irqsave(&m66592->lock, flags);
1500 if (m66592->gadget.speed != USB_SPEED_UNKNOWN)
1501 m66592_usb_disconnect(m66592);
1502 spin_unlock_irqrestore(&m66592->lock, flags);
1503
1504 m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1505
1506 driver->unbind(&m66592->gadget);
1507 m66592->gadget.dev.driver = NULL;
1508
1509 init_controller(m66592);
1510 disable_controller(m66592);
1511
1512 device_del(&m66592->gadget.dev);
1513 m66592->driver = NULL;
1514 return 0;
1515 }
1516 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1517
1518 /*-------------------------------------------------------------------------*/
1519 static int m66592_get_frame(struct usb_gadget *_gadget)
1520 {
1521 struct m66592 *m66592 = gadget_to_m66592(_gadget);
1522 return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
1523 }
1524
1525 static struct usb_gadget_ops m66592_gadget_ops = {
1526 .get_frame = m66592_get_frame,
1527 };
1528
1529 static int __exit m66592_remove(struct platform_device *pdev)
1530 {
1531 struct m66592 *m66592 = dev_get_drvdata(&pdev->dev);
1532
1533 del_timer_sync(&m66592->timer);
1534 iounmap(m66592->reg);
1535 free_irq(platform_get_irq(pdev, 0), m66592);
1536 m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1537 #if defined(CONFIG_SUPERH_BUILT_IN_M66592) && defined(CONFIG_HAVE_CLK)
1538 clk_disable(m66592->clk);
1539 clk_put(m66592->clk);
1540 #endif
1541 kfree(m66592);
1542 return 0;
1543 }
1544
1545 static void nop_completion(struct usb_ep *ep, struct usb_request *r)
1546 {
1547 }
1548
1549 static int __init m66592_probe(struct platform_device *pdev)
1550 {
1551 struct resource *res;
1552 int irq;
1553 void __iomem *reg = NULL;
1554 struct m66592 *m66592 = NULL;
1555 #if defined(CONFIG_SUPERH_BUILT_IN_M66592) && defined(CONFIG_HAVE_CLK)
1556 char clk_name[8];
1557 #endif
1558 int ret = 0;
1559 int i;
1560
1561 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1562 if (!res) {
1563 ret = -ENODEV;
1564 pr_err("platform_get_resource error.\n");
1565 goto clean_up;
1566 }
1567
1568 irq = platform_get_irq(pdev, 0);
1569 if (irq < 0) {
1570 ret = -ENODEV;
1571 pr_err("platform_get_irq error.\n");
1572 goto clean_up;
1573 }
1574
1575 reg = ioremap(res->start, resource_size(res));
1576 if (reg == NULL) {
1577 ret = -ENOMEM;
1578 pr_err("ioremap error.\n");
1579 goto clean_up;
1580 }
1581
1582 /* initialize ucd */
1583 m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
1584 if (m66592 == NULL) {
1585 pr_err("kzalloc error\n");
1586 goto clean_up;
1587 }
1588
1589 spin_lock_init(&m66592->lock);
1590 dev_set_drvdata(&pdev->dev, m66592);
1591
1592 m66592->gadget.ops = &m66592_gadget_ops;
1593 device_initialize(&m66592->gadget.dev);
1594 dev_set_name(&m66592->gadget.dev, "gadget");
1595 m66592->gadget.is_dualspeed = 1;
1596 m66592->gadget.dev.parent = &pdev->dev;
1597 m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
1598 m66592->gadget.dev.release = pdev->dev.release;
1599 m66592->gadget.name = udc_name;
1600
1601 init_timer(&m66592->timer);
1602 m66592->timer.function = m66592_timer;
1603 m66592->timer.data = (unsigned long)m66592;
1604 m66592->reg = reg;
1605
1606 m66592->bi_bufnum = M66592_BASE_BUFNUM;
1607
1608 ret = request_irq(irq, m66592_irq, IRQF_DISABLED | IRQF_SHARED,
1609 udc_name, m66592);
1610 if (ret < 0) {
1611 pr_err("request_irq error (%d)\n", ret);
1612 goto clean_up;
1613 }
1614
1615 #if defined(CONFIG_SUPERH_BUILT_IN_M66592) && defined(CONFIG_HAVE_CLK)
1616 snprintf(clk_name, sizeof(clk_name), "usbf%d", pdev->id);
1617 m66592->clk = clk_get(&pdev->dev, clk_name);
1618 if (IS_ERR(m66592->clk)) {
1619 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
1620 ret = PTR_ERR(m66592->clk);
1621 goto clean_up2;
1622 }
1623 clk_enable(m66592->clk);
1624 #endif
1625 INIT_LIST_HEAD(&m66592->gadget.ep_list);
1626 m66592->gadget.ep0 = &m66592->ep[0].ep;
1627 INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
1628 for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
1629 struct m66592_ep *ep = &m66592->ep[i];
1630
1631 if (i != 0) {
1632 INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
1633 list_add_tail(&m66592->ep[i].ep.ep_list,
1634 &m66592->gadget.ep_list);
1635 }
1636 ep->m66592 = m66592;
1637 INIT_LIST_HEAD(&ep->queue);
1638 ep->ep.name = m66592_ep_name[i];
1639 ep->ep.ops = &m66592_ep_ops;
1640 ep->ep.maxpacket = 512;
1641 }
1642 m66592->ep[0].ep.maxpacket = 64;
1643 m66592->ep[0].pipenum = 0;
1644 m66592->ep[0].fifoaddr = M66592_CFIFO;
1645 m66592->ep[0].fifosel = M66592_CFIFOSEL;
1646 m66592->ep[0].fifoctr = M66592_CFIFOCTR;
1647 m66592->ep[0].fifotrn = 0;
1648 m66592->ep[0].pipectr = get_pipectr_addr(0);
1649 m66592->pipenum2ep[0] = &m66592->ep[0];
1650 m66592->epaddr2ep[0] = &m66592->ep[0];
1651
1652 the_controller = m66592;
1653
1654 m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
1655 if (m66592->ep0_req == NULL)
1656 goto clean_up3;
1657 m66592->ep0_req->complete = nop_completion;
1658
1659 init_controller(m66592);
1660
1661 dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
1662 return 0;
1663
1664 clean_up3:
1665 #if defined(CONFIG_SUPERH_BUILT_IN_M66592) && defined(CONFIG_HAVE_CLK)
1666 clk_disable(m66592->clk);
1667 clk_put(m66592->clk);
1668 clean_up2:
1669 #endif
1670 free_irq(irq, m66592);
1671 clean_up:
1672 if (m66592) {
1673 if (m66592->ep0_req)
1674 m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1675 kfree(m66592);
1676 }
1677 if (reg)
1678 iounmap(reg);
1679
1680 return ret;
1681 }
1682
1683 /*-------------------------------------------------------------------------*/
1684 static struct platform_driver m66592_driver = {
1685 .remove = __exit_p(m66592_remove),
1686 .driver = {
1687 .name = (char *) udc_name,
1688 .owner = THIS_MODULE,
1689 },
1690 };
1691
1692 static int __init m66592_udc_init(void)
1693 {
1694 return platform_driver_probe(&m66592_driver, m66592_probe);
1695 }
1696 module_init(m66592_udc_init);
1697
1698 static void __exit m66592_udc_cleanup(void)
1699 {
1700 platform_driver_unregister(&m66592_driver);
1701 }
1702 module_exit(m66592_udc_cleanup);
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