include/asm-ppc/commproc.h

   1 /*
   2  * MPC8xx Communication Processor Module.
   3  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
   4  *
   5  * This file contains structures and information for the communication
   6  * processor channels.  Some CPM control and status is available
   7  * throught the MPC8xx internal memory map.  See immap.h for details.
   8  * This file only contains what I need for the moment, not the total
   9  * CPM capabilities.  I (or someone else) will add definitions as they
  10  * are needed.  -- Dan
  11  *
  12  * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
  13  * bytes of the DP RAM and relocates the I2C parameter area to the
  14  * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
  15  * or other use.
  16  */
  17 #ifndef __CPM_8XX__
  18 #define __CPM_8XX__
  19
  20 #include <asm/8xx_immap.h>
  21 #include <asm/ptrace.h>
  22
  23 /* CPM Command register.
  24 */
  25 #define CPM_CR_RST      ((ushort)0x8000)
  26 #define CPM_CR_OPCODE   ((ushort)0x0f00)
  27 #define CPM_CR_CHAN     ((ushort)0x00f0)
  28 #define CPM_CR_FLG      ((ushort)0x0001)
  29
  30 /* Some commands (there are more...later)
  31 */
  32 #define CPM_CR_INIT_TRX         ((ushort)0x0000)
  33 #define CPM_CR_INIT_RX          ((ushort)0x0001)
  34 #define CPM_CR_INIT_TX          ((ushort)0x0002)
  35 #define CPM_CR_HUNT_MODE        ((ushort)0x0003)
  36 #define CPM_CR_STOP_TX          ((ushort)0x0004)
  37 #define CPM_CR_GRA_STOP_TX      ((ushort)0x0005)
  38 #define CPM_CR_RESTART_TX       ((ushort)0x0006)
  39 #define CPM_CR_CLOSE_RX_BD      ((ushort)0x0007)
  40 #define CPM_CR_SET_GADDR        ((ushort)0x0008)
  41 #define CPM_CR_SET_TIMER        CPM_CR_SET_GADDR
  42
  43 /* Channel numbers.
  44 */
  45 #define CPM_CR_CH_SCC1          ((ushort)0x0000)
  46 #define CPM_CR_CH_I2C           ((ushort)0x0001)        /* I2C and IDMA1 */
  47 #define CPM_CR_CH_SCC2          ((ushort)0x0004)
  48 #define CPM_CR_CH_SPI           ((ushort)0x0005)        /* SPI / IDMA2 / Timers */
  49 #define CPM_CR_CH_TIMER         CPM_CR_CH_SPI
  50 #define CPM_CR_CH_SCC3          ((ushort)0x0008)
  51 #define CPM_CR_CH_SMC1          ((ushort)0x0009)        /* SMC1 / DSP1 */
  52 #define CPM_CR_CH_SCC4          ((ushort)0x000c)
  53 #define CPM_CR_CH_SMC2          ((ushort)0x000d)        /* SMC2 / DSP2 */
  54
  55 #define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
  56
  57 /* The dual ported RAM is multi-functional.  Some areas can be (and are
  58  * being) used for microcode.  There is an area that can only be used
  59  * as data ram for buffer descriptors, which is all we use right now.
  60  * Currently the first 512 and last 256 bytes are used for microcode.
  61  */
  62 #define CPM_DATAONLY_BASE       ((uint)0x0800)
  63 #define CPM_DATAONLY_SIZE       ((uint)0x0700)
  64 #define CPM_DP_NOSPACE          ((uint)0x7fffffff)
  65
  66 static inline long IS_DPERR(const uint offset)
  67 {
  68         return (uint)offset > (uint)-1000L;
  69 }
  70
  71 /* Export the base address of the communication processor registers
  72  * and dual port ram.
  73  */
  74 extern  cpm8xx_t        *cpmp;          /* Pointer to comm processor */
  75 extern uint cpm_dpalloc(uint size, uint align);
  76 extern int cpm_dpfree(uint offset);
  77 extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align);
  78 extern void cpm_dpdump(void);
  79 extern void *cpm_dpram_addr(uint offset);
  80 extern uint cpm_dpram_phys(u8* addr);
  81 extern void cpm_setbrg(uint brg, uint rate);
  82
  83 extern uint m8xx_cpm_hostalloc(uint size);
  84 extern int  m8xx_cpm_hostfree(uint start);
  85 extern void m8xx_cpm_hostdump(void);
  86
  87 extern void cpm_load_patch(volatile immap_t *immr);
  88
  89 /* Buffer descriptors used by many of the CPM protocols.
  90 */
  91 typedef struct cpm_buf_desc {
  92         ushort  cbd_sc;         /* Status and Control */
  93         ushort  cbd_datlen;     /* Data length in buffer */
  94         uint    cbd_bufaddr;    /* Buffer address in host memory */
  95 } cbd_t;
  96
  97 #define BD_SC_EMPTY     ((ushort)0x8000)        /* Receive is empty */
  98 #define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
  99 #define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
 100 #define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
 101 #define BD_SC_LAST      ((ushort)0x0800)        /* Last buffer in frame */
 102 #define BD_SC_TC        ((ushort)0x0400)        /* Transmit CRC */
 103 #define BD_SC_CM        ((ushort)0x0200)        /* Continous mode */
 104 #define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
 105 #define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
 106 #define BD_SC_BR        ((ushort)0x0020)        /* Break received */
 107 #define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
 108 #define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
 109 #define BD_SC_NAK       ((ushort)0x0004)        /* NAK - did not respond */
 110 #define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
 111 #define BD_SC_UN        ((ushort)0x0002)        /* Underrun */
 112 #define BD_SC_CD        ((ushort)0x0001)        /* ?? */
 113 #define BD_SC_CL        ((ushort)0x0001)        /* Collision */
 114
 115 /* Parameter RAM offsets.
 116 */
 117 #define PROFF_SCC1      ((uint)0x0000)
 118 #define PROFF_IIC       ((uint)0x0080)
 119 #define PROFF_SCC2      ((uint)0x0100)
 120 #define PROFF_SPI       ((uint)0x0180)
 121 #define PROFF_SCC3      ((uint)0x0200)
 122 #define PROFF_SMC1      ((uint)0x0280)
 123 #define PROFF_SCC4      ((uint)0x0300)
 124 #define PROFF_SMC2      ((uint)0x0380)
 125
 126 /* Define enough so I can at least use the serial port as a UART.
 127  * The MBX uses SMC1 as the host serial port.
 128  */
 129 typedef struct smc_uart {
 130         ushort  smc_rbase;      /* Rx Buffer descriptor base address */
 131         ushort  smc_tbase;      /* Tx Buffer descriptor base address */
 132         u_char  smc_rfcr;       /* Rx function code */
 133         u_char  smc_tfcr;       /* Tx function code */
 134         ushort  smc_mrblr;      /* Max receive buffer length */
 135         uint    smc_rstate;     /* Internal */
 136         uint    smc_idp;        /* Internal */
 137         ushort  smc_rbptr;      /* Internal */
 138         ushort  smc_ibc;        /* Internal */
 139         uint    smc_rxtmp;      /* Internal */
 140         uint    smc_tstate;     /* Internal */
 141         uint    smc_tdp;        /* Internal */
 142         ushort  smc_tbptr;      /* Internal */
 143         ushort  smc_tbc;        /* Internal */
 144         uint    smc_txtmp;      /* Internal */
 145         ushort  smc_maxidl;     /* Maximum idle characters */
 146         ushort  smc_tmpidl;     /* Temporary idle counter */
 147         ushort  smc_brklen;     /* Last received break length */
 148         ushort  smc_brkec;      /* rcv'd break condition counter */
 149         ushort  smc_brkcr;      /* xmt break count register */
 150         ushort  smc_rmask;      /* Temporary bit mask */
 151         char    res1[8];        /* Reserved */
 152         ushort  smc_rpbase;     /* Relocation pointer */
 153 } smc_uart_t;
 154
 155 /* Function code bits.
 156 */
 157 #define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
 158
 159 /* SMC uart mode register.
 160 */
 161 #define SMCMR_REN       ((ushort)0x0001)
 162 #define SMCMR_TEN       ((ushort)0x0002)
 163 #define SMCMR_DM        ((ushort)0x000c)
 164 #define SMCMR_SM_GCI    ((ushort)0x0000)
 165 #define SMCMR_SM_UART   ((ushort)0x0020)
 166 #define SMCMR_SM_TRANS  ((ushort)0x0030)
 167 #define SMCMR_SM_MASK   ((ushort)0x0030)
 168 #define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
 169 #define SMCMR_REVD      SMCMR_PM_EVEN
 170 #define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
 171 #define SMCMR_BS        SMCMR_PEN
 172 #define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
 173 #define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
 174 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
 175
 176 /* SMC2 as Centronics parallel printer.  It is half duplex, in that
 177  * it can only receive or transmit.  The parameter ram values for
 178  * each direction are either unique or properly overlap, so we can
 179  * include them in one structure.
 180  */
 181 typedef struct smc_centronics {
 182         ushort  scent_rbase;
 183         ushort  scent_tbase;
 184         u_char  scent_cfcr;
 185         u_char  scent_smask;
 186         ushort  scent_mrblr;
 187         uint    scent_rstate;
 188         uint    scent_r_ptr;
 189         ushort  scent_rbptr;
 190         ushort  scent_r_cnt;
 191         uint    scent_rtemp;
 192         uint    scent_tstate;
 193         uint    scent_t_ptr;
 194         ushort  scent_tbptr;
 195         ushort  scent_t_cnt;
 196         uint    scent_ttemp;
 197         ushort  scent_max_sl;
 198         ushort  scent_sl_cnt;
 199         ushort  scent_character1;
 200         ushort  scent_character2;
 201         ushort  scent_character3;
 202         ushort  scent_character4;
 203         ushort  scent_character5;
 204         ushort  scent_character6;
 205         ushort  scent_character7;
 206         ushort  scent_character8;
 207         ushort  scent_rccm;
 208         ushort  scent_rccr;
 209 } smc_cent_t;
 210
 211 /* Centronics Status Mask Register.
 212 */
 213 #define SMC_CENT_F      ((u_char)0x08)
 214 #define SMC_CENT_PE     ((u_char)0x04)
 215 #define SMC_CENT_S      ((u_char)0x02)
 216
 217 /* SMC Event and Mask register.
 218 */
 219 #define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
 220 #define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
 221 #define SMCM_TXE        ((unsigned char)0x10)   /* When in Transparent Mode */
 222 #define SMCM_BSY        ((unsigned char)0x04)
 223 #define SMCM_TX         ((unsigned char)0x02)
 224 #define SMCM_RX         ((unsigned char)0x01)
 225
 226 /* Baud rate generators.
 227 */
 228 #define CPM_BRG_RST             ((uint)0x00020000)
 229 #define CPM_BRG_EN              ((uint)0x00010000)
 230 #define CPM_BRG_EXTC_INT        ((uint)0x00000000)
 231 #define CPM_BRG_EXTC_CLK2       ((uint)0x00004000)
 232 #define CPM_BRG_EXTC_CLK6       ((uint)0x00008000)
 233 #define CPM_BRG_ATB             ((uint)0x00002000)
 234 #define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
 235 #define CPM_BRG_DIV16           ((uint)0x00000001)
 236
 237 /* SI Clock Route Register
 238 */
 239 #define SICR_RCLK_SCC1_BRG1     ((uint)0x00000000)
 240 #define SICR_TCLK_SCC1_BRG1     ((uint)0x00000000)
 241 #define SICR_RCLK_SCC2_BRG2     ((uint)0x00000800)
 242 #define SICR_TCLK_SCC2_BRG2     ((uint)0x00000100)
 243 #define SICR_RCLK_SCC3_BRG3     ((uint)0x00100000)
 244 #define SICR_TCLK_SCC3_BRG3     ((uint)0x00020000)
 245 #define SICR_RCLK_SCC4_BRG4     ((uint)0x18000000)
 246 #define SICR_TCLK_SCC4_BRG4     ((uint)0x03000000)
 247
 248 /* SCCs.
 249 */
 250 #define SCC_GSMRH_IRP           ((uint)0x00040000)
 251 #define SCC_GSMRH_GDE           ((uint)0x00010000)
 252 #define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
 253 #define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
 254 #define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
 255 #define SCC_GSMRH_REVD          ((uint)0x00002000)
 256 #define SCC_GSMRH_TRX           ((uint)0x00001000)
 257 #define SCC_GSMRH_TTX           ((uint)0x00000800)
 258 #define SCC_GSMRH_CDP           ((uint)0x00000400)
 259 #define SCC_GSMRH_CTSP          ((uint)0x00000200)
 260 #define SCC_GSMRH_CDS           ((uint)0x00000100)
 261 #define SCC_GSMRH_CTSS          ((uint)0x00000080)
 262 #define SCC_GSMRH_TFL           ((uint)0x00000040)
 263 #define SCC_GSMRH_RFW           ((uint)0x00000020)
 264 #define SCC_GSMRH_TXSY          ((uint)0x00000010)
 265 #define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
 266 #define SCC_GSMRH_SYNL8         ((uint)0x00000008)
 267 #define SCC_GSMRH_SYNL4         ((uint)0x00000004)
 268 #define SCC_GSMRH_RTSM          ((uint)0x00000002)
 269 #define SCC_GSMRH_RSYN          ((uint)0x00000001)
 270
 271 #define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
 272 #define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
 273 #define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
 274 #define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
 275 #define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
 276 #define SCC_GSMRL_TCI           ((uint)0x10000000)
 277 #define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
 278 #define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
 279 #define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
 280 #define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
 281 #define SCC_GSMRL_RINV          ((uint)0x02000000)
 282 #define SCC_GSMRL_TINV          ((uint)0x01000000)
 283 #define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
 284 #define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
 285 #define SCC_GSMRL_TPL_48        ((uint)0x00800000)
 286 #define SCC_GSMRL_TPL_32        ((uint)0x00600000)
 287 #define SCC_GSMRL_TPL_16        ((uint)0x00400000)
 288 #define SCC_GSMRL_TPL_8         ((uint)0x00200000)
 289 #define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
 290 #define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
 291 #define SCC_GSMRL_TPP_01        ((uint)0x00100000)
 292 #define SCC_GSMRL_TPP_10        ((uint)0x00080000)
 293 #define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
 294 #define SCC_GSMRL_TEND          ((uint)0x00040000)
 295 #define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
 296 #define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
 297 #define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
 298 #define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
 299 #define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
 300 #define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
 301 #define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
 302 #define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
 303 #define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
 304 #define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
 305 #define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
 306 #define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
 307 #define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
 308 #define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
 309 #define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
 310 #define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
 311 #define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
 312 #define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
 313 #define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
 314 #define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
 315 #define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
 316 #define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
 317 #define SCC_GSMRL_ENR           ((uint)0x00000020)
 318 #define SCC_GSMRL_ENT           ((uint)0x00000010)
 319 #define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
 320 #define SCC_GSMRL_MODE_QMC      ((uint)0x0000000a)
 321 #define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
 322 #define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
 323 #define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
 324 #define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
 325 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
 326 #define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
 327 #define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
 328 #define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
 329 #define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
 330
 331 #define SCC_TODR_TOD            ((ushort)0x8000)
 332
 333 /* SCC Event and Mask register.
 334 */
 335 #define SCCM_TXE        ((unsigned char)0x10)
 336 #define SCCM_BSY        ((unsigned char)0x04)
 337 #define SCCM_TX         ((unsigned char)0x02)
 338 #define SCCM_RX         ((unsigned char)0x01)
 339
 340 typedef struct scc_param {
 341         ushort  scc_rbase;      /* Rx Buffer descriptor base address */
 342         ushort  scc_tbase;      /* Tx Buffer descriptor base address */
 343         u_char  scc_rfcr;       /* Rx function code */
 344         u_char  scc_tfcr;       /* Tx function code */
 345         ushort  scc_mrblr;      /* Max receive buffer length */
 346         uint    scc_rstate;     /* Internal */
 347         uint    scc_idp;        /* Internal */
 348         ushort  scc_rbptr;      /* Internal */
 349         ushort  scc_ibc;        /* Internal */
 350         uint    scc_rxtmp;      /* Internal */
 351         uint    scc_tstate;     /* Internal */
 352         uint    scc_tdp;        /* Internal */
 353         ushort  scc_tbptr;      /* Internal */
 354         ushort  scc_tbc;        /* Internal */
 355         uint    scc_txtmp;      /* Internal */
 356         uint    scc_rcrc;       /* Internal */
 357         uint    scc_tcrc;       /* Internal */
 358 } sccp_t;
 359
 360 /* Function code bits.
 361 */
 362 #define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
 363
 364 /* CPM Ethernet through SCCx.
 365  */
 366 typedef struct scc_enet {
 367         sccp_t  sen_genscc;
 368         uint    sen_cpres;      /* Preset CRC */
 369         uint    sen_cmask;      /* Constant mask for CRC */
 370         uint    sen_crcec;      /* CRC Error counter */
 371         uint    sen_alec;       /* alignment error counter */
 372         uint    sen_disfc;      /* discard frame counter */
 373         ushort  sen_pads;       /* Tx short frame pad character */
 374         ushort  sen_retlim;     /* Retry limit threshold */
 375         ushort  sen_retcnt;     /* Retry limit counter */
 376         ushort  sen_maxflr;     /* maximum frame length register */
 377         ushort  sen_minflr;     /* minimum frame length register */
 378         ushort  sen_maxd1;      /* maximum DMA1 length */
 379         ushort  sen_maxd2;      /* maximum DMA2 length */
 380         ushort  sen_maxd;       /* Rx max DMA */
 381         ushort  sen_dmacnt;     /* Rx DMA counter */
 382         ushort  sen_maxb;       /* Max BD byte count */
 383         ushort  sen_gaddr1;     /* Group address filter */
 384         ushort  sen_gaddr2;
 385         ushort  sen_gaddr3;
 386         ushort  sen_gaddr4;
 387         uint    sen_tbuf0data0; /* Save area 0 - current frame */
 388         uint    sen_tbuf0data1; /* Save area 1 - current frame */
 389         uint    sen_tbuf0rba;   /* Internal */
 390         uint    sen_tbuf0crc;   /* Internal */
 391         ushort  sen_tbuf0bcnt;  /* Internal */
 392         ushort  sen_paddrh;     /* physical address (MSB) */
 393         ushort  sen_paddrm;
 394         ushort  sen_paddrl;     /* physical address (LSB) */
 395         ushort  sen_pper;       /* persistence */
 396         ushort  sen_rfbdptr;    /* Rx first BD pointer */
 397         ushort  sen_tfbdptr;    /* Tx first BD pointer */
 398         ushort  sen_tlbdptr;    /* Tx last BD pointer */
 399         uint    sen_tbuf1data0; /* Save area 0 - current frame */
 400         uint    sen_tbuf1data1; /* Save area 1 - current frame */
 401         uint    sen_tbuf1rba;   /* Internal */
 402         uint    sen_tbuf1crc;   /* Internal */
 403         ushort  sen_tbuf1bcnt;  /* Internal */
 404         ushort  sen_txlen;      /* Tx Frame length counter */
 405         ushort  sen_iaddr1;     /* Individual address filter */
 406         ushort  sen_iaddr2;
 407         ushort  sen_iaddr3;
 408         ushort  sen_iaddr4;
 409         ushort  sen_boffcnt;    /* Backoff counter */
 410
 411         /* NOTE: Some versions of the manual have the following items
 412          * incorrectly documented.  Below is the proper order.
 413          */
 414         ushort  sen_taddrh;     /* temp address (MSB) */
 415         ushort  sen_taddrm;
 416         ushort  sen_taddrl;     /* temp address (LSB) */
 417 } scc_enet_t;
 418
 419 /* SCC Event register as used by Ethernet.
 420 */
 421 #define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
 422 #define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
 423 #define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
 424 #define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
 425 #define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
 426 #define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
 427
 428 /* SCC Mode Register (PMSR) as used by Ethernet.
 429 */
 430 #define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
 431 #define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
 432 #define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
 433 #define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
 434 #define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
 435 #define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
 436 #define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
 437 #define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
 438 #define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
 439 #define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
 440 #define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
 441 #define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
 442 #define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
 443
 444 /* Buffer descriptor control/status used by Ethernet receive.
 445 */
 446 #define BD_ENET_RX_EMPTY        ((ushort)0x8000)
 447 #define BD_ENET_RX_WRAP         ((ushort)0x2000)
 448 #define BD_ENET_RX_INTR         ((ushort)0x1000)
 449 #define BD_ENET_RX_LAST         ((ushort)0x0800)
 450 #define BD_ENET_RX_FIRST        ((ushort)0x0400)
 451 #define BD_ENET_RX_MISS         ((ushort)0x0100)
 452 #define BD_ENET_RX_LG           ((ushort)0x0020)
 453 #define BD_ENET_RX_NO           ((ushort)0x0010)
 454 #define BD_ENET_RX_SH           ((ushort)0x0008)
 455 #define BD_ENET_RX_CR           ((ushort)0x0004)
 456 #define BD_ENET_RX_OV           ((ushort)0x0002)
 457 #define BD_ENET_RX_CL           ((ushort)0x0001)
 458 #define BD_ENET_RX_BC           ((ushort)0x0080)        /* DA is Broadcast */
 459 #define BD_ENET_RX_MC           ((ushort)0x0040)        /* DA is Multicast */
 460 #define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */
 461
 462 /* Buffer descriptor control/status used by Ethernet transmit.
 463 */
 464 #define BD_ENET_TX_READY        ((ushort)0x8000)
 465 #define BD_ENET_TX_PAD          ((ushort)0x4000)
 466 #define BD_ENET_TX_WRAP         ((ushort)0x2000)
 467 #define BD_ENET_TX_INTR         ((ushort)0x1000)
 468 #define BD_ENET_TX_LAST         ((ushort)0x0800)
 469 #define BD_ENET_TX_TC           ((ushort)0x0400)
 470 #define BD_ENET_TX_DEF          ((ushort)0x0200)
 471 #define BD_ENET_TX_HB           ((ushort)0x0100)
 472 #define BD_ENET_TX_LC           ((ushort)0x0080)
 473 #define BD_ENET_TX_RL           ((ushort)0x0040)
 474 #define BD_ENET_TX_RCMASK       ((ushort)0x003c)
 475 #define BD_ENET_TX_UN           ((ushort)0x0002)
 476 #define BD_ENET_TX_CSL          ((ushort)0x0001)
 477 #define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
 478
 479 /* SCC as UART
 480 */
 481 typedef struct scc_uart {
 482         sccp_t  scc_genscc;
 483         char    res1[8];        /* Reserved */
 484         ushort  scc_maxidl;     /* Maximum idle chars */
 485         ushort  scc_idlc;       /* temp idle counter */
 486         ushort  scc_brkcr;      /* Break count register */
 487         ushort  scc_parec;      /* receive parity error counter */
 488         ushort  scc_frmec;      /* receive framing error counter */
 489         ushort  scc_nosec;      /* receive noise counter */
 490         ushort  scc_brkec;      /* receive break condition counter */
 491         ushort  scc_brkln;      /* last received break length */
 492         ushort  scc_uaddr1;     /* UART address character 1 */
 493         ushort  scc_uaddr2;     /* UART address character 2 */
 494         ushort  scc_rtemp;      /* Temp storage */
 495         ushort  scc_toseq;      /* Transmit out of sequence char */
 496         ushort  scc_char1;      /* control character 1 */
 497         ushort  scc_char2;      /* control character 2 */
 498         ushort  scc_char3;      /* control character 3 */
 499         ushort  scc_char4;      /* control character 4 */
 500         ushort  scc_char5;      /* control character 5 */
 501         ushort  scc_char6;      /* control character 6 */
 502         ushort  scc_char7;      /* control character 7 */
 503         ushort  scc_char8;      /* control character 8 */
 504         ushort  scc_rccm;       /* receive control character mask */
 505         ushort  scc_rccr;       /* receive control character register */
 506         ushort  scc_rlbc;       /* receive last break character */
 507 } scc_uart_t;
 508
 509 /* SCC Event and Mask registers when it is used as a UART.
 510 */
 511 #define UART_SCCM_GLR           ((ushort)0x1000)
 512 #define UART_SCCM_GLT           ((ushort)0x0800)
 513 #define UART_SCCM_AB            ((ushort)0x0200)
 514 #define UART_SCCM_IDL           ((ushort)0x0100)
 515 #define UART_SCCM_GRA           ((ushort)0x0080)
 516 #define UART_SCCM_BRKE          ((ushort)0x0040)
 517 #define UART_SCCM_BRKS          ((ushort)0x0020)
 518 #define UART_SCCM_CCR           ((ushort)0x0008)
 519 #define UART_SCCM_BSY           ((ushort)0x0004)
 520 #define UART_SCCM_TX            ((ushort)0x0002)
 521 #define UART_SCCM_RX            ((ushort)0x0001)
 522
 523 /* The SCC PMSR when used as a UART.
 524 */
 525 #define SCU_PSMR_FLC            ((ushort)0x8000)
 526 #define SCU_PSMR_SL             ((ushort)0x4000)
 527 #define SCU_PSMR_CL             ((ushort)0x3000)
 528 #define SCU_PSMR_UM             ((ushort)0x0c00)
 529 #define SCU_PSMR_FRZ            ((ushort)0x0200)
 530 #define SCU_PSMR_RZS            ((ushort)0x0100)
 531 #define SCU_PSMR_SYN            ((ushort)0x0080)
 532 #define SCU_PSMR_DRT            ((ushort)0x0040)
 533 #define SCU_PSMR_PEN            ((ushort)0x0010)
 534 #define SCU_PSMR_RPM            ((ushort)0x000c)
 535 #define SCU_PSMR_REVP           ((ushort)0x0008)
 536 #define SCU_PSMR_TPM            ((ushort)0x0003)
 537 #define SCU_PSMR_TEVP           ((ushort)0x0002)
 538
 539 /* CPM Transparent mode SCC.
 540  */
 541 typedef struct scc_trans {
 542         sccp_t  st_genscc;
 543         uint    st_cpres;       /* Preset CRC */
 544         uint    st_cmask;       /* Constant mask for CRC */
 545 } scc_trans_t;
 546
 547 #define BD_SCC_TX_LAST          ((ushort)0x0800)
 548
 549 /* IIC parameter RAM.
 550 */
 551 typedef struct iic {
 552         ushort  iic_rbase;      /* Rx Buffer descriptor base address */
 553         ushort  iic_tbase;      /* Tx Buffer descriptor base address */
 554         u_char  iic_rfcr;       /* Rx function code */
 555         u_char  iic_tfcr;       /* Tx function code */
 556         ushort  iic_mrblr;      /* Max receive buffer length */
 557         uint    iic_rstate;     /* Internal */
 558         uint    iic_rdp;        /* Internal */
 559         ushort  iic_rbptr;      /* Internal */
 560         ushort  iic_rbc;        /* Internal */
 561         uint    iic_rxtmp;      /* Internal */
 562         uint    iic_tstate;     /* Internal */
 563         uint    iic_tdp;        /* Internal */
 564         ushort  iic_tbptr;      /* Internal */
 565         ushort  iic_tbc;        /* Internal */
 566         uint    iic_txtmp;      /* Internal */
 567         char    res1[4];        /* Reserved */
 568         ushort  iic_rpbase;     /* Relocation pointer */
 569         char    res2[2];        /* Reserved */
 570 } iic_t;
 571
 572 #define BD_IIC_START            ((ushort)0x0400)
 573
 574 /* SPI parameter RAM.
 575 */
 576 typedef struct spi {
 577         ushort  spi_rbase;      /* Rx Buffer descriptor base address */
 578         ushort  spi_tbase;      /* Tx Buffer descriptor base address */
 579         u_char  spi_rfcr;       /* Rx function code */
 580         u_char  spi_tfcr;       /* Tx function code */
 581         ushort  spi_mrblr;      /* Max receive buffer length */
 582         uint    spi_rstate;     /* Internal */
 583         uint    spi_rdp;        /* Internal */
 584         ushort  spi_rbptr;      /* Internal */
 585         ushort  spi_rbc;        /* Internal */
 586         uint    spi_rxtmp;      /* Internal */
 587         uint    spi_tstate;     /* Internal */
 588         uint    spi_tdp;        /* Internal */
 589         ushort  spi_tbptr;      /* Internal */
 590         ushort  spi_tbc;        /* Internal */
 591         uint    spi_txtmp;      /* Internal */
 592         uint    spi_res;
 593         ushort  spi_rpbase;     /* Relocation pointer */
 594         ushort  spi_res2;
 595 } spi_t;
 596
 597 /* SPI Mode register.
 598 */
 599 #define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
 600 #define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
 601 #define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
 602 #define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
 603 #define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
 604 #define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
 605 #define SPMODE_EN       ((ushort)0x0100)        /* Enable */
 606 #define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
 607 #define SPMODE_LEN4     ((ushort)0x0030)        /*  4 bits per char */
 608 #define SPMODE_LEN8     ((ushort)0x0070)        /*  8 bits per char */
 609 #define SPMODE_LEN16    ((ushort)0x00f0)        /* 16 bits per char */
 610 #define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
 611
 612 /* SPIE fields */
 613 #define SPIE_MME        0x20
 614 #define SPIE_TXE        0x10
 615 #define SPIE_BSY        0x04
 616 #define SPIE_TXB        0x02
 617 #define SPIE_RXB        0x01
 618
 619 /*
 620  * RISC Controller Configuration Register definitons
 621  */
 622 #define RCCR_TIME       0x8000                  /* RISC Timer Enable */
 623 #define RCCR_TIMEP(t)   (((t) & 0x3F)<<8)       /* RISC Timer Period */
 624 #define RCCR_TIME_MASK  0x00FF                  /* not RISC Timer related bits */
 625
 626 /* RISC Timer Parameter RAM offset */
 627 #define PROFF_RTMR      ((uint)0x01B0)
 628
 629 typedef struct risc_timer_pram {
 630         unsigned short  tm_base;        /* RISC Timer Table Base Address */
 631         unsigned short  tm_ptr;         /* RISC Timer Table Pointer (internal) */
 632         unsigned short  r_tmr;          /* RISC Timer Mode Register */
 633         unsigned short  r_tmv;          /* RISC Timer Valid Register */
 634         unsigned long   tm_cmd;         /* RISC Timer Command Register */
 635         unsigned long   tm_cnt;         /* RISC Timer Internal Count */
 636 } rt_pram_t;
 637
 638 /* Bits in RISC Timer Command Register */
 639 #define TM_CMD_VALID    0x80000000      /* Valid - Enables the timer */
 640 #define TM_CMD_RESTART  0x40000000      /* Restart - for automatic restart */
 641 #define TM_CMD_PWM      0x20000000      /* Run in Pulse Width Modulation Mode */
 642 #define TM_CMD_NUM(n)   (((n)&0xF)<<16) /* Timer Number */
 643 #define TM_CMD_PERIOD(p) ((p)&0xFFFF)   /* Timer Period */
 644
 645 /* CPM interrupts.  There are nearly 32 interrupts generated by CPM
 646  * channels or devices.  All of these are presented to the PPC core
 647  * as a single interrupt.  The CPM interrupt handler dispatches its
 648  * own handlers, in a similar fashion to the PPC core handler.  We
 649  * use the table as defined in the manuals (i.e. no special high
 650  * priority and SCC1 == SCCa, etc...).
 651  */
 652 #define CPMVEC_NR               32
 653 #define CPMVEC_PIO_PC15         ((ushort)0x1f)
 654 #define CPMVEC_SCC1             ((ushort)0x1e)
 655 #define CPMVEC_SCC2             ((ushort)0x1d)
 656 #define CPMVEC_SCC3             ((ushort)0x1c)
 657 #define CPMVEC_SCC4             ((ushort)0x1b)
 658 #define CPMVEC_PIO_PC14         ((ushort)0x1a)
 659 #define CPMVEC_TIMER1           ((ushort)0x19)
 660 #define CPMVEC_PIO_PC13         ((ushort)0x18)
 661 #define CPMVEC_PIO_PC12         ((ushort)0x17)
 662 #define CPMVEC_SDMA_CB_ERR      ((ushort)0x16)
 663 #define CPMVEC_IDMA1            ((ushort)0x15)
 664 #define CPMVEC_IDMA2            ((ushort)0x14)
 665 #define CPMVEC_TIMER2           ((ushort)0x12)
 666 #define CPMVEC_RISCTIMER        ((ushort)0x11)
 667 #define CPMVEC_I2C              ((ushort)0x10)
 668 #define CPMVEC_PIO_PC11         ((ushort)0x0f)
 669 #define CPMVEC_PIO_PC10         ((ushort)0x0e)
 670 #define CPMVEC_TIMER3           ((ushort)0x0c)
 671 #define CPMVEC_PIO_PC9          ((ushort)0x0b)
 672 #define CPMVEC_PIO_PC8          ((ushort)0x0a)
 673 #define CPMVEC_PIO_PC7          ((ushort)0x09)
 674 #define CPMVEC_TIMER4           ((ushort)0x07)
 675 #define CPMVEC_PIO_PC6          ((ushort)0x06)
 676 #define CPMVEC_SPI              ((ushort)0x05)
 677 #define CPMVEC_SMC1             ((ushort)0x04)
 678 #define CPMVEC_SMC2             ((ushort)0x03)
 679 #define CPMVEC_PIO_PC5          ((ushort)0x02)
 680 #define CPMVEC_PIO_PC4          ((ushort)0x01)
 681 #define CPMVEC_ERROR            ((ushort)0x00)
 682
 683 /* CPM interrupt configuration vector.
 684 */
 685 #define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
 686 #define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
 687 #define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
 688 #define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
 689 #define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrrupt */
 690 #define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
 691 #define CICR_IEN                ((uint)0x00000080)      /* Int. enable */
 692 #define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
 693
 694 extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
 695 extern void cpm_free_handler(int vec);
 696
 697 #endif /* __CPM_8XX__ */