2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
63 #include <asm/uv/uv_hub.h>
64 #include <asm/uv/uv_irq.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug
= -1;
76 static DEFINE_SPINLOCK(ioapic_lock
);
77 static DEFINE_SPINLOCK(vector_lock
);
80 * # of IRQ routing registers
82 int nr_ioapic_registers
[MAX_IO_APICS
];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics
[MAX_IO_APICS
];
88 /* MP IRQ source entries */
89 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
98 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
100 int skip_ioapic_setup
;
102 void arch_disable_smp_support(void)
106 noioapicreroute
= -1;
108 skip_ioapic_setup
= 1;
111 static int __init
parse_noapic(char *str
)
113 /* disable IO-APIC */
114 arch_disable_smp_support();
117 early_param("noapic", parse_noapic
);
119 struct irq_pin_list
{
121 struct irq_pin_list
*next
;
124 static struct irq_pin_list
*get_one_free_irq_2_pin(int node
)
126 struct irq_pin_list
*pin
;
128 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
134 * This is performance-critical, we want to do it O(1)
136 * Most irqs are mapped 1:1 with pins.
139 struct irq_pin_list
*irq_2_pin
;
140 cpumask_var_t domain
;
141 cpumask_var_t old_domain
;
142 unsigned move_cleanup_count
;
144 u8 move_in_progress
: 1;
147 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
148 #ifdef CONFIG_SPARSE_IRQ
149 static struct irq_cfg irq_cfgx
[] = {
151 static struct irq_cfg irq_cfgx
[NR_IRQS
] = {
153 [0] = { .vector
= IRQ0_VECTOR
, },
154 [1] = { .vector
= IRQ1_VECTOR
, },
155 [2] = { .vector
= IRQ2_VECTOR
, },
156 [3] = { .vector
= IRQ3_VECTOR
, },
157 [4] = { .vector
= IRQ4_VECTOR
, },
158 [5] = { .vector
= IRQ5_VECTOR
, },
159 [6] = { .vector
= IRQ6_VECTOR
, },
160 [7] = { .vector
= IRQ7_VECTOR
, },
161 [8] = { .vector
= IRQ8_VECTOR
, },
162 [9] = { .vector
= IRQ9_VECTOR
, },
163 [10] = { .vector
= IRQ10_VECTOR
, },
164 [11] = { .vector
= IRQ11_VECTOR
, },
165 [12] = { .vector
= IRQ12_VECTOR
, },
166 [13] = { .vector
= IRQ13_VECTOR
, },
167 [14] = { .vector
= IRQ14_VECTOR
, },
168 [15] = { .vector
= IRQ15_VECTOR
, },
171 int __init
arch_early_irq_init(void)
174 struct irq_desc
*desc
;
180 count
= ARRAY_SIZE(irq_cfgx
);
181 node
= cpu_to_node(boot_cpu_id
);
183 for (i
= 0; i
< count
; i
++) {
184 desc
= irq_to_desc(i
);
185 desc
->chip_data
= &cfg
[i
];
186 zalloc_cpumask_var_node(&cfg
[i
].domain
, GFP_NOWAIT
, node
);
187 zalloc_cpumask_var_node(&cfg
[i
].old_domain
, GFP_NOWAIT
, node
);
188 if (i
< NR_IRQS_LEGACY
)
189 cpumask_setall(cfg
[i
].domain
);
195 #ifdef CONFIG_SPARSE_IRQ
196 static struct irq_cfg
*irq_cfg(unsigned int irq
)
198 struct irq_cfg
*cfg
= NULL
;
199 struct irq_desc
*desc
;
201 desc
= irq_to_desc(irq
);
203 cfg
= desc
->chip_data
;
208 static struct irq_cfg
*get_one_free_irq_cfg(int node
)
212 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
214 if (!alloc_cpumask_var_node(&cfg
->domain
, GFP_ATOMIC
, node
)) {
217 } else if (!alloc_cpumask_var_node(&cfg
->old_domain
,
219 free_cpumask_var(cfg
->domain
);
223 cpumask_clear(cfg
->domain
);
224 cpumask_clear(cfg
->old_domain
);
231 int arch_init_chip_data(struct irq_desc
*desc
, int node
)
235 cfg
= desc
->chip_data
;
237 desc
->chip_data
= get_one_free_irq_cfg(node
);
238 if (!desc
->chip_data
) {
239 printk(KERN_ERR
"can not alloc irq_cfg\n");
247 /* for move_irq_desc */
249 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int node
)
251 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
253 cfg
->irq_2_pin
= NULL
;
254 old_entry
= old_cfg
->irq_2_pin
;
258 entry
= get_one_free_irq_2_pin(node
);
262 entry
->apic
= old_entry
->apic
;
263 entry
->pin
= old_entry
->pin
;
266 old_entry
= old_entry
->next
;
268 entry
= get_one_free_irq_2_pin(node
);
276 /* still use the old one */
279 entry
->apic
= old_entry
->apic
;
280 entry
->pin
= old_entry
->pin
;
283 old_entry
= old_entry
->next
;
287 cfg
->irq_2_pin
= head
;
290 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
292 struct irq_pin_list
*entry
, *next
;
294 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
297 entry
= old_cfg
->irq_2_pin
;
304 old_cfg
->irq_2_pin
= NULL
;
307 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
308 struct irq_desc
*desc
, int node
)
311 struct irq_cfg
*old_cfg
;
313 cfg
= get_one_free_irq_cfg(node
);
318 desc
->chip_data
= cfg
;
320 old_cfg
= old_desc
->chip_data
;
322 memcpy(cfg
, old_cfg
, sizeof(struct irq_cfg
));
324 init_copy_irq_2_pin(old_cfg
, cfg
, node
);
327 static void free_irq_cfg(struct irq_cfg
*old_cfg
)
332 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
334 struct irq_cfg
*old_cfg
, *cfg
;
336 old_cfg
= old_desc
->chip_data
;
337 cfg
= desc
->chip_data
;
343 free_irq_2_pin(old_cfg
, cfg
);
344 free_irq_cfg(old_cfg
);
345 old_desc
->chip_data
= NULL
;
348 /* end for move_irq_desc */
351 static struct irq_cfg
*irq_cfg(unsigned int irq
)
353 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
360 unsigned int unused
[3];
362 unsigned int unused2
[11];
366 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
368 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
369 + (mp_ioapics
[idx
].apicaddr
& ~PAGE_MASK
);
372 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
374 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
375 writel(vector
, &io_apic
->eoi
);
378 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
380 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
381 writel(reg
, &io_apic
->index
);
382 return readl(&io_apic
->data
);
385 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
387 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
388 writel(reg
, &io_apic
->index
);
389 writel(value
, &io_apic
->data
);
393 * Re-write a value: to be used for read-modify-write
394 * cycles where the read already set up the index register.
396 * Older SiS APIC requires we rewrite the index register
398 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
400 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
403 writel(reg
, &io_apic
->index
);
404 writel(value
, &io_apic
->data
);
407 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
409 struct irq_pin_list
*entry
;
412 spin_lock_irqsave(&ioapic_lock
, flags
);
413 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
418 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
419 /* Is the remote IRR bit set? */
420 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
421 spin_unlock_irqrestore(&ioapic_lock
, flags
);
425 spin_unlock_irqrestore(&ioapic_lock
, flags
);
431 struct { u32 w1
, w2
; };
432 struct IO_APIC_route_entry entry
;
435 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
437 union entry_union eu
;
439 spin_lock_irqsave(&ioapic_lock
, flags
);
440 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
441 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
442 spin_unlock_irqrestore(&ioapic_lock
, flags
);
447 * When we write a new IO APIC routing entry, we need to write the high
448 * word first! If the mask bit in the low word is clear, we will enable
449 * the interrupt, and we need to make sure the entry is fully populated
450 * before that happens.
453 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
455 union entry_union eu
= {{0, 0}};
458 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
459 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
462 void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
465 spin_lock_irqsave(&ioapic_lock
, flags
);
466 __ioapic_write_entry(apic
, pin
, e
);
467 spin_unlock_irqrestore(&ioapic_lock
, flags
);
471 * When we mask an IO APIC routing entry, we need to write the low
472 * word first, in order to set the mask bit before we change the
475 static void ioapic_mask_entry(int apic
, int pin
)
478 union entry_union eu
= { .entry
.mask
= 1 };
480 spin_lock_irqsave(&ioapic_lock
, flags
);
481 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
482 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
483 spin_unlock_irqrestore(&ioapic_lock
, flags
);
487 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
488 * shared ISA-space IRQs, so we have to support them. We are super
489 * fast in the common case, and fast for shared ISA-space IRQs.
491 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
493 struct irq_pin_list
**entryp
, *entry
;
495 for (entryp
= &cfg
->irq_2_pin
;
497 entryp
= &(*entryp
)->next
) {
499 /* not again, please */
500 if (entry
->apic
== apic
&& entry
->pin
== pin
)
504 entry
= get_one_free_irq_2_pin(node
);
512 * Reroute an IRQ to a different pin.
514 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
515 int oldapic
, int oldpin
,
516 int newapic
, int newpin
)
518 struct irq_pin_list
*entry
;
520 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
521 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
522 entry
->apic
= newapic
;
524 /* every one is different, right? */
529 /* old apic/pin didn't exist, so just add new ones */
530 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
533 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
534 int mask_and
, int mask_or
,
535 void (*final
)(struct irq_pin_list
*entry
))
538 struct irq_pin_list
*entry
;
540 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
543 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
546 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
552 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
554 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
557 static void io_apic_sync(struct irq_pin_list
*entry
)
560 * Synchronize the IO-APIC and the CPU by doing
561 * a dummy read from the IO-APIC
563 struct io_apic __iomem
*io_apic
;
564 io_apic
= io_apic_base(entry
->apic
);
565 readl(&io_apic
->data
);
568 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
570 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
573 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg
*cfg
)
575 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
576 IO_APIC_REDIR_MASKED
, NULL
);
579 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg
*cfg
)
581 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
,
582 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
585 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
587 struct irq_cfg
*cfg
= desc
->chip_data
;
592 spin_lock_irqsave(&ioapic_lock
, flags
);
593 __mask_IO_APIC_irq(cfg
);
594 spin_unlock_irqrestore(&ioapic_lock
, flags
);
597 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
599 struct irq_cfg
*cfg
= desc
->chip_data
;
602 spin_lock_irqsave(&ioapic_lock
, flags
);
603 __unmask_IO_APIC_irq(cfg
);
604 spin_unlock_irqrestore(&ioapic_lock
, flags
);
607 static void mask_IO_APIC_irq(unsigned int irq
)
609 struct irq_desc
*desc
= irq_to_desc(irq
);
611 mask_IO_APIC_irq_desc(desc
);
613 static void unmask_IO_APIC_irq(unsigned int irq
)
615 struct irq_desc
*desc
= irq_to_desc(irq
);
617 unmask_IO_APIC_irq_desc(desc
);
620 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
622 struct IO_APIC_route_entry entry
;
624 /* Check delivery_mode to be sure we're not clearing an SMI pin */
625 entry
= ioapic_read_entry(apic
, pin
);
626 if (entry
.delivery_mode
== dest_SMI
)
629 * Disable it in the IO-APIC irq-routing table:
631 ioapic_mask_entry(apic
, pin
);
634 static void clear_IO_APIC (void)
638 for (apic
= 0; apic
< nr_ioapics
; apic
++)
639 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
640 clear_IO_APIC_pin(apic
, pin
);
645 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
646 * specific CPU-side IRQs.
650 static int pirq_entries
[MAX_PIRQS
] = {
651 [0 ... MAX_PIRQS
- 1] = -1
654 static int __init
ioapic_pirq_setup(char *str
)
657 int ints
[MAX_PIRQS
+1];
659 get_options(str
, ARRAY_SIZE(ints
), ints
);
661 apic_printk(APIC_VERBOSE
, KERN_INFO
662 "PIRQ redirection, working around broken MP-BIOS.\n");
664 if (ints
[0] < MAX_PIRQS
)
667 for (i
= 0; i
< max
; i
++) {
668 apic_printk(APIC_VERBOSE
, KERN_DEBUG
669 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
671 * PIRQs are mapped upside down, usually.
673 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
678 __setup("pirq=", ioapic_pirq_setup
);
679 #endif /* CONFIG_X86_32 */
681 struct IO_APIC_route_entry
**alloc_ioapic_entries(void)
684 struct IO_APIC_route_entry
**ioapic_entries
;
686 ioapic_entries
= kzalloc(sizeof(*ioapic_entries
) * nr_ioapics
,
691 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
692 ioapic_entries
[apic
] =
693 kzalloc(sizeof(struct IO_APIC_route_entry
) *
694 nr_ioapic_registers
[apic
], GFP_ATOMIC
);
695 if (!ioapic_entries
[apic
])
699 return ioapic_entries
;
703 kfree(ioapic_entries
[apic
]);
704 kfree(ioapic_entries
);
710 * Saves all the IO-APIC RTE's
712 int save_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
719 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
720 if (!ioapic_entries
[apic
])
723 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
724 ioapic_entries
[apic
][pin
] =
725 ioapic_read_entry(apic
, pin
);
732 * Mask all IO APIC entries.
734 void mask_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
741 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
742 if (!ioapic_entries
[apic
])
745 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
746 struct IO_APIC_route_entry entry
;
748 entry
= ioapic_entries
[apic
][pin
];
751 ioapic_write_entry(apic
, pin
, entry
);
758 * Restore IO APIC entries which was saved in ioapic_entries.
760 int restore_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
767 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
768 if (!ioapic_entries
[apic
])
771 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
772 ioapic_write_entry(apic
, pin
,
773 ioapic_entries
[apic
][pin
]);
778 void free_ioapic_entries(struct IO_APIC_route_entry
**ioapic_entries
)
782 for (apic
= 0; apic
< nr_ioapics
; apic
++)
783 kfree(ioapic_entries
[apic
]);
785 kfree(ioapic_entries
);
789 * Find the IRQ entry number of a certain pin.
791 static int find_irq_entry(int apic
, int pin
, int type
)
795 for (i
= 0; i
< mp_irq_entries
; i
++)
796 if (mp_irqs
[i
].irqtype
== type
&&
797 (mp_irqs
[i
].dstapic
== mp_ioapics
[apic
].apicid
||
798 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
799 mp_irqs
[i
].dstirq
== pin
)
806 * Find the pin to which IRQ[irq] (ISA) is connected
808 static int __init
find_isa_irq_pin(int irq
, int type
)
812 for (i
= 0; i
< mp_irq_entries
; i
++) {
813 int lbus
= mp_irqs
[i
].srcbus
;
815 if (test_bit(lbus
, mp_bus_not_pci
) &&
816 (mp_irqs
[i
].irqtype
== type
) &&
817 (mp_irqs
[i
].srcbusirq
== irq
))
819 return mp_irqs
[i
].dstirq
;
824 static int __init
find_isa_irq_apic(int irq
, int type
)
828 for (i
= 0; i
< mp_irq_entries
; i
++) {
829 int lbus
= mp_irqs
[i
].srcbus
;
831 if (test_bit(lbus
, mp_bus_not_pci
) &&
832 (mp_irqs
[i
].irqtype
== type
) &&
833 (mp_irqs
[i
].srcbusirq
== irq
))
836 if (i
< mp_irq_entries
) {
838 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
839 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
)
847 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
849 * EISA Edge/Level control register, ELCR
851 static int EISA_ELCR(unsigned int irq
)
853 if (irq
< NR_IRQS_LEGACY
) {
854 unsigned int port
= 0x4d0 + (irq
>> 3);
855 return (inb(port
) >> (irq
& 7)) & 1;
857 apic_printk(APIC_VERBOSE
, KERN_INFO
858 "Broken MPtable reports ISA irq %d\n", irq
);
864 /* ISA interrupts are always polarity zero edge triggered,
865 * when listed as conforming in the MP table. */
867 #define default_ISA_trigger(idx) (0)
868 #define default_ISA_polarity(idx) (0)
870 /* EISA interrupts are always polarity zero and can be edge or level
871 * trigger depending on the ELCR value. If an interrupt is listed as
872 * EISA conforming in the MP table, that means its trigger type must
873 * be read in from the ELCR */
875 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
876 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
878 /* PCI interrupts are always polarity one level triggered,
879 * when listed as conforming in the MP table. */
881 #define default_PCI_trigger(idx) (1)
882 #define default_PCI_polarity(idx) (1)
884 /* MCA interrupts are always polarity zero level triggered,
885 * when listed as conforming in the MP table. */
887 #define default_MCA_trigger(idx) (1)
888 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
890 static int MPBIOS_polarity(int idx
)
892 int bus
= mp_irqs
[idx
].srcbus
;
896 * Determine IRQ line polarity (high active or low active):
898 switch (mp_irqs
[idx
].irqflag
& 3)
900 case 0: /* conforms, ie. bus-type dependent polarity */
901 if (test_bit(bus
, mp_bus_not_pci
))
902 polarity
= default_ISA_polarity(idx
);
904 polarity
= default_PCI_polarity(idx
);
906 case 1: /* high active */
911 case 2: /* reserved */
913 printk(KERN_WARNING
"broken BIOS!!\n");
917 case 3: /* low active */
922 default: /* invalid */
924 printk(KERN_WARNING
"broken BIOS!!\n");
932 static int MPBIOS_trigger(int idx
)
934 int bus
= mp_irqs
[idx
].srcbus
;
938 * Determine IRQ trigger mode (edge or level sensitive):
940 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
942 case 0: /* conforms, ie. bus-type dependent */
943 if (test_bit(bus
, mp_bus_not_pci
))
944 trigger
= default_ISA_trigger(idx
);
946 trigger
= default_PCI_trigger(idx
);
947 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
948 switch (mp_bus_id_to_type
[bus
]) {
949 case MP_BUS_ISA
: /* ISA pin */
951 /* set before the switch */
954 case MP_BUS_EISA
: /* EISA pin */
956 trigger
= default_EISA_trigger(idx
);
959 case MP_BUS_PCI
: /* PCI pin */
961 /* set before the switch */
964 case MP_BUS_MCA
: /* MCA pin */
966 trigger
= default_MCA_trigger(idx
);
971 printk(KERN_WARNING
"broken BIOS!!\n");
983 case 2: /* reserved */
985 printk(KERN_WARNING
"broken BIOS!!\n");
994 default: /* invalid */
996 printk(KERN_WARNING
"broken BIOS!!\n");
1004 static inline int irq_polarity(int idx
)
1006 return MPBIOS_polarity(idx
);
1009 static inline int irq_trigger(int idx
)
1011 return MPBIOS_trigger(idx
);
1014 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1015 static int pin_2_irq(int idx
, int apic
, int pin
)
1018 int bus
= mp_irqs
[idx
].srcbus
;
1021 * Debugging check, we are in big trouble if this message pops up!
1023 if (mp_irqs
[idx
].dstirq
!= pin
)
1024 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1026 if (test_bit(bus
, mp_bus_not_pci
)) {
1027 irq
= mp_irqs
[idx
].srcbusirq
;
1030 * PCI IRQs are mapped in order
1034 irq
+= nr_ioapic_registers
[i
++];
1037 * For MPS mode, so far only needed by ES7000 platform
1039 if (ioapic_renumber_irq
)
1040 irq
= ioapic_renumber_irq(apic
, irq
);
1043 #ifdef CONFIG_X86_32
1045 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1047 if ((pin
>= 16) && (pin
<= 23)) {
1048 if (pirq_entries
[pin
-16] != -1) {
1049 if (!pirq_entries
[pin
-16]) {
1050 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1051 "disabling PIRQ%d\n", pin
-16);
1053 irq
= pirq_entries
[pin
-16];
1054 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1055 "using PIRQ%d -> IRQ %d\n",
1066 * Find a specific PCI IRQ entry.
1067 * Not an __init, possibly needed by modules
1069 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
1070 struct io_apic_irq_attr
*irq_attr
)
1072 int apic
, i
, best_guess
= -1;
1074 apic_printk(APIC_DEBUG
,
1075 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1077 if (test_bit(bus
, mp_bus_not_pci
)) {
1078 apic_printk(APIC_VERBOSE
,
1079 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1082 for (i
= 0; i
< mp_irq_entries
; i
++) {
1083 int lbus
= mp_irqs
[i
].srcbus
;
1085 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1086 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
||
1087 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1090 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1091 !mp_irqs
[i
].irqtype
&&
1093 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1094 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1096 if (!(apic
|| IO_APIC_IRQ(irq
)))
1099 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1100 set_io_apic_irq_attr(irq_attr
, apic
,
1107 * Use the first all-but-pin matching entry as a
1108 * best-guess fuzzy result for broken mptables.
1110 if (best_guess
< 0) {
1111 set_io_apic_irq_attr(irq_attr
, apic
,
1121 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1123 void lock_vector_lock(void)
1125 /* Used to the online set of cpus does not change
1126 * during assign_irq_vector.
1128 spin_lock(&vector_lock
);
1131 void unlock_vector_lock(void)
1133 spin_unlock(&vector_lock
);
1137 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1140 * NOTE! The local APIC isn't very good at handling
1141 * multiple interrupts at the same interrupt level.
1142 * As the interrupt level is determined by taking the
1143 * vector number and shifting that right by 4, we
1144 * want to spread these out a bit so that they don't
1145 * all fall in the same interrupt level.
1147 * Also, we've got to be careful not to trash gate
1148 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1150 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1151 unsigned int old_vector
;
1153 cpumask_var_t tmp_mask
;
1155 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1158 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1161 old_vector
= cfg
->vector
;
1163 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1164 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1165 if (!cpumask_empty(tmp_mask
)) {
1166 free_cpumask_var(tmp_mask
);
1171 /* Only try and allocate irqs on cpus that are present */
1173 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1177 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1179 vector
= current_vector
;
1180 offset
= current_offset
;
1183 if (vector
>= first_system_vector
) {
1184 /* If out of vectors on large boxen, must share them. */
1185 offset
= (offset
+ 1) % 8;
1186 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1188 if (unlikely(current_vector
== vector
))
1191 if (test_bit(vector
, used_vectors
))
1194 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1195 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1198 current_vector
= vector
;
1199 current_offset
= offset
;
1201 cfg
->move_in_progress
= 1;
1202 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1204 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1205 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1206 cfg
->vector
= vector
;
1207 cpumask_copy(cfg
->domain
, tmp_mask
);
1211 free_cpumask_var(tmp_mask
);
1216 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1219 unsigned long flags
;
1221 spin_lock_irqsave(&vector_lock
, flags
);
1222 err
= __assign_irq_vector(irq
, cfg
, mask
);
1223 spin_unlock_irqrestore(&vector_lock
, flags
);
1227 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1231 BUG_ON(!cfg
->vector
);
1233 vector
= cfg
->vector
;
1234 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1235 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1238 cpumask_clear(cfg
->domain
);
1240 if (likely(!cfg
->move_in_progress
))
1242 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1243 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1245 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1247 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1251 cfg
->move_in_progress
= 0;
1254 void __setup_vector_irq(int cpu
)
1256 /* Initialize vector_irq on a new cpu */
1257 /* This function must be called with vector_lock held */
1259 struct irq_cfg
*cfg
;
1260 struct irq_desc
*desc
;
1262 /* Mark the inuse vectors */
1263 for_each_irq_desc(irq
, desc
) {
1264 cfg
= desc
->chip_data
;
1265 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1267 vector
= cfg
->vector
;
1268 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1270 /* Mark the free vectors */
1271 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1272 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1277 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1278 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1282 static struct irq_chip ioapic_chip
;
1283 static struct irq_chip ir_ioapic_chip
;
1285 #define IOAPIC_AUTO -1
1286 #define IOAPIC_EDGE 0
1287 #define IOAPIC_LEVEL 1
1289 #ifdef CONFIG_X86_32
1290 static inline int IO_APIC_irq_trigger(int irq
)
1294 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1295 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1296 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1297 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1298 return irq_trigger(idx
);
1302 * nonexistent IRQs are edge default
1307 static inline int IO_APIC_irq_trigger(int irq
)
1313 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1316 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1317 trigger
== IOAPIC_LEVEL
)
1318 desc
->status
|= IRQ_LEVEL
;
1320 desc
->status
&= ~IRQ_LEVEL
;
1322 if (irq_remapped(irq
)) {
1323 desc
->status
|= IRQ_MOVE_PCNTXT
;
1325 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1329 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1330 handle_edge_irq
, "edge");
1334 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1335 trigger
== IOAPIC_LEVEL
)
1336 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1340 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1341 handle_edge_irq
, "edge");
1344 int setup_ioapic_entry(int apic_id
, int irq
,
1345 struct IO_APIC_route_entry
*entry
,
1346 unsigned int destination
, int trigger
,
1347 int polarity
, int vector
, int pin
)
1350 * add it to the IO-APIC irq-routing table:
1352 memset(entry
,0,sizeof(*entry
));
1354 if (intr_remapping_enabled
) {
1355 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1357 struct IR_IO_APIC_route_entry
*ir_entry
=
1358 (struct IR_IO_APIC_route_entry
*) entry
;
1362 panic("No mapping iommu for ioapic %d\n", apic_id
);
1364 index
= alloc_irte(iommu
, irq
, 1);
1366 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1368 memset(&irte
, 0, sizeof(irte
));
1371 irte
.dst_mode
= apic
->irq_dest_mode
;
1373 * Trigger mode in the IRTE will always be edge, and the
1374 * actual level or edge trigger will be setup in the IO-APIC
1375 * RTE. This will help simplify level triggered irq migration.
1376 * For more details, see the comments above explainig IO-APIC
1377 * irq migration in the presence of interrupt-remapping.
1379 irte
.trigger_mode
= 0;
1380 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
1381 irte
.vector
= vector
;
1382 irte
.dest_id
= IRTE_DEST(destination
);
1384 /* Set source-id of interrupt request */
1385 set_ioapic_sid(&irte
, apic_id
);
1387 modify_irte(irq
, &irte
);
1389 ir_entry
->index2
= (index
>> 15) & 0x1;
1391 ir_entry
->format
= 1;
1392 ir_entry
->index
= (index
& 0x7fff);
1394 * IO-APIC RTE will be configured with virtual vector.
1395 * irq handler will do the explicit EOI to the io-apic.
1397 ir_entry
->vector
= pin
;
1399 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1400 entry
->dest_mode
= apic
->irq_dest_mode
;
1401 entry
->dest
= destination
;
1402 entry
->vector
= vector
;
1405 entry
->mask
= 0; /* enable IRQ */
1406 entry
->trigger
= trigger
;
1407 entry
->polarity
= polarity
;
1409 /* Mask level triggered irqs.
1410 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1417 static void setup_IO_APIC_irq(int apic_id
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1418 int trigger
, int polarity
)
1420 struct irq_cfg
*cfg
;
1421 struct IO_APIC_route_entry entry
;
1424 if (!IO_APIC_IRQ(irq
))
1427 cfg
= desc
->chip_data
;
1429 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1432 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1434 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1435 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1436 "IRQ %d Mode:%i Active:%i)\n",
1437 apic_id
, mp_ioapics
[apic_id
].apicid
, pin
, cfg
->vector
,
1438 irq
, trigger
, polarity
);
1441 if (setup_ioapic_entry(mp_ioapics
[apic_id
].apicid
, irq
, &entry
,
1442 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1443 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1444 mp_ioapics
[apic_id
].apicid
, pin
);
1445 __clear_irq_vector(irq
, cfg
);
1449 ioapic_register_intr(irq
, desc
, trigger
);
1450 if (irq
< NR_IRQS_LEGACY
)
1451 disable_8259A_irq(irq
);
1453 ioapic_write_entry(apic_id
, pin
, entry
);
1457 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
1458 } mp_ioapic_routing
[MAX_IO_APICS
];
1460 static void __init
setup_IO_APIC_irqs(void)
1462 int apic_id
= 0, pin
, idx
, irq
;
1464 struct irq_desc
*desc
;
1465 struct irq_cfg
*cfg
;
1466 int node
= cpu_to_node(boot_cpu_id
);
1468 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1471 if (!acpi_disabled
&& acpi_ioapic
) {
1472 apic_id
= mp_find_ioapic(0);
1478 for (pin
= 0; pin
< nr_ioapic_registers
[apic_id
]; pin
++) {
1479 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1483 apic_printk(APIC_VERBOSE
,
1484 KERN_DEBUG
" %d-%d",
1485 mp_ioapics
[apic_id
].apicid
, pin
);
1487 apic_printk(APIC_VERBOSE
, " %d-%d",
1488 mp_ioapics
[apic_id
].apicid
, pin
);
1492 apic_printk(APIC_VERBOSE
,
1493 " (apicid-pin) not connected\n");
1497 irq
= pin_2_irq(idx
, apic_id
, pin
);
1500 * Skip the timer IRQ if there's a quirk handler
1501 * installed and if it returns 1:
1503 if (apic
->multi_timer_check
&&
1504 apic
->multi_timer_check(apic_id
, irq
))
1507 desc
= irq_to_desc_alloc_node(irq
, node
);
1509 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1512 cfg
= desc
->chip_data
;
1513 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1515 * don't mark it in pin_programmed, so later acpi could
1516 * set it correctly when irq < 16
1518 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1519 irq_trigger(idx
), irq_polarity(idx
));
1523 apic_printk(APIC_VERBOSE
,
1524 " (apicid-pin) not connected\n");
1528 * Set up the timer pin, possibly with the 8259A-master behind.
1530 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1533 struct IO_APIC_route_entry entry
;
1535 if (intr_remapping_enabled
)
1538 memset(&entry
, 0, sizeof(entry
));
1541 * We use logical delivery to get the timer IRQ
1544 entry
.dest_mode
= apic
->irq_dest_mode
;
1545 entry
.mask
= 0; /* don't mask IRQ for edge */
1546 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1547 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1550 entry
.vector
= vector
;
1553 * The timer IRQ doesn't have to know that behind the
1554 * scene we may have a 8259A-master in AEOI mode ...
1556 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1559 * Add it to the IO-APIC irq-routing table:
1561 ioapic_write_entry(apic_id
, pin
, entry
);
1565 __apicdebuginit(void) print_IO_APIC(void)
1568 union IO_APIC_reg_00 reg_00
;
1569 union IO_APIC_reg_01 reg_01
;
1570 union IO_APIC_reg_02 reg_02
;
1571 union IO_APIC_reg_03 reg_03
;
1572 unsigned long flags
;
1573 struct irq_cfg
*cfg
;
1574 struct irq_desc
*desc
;
1577 if (apic_verbosity
== APIC_QUIET
)
1580 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1581 for (i
= 0; i
< nr_ioapics
; i
++)
1582 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1583 mp_ioapics
[i
].apicid
, nr_ioapic_registers
[i
]);
1586 * We are a bit conservative about what we expect. We have to
1587 * know about every hardware change ASAP.
1589 printk(KERN_INFO
"testing the IO APIC.......................\n");
1591 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1593 spin_lock_irqsave(&ioapic_lock
, flags
);
1594 reg_00
.raw
= io_apic_read(apic
, 0);
1595 reg_01
.raw
= io_apic_read(apic
, 1);
1596 if (reg_01
.bits
.version
>= 0x10)
1597 reg_02
.raw
= io_apic_read(apic
, 2);
1598 if (reg_01
.bits
.version
>= 0x20)
1599 reg_03
.raw
= io_apic_read(apic
, 3);
1600 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1603 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].apicid
);
1604 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1605 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1606 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1607 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1609 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1610 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1612 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1613 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1616 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1617 * but the value of reg_02 is read as the previous read register
1618 * value, so ignore it if reg_02 == reg_01.
1620 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1621 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1622 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1626 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1627 * or reg_03, but the value of reg_0[23] is read as the previous read
1628 * register value, so ignore it if reg_03 == reg_0[12].
1630 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1631 reg_03
.raw
!= reg_01
.raw
) {
1632 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1633 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1636 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1638 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1639 " Stat Dmod Deli Vect: \n");
1641 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1642 struct IO_APIC_route_entry entry
;
1644 entry
= ioapic_read_entry(apic
, i
);
1646 printk(KERN_DEBUG
" %02x %03X ",
1651 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1656 entry
.delivery_status
,
1658 entry
.delivery_mode
,
1663 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1664 for_each_irq_desc(irq
, desc
) {
1665 struct irq_pin_list
*entry
;
1667 cfg
= desc
->chip_data
;
1668 entry
= cfg
->irq_2_pin
;
1671 printk(KERN_DEBUG
"IRQ%d ", irq
);
1673 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1676 entry
= entry
->next
;
1681 printk(KERN_INFO
".................................... done.\n");
1686 __apicdebuginit(void) print_APIC_field(int base
)
1690 if (apic_verbosity
== APIC_QUIET
)
1695 for (i
= 0; i
< 8; i
++)
1696 printk(KERN_CONT
"%08x", apic_read(base
+ i
*0x10));
1698 printk(KERN_CONT
"\n");
1701 __apicdebuginit(void) print_local_APIC(void *dummy
)
1703 unsigned int i
, v
, ver
, maxlvt
;
1706 if (apic_verbosity
== APIC_QUIET
)
1709 printk(KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1710 smp_processor_id(), hard_smp_processor_id());
1711 v
= apic_read(APIC_ID
);
1712 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1713 v
= apic_read(APIC_LVR
);
1714 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1715 ver
= GET_APIC_VERSION(v
);
1716 maxlvt
= lapic_get_maxlvt();
1718 v
= apic_read(APIC_TASKPRI
);
1719 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1721 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1722 if (!APIC_XAPIC(ver
)) {
1723 v
= apic_read(APIC_ARBPRI
);
1724 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1725 v
& APIC_ARBPRI_MASK
);
1727 v
= apic_read(APIC_PROCPRI
);
1728 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1732 * Remote read supported only in the 82489DX and local APIC for
1733 * Pentium processors.
1735 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1736 v
= apic_read(APIC_RRR
);
1737 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1740 v
= apic_read(APIC_LDR
);
1741 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1742 if (!x2apic_enabled()) {
1743 v
= apic_read(APIC_DFR
);
1744 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1746 v
= apic_read(APIC_SPIV
);
1747 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1749 printk(KERN_DEBUG
"... APIC ISR field:\n");
1750 print_APIC_field(APIC_ISR
);
1751 printk(KERN_DEBUG
"... APIC TMR field:\n");
1752 print_APIC_field(APIC_TMR
);
1753 printk(KERN_DEBUG
"... APIC IRR field:\n");
1754 print_APIC_field(APIC_IRR
);
1756 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1757 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1758 apic_write(APIC_ESR
, 0);
1760 v
= apic_read(APIC_ESR
);
1761 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1764 icr
= apic_icr_read();
1765 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1766 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1768 v
= apic_read(APIC_LVTT
);
1769 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1771 if (maxlvt
> 3) { /* PC is LVT#4. */
1772 v
= apic_read(APIC_LVTPC
);
1773 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1775 v
= apic_read(APIC_LVT0
);
1776 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1777 v
= apic_read(APIC_LVT1
);
1778 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1780 if (maxlvt
> 2) { /* ERR is LVT#3. */
1781 v
= apic_read(APIC_LVTERR
);
1782 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1785 v
= apic_read(APIC_TMICT
);
1786 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1787 v
= apic_read(APIC_TMCCT
);
1788 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1789 v
= apic_read(APIC_TDCR
);
1790 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1792 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1793 v
= apic_read(APIC_EFEAT
);
1794 maxlvt
= (v
>> 16) & 0xff;
1795 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1796 v
= apic_read(APIC_ECTRL
);
1797 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1798 for (i
= 0; i
< maxlvt
; i
++) {
1799 v
= apic_read(APIC_EILVTn(i
));
1800 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1806 __apicdebuginit(void) print_all_local_APICs(void)
1811 for_each_online_cpu(cpu
)
1812 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1816 __apicdebuginit(void) print_PIC(void)
1819 unsigned long flags
;
1821 if (apic_verbosity
== APIC_QUIET
)
1824 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1826 spin_lock_irqsave(&i8259A_lock
, flags
);
1828 v
= inb(0xa1) << 8 | inb(0x21);
1829 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1831 v
= inb(0xa0) << 8 | inb(0x20);
1832 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1836 v
= inb(0xa0) << 8 | inb(0x20);
1840 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1842 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1844 v
= inb(0x4d1) << 8 | inb(0x4d0);
1845 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1848 __apicdebuginit(int) print_all_ICs(void)
1852 /* don't print out if apic is not there */
1853 if (!cpu_has_apic
|| disable_apic
)
1856 print_all_local_APICs();
1862 fs_initcall(print_all_ICs
);
1865 /* Where if anywhere is the i8259 connect in external int mode */
1866 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1868 void __init
enable_IO_APIC(void)
1870 union IO_APIC_reg_01 reg_01
;
1871 int i8259_apic
, i8259_pin
;
1873 unsigned long flags
;
1876 * The number of IO-APIC IRQ registers (== #pins):
1878 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1879 spin_lock_irqsave(&ioapic_lock
, flags
);
1880 reg_01
.raw
= io_apic_read(apic
, 1);
1881 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1882 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1884 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1886 /* See if any of the pins is in ExtINT mode */
1887 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1888 struct IO_APIC_route_entry entry
;
1889 entry
= ioapic_read_entry(apic
, pin
);
1891 /* If the interrupt line is enabled and in ExtInt mode
1892 * I have found the pin where the i8259 is connected.
1894 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1895 ioapic_i8259
.apic
= apic
;
1896 ioapic_i8259
.pin
= pin
;
1902 /* Look to see what if the MP table has reported the ExtINT */
1903 /* If we could not find the appropriate pin by looking at the ioapic
1904 * the i8259 probably is not connected the ioapic but give the
1905 * mptable a chance anyway.
1907 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1908 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1909 /* Trust the MP table if nothing is setup in the hardware */
1910 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1911 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1912 ioapic_i8259
.pin
= i8259_pin
;
1913 ioapic_i8259
.apic
= i8259_apic
;
1915 /* Complain if the MP table and the hardware disagree */
1916 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1917 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1919 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1923 * Do not trust the IO-APIC being empty at bootup
1929 * Not an __init, needed by the reboot code
1931 void disable_IO_APIC(void)
1934 * Clear the IO-APIC before rebooting:
1939 * If the i8259 is routed through an IOAPIC
1940 * Put that IOAPIC in virtual wire mode
1941 * so legacy interrupts can be delivered.
1943 * With interrupt-remapping, for now we will use virtual wire A mode,
1944 * as virtual wire B is little complex (need to configure both
1945 * IOAPIC RTE aswell as interrupt-remapping table entry).
1946 * As this gets called during crash dump, keep this simple for now.
1948 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
1949 struct IO_APIC_route_entry entry
;
1951 memset(&entry
, 0, sizeof(entry
));
1952 entry
.mask
= 0; /* Enabled */
1953 entry
.trigger
= 0; /* Edge */
1955 entry
.polarity
= 0; /* High */
1956 entry
.delivery_status
= 0;
1957 entry
.dest_mode
= 0; /* Physical */
1958 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1960 entry
.dest
= read_apic_id();
1963 * Add it to the IO-APIC irq-routing table:
1965 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1969 * Use virtual wire A mode when interrupt remapping is enabled.
1972 disconnect_bsp_APIC(!intr_remapping_enabled
&&
1973 ioapic_i8259
.pin
!= -1);
1976 #ifdef CONFIG_X86_32
1978 * function to set the IO-APIC physical IDs based on the
1979 * values stored in the MPC table.
1981 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1984 static void __init
setup_ioapic_ids_from_mpc(void)
1986 union IO_APIC_reg_00 reg_00
;
1987 physid_mask_t phys_id_present_map
;
1990 unsigned char old_id
;
1991 unsigned long flags
;
1993 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
1997 * Don't check I/O APIC IDs for xAPIC systems. They have
1998 * no meaning without the serial APIC bus.
2000 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2001 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2004 * This is broken; anything with a real cpu count has to
2005 * circumvent this idiocy regardless.
2007 phys_id_present_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
2010 * Set the IOAPIC ID to the value stored in the MPC table.
2012 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
2014 /* Read the register 0 value */
2015 spin_lock_irqsave(&ioapic_lock
, flags
);
2016 reg_00
.raw
= io_apic_read(apic_id
, 0);
2017 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2019 old_id
= mp_ioapics
[apic_id
].apicid
;
2021 if (mp_ioapics
[apic_id
].apicid
>= get_physical_broadcast()) {
2022 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2023 apic_id
, mp_ioapics
[apic_id
].apicid
);
2024 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2026 mp_ioapics
[apic_id
].apicid
= reg_00
.bits
.ID
;
2030 * Sanity check, is the ID really free? Every APIC in a
2031 * system must have a unique ID or we get lots of nice
2032 * 'stuck on smp_invalidate_needed IPI wait' messages.
2034 if (apic
->check_apicid_used(phys_id_present_map
,
2035 mp_ioapics
[apic_id
].apicid
)) {
2036 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2037 apic_id
, mp_ioapics
[apic_id
].apicid
);
2038 for (i
= 0; i
< get_physical_broadcast(); i
++)
2039 if (!physid_isset(i
, phys_id_present_map
))
2041 if (i
>= get_physical_broadcast())
2042 panic("Max APIC ID exceeded!\n");
2043 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2045 physid_set(i
, phys_id_present_map
);
2046 mp_ioapics
[apic_id
].apicid
= i
;
2049 tmp
= apic
->apicid_to_cpu_present(mp_ioapics
[apic_id
].apicid
);
2050 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2051 "phys_id_present_map\n",
2052 mp_ioapics
[apic_id
].apicid
);
2053 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2058 * We need to adjust the IRQ routing table
2059 * if the ID changed.
2061 if (old_id
!= mp_ioapics
[apic_id
].apicid
)
2062 for (i
= 0; i
< mp_irq_entries
; i
++)
2063 if (mp_irqs
[i
].dstapic
== old_id
)
2065 = mp_ioapics
[apic_id
].apicid
;
2068 * Read the right value from the MPC table and
2069 * write it into the ID register.
2071 apic_printk(APIC_VERBOSE
, KERN_INFO
2072 "...changing IO-APIC physical APIC ID to %d ...",
2073 mp_ioapics
[apic_id
].apicid
);
2075 reg_00
.bits
.ID
= mp_ioapics
[apic_id
].apicid
;
2076 spin_lock_irqsave(&ioapic_lock
, flags
);
2077 io_apic_write(apic_id
, 0, reg_00
.raw
);
2078 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2083 spin_lock_irqsave(&ioapic_lock
, flags
);
2084 reg_00
.raw
= io_apic_read(apic_id
, 0);
2085 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2086 if (reg_00
.bits
.ID
!= mp_ioapics
[apic_id
].apicid
)
2087 printk("could not set ID!\n");
2089 apic_printk(APIC_VERBOSE
, " ok.\n");
2094 int no_timer_check __initdata
;
2096 static int __init
notimercheck(char *s
)
2101 __setup("no_timer_check", notimercheck
);
2104 * There is a nasty bug in some older SMP boards, their mptable lies
2105 * about the timer IRQ. We do the following to work around the situation:
2107 * - timer IRQ defaults to IO-APIC IRQ
2108 * - if this function detects that timer IRQs are defunct, then we fall
2109 * back to ISA timer IRQs
2111 static int __init
timer_irq_works(void)
2113 unsigned long t1
= jiffies
;
2114 unsigned long flags
;
2119 local_save_flags(flags
);
2121 /* Let ten ticks pass... */
2122 mdelay((10 * 1000) / HZ
);
2123 local_irq_restore(flags
);
2126 * Expect a few ticks at least, to be sure some possible
2127 * glue logic does not lock up after one or two first
2128 * ticks in a non-ExtINT mode. Also the local APIC
2129 * might have cached one ExtINT interrupt. Finally, at
2130 * least one tick may be lost due to delays.
2134 if (time_after(jiffies
, t1
+ 4))
2140 * In the SMP+IOAPIC case it might happen that there are an unspecified
2141 * number of pending IRQ events unhandled. These cases are very rare,
2142 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2143 * better to do it this way as thus we do not have to be aware of
2144 * 'pending' interrupts in the IRQ path, except at this point.
2147 * Edge triggered needs to resend any interrupt
2148 * that was delayed but this is now handled in the device
2153 * Starting up a edge-triggered IO-APIC interrupt is
2154 * nasty - we need to make sure that we get the edge.
2155 * If it is already asserted for some reason, we need
2156 * return 1 to indicate that is was pending.
2158 * This is not complete - we should be able to fake
2159 * an edge even if it isn't on the 8259A...
2162 static unsigned int startup_ioapic_irq(unsigned int irq
)
2164 int was_pending
= 0;
2165 unsigned long flags
;
2166 struct irq_cfg
*cfg
;
2168 spin_lock_irqsave(&ioapic_lock
, flags
);
2169 if (irq
< NR_IRQS_LEGACY
) {
2170 disable_8259A_irq(irq
);
2171 if (i8259A_irq_pending(irq
))
2175 __unmask_IO_APIC_irq(cfg
);
2176 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2181 #ifdef CONFIG_X86_64
2182 static int ioapic_retrigger_irq(unsigned int irq
)
2185 struct irq_cfg
*cfg
= irq_cfg(irq
);
2186 unsigned long flags
;
2188 spin_lock_irqsave(&vector_lock
, flags
);
2189 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2190 spin_unlock_irqrestore(&vector_lock
, flags
);
2195 static int ioapic_retrigger_irq(unsigned int irq
)
2197 apic
->send_IPI_self(irq_cfg(irq
)->vector
);
2204 * Level and edge triggered IO-APIC interrupts need different handling,
2205 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2206 * handled with the level-triggered descriptor, but that one has slightly
2207 * more overhead. Level-triggered interrupts cannot be handled with the
2208 * edge-triggered handler, without risking IRQ storms and other ugly
2213 static void send_cleanup_vector(struct irq_cfg
*cfg
)
2215 cpumask_var_t cleanup_mask
;
2217 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2219 cfg
->move_cleanup_count
= 0;
2220 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2221 cfg
->move_cleanup_count
++;
2222 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2223 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2225 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2226 cfg
->move_cleanup_count
= cpumask_weight(cleanup_mask
);
2227 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2228 free_cpumask_var(cleanup_mask
);
2230 cfg
->move_in_progress
= 0;
2233 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2236 struct irq_pin_list
*entry
;
2237 u8 vector
= cfg
->vector
;
2239 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
2245 * With interrupt-remapping, destination information comes
2246 * from interrupt-remapping table entry.
2248 if (!irq_remapped(irq
))
2249 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2250 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2251 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2253 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2258 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
);
2261 * Either sets desc->affinity to a valid value, and returns
2262 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2263 * leaves desc->affinity untouched.
2266 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
)
2268 struct irq_cfg
*cfg
;
2271 if (!cpumask_intersects(mask
, cpu_online_mask
))
2275 cfg
= desc
->chip_data
;
2276 if (assign_irq_vector(irq
, cfg
, mask
))
2279 cpumask_copy(desc
->affinity
, mask
);
2281 return apic
->cpu_mask_to_apicid_and(desc
->affinity
, cfg
->domain
);
2285 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2287 struct irq_cfg
*cfg
;
2288 unsigned long flags
;
2294 cfg
= desc
->chip_data
;
2296 spin_lock_irqsave(&ioapic_lock
, flags
);
2297 dest
= set_desc_affinity(desc
, mask
);
2298 if (dest
!= BAD_APICID
) {
2299 /* Only the high 8 bits are valid. */
2300 dest
= SET_APIC_LOGICAL_ID(dest
);
2301 __target_IO_APIC_irq(irq
, dest
, cfg
);
2304 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2310 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
2312 struct irq_desc
*desc
;
2314 desc
= irq_to_desc(irq
);
2316 return set_ioapic_affinity_irq_desc(desc
, mask
);
2319 #ifdef CONFIG_INTR_REMAP
2322 * Migrate the IO-APIC irq in the presence of intr-remapping.
2324 * For both level and edge triggered, irq migration is a simple atomic
2325 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2327 * For level triggered, we eliminate the io-apic RTE modification (with the
2328 * updated vector information), by using a virtual vector (io-apic pin number).
2329 * Real vector that is used for interrupting cpu will be coming from
2330 * the interrupt-remapping table entry.
2333 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2335 struct irq_cfg
*cfg
;
2341 if (!cpumask_intersects(mask
, cpu_online_mask
))
2345 if (get_irte(irq
, &irte
))
2348 cfg
= desc
->chip_data
;
2349 if (assign_irq_vector(irq
, cfg
, mask
))
2352 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2354 irte
.vector
= cfg
->vector
;
2355 irte
.dest_id
= IRTE_DEST(dest
);
2358 * Modified the IRTE and flushes the Interrupt entry cache.
2360 modify_irte(irq
, &irte
);
2362 if (cfg
->move_in_progress
)
2363 send_cleanup_vector(cfg
);
2365 cpumask_copy(desc
->affinity
, mask
);
2371 * Migrates the IRQ destination in the process context.
2373 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2374 const struct cpumask
*mask
)
2376 return migrate_ioapic_irq_desc(desc
, mask
);
2378 static int set_ir_ioapic_affinity_irq(unsigned int irq
,
2379 const struct cpumask
*mask
)
2381 struct irq_desc
*desc
= irq_to_desc(irq
);
2383 return set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2386 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2387 const struct cpumask
*mask
)
2393 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2395 unsigned vector
, me
;
2401 me
= smp_processor_id();
2402 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2405 struct irq_desc
*desc
;
2406 struct irq_cfg
*cfg
;
2407 irq
= __get_cpu_var(vector_irq
)[vector
];
2412 desc
= irq_to_desc(irq
);
2417 spin_lock(&desc
->lock
);
2418 if (!cfg
->move_cleanup_count
)
2421 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2424 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2426 * Check if the vector that needs to be cleanedup is
2427 * registered at the cpu's IRR. If so, then this is not
2428 * the best time to clean it up. Lets clean it up in the
2429 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2432 if (irr
& (1 << (vector
% 32))) {
2433 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2436 __get_cpu_var(vector_irq
)[vector
] = -1;
2437 cfg
->move_cleanup_count
--;
2439 spin_unlock(&desc
->lock
);
2445 static void irq_complete_move(struct irq_desc
**descp
)
2447 struct irq_desc
*desc
= *descp
;
2448 struct irq_cfg
*cfg
= desc
->chip_data
;
2449 unsigned vector
, me
;
2451 if (likely(!cfg
->move_in_progress
))
2454 vector
= ~get_irq_regs()->orig_ax
;
2455 me
= smp_processor_id();
2457 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2458 send_cleanup_vector(cfg
);
2461 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2464 static void ack_apic_edge(unsigned int irq
)
2466 struct irq_desc
*desc
= irq_to_desc(irq
);
2468 irq_complete_move(&desc
);
2469 move_native_irq(irq
);
2473 atomic_t irq_mis_count
;
2475 static void ack_apic_level(unsigned int irq
)
2477 struct irq_desc
*desc
= irq_to_desc(irq
);
2480 struct irq_cfg
*cfg
;
2481 int do_unmask_irq
= 0;
2483 irq_complete_move(&desc
);
2484 #ifdef CONFIG_GENERIC_PENDING_IRQ
2485 /* If we are moving the irq we need to mask it */
2486 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2488 mask_IO_APIC_irq_desc(desc
);
2493 * It appears there is an erratum which affects at least version 0x11
2494 * of I/O APIC (that's the 82093AA and cores integrated into various
2495 * chipsets). Under certain conditions a level-triggered interrupt is
2496 * erroneously delivered as edge-triggered one but the respective IRR
2497 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2498 * message but it will never arrive and further interrupts are blocked
2499 * from the source. The exact reason is so far unknown, but the
2500 * phenomenon was observed when two consecutive interrupt requests
2501 * from a given source get delivered to the same CPU and the source is
2502 * temporarily disabled in between.
2504 * A workaround is to simulate an EOI message manually. We achieve it
2505 * by setting the trigger mode to edge and then to level when the edge
2506 * trigger mode gets detected in the TMR of a local APIC for a
2507 * level-triggered interrupt. We mask the source for the time of the
2508 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2509 * The idea is from Manfred Spraul. --macro
2511 cfg
= desc
->chip_data
;
2513 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2516 * We must acknowledge the irq before we move it or the acknowledge will
2517 * not propagate properly.
2521 /* Now we can move and renable the irq */
2522 if (unlikely(do_unmask_irq
)) {
2523 /* Only migrate the irq if the ack has been received.
2525 * On rare occasions the broadcast level triggered ack gets
2526 * delayed going to ioapics, and if we reprogram the
2527 * vector while Remote IRR is still set the irq will never
2530 * To prevent this scenario we read the Remote IRR bit
2531 * of the ioapic. This has two effects.
2532 * - On any sane system the read of the ioapic will
2533 * flush writes (and acks) going to the ioapic from
2535 * - We get to see if the ACK has actually been delivered.
2537 * Based on failed experiments of reprogramming the
2538 * ioapic entry from outside of irq context starting
2539 * with masking the ioapic entry and then polling until
2540 * Remote IRR was clear before reprogramming the
2541 * ioapic I don't trust the Remote IRR bit to be
2542 * completey accurate.
2544 * However there appears to be no other way to plug
2545 * this race, so if the Remote IRR bit is not
2546 * accurate and is causing problems then it is a hardware bug
2547 * and you can go talk to the chipset vendor about it.
2549 cfg
= desc
->chip_data
;
2550 if (!io_apic_level_ack_pending(cfg
))
2551 move_masked_irq(irq
);
2552 unmask_IO_APIC_irq_desc(desc
);
2555 /* Tail end of version 0x11 I/O APIC bug workaround */
2556 if (!(v
& (1 << (i
& 0x1f)))) {
2557 atomic_inc(&irq_mis_count
);
2558 spin_lock(&ioapic_lock
);
2559 __mask_and_edge_IO_APIC_irq(cfg
);
2560 __unmask_and_level_IO_APIC_irq(cfg
);
2561 spin_unlock(&ioapic_lock
);
2565 #ifdef CONFIG_INTR_REMAP
2566 static void __eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2569 struct irq_pin_list
*entry
;
2571 entry
= cfg
->irq_2_pin
;
2579 io_apic_eoi(apic
, pin
);
2580 entry
= entry
->next
;
2585 eoi_ioapic_irq(struct irq_desc
*desc
)
2587 struct irq_cfg
*cfg
;
2588 unsigned long flags
;
2592 cfg
= desc
->chip_data
;
2594 spin_lock_irqsave(&ioapic_lock
, flags
);
2595 __eoi_ioapic_irq(irq
, cfg
);
2596 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2599 static void ir_ack_apic_edge(unsigned int irq
)
2604 static void ir_ack_apic_level(unsigned int irq
)
2606 struct irq_desc
*desc
= irq_to_desc(irq
);
2609 eoi_ioapic_irq(desc
);
2611 #endif /* CONFIG_INTR_REMAP */
2613 static struct irq_chip ioapic_chip __read_mostly
= {
2615 .startup
= startup_ioapic_irq
,
2616 .mask
= mask_IO_APIC_irq
,
2617 .unmask
= unmask_IO_APIC_irq
,
2618 .ack
= ack_apic_edge
,
2619 .eoi
= ack_apic_level
,
2621 .set_affinity
= set_ioapic_affinity_irq
,
2623 .retrigger
= ioapic_retrigger_irq
,
2626 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2627 .name
= "IR-IO-APIC",
2628 .startup
= startup_ioapic_irq
,
2629 .mask
= mask_IO_APIC_irq
,
2630 .unmask
= unmask_IO_APIC_irq
,
2631 #ifdef CONFIG_INTR_REMAP
2632 .ack
= ir_ack_apic_edge
,
2633 .eoi
= ir_ack_apic_level
,
2635 .set_affinity
= set_ir_ioapic_affinity_irq
,
2638 .retrigger
= ioapic_retrigger_irq
,
2641 static inline void init_IO_APIC_traps(void)
2644 struct irq_desc
*desc
;
2645 struct irq_cfg
*cfg
;
2648 * NOTE! The local APIC isn't very good at handling
2649 * multiple interrupts at the same interrupt level.
2650 * As the interrupt level is determined by taking the
2651 * vector number and shifting that right by 4, we
2652 * want to spread these out a bit so that they don't
2653 * all fall in the same interrupt level.
2655 * Also, we've got to be careful not to trash gate
2656 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2658 for_each_irq_desc(irq
, desc
) {
2659 cfg
= desc
->chip_data
;
2660 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2662 * Hmm.. We don't have an entry for this,
2663 * so default to an old-fashioned 8259
2664 * interrupt if we can..
2666 if (irq
< NR_IRQS_LEGACY
)
2667 make_8259A_irq(irq
);
2669 /* Strange. Oh, well.. */
2670 desc
->chip
= &no_irq_chip
;
2676 * The local APIC irq-chip implementation:
2679 static void mask_lapic_irq(unsigned int irq
)
2683 v
= apic_read(APIC_LVT0
);
2684 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2687 static void unmask_lapic_irq(unsigned int irq
)
2691 v
= apic_read(APIC_LVT0
);
2692 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2695 static void ack_lapic_irq(unsigned int irq
)
2700 static struct irq_chip lapic_chip __read_mostly
= {
2701 .name
= "local-APIC",
2702 .mask
= mask_lapic_irq
,
2703 .unmask
= unmask_lapic_irq
,
2704 .ack
= ack_lapic_irq
,
2707 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2709 desc
->status
&= ~IRQ_LEVEL
;
2710 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2714 static void __init
setup_nmi(void)
2717 * Dirty trick to enable the NMI watchdog ...
2718 * We put the 8259A master into AEOI mode and
2719 * unmask on all local APICs LVT0 as NMI.
2721 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2722 * is from Maciej W. Rozycki - so we do not have to EOI from
2723 * the NMI handler or the timer interrupt.
2725 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2727 enable_NMI_through_LVT0();
2729 apic_printk(APIC_VERBOSE
, " done.\n");
2733 * This looks a bit hackish but it's about the only one way of sending
2734 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2735 * not support the ExtINT mode, unfortunately. We need to send these
2736 * cycles as some i82489DX-based boards have glue logic that keeps the
2737 * 8259A interrupt line asserted until INTA. --macro
2739 static inline void __init
unlock_ExtINT_logic(void)
2742 struct IO_APIC_route_entry entry0
, entry1
;
2743 unsigned char save_control
, save_freq_select
;
2745 pin
= find_isa_irq_pin(8, mp_INT
);
2750 apic
= find_isa_irq_apic(8, mp_INT
);
2756 entry0
= ioapic_read_entry(apic
, pin
);
2757 clear_IO_APIC_pin(apic
, pin
);
2759 memset(&entry1
, 0, sizeof(entry1
));
2761 entry1
.dest_mode
= 0; /* physical delivery */
2762 entry1
.mask
= 0; /* unmask IRQ now */
2763 entry1
.dest
= hard_smp_processor_id();
2764 entry1
.delivery_mode
= dest_ExtINT
;
2765 entry1
.polarity
= entry0
.polarity
;
2769 ioapic_write_entry(apic
, pin
, entry1
);
2771 save_control
= CMOS_READ(RTC_CONTROL
);
2772 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2773 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2775 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2780 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2784 CMOS_WRITE(save_control
, RTC_CONTROL
);
2785 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2786 clear_IO_APIC_pin(apic
, pin
);
2788 ioapic_write_entry(apic
, pin
, entry0
);
2791 static int disable_timer_pin_1 __initdata
;
2792 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2793 static int __init
disable_timer_pin_setup(char *arg
)
2795 disable_timer_pin_1
= 1;
2798 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2800 int timer_through_8259 __initdata
;
2803 * This code may look a bit paranoid, but it's supposed to cooperate with
2804 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2805 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2806 * fanatically on his truly buggy board.
2808 * FIXME: really need to revamp this for all platforms.
2810 static inline void __init
check_timer(void)
2812 struct irq_desc
*desc
= irq_to_desc(0);
2813 struct irq_cfg
*cfg
= desc
->chip_data
;
2814 int node
= cpu_to_node(boot_cpu_id
);
2815 int apic1
, pin1
, apic2
, pin2
;
2816 unsigned long flags
;
2819 local_irq_save(flags
);
2822 * get/set the timer IRQ vector:
2824 disable_8259A_irq(0);
2825 assign_irq_vector(0, cfg
, apic
->target_cpus());
2828 * As IRQ0 is to be enabled in the 8259A, the virtual
2829 * wire has to be disabled in the local APIC. Also
2830 * timer interrupts need to be acknowledged manually in
2831 * the 8259A for the i82489DX when using the NMI
2832 * watchdog as that APIC treats NMIs as level-triggered.
2833 * The AEOI mode will finish them in the 8259A
2836 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2838 #ifdef CONFIG_X86_32
2842 ver
= apic_read(APIC_LVR
);
2843 ver
= GET_APIC_VERSION(ver
);
2844 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2848 pin1
= find_isa_irq_pin(0, mp_INT
);
2849 apic1
= find_isa_irq_apic(0, mp_INT
);
2850 pin2
= ioapic_i8259
.pin
;
2851 apic2
= ioapic_i8259
.apic
;
2853 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2854 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2855 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2858 * Some BIOS writers are clueless and report the ExtINTA
2859 * I/O APIC input from the cascaded 8259A as the timer
2860 * interrupt input. So just in case, if only one pin
2861 * was found above, try it both directly and through the
2865 if (intr_remapping_enabled
)
2866 panic("BIOS bug: timer not connected to IO-APIC");
2870 } else if (pin2
== -1) {
2877 * Ok, does IRQ0 through the IOAPIC work?
2880 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2881 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2883 /* for edge trigger, setup_IO_APIC_irq already
2884 * leave it unmasked.
2885 * so only need to unmask if it is level-trigger
2886 * do we really have level trigger timer?
2889 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2890 if (idx
!= -1 && irq_trigger(idx
))
2891 unmask_IO_APIC_irq_desc(desc
);
2893 if (timer_irq_works()) {
2894 if (nmi_watchdog
== NMI_IO_APIC
) {
2896 enable_8259A_irq(0);
2898 if (disable_timer_pin_1
> 0)
2899 clear_IO_APIC_pin(0, pin1
);
2902 if (intr_remapping_enabled
)
2903 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2904 local_irq_disable();
2905 clear_IO_APIC_pin(apic1
, pin1
);
2907 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2908 "8254 timer not connected to IO-APIC\n");
2910 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2911 "(IRQ0) through the 8259A ...\n");
2912 apic_printk(APIC_QUIET
, KERN_INFO
2913 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2915 * legacy devices should be connected to IO APIC #0
2917 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
2918 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2919 enable_8259A_irq(0);
2920 if (timer_irq_works()) {
2921 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2922 timer_through_8259
= 1;
2923 if (nmi_watchdog
== NMI_IO_APIC
) {
2924 disable_8259A_irq(0);
2926 enable_8259A_irq(0);
2931 * Cleanup, just in case ...
2933 local_irq_disable();
2934 disable_8259A_irq(0);
2935 clear_IO_APIC_pin(apic2
, pin2
);
2936 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2939 if (nmi_watchdog
== NMI_IO_APIC
) {
2940 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2941 "through the IO-APIC - disabling NMI Watchdog!\n");
2942 nmi_watchdog
= NMI_NONE
;
2944 #ifdef CONFIG_X86_32
2948 apic_printk(APIC_QUIET
, KERN_INFO
2949 "...trying to set up timer as Virtual Wire IRQ...\n");
2951 lapic_register_intr(0, desc
);
2952 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2953 enable_8259A_irq(0);
2955 if (timer_irq_works()) {
2956 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2959 local_irq_disable();
2960 disable_8259A_irq(0);
2961 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2962 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2964 apic_printk(APIC_QUIET
, KERN_INFO
2965 "...trying to set up timer as ExtINT IRQ...\n");
2969 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2971 unlock_ExtINT_logic();
2973 if (timer_irq_works()) {
2974 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2977 local_irq_disable();
2978 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2979 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2980 "report. Then try booting with the 'noapic' option.\n");
2982 local_irq_restore(flags
);
2986 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2987 * to devices. However there may be an I/O APIC pin available for
2988 * this interrupt regardless. The pin may be left unconnected, but
2989 * typically it will be reused as an ExtINT cascade interrupt for
2990 * the master 8259A. In the MPS case such a pin will normally be
2991 * reported as an ExtINT interrupt in the MP table. With ACPI
2992 * there is no provision for ExtINT interrupts, and in the absence
2993 * of an override it would be treated as an ordinary ISA I/O APIC
2994 * interrupt, that is edge-triggered and unmasked by default. We
2995 * used to do this, but it caused problems on some systems because
2996 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2997 * the same ExtINT cascade interrupt to drive the local APIC of the
2998 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2999 * the I/O APIC in all cases now. No actual device should request
3000 * it anyway. --macro
3002 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3004 void __init
setup_IO_APIC(void)
3008 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3011 io_apic_irqs
= ~PIC_IRQS
;
3013 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3015 * Set up IO-APIC IRQ routing.
3017 #ifdef CONFIG_X86_32
3019 setup_ioapic_ids_from_mpc();
3022 setup_IO_APIC_irqs();
3023 init_IO_APIC_traps();
3028 * Called after all the initialization is done. If we didnt find any
3029 * APIC bugs then we can allow the modify fast path
3032 static int __init
io_apic_bug_finalize(void)
3034 if (sis_apic_bug
== -1)
3039 late_initcall(io_apic_bug_finalize
);
3041 struct sysfs_ioapic_data
{
3042 struct sys_device dev
;
3043 struct IO_APIC_route_entry entry
[0];
3045 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3047 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3049 struct IO_APIC_route_entry
*entry
;
3050 struct sysfs_ioapic_data
*data
;
3053 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3054 entry
= data
->entry
;
3055 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3056 *entry
= ioapic_read_entry(dev
->id
, i
);
3061 static int ioapic_resume(struct sys_device
*dev
)
3063 struct IO_APIC_route_entry
*entry
;
3064 struct sysfs_ioapic_data
*data
;
3065 unsigned long flags
;
3066 union IO_APIC_reg_00 reg_00
;
3069 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3070 entry
= data
->entry
;
3072 spin_lock_irqsave(&ioapic_lock
, flags
);
3073 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3074 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].apicid
) {
3075 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].apicid
;
3076 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3078 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3079 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3080 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3085 static struct sysdev_class ioapic_sysdev_class
= {
3087 .suspend
= ioapic_suspend
,
3088 .resume
= ioapic_resume
,
3091 static int __init
ioapic_init_sysfs(void)
3093 struct sys_device
* dev
;
3096 error
= sysdev_class_register(&ioapic_sysdev_class
);
3100 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3101 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3102 * sizeof(struct IO_APIC_route_entry
);
3103 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3104 if (!mp_ioapic_data
[i
]) {
3105 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3108 dev
= &mp_ioapic_data
[i
]->dev
;
3110 dev
->cls
= &ioapic_sysdev_class
;
3111 error
= sysdev_register(dev
);
3113 kfree(mp_ioapic_data
[i
]);
3114 mp_ioapic_data
[i
] = NULL
;
3115 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3123 device_initcall(ioapic_init_sysfs
);
3125 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
3127 * Dynamic irq allocate and deallocation
3129 unsigned int create_irq_nr(unsigned int irq_want
, int node
)
3131 /* Allocate an unused irq */
3134 unsigned long flags
;
3135 struct irq_cfg
*cfg_new
= NULL
;
3136 struct irq_desc
*desc_new
= NULL
;
3139 if (irq_want
< nr_irqs_gsi
)
3140 irq_want
= nr_irqs_gsi
;
3142 spin_lock_irqsave(&vector_lock
, flags
);
3143 for (new = irq_want
; new < nr_irqs
; new++) {
3144 desc_new
= irq_to_desc_alloc_node(new, node
);
3146 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3149 cfg_new
= desc_new
->chip_data
;
3151 if (cfg_new
->vector
!= 0)
3154 desc_new
= move_irq_desc(desc_new
, node
);
3156 if (__assign_irq_vector(new, cfg_new
, apic
->target_cpus()) == 0)
3160 spin_unlock_irqrestore(&vector_lock
, flags
);
3163 dynamic_irq_init(irq
);
3164 /* restore it, in case dynamic_irq_init clear it */
3166 desc_new
->chip_data
= cfg_new
;
3171 int create_irq(void)
3173 int node
= cpu_to_node(boot_cpu_id
);
3174 unsigned int irq_want
;
3177 irq_want
= nr_irqs_gsi
;
3178 irq
= create_irq_nr(irq_want
, node
);
3186 void destroy_irq(unsigned int irq
)
3188 unsigned long flags
;
3189 struct irq_cfg
*cfg
;
3190 struct irq_desc
*desc
;
3192 /* store it, in case dynamic_irq_cleanup clear it */
3193 desc
= irq_to_desc(irq
);
3194 cfg
= desc
->chip_data
;
3195 dynamic_irq_cleanup(irq
);
3196 /* connect back irq_cfg */
3198 desc
->chip_data
= cfg
;
3201 spin_lock_irqsave(&vector_lock
, flags
);
3202 __clear_irq_vector(irq
, cfg
);
3203 spin_unlock_irqrestore(&vector_lock
, flags
);
3207 * MSI message composition
3209 #ifdef CONFIG_PCI_MSI
3210 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3212 struct irq_cfg
*cfg
;
3220 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3224 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3226 if (irq_remapped(irq
)) {
3231 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3232 BUG_ON(ir_index
== -1);
3234 memset (&irte
, 0, sizeof(irte
));
3237 irte
.dst_mode
= apic
->irq_dest_mode
;
3238 irte
.trigger_mode
= 0; /* edge */
3239 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
3240 irte
.vector
= cfg
->vector
;
3241 irte
.dest_id
= IRTE_DEST(dest
);
3243 /* Set source-id of interrupt request */
3244 set_msi_sid(&irte
, pdev
);
3246 modify_irte(irq
, &irte
);
3248 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3249 msg
->data
= sub_handle
;
3250 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3252 MSI_ADDR_IR_INDEX1(ir_index
) |
3253 MSI_ADDR_IR_INDEX2(ir_index
);
3255 if (x2apic_enabled())
3256 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3257 MSI_ADDR_EXT_DEST_ID(dest
);
3259 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3263 ((apic
->irq_dest_mode
== 0) ?
3264 MSI_ADDR_DEST_MODE_PHYSICAL
:
3265 MSI_ADDR_DEST_MODE_LOGICAL
) |
3266 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3267 MSI_ADDR_REDIRECTION_CPU
:
3268 MSI_ADDR_REDIRECTION_LOWPRI
) |
3269 MSI_ADDR_DEST_ID(dest
);
3272 MSI_DATA_TRIGGER_EDGE
|
3273 MSI_DATA_LEVEL_ASSERT
|
3274 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3275 MSI_DATA_DELIVERY_FIXED
:
3276 MSI_DATA_DELIVERY_LOWPRI
) |
3277 MSI_DATA_VECTOR(cfg
->vector
);
3283 static int set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3285 struct irq_desc
*desc
= irq_to_desc(irq
);
3286 struct irq_cfg
*cfg
;
3290 dest
= set_desc_affinity(desc
, mask
);
3291 if (dest
== BAD_APICID
)
3294 cfg
= desc
->chip_data
;
3296 read_msi_msg_desc(desc
, &msg
);
3298 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3299 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3300 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3301 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3303 write_msi_msg_desc(desc
, &msg
);
3307 #ifdef CONFIG_INTR_REMAP
3309 * Migrate the MSI irq to another cpumask. This migration is
3310 * done in the process context using interrupt-remapping hardware.
3313 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3315 struct irq_desc
*desc
= irq_to_desc(irq
);
3316 struct irq_cfg
*cfg
= desc
->chip_data
;
3320 if (get_irte(irq
, &irte
))
3323 dest
= set_desc_affinity(desc
, mask
);
3324 if (dest
== BAD_APICID
)
3327 irte
.vector
= cfg
->vector
;
3328 irte
.dest_id
= IRTE_DEST(dest
);
3331 * atomically update the IRTE with the new destination and vector.
3333 modify_irte(irq
, &irte
);
3336 * After this point, all the interrupts will start arriving
3337 * at the new destination. So, time to cleanup the previous
3338 * vector allocation.
3340 if (cfg
->move_in_progress
)
3341 send_cleanup_vector(cfg
);
3347 #endif /* CONFIG_SMP */
3350 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3351 * which implement the MSI or MSI-X Capability Structure.
3353 static struct irq_chip msi_chip
= {
3355 .unmask
= unmask_msi_irq
,
3356 .mask
= mask_msi_irq
,
3357 .ack
= ack_apic_edge
,
3359 .set_affinity
= set_msi_irq_affinity
,
3361 .retrigger
= ioapic_retrigger_irq
,
3364 static struct irq_chip msi_ir_chip
= {
3365 .name
= "IR-PCI-MSI",
3366 .unmask
= unmask_msi_irq
,
3367 .mask
= mask_msi_irq
,
3368 #ifdef CONFIG_INTR_REMAP
3369 .ack
= ir_ack_apic_edge
,
3371 .set_affinity
= ir_set_msi_irq_affinity
,
3374 .retrigger
= ioapic_retrigger_irq
,
3378 * Map the PCI dev to the corresponding remapping hardware unit
3379 * and allocate 'nvec' consecutive interrupt-remapping table entries
3382 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3384 struct intel_iommu
*iommu
;
3387 iommu
= map_dev_to_ir(dev
);
3390 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3394 index
= alloc_irte(iommu
, irq
, nvec
);
3397 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3404 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3409 ret
= msi_compose_msg(dev
, irq
, &msg
);
3413 set_irq_msi(irq
, msidesc
);
3414 write_msi_msg(irq
, &msg
);
3416 if (irq_remapped(irq
)) {
3417 struct irq_desc
*desc
= irq_to_desc(irq
);
3419 * irq migration in process context
3421 desc
->status
|= IRQ_MOVE_PCNTXT
;
3422 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3424 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3426 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3431 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3434 int ret
, sub_handle
;
3435 struct msi_desc
*msidesc
;
3436 unsigned int irq_want
;
3437 struct intel_iommu
*iommu
= NULL
;
3441 /* x86 doesn't support multiple MSI yet */
3442 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3445 node
= dev_to_node(&dev
->dev
);
3446 irq_want
= nr_irqs_gsi
;
3448 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3449 irq
= create_irq_nr(irq_want
, node
);
3453 if (!intr_remapping_enabled
)
3458 * allocate the consecutive block of IRTE's
3461 index
= msi_alloc_irte(dev
, irq
, nvec
);
3467 iommu
= map_dev_to_ir(dev
);
3473 * setup the mapping between the irq and the IRTE
3474 * base index, the sub_handle pointing to the
3475 * appropriate interrupt remap table entry.
3477 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3480 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3492 void arch_teardown_msi_irq(unsigned int irq
)
3497 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3499 static int dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3501 struct irq_desc
*desc
= irq_to_desc(irq
);
3502 struct irq_cfg
*cfg
;
3506 dest
= set_desc_affinity(desc
, mask
);
3507 if (dest
== BAD_APICID
)
3510 cfg
= desc
->chip_data
;
3512 dmar_msi_read(irq
, &msg
);
3514 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3515 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3516 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3517 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3519 dmar_msi_write(irq
, &msg
);
3524 #endif /* CONFIG_SMP */
3526 static struct irq_chip dmar_msi_type
= {
3528 .unmask
= dmar_msi_unmask
,
3529 .mask
= dmar_msi_mask
,
3530 .ack
= ack_apic_edge
,
3532 .set_affinity
= dmar_msi_set_affinity
,
3534 .retrigger
= ioapic_retrigger_irq
,
3537 int arch_setup_dmar_msi(unsigned int irq
)
3542 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3545 dmar_msi_write(irq
, &msg
);
3546 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3552 #ifdef CONFIG_HPET_TIMER
3555 static int hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3557 struct irq_desc
*desc
= irq_to_desc(irq
);
3558 struct irq_cfg
*cfg
;
3562 dest
= set_desc_affinity(desc
, mask
);
3563 if (dest
== BAD_APICID
)
3566 cfg
= desc
->chip_data
;
3568 hpet_msi_read(irq
, &msg
);
3570 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3571 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3572 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3573 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3575 hpet_msi_write(irq
, &msg
);
3580 #endif /* CONFIG_SMP */
3582 static struct irq_chip hpet_msi_type
= {
3584 .unmask
= hpet_msi_unmask
,
3585 .mask
= hpet_msi_mask
,
3586 .ack
= ack_apic_edge
,
3588 .set_affinity
= hpet_msi_set_affinity
,
3590 .retrigger
= ioapic_retrigger_irq
,
3593 int arch_setup_hpet_msi(unsigned int irq
)
3597 struct irq_desc
*desc
= irq_to_desc(irq
);
3599 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3603 hpet_msi_write(irq
, &msg
);
3604 desc
->status
|= IRQ_MOVE_PCNTXT
;
3605 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
, handle_edge_irq
,
3612 #endif /* CONFIG_PCI_MSI */
3614 * Hypertransport interrupt support
3616 #ifdef CONFIG_HT_IRQ
3620 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3622 struct ht_irq_msg msg
;
3623 fetch_ht_irq_msg(irq
, &msg
);
3625 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3626 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3628 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3629 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3631 write_ht_irq_msg(irq
, &msg
);
3634 static int set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3636 struct irq_desc
*desc
= irq_to_desc(irq
);
3637 struct irq_cfg
*cfg
;
3640 dest
= set_desc_affinity(desc
, mask
);
3641 if (dest
== BAD_APICID
)
3644 cfg
= desc
->chip_data
;
3646 target_ht_irq(irq
, dest
, cfg
->vector
);
3653 static struct irq_chip ht_irq_chip
= {
3655 .mask
= mask_ht_irq
,
3656 .unmask
= unmask_ht_irq
,
3657 .ack
= ack_apic_edge
,
3659 .set_affinity
= set_ht_irq_affinity
,
3661 .retrigger
= ioapic_retrigger_irq
,
3664 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3666 struct irq_cfg
*cfg
;
3673 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3675 struct ht_irq_msg msg
;
3678 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3679 apic
->target_cpus());
3681 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3685 HT_IRQ_LOW_DEST_ID(dest
) |
3686 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3687 ((apic
->irq_dest_mode
== 0) ?
3688 HT_IRQ_LOW_DM_PHYSICAL
:
3689 HT_IRQ_LOW_DM_LOGICAL
) |
3690 HT_IRQ_LOW_RQEOI_EDGE
|
3691 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3692 HT_IRQ_LOW_MT_FIXED
:
3693 HT_IRQ_LOW_MT_ARBITRATED
) |
3694 HT_IRQ_LOW_IRQ_MASKED
;
3696 write_ht_irq_msg(irq
, &msg
);
3698 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3699 handle_edge_irq
, "edge");
3701 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3705 #endif /* CONFIG_HT_IRQ */
3707 #ifdef CONFIG_X86_UV
3709 * Re-target the irq to the specified CPU and enable the specified MMR located
3710 * on the specified blade to allow the sending of MSIs to the specified CPU.
3712 int arch_enable_uv_irq(char *irq_name
, unsigned int irq
, int cpu
, int mmr_blade
,
3713 unsigned long mmr_offset
)
3715 const struct cpumask
*eligible_cpu
= cpumask_of(cpu
);
3716 struct irq_cfg
*cfg
;
3718 unsigned long mmr_value
;
3719 struct uv_IO_APIC_route_entry
*entry
;
3720 unsigned long flags
;
3723 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3727 err
= assign_irq_vector(irq
, cfg
, eligible_cpu
);
3731 spin_lock_irqsave(&vector_lock
, flags
);
3732 set_irq_chip_and_handler_name(irq
, &uv_irq_chip
, handle_percpu_irq
,
3734 spin_unlock_irqrestore(&vector_lock
, flags
);
3737 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3738 entry
->vector
= cfg
->vector
;
3739 entry
->delivery_mode
= apic
->irq_delivery_mode
;
3740 entry
->dest_mode
= apic
->irq_dest_mode
;
3741 entry
->polarity
= 0;
3744 entry
->dest
= apic
->cpu_mask_to_apicid(eligible_cpu
);
3746 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3747 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3753 * Disable the specified MMR located on the specified blade so that MSIs are
3754 * longer allowed to be sent.
3756 void arch_disable_uv_irq(int mmr_blade
, unsigned long mmr_offset
)
3758 unsigned long mmr_value
;
3759 struct uv_IO_APIC_route_entry
*entry
;
3762 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3765 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3768 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3769 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3771 #endif /* CONFIG_X86_64 */
3773 int __init
io_apic_get_redir_entries (int ioapic
)
3775 union IO_APIC_reg_01 reg_01
;
3776 unsigned long flags
;
3778 spin_lock_irqsave(&ioapic_lock
, flags
);
3779 reg_01
.raw
= io_apic_read(ioapic
, 1);
3780 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3782 return reg_01
.bits
.entries
;
3785 void __init
probe_nr_irqs_gsi(void)
3789 nr
= acpi_probe_gsi();
3790 if (nr
> nr_irqs_gsi
) {
3793 /* for acpi=off or acpi is not compiled in */
3797 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3798 nr
+= io_apic_get_redir_entries(idx
) + 1;
3800 if (nr
> nr_irqs_gsi
)
3804 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3807 #ifdef CONFIG_SPARSE_IRQ
3808 int __init
arch_probe_nr_irqs(void)
3812 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3813 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3815 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3816 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3818 * for MSI and HT dyn irq
3820 nr
+= nr_irqs_gsi
* 16;
3829 static int __io_apic_set_pci_routing(struct device
*dev
, int irq
,
3830 struct io_apic_irq_attr
*irq_attr
)
3832 struct irq_desc
*desc
;
3833 struct irq_cfg
*cfg
;
3836 int trigger
, polarity
;
3838 ioapic
= irq_attr
->ioapic
;
3839 if (!IO_APIC_IRQ(irq
)) {
3840 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3846 node
= dev_to_node(dev
);
3848 node
= cpu_to_node(boot_cpu_id
);
3850 desc
= irq_to_desc_alloc_node(irq
, node
);
3852 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3856 pin
= irq_attr
->ioapic_pin
;
3857 trigger
= irq_attr
->trigger
;
3858 polarity
= irq_attr
->polarity
;
3861 * IRQs < 16 are already in the irq_2_pin[] map
3863 if (irq
>= NR_IRQS_LEGACY
) {
3864 cfg
= desc
->chip_data
;
3865 add_pin_to_irq_node(cfg
, node
, ioapic
, pin
);
3868 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, trigger
, polarity
);
3873 int io_apic_set_pci_routing(struct device
*dev
, int irq
,
3874 struct io_apic_irq_attr
*irq_attr
)
3878 * Avoid pin reprogramming. PRTs typically include entries
3879 * with redundant pin->gsi mappings (but unique PCI devices);
3880 * we only program the IOAPIC on the first.
3882 ioapic
= irq_attr
->ioapic
;
3883 pin
= irq_attr
->ioapic_pin
;
3884 if (test_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
)) {
3885 pr_debug("Pin %d-%d already programmed\n",
3886 mp_ioapics
[ioapic
].apicid
, pin
);
3889 set_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
);
3891 return __io_apic_set_pci_routing(dev
, irq
, irq_attr
);
3894 /* --------------------------------------------------------------------------
3895 ACPI-based IOAPIC Configuration
3896 -------------------------------------------------------------------------- */
3900 #ifdef CONFIG_X86_32
3901 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3903 union IO_APIC_reg_00 reg_00
;
3904 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3906 unsigned long flags
;
3910 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3911 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3912 * supports up to 16 on one shared APIC bus.
3914 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3915 * advantage of new APIC bus architecture.
3918 if (physids_empty(apic_id_map
))
3919 apic_id_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
3921 spin_lock_irqsave(&ioapic_lock
, flags
);
3922 reg_00
.raw
= io_apic_read(ioapic
, 0);
3923 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3925 if (apic_id
>= get_physical_broadcast()) {
3926 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3927 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3928 apic_id
= reg_00
.bits
.ID
;
3932 * Every APIC in a system must have a unique ID or we get lots of nice
3933 * 'stuck on smp_invalidate_needed IPI wait' messages.
3935 if (apic
->check_apicid_used(apic_id_map
, apic_id
)) {
3937 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3938 if (!apic
->check_apicid_used(apic_id_map
, i
))
3942 if (i
== get_physical_broadcast())
3943 panic("Max apic_id exceeded!\n");
3945 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3946 "trying %d\n", ioapic
, apic_id
, i
);
3951 tmp
= apic
->apicid_to_cpu_present(apic_id
);
3952 physids_or(apic_id_map
, apic_id_map
, tmp
);
3954 if (reg_00
.bits
.ID
!= apic_id
) {
3955 reg_00
.bits
.ID
= apic_id
;
3957 spin_lock_irqsave(&ioapic_lock
, flags
);
3958 io_apic_write(ioapic
, 0, reg_00
.raw
);
3959 reg_00
.raw
= io_apic_read(ioapic
, 0);
3960 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3963 if (reg_00
.bits
.ID
!= apic_id
) {
3964 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3969 apic_printk(APIC_VERBOSE
, KERN_INFO
3970 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3976 int __init
io_apic_get_version(int ioapic
)
3978 union IO_APIC_reg_01 reg_01
;
3979 unsigned long flags
;
3981 spin_lock_irqsave(&ioapic_lock
, flags
);
3982 reg_01
.raw
= io_apic_read(ioapic
, 1);
3983 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3985 return reg_01
.bits
.version
;
3988 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
3992 if (skip_ioapic_setup
)
3995 for (i
= 0; i
< mp_irq_entries
; i
++)
3996 if (mp_irqs
[i
].irqtype
== mp_INT
&&
3997 mp_irqs
[i
].srcbusirq
== bus_irq
)
3999 if (i
>= mp_irq_entries
)
4002 *trigger
= irq_trigger(i
);
4003 *polarity
= irq_polarity(i
);
4007 #endif /* CONFIG_ACPI */
4010 * This function currently is only a helper for the i386 smp boot process where
4011 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4012 * so mask in all cases should simply be apic->target_cpus()
4015 void __init
setup_ioapic_dest(void)
4017 int pin
, ioapic
= 0, irq
, irq_entry
;
4018 struct irq_desc
*desc
;
4019 const struct cpumask
*mask
;
4021 if (skip_ioapic_setup
== 1)
4025 if (!acpi_disabled
&& acpi_ioapic
) {
4026 ioapic
= mp_find_ioapic(0);
4032 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4033 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4034 if (irq_entry
== -1)
4036 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4038 desc
= irq_to_desc(irq
);
4041 * Honour affinities which have been set in early boot
4044 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4045 mask
= desc
->affinity
;
4047 mask
= apic
->target_cpus();
4049 if (intr_remapping_enabled
)
4050 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4052 set_ioapic_affinity_irq_desc(desc
, mask
);
4058 #define IOAPIC_RESOURCE_NAME_SIZE 11
4060 static struct resource
*ioapic_resources
;
4062 static struct resource
* __init
ioapic_setup_resources(void)
4065 struct resource
*res
;
4069 if (nr_ioapics
<= 0)
4072 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4075 mem
= alloc_bootmem(n
);
4079 mem
+= sizeof(struct resource
) * nr_ioapics
;
4081 for (i
= 0; i
< nr_ioapics
; i
++) {
4083 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4084 sprintf(mem
, "IOAPIC %u", i
);
4085 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4089 ioapic_resources
= res
;
4094 void __init
ioapic_init_mappings(void)
4096 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4097 struct resource
*ioapic_res
;
4100 ioapic_res
= ioapic_setup_resources();
4101 for (i
= 0; i
< nr_ioapics
; i
++) {
4102 if (smp_found_config
) {
4103 ioapic_phys
= mp_ioapics
[i
].apicaddr
;
4104 #ifdef CONFIG_X86_32
4107 "WARNING: bogus zero IO-APIC "
4108 "address found in MPTABLE, "
4109 "disabling IO/APIC support!\n");
4110 smp_found_config
= 0;
4111 skip_ioapic_setup
= 1;
4112 goto fake_ioapic_page
;
4116 #ifdef CONFIG_X86_32
4119 ioapic_phys
= (unsigned long)
4120 alloc_bootmem_pages(PAGE_SIZE
);
4121 ioapic_phys
= __pa(ioapic_phys
);
4123 set_fixmap_nocache(idx
, ioapic_phys
);
4124 apic_printk(APIC_VERBOSE
,
4125 "mapped IOAPIC to %08lx (%08lx)\n",
4126 __fix_to_virt(idx
), ioapic_phys
);
4129 if (ioapic_res
!= NULL
) {
4130 ioapic_res
->start
= ioapic_phys
;
4131 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
4137 static int __init
ioapic_insert_resources(void)
4140 struct resource
*r
= ioapic_resources
;
4143 if (nr_ioapics
> 0) {
4145 "IO APIC resources couldn't be allocated.\n");
4151 for (i
= 0; i
< nr_ioapics
; i
++) {
4152 insert_resource(&iomem_resource
, r
);
4159 /* Insert the IO APIC resources after PCI initialization has occured to handle
4160 * IO APICS that are mapped in on a BAR in PCI space. */
4161 late_initcall(ioapic_insert_resources
);