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[MIPS] Reduce race between cpu_wait() and need_resched() checking
[linux-2.6/linux-2.6-openrd.git] / arch / mips / kernel / cpu-probe.c
blob9fbf8430c8499972ab80047026c803e64306a253
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/stddef.h>
18
19 #include <asm/cpu.h>
20 #include <asm/fpu.h>
21 #include <asm/mipsregs.h>
22 #include <asm/system.h>
23
24 /*
25 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
26 * the implementation of the "wait" feature differs between CPU families. This
27 * points to the function that implements CPU specific wait.
28 * The wait instruction stops the pipeline and reduces the power consumption of
29 * the CPU very much.
30 */
31 void (*cpu_wait)(void) = NULL;
32
33 static void r3081_wait(void)
34 {
35 unsigned long cfg = read_c0_conf();
36 write_c0_conf(cfg | R30XX_CONF_HALT);
37 }
38
39 static void r39xx_wait(void)
40 {
41 local_irq_disable();
42 if (!need_resched())
43 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
44 local_irq_enable();
45 }
46
47 /*
48 * There is a race when WAIT instruction executed with interrupt
49 * enabled.
50 * But it is implementation-dependent wheter the pipelie restarts when
51 * a non-enabled interrupt is requested.
52 */
53 static void r4k_wait(void)
54 {
55 __asm__(" .set mips3 \n"
56 " wait \n"
57 " .set mips0 \n");
58 }
59
60 /*
61 * This variant is preferable as it allows testing need_resched and going to
62 * sleep depending on the outcome atomically. Unfortunately the "It is
63 * implementation-dependent whether the pipeline restarts when a non-enabled
64 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
65 * using this version a gamble.
66 */
67 static void r4k_wait_irqoff(void)
68 {
69 local_irq_disable();
70 if (!need_resched())
71 __asm__(" .set mips3 \n"
72 " wait \n"
73 " .set mips0 \n");
74 local_irq_enable();
75 }
76
77 /* The Au1xxx wait is available only if using 32khz counter or
78 * external timer source, but specifically not CP0 Counter. */
79 int allow_au1k_wait;
80
81 static void au1k_wait(void)
82 {
83 /* using the wait instruction makes CP0 counter unusable */
84 __asm__(" .set mips3 \n"
85 " cache 0x14, 0(%0) \n"
86 " cache 0x14, 32(%0) \n"
87 " sync \n"
88 " nop \n"
89 " wait \n"
90 " nop \n"
91 " nop \n"
92 " nop \n"
93 " nop \n"
94 " .set mips0 \n"
95 : : "r" (au1k_wait));
96 }
97
98 static int __initdata nowait = 0;
99
100 int __init wait_disable(char *s)
101 {
102 nowait = 1;
103
104 return 1;
105 }
106
107 __setup("nowait", wait_disable);
108
109 static inline void check_wait(void)
110 {
111 struct cpuinfo_mips *c = &current_cpu_data;
112
113 printk("Checking for 'wait' instruction... ");
114 if (nowait) {
115 printk (" disabled.\n");
116 return;
117 }
118
119 switch (c->cputype) {
120 case CPU_R3081:
121 case CPU_R3081E:
122 cpu_wait = r3081_wait;
123 printk(" available.\n");
124 break;
125 case CPU_TX3927:
126 cpu_wait = r39xx_wait;
127 printk(" available.\n");
128 break;
129 case CPU_R4200:
130 /* case CPU_R4300: */
131 case CPU_R4600:
132 case CPU_R4640:
133 case CPU_R4650:
134 case CPU_R4700:
135 case CPU_R5000:
136 case CPU_NEVADA:
137 case CPU_RM7000:
138 case CPU_RM9000:
139 case CPU_4KC:
140 case CPU_4KEC:
141 case CPU_4KSC:
142 case CPU_5KC:
143 /* case CPU_20KC:*/
144 case CPU_24K:
145 case CPU_25KF:
146 case CPU_34K:
147 case CPU_74K:
148 case CPU_PR4450:
149 cpu_wait = r4k_wait;
150 printk(" available.\n");
151 break;
152 case CPU_TX49XX:
153 cpu_wait = r4k_wait_irqoff;
154 printk(" available.\n");
155 break;
156 case CPU_AU1000:
157 case CPU_AU1100:
158 case CPU_AU1500:
159 case CPU_AU1550:
160 case CPU_AU1200:
161 if (allow_au1k_wait) {
162 cpu_wait = au1k_wait;
163 printk(" available.\n");
164 } else
165 printk(" unavailable.\n");
166 break;
167 default:
168 printk(" unavailable.\n");
169 break;
170 }
171 }
172
173 void __init check_bugs32(void)
174 {
175 check_wait();
176 }
177
178 /*
179 * Probe whether cpu has config register by trying to play with
180 * alternate cache bit and see whether it matters.
181 * It's used by cpu_probe to distinguish between R3000A and R3081.
182 */
183 static inline int cpu_has_confreg(void)
184 {
185 #ifdef CONFIG_CPU_R3000
186 extern unsigned long r3k_cache_size(unsigned long);
187 unsigned long size1, size2;
188 unsigned long cfg = read_c0_conf();
189
190 size1 = r3k_cache_size(ST0_ISC);
191 write_c0_conf(cfg ^ R30XX_CONF_AC);
192 size2 = r3k_cache_size(ST0_ISC);
193 write_c0_conf(cfg);
194 return size1 != size2;
195 #else
196 return 0;
197 #endif
198 }
199
200 /*
201 * Get the FPU Implementation/Revision.
202 */
203 static inline unsigned long cpu_get_fpu_id(void)
204 {
205 unsigned long tmp, fpu_id;
206
207 tmp = read_c0_status();
208 __enable_fpu();
209 fpu_id = read_32bit_cp1_register(CP1_REVISION);
210 write_c0_status(tmp);
211 return fpu_id;
212 }
213
214 /*
215 * Check the CPU has an FPU the official way.
216 */
217 static inline int __cpu_has_fpu(void)
218 {
219 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
220 }
221
222 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
223 | MIPS_CPU_COUNTER)
224
225 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
226 {
227 switch (c->processor_id & 0xff00) {
228 case PRID_IMP_R2000:
229 c->cputype = CPU_R2000;
230 c->isa_level = MIPS_CPU_ISA_I;
231 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
232 MIPS_CPU_NOFPUEX;
233 if (__cpu_has_fpu())
234 c->options |= MIPS_CPU_FPU;
235 c->tlbsize = 64;
236 break;
237 case PRID_IMP_R3000:
238 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
239 if (cpu_has_confreg())
240 c->cputype = CPU_R3081E;
241 else
242 c->cputype = CPU_R3000A;
243 else
244 c->cputype = CPU_R3000;
245 c->isa_level = MIPS_CPU_ISA_I;
246 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
247 MIPS_CPU_NOFPUEX;
248 if (__cpu_has_fpu())
249 c->options |= MIPS_CPU_FPU;
250 c->tlbsize = 64;
251 break;
252 case PRID_IMP_R4000:
253 if (read_c0_config() & CONF_SC) {
254 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
255 c->cputype = CPU_R4400PC;
256 else
257 c->cputype = CPU_R4000PC;
258 } else {
259 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
260 c->cputype = CPU_R4400SC;
261 else
262 c->cputype = CPU_R4000SC;
263 }
264
265 c->isa_level = MIPS_CPU_ISA_III;
266 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
267 MIPS_CPU_WATCH | MIPS_CPU_VCE |
268 MIPS_CPU_LLSC;
269 c->tlbsize = 48;
270 break;
271 case PRID_IMP_VR41XX:
272 switch (c->processor_id & 0xf0) {
273 case PRID_REV_VR4111:
274 c->cputype = CPU_VR4111;
275 break;
276 case PRID_REV_VR4121:
277 c->cputype = CPU_VR4121;
278 break;
279 case PRID_REV_VR4122:
280 if ((c->processor_id & 0xf) < 0x3)
281 c->cputype = CPU_VR4122;
282 else
283 c->cputype = CPU_VR4181A;
284 break;
285 case PRID_REV_VR4130:
286 if ((c->processor_id & 0xf) < 0x4)
287 c->cputype = CPU_VR4131;
288 else
289 c->cputype = CPU_VR4133;
290 break;
291 default:
292 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
293 c->cputype = CPU_VR41XX;
294 break;
295 }
296 c->isa_level = MIPS_CPU_ISA_III;
297 c->options = R4K_OPTS;
298 c->tlbsize = 32;
299 break;
300 case PRID_IMP_R4300:
301 c->cputype = CPU_R4300;
302 c->isa_level = MIPS_CPU_ISA_III;
303 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
304 MIPS_CPU_LLSC;
305 c->tlbsize = 32;
306 break;
307 case PRID_IMP_R4600:
308 c->cputype = CPU_R4600;
309 c->isa_level = MIPS_CPU_ISA_III;
310 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
311 MIPS_CPU_LLSC;
312 c->tlbsize = 48;
313 break;
314 #if 0
315 case PRID_IMP_R4650:
316 /*
317 * This processor doesn't have an MMU, so it's not
318 * "real easy" to run Linux on it. It is left purely
319 * for documentation. Commented out because it shares
320 * it's c0_prid id number with the TX3900.
321 */
322 c->cputype = CPU_R4650;
323 c->isa_level = MIPS_CPU_ISA_III;
324 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
325 c->tlbsize = 48;
326 break;
327 #endif
328 case PRID_IMP_TX39:
329 c->isa_level = MIPS_CPU_ISA_I;
330 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
331
332 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
333 c->cputype = CPU_TX3927;
334 c->tlbsize = 64;
335 } else {
336 switch (c->processor_id & 0xff) {
337 case PRID_REV_TX3912:
338 c->cputype = CPU_TX3912;
339 c->tlbsize = 32;
340 break;
341 case PRID_REV_TX3922:
342 c->cputype = CPU_TX3922;
343 c->tlbsize = 64;
344 break;
345 default:
346 c->cputype = CPU_UNKNOWN;
347 break;
348 }
349 }
350 break;
351 case PRID_IMP_R4700:
352 c->cputype = CPU_R4700;
353 c->isa_level = MIPS_CPU_ISA_III;
354 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
355 MIPS_CPU_LLSC;
356 c->tlbsize = 48;
357 break;
358 case PRID_IMP_TX49:
359 c->cputype = CPU_TX49XX;
360 c->isa_level = MIPS_CPU_ISA_III;
361 c->options = R4K_OPTS | MIPS_CPU_LLSC;
362 if (!(c->processor_id & 0x08))
363 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
364 c->tlbsize = 48;
365 break;
366 case PRID_IMP_R5000:
367 c->cputype = CPU_R5000;
368 c->isa_level = MIPS_CPU_ISA_IV;
369 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
370 MIPS_CPU_LLSC;
371 c->tlbsize = 48;
372 break;
373 case PRID_IMP_R5432:
374 c->cputype = CPU_R5432;
375 c->isa_level = MIPS_CPU_ISA_IV;
376 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
377 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
378 c->tlbsize = 48;
379 break;
380 case PRID_IMP_R5500:
381 c->cputype = CPU_R5500;
382 c->isa_level = MIPS_CPU_ISA_IV;
383 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
384 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
385 c->tlbsize = 48;
386 break;
387 case PRID_IMP_NEVADA:
388 c->cputype = CPU_NEVADA;
389 c->isa_level = MIPS_CPU_ISA_IV;
390 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
391 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
392 c->tlbsize = 48;
393 break;
394 case PRID_IMP_R6000:
395 c->cputype = CPU_R6000;
396 c->isa_level = MIPS_CPU_ISA_II;
397 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
398 MIPS_CPU_LLSC;
399 c->tlbsize = 32;
400 break;
401 case PRID_IMP_R6000A:
402 c->cputype = CPU_R6000A;
403 c->isa_level = MIPS_CPU_ISA_II;
404 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
405 MIPS_CPU_LLSC;
406 c->tlbsize = 32;
407 break;
408 case PRID_IMP_RM7000:
409 c->cputype = CPU_RM7000;
410 c->isa_level = MIPS_CPU_ISA_IV;
411 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
412 MIPS_CPU_LLSC;
413 /*
414 * Undocumented RM7000: Bit 29 in the info register of
415 * the RM7000 v2.0 indicates if the TLB has 48 or 64
416 * entries.
417 *
418 * 29 1 => 64 entry JTLB
419 * 0 => 48 entry JTLB
420 */
421 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
422 break;
423 case PRID_IMP_RM9000:
424 c->cputype = CPU_RM9000;
425 c->isa_level = MIPS_CPU_ISA_IV;
426 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
427 MIPS_CPU_LLSC;
428 /*
429 * Bit 29 in the info register of the RM9000
430 * indicates if the TLB has 48 or 64 entries.
431 *
432 * 29 1 => 64 entry JTLB
433 * 0 => 48 entry JTLB
434 */
435 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
436 break;
437 case PRID_IMP_R8000:
438 c->cputype = CPU_R8000;
439 c->isa_level = MIPS_CPU_ISA_IV;
440 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
441 MIPS_CPU_FPU | MIPS_CPU_32FPR |
442 MIPS_CPU_LLSC;
443 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
444 break;
445 case PRID_IMP_R10000:
446 c->cputype = CPU_R10000;
447 c->isa_level = MIPS_CPU_ISA_IV;
448 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
449 MIPS_CPU_FPU | MIPS_CPU_32FPR |
450 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
451 MIPS_CPU_LLSC;
452 c->tlbsize = 64;
453 break;
454 case PRID_IMP_R12000:
455 c->cputype = CPU_R12000;
456 c->isa_level = MIPS_CPU_ISA_IV;
457 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
458 MIPS_CPU_FPU | MIPS_CPU_32FPR |
459 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
460 MIPS_CPU_LLSC;
461 c->tlbsize = 64;
462 break;
463 case PRID_IMP_R14000:
464 c->cputype = CPU_R14000;
465 c->isa_level = MIPS_CPU_ISA_IV;
466 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
467 MIPS_CPU_FPU | MIPS_CPU_32FPR |
468 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
469 MIPS_CPU_LLSC;
470 c->tlbsize = 64;
471 break;
472 }
473 }
474
475 static char unknown_isa[] __initdata = KERN_ERR \
476 "Unsupported ISA type, c0.config0: %d.";
477
478 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
479 {
480 unsigned int config0;
481 int isa;
482
483 config0 = read_c0_config();
484
485 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
486 c->options |= MIPS_CPU_TLB;
487 isa = (config0 & MIPS_CONF_AT) >> 13;
488 switch (isa) {
489 case 0:
490 switch ((config0 & MIPS_CONF_AR) >> 10) {
491 case 0:
492 c->isa_level = MIPS_CPU_ISA_M32R1;
493 break;
494 case 1:
495 c->isa_level = MIPS_CPU_ISA_M32R2;
496 break;
497 default:
498 goto unknown;
499 }
500 break;
501 case 2:
502 switch ((config0 & MIPS_CONF_AR) >> 10) {
503 case 0:
504 c->isa_level = MIPS_CPU_ISA_M64R1;
505 break;
506 case 1:
507 c->isa_level = MIPS_CPU_ISA_M64R2;
508 break;
509 default:
510 goto unknown;
511 }
512 break;
513 default:
514 goto unknown;
515 }
516
517 return config0 & MIPS_CONF_M;
518
519 unknown:
520 panic(unknown_isa, config0);
521 }
522
523 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
524 {
525 unsigned int config1;
526
527 config1 = read_c0_config1();
528
529 if (config1 & MIPS_CONF1_MD)
530 c->ases |= MIPS_ASE_MDMX;
531 if (config1 & MIPS_CONF1_WR)
532 c->options |= MIPS_CPU_WATCH;
533 if (config1 & MIPS_CONF1_CA)
534 c->ases |= MIPS_ASE_MIPS16;
535 if (config1 & MIPS_CONF1_EP)
536 c->options |= MIPS_CPU_EJTAG;
537 if (config1 & MIPS_CONF1_FP) {
538 c->options |= MIPS_CPU_FPU;
539 c->options |= MIPS_CPU_32FPR;
540 }
541 if (cpu_has_tlb)
542 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
543
544 return config1 & MIPS_CONF_M;
545 }
546
547 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
548 {
549 unsigned int config2;
550
551 config2 = read_c0_config2();
552
553 if (config2 & MIPS_CONF2_SL)
554 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
555
556 return config2 & MIPS_CONF_M;
557 }
558
559 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
560 {
561 unsigned int config3;
562
563 config3 = read_c0_config3();
564
565 if (config3 & MIPS_CONF3_SM)
566 c->ases |= MIPS_ASE_SMARTMIPS;
567 if (config3 & MIPS_CONF3_DSP)
568 c->ases |= MIPS_ASE_DSP;
569 if (config3 & MIPS_CONF3_VINT)
570 c->options |= MIPS_CPU_VINT;
571 if (config3 & MIPS_CONF3_VEIC)
572 c->options |= MIPS_CPU_VEIC;
573 if (config3 & MIPS_CONF3_MT)
574 c->ases |= MIPS_ASE_MIPSMT;
575
576 return config3 & MIPS_CONF_M;
577 }
578
579 static void __init decode_configs(struct cpuinfo_mips *c)
580 {
581 /* MIPS32 or MIPS64 compliant CPU. */
582 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
583 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
584
585 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
586
587 /* Read Config registers. */
588 if (!decode_config0(c))
589 return; /* actually worth a panic() */
590 if (!decode_config1(c))
591 return;
592 if (!decode_config2(c))
593 return;
594 if (!decode_config3(c))
595 return;
596 }
597
598 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
599 {
600 decode_configs(c);
601 switch (c->processor_id & 0xff00) {
602 case PRID_IMP_4KC:
603 c->cputype = CPU_4KC;
604 break;
605 case PRID_IMP_4KEC:
606 c->cputype = CPU_4KEC;
607 break;
608 case PRID_IMP_4KECR2:
609 c->cputype = CPU_4KEC;
610 break;
611 case PRID_IMP_4KSC:
612 case PRID_IMP_4KSD:
613 c->cputype = CPU_4KSC;
614 break;
615 case PRID_IMP_5KC:
616 c->cputype = CPU_5KC;
617 break;
618 case PRID_IMP_20KC:
619 c->cputype = CPU_20KC;
620 break;
621 case PRID_IMP_24K:
622 case PRID_IMP_24KE:
623 c->cputype = CPU_24K;
624 break;
625 case PRID_IMP_25KF:
626 c->cputype = CPU_25KF;
627 break;
628 case PRID_IMP_34K:
629 c->cputype = CPU_34K;
630 break;
631 case PRID_IMP_74K:
632 c->cputype = CPU_74K;
633 break;
634 }
635 }
636
637 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
638 {
639 decode_configs(c);
640 switch (c->processor_id & 0xff00) {
641 case PRID_IMP_AU1_REV1:
642 case PRID_IMP_AU1_REV2:
643 switch ((c->processor_id >> 24) & 0xff) {
644 case 0:
645 c->cputype = CPU_AU1000;
646 break;
647 case 1:
648 c->cputype = CPU_AU1500;
649 break;
650 case 2:
651 c->cputype = CPU_AU1100;
652 break;
653 case 3:
654 c->cputype = CPU_AU1550;
655 break;
656 case 4:
657 c->cputype = CPU_AU1200;
658 break;
659 default:
660 panic("Unknown Au Core!");
661 break;
662 }
663 break;
664 }
665 }
666
667 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
668 {
669 decode_configs(c);
670
671 /*
672 * For historical reasons the SB1 comes with it's own variant of
673 * cache code which eventually will be folded into c-r4k.c. Until
674 * then we pretend it's got it's own cache architecture.
675 */
676 c->options &= ~MIPS_CPU_4K_CACHE;
677 c->options |= MIPS_CPU_SB1_CACHE;
678
679 switch (c->processor_id & 0xff00) {
680 case PRID_IMP_SB1:
681 c->cputype = CPU_SB1;
682 /* FPU in pass1 is known to have issues. */
683 if ((c->processor_id & 0xff) < 0x02)
684 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
685 break;
686 case PRID_IMP_SB1A:
687 c->cputype = CPU_SB1A;
688 break;
689 }
690 }
691
692 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
693 {
694 decode_configs(c);
695 switch (c->processor_id & 0xff00) {
696 case PRID_IMP_SR71000:
697 c->cputype = CPU_SR71000;
698 c->scache.ways = 8;
699 c->tlbsize = 64;
700 break;
701 }
702 }
703
704 static inline void cpu_probe_philips(struct cpuinfo_mips *c)
705 {
706 decode_configs(c);
707 switch (c->processor_id & 0xff00) {
708 case PRID_IMP_PR4450:
709 c->cputype = CPU_PR4450;
710 c->isa_level = MIPS_CPU_ISA_M32R1;
711 break;
712 default:
713 panic("Unknown Philips Core!"); /* REVISIT: die? */
714 break;
715 }
716 }
717
718
719 __init void cpu_probe(void)
720 {
721 struct cpuinfo_mips *c = &current_cpu_data;
722
723 c->processor_id = PRID_IMP_UNKNOWN;
724 c->fpu_id = FPIR_IMP_NONE;
725 c->cputype = CPU_UNKNOWN;
726
727 c->processor_id = read_c0_prid();
728 switch (c->processor_id & 0xff0000) {
729 case PRID_COMP_LEGACY:
730 cpu_probe_legacy(c);
731 break;
732 case PRID_COMP_MIPS:
733 cpu_probe_mips(c);
734 break;
735 case PRID_COMP_ALCHEMY:
736 cpu_probe_alchemy(c);
737 break;
738 case PRID_COMP_SIBYTE:
739 cpu_probe_sibyte(c);
740 break;
741 case PRID_COMP_SANDCRAFT:
742 cpu_probe_sandcraft(c);
743 break;
744 case PRID_COMP_PHILIPS:
745 cpu_probe_philips(c);
746 break;
747 default:
748 c->cputype = CPU_UNKNOWN;
749 }
750 if (c->options & MIPS_CPU_FPU) {
751 c->fpu_id = cpu_get_fpu_id();
752
753 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
754 c->isa_level == MIPS_CPU_ISA_M32R2 ||
755 c->isa_level == MIPS_CPU_ISA_M64R1 ||
756 c->isa_level == MIPS_CPU_ISA_M64R2) {
757 if (c->fpu_id & MIPS_FPIR_3D)
758 c->ases |= MIPS_ASE_MIPS3D;
759 }
760 }
761 }
762
763 __init void cpu_report(void)
764 {
765 struct cpuinfo_mips *c = &current_cpu_data;
766
767 printk("CPU revision is: %08x\n", c->processor_id);
768 if (c->options & MIPS_CPU_FPU)
769 printk("FPU revision is: %08x\n", c->fpu_id);
770 }
linux 2.6 git repository for openrd