2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/stddef.h>
21 #include <asm/mipsregs.h>
22 #include <asm/system.h>
25 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
26 * the implementation of the "wait" feature differs between CPU families. This
27 * points to the function that implements CPU specific wait.
28 * The wait instruction stops the pipeline and reduces the power consumption of
31 void (*cpu_wait
)(void) = NULL
;
33 static void r3081_wait(void)
35 unsigned long cfg
= read_c0_conf();
36 write_c0_conf(cfg
| R30XX_CONF_HALT
);
39 static void r39xx_wait(void)
43 write_c0_conf(read_c0_conf() | TX39_CONF_HALT
);
48 * There is a race when WAIT instruction executed with interrupt
50 * But it is implementation-dependent wheter the pipelie restarts when
51 * a non-enabled interrupt is requested.
53 static void r4k_wait(void)
55 __asm__(" .set mips3 \n"
61 * This variant is preferable as it allows testing need_resched and going to
62 * sleep depending on the outcome atomically. Unfortunately the "It is
63 * implementation-dependent whether the pipeline restarts when a non-enabled
64 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
65 * using this version a gamble.
67 static void r4k_wait_irqoff(void)
71 __asm__(" .set mips3 \n"
77 /* The Au1xxx wait is available only if using 32khz counter or
78 * external timer source, but specifically not CP0 Counter. */
81 static void au1k_wait(void)
83 /* using the wait instruction makes CP0 counter unusable */
84 __asm__(" .set mips3 \n"
85 " cache 0x14, 0(%0) \n"
86 " cache 0x14, 32(%0) \n"
98 static int __initdata nowait
= 0;
100 int __init
wait_disable(char *s
)
107 __setup("nowait", wait_disable
);
109 static inline void check_wait(void)
111 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
113 printk("Checking for 'wait' instruction... ");
115 printk (" disabled.\n");
119 switch (c
->cputype
) {
122 cpu_wait
= r3081_wait
;
123 printk(" available.\n");
126 cpu_wait
= r39xx_wait
;
127 printk(" available.\n");
130 /* case CPU_R4300: */
150 printk(" available.\n");
153 cpu_wait
= r4k_wait_irqoff
;
154 printk(" available.\n");
161 if (allow_au1k_wait
) {
162 cpu_wait
= au1k_wait
;
163 printk(" available.\n");
165 printk(" unavailable.\n");
168 printk(" unavailable.\n");
173 void __init
check_bugs32(void)
179 * Probe whether cpu has config register by trying to play with
180 * alternate cache bit and see whether it matters.
181 * It's used by cpu_probe to distinguish between R3000A and R3081.
183 static inline int cpu_has_confreg(void)
185 #ifdef CONFIG_CPU_R3000
186 extern unsigned long r3k_cache_size(unsigned long);
187 unsigned long size1
, size2
;
188 unsigned long cfg
= read_c0_conf();
190 size1
= r3k_cache_size(ST0_ISC
);
191 write_c0_conf(cfg
^ R30XX_CONF_AC
);
192 size2
= r3k_cache_size(ST0_ISC
);
194 return size1
!= size2
;
201 * Get the FPU Implementation/Revision.
203 static inline unsigned long cpu_get_fpu_id(void)
205 unsigned long tmp
, fpu_id
;
207 tmp
= read_c0_status();
209 fpu_id
= read_32bit_cp1_register(CP1_REVISION
);
210 write_c0_status(tmp
);
215 * Check the CPU has an FPU the official way.
217 static inline int __cpu_has_fpu(void)
219 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE
);
222 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
225 static inline void cpu_probe_legacy(struct cpuinfo_mips
*c
)
227 switch (c
->processor_id
& 0xff00) {
229 c
->cputype
= CPU_R2000
;
230 c
->isa_level
= MIPS_CPU_ISA_I
;
231 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
234 c
->options
|= MIPS_CPU_FPU
;
238 if ((c
->processor_id
& 0xff) == PRID_REV_R3000A
)
239 if (cpu_has_confreg())
240 c
->cputype
= CPU_R3081E
;
242 c
->cputype
= CPU_R3000A
;
244 c
->cputype
= CPU_R3000
;
245 c
->isa_level
= MIPS_CPU_ISA_I
;
246 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
249 c
->options
|= MIPS_CPU_FPU
;
253 if (read_c0_config() & CONF_SC
) {
254 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
)
255 c
->cputype
= CPU_R4400PC
;
257 c
->cputype
= CPU_R4000PC
;
259 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
)
260 c
->cputype
= CPU_R4400SC
;
262 c
->cputype
= CPU_R4000SC
;
265 c
->isa_level
= MIPS_CPU_ISA_III
;
266 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
267 MIPS_CPU_WATCH
| MIPS_CPU_VCE
|
271 case PRID_IMP_VR41XX
:
272 switch (c
->processor_id
& 0xf0) {
273 case PRID_REV_VR4111
:
274 c
->cputype
= CPU_VR4111
;
276 case PRID_REV_VR4121
:
277 c
->cputype
= CPU_VR4121
;
279 case PRID_REV_VR4122
:
280 if ((c
->processor_id
& 0xf) < 0x3)
281 c
->cputype
= CPU_VR4122
;
283 c
->cputype
= CPU_VR4181A
;
285 case PRID_REV_VR4130
:
286 if ((c
->processor_id
& 0xf) < 0x4)
287 c
->cputype
= CPU_VR4131
;
289 c
->cputype
= CPU_VR4133
;
292 printk(KERN_INFO
"Unexpected CPU of NEC VR4100 series\n");
293 c
->cputype
= CPU_VR41XX
;
296 c
->isa_level
= MIPS_CPU_ISA_III
;
297 c
->options
= R4K_OPTS
;
301 c
->cputype
= CPU_R4300
;
302 c
->isa_level
= MIPS_CPU_ISA_III
;
303 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
308 c
->cputype
= CPU_R4600
;
309 c
->isa_level
= MIPS_CPU_ISA_III
;
310 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
317 * This processor doesn't have an MMU, so it's not
318 * "real easy" to run Linux on it. It is left purely
319 * for documentation. Commented out because it shares
320 * it's c0_prid id number with the TX3900.
322 c
->cputype
= CPU_R4650
;
323 c
->isa_level
= MIPS_CPU_ISA_III
;
324 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
329 c
->isa_level
= MIPS_CPU_ISA_I
;
330 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_TX39_CACHE
;
332 if ((c
->processor_id
& 0xf0) == (PRID_REV_TX3927
& 0xf0)) {
333 c
->cputype
= CPU_TX3927
;
336 switch (c
->processor_id
& 0xff) {
337 case PRID_REV_TX3912
:
338 c
->cputype
= CPU_TX3912
;
341 case PRID_REV_TX3922
:
342 c
->cputype
= CPU_TX3922
;
346 c
->cputype
= CPU_UNKNOWN
;
352 c
->cputype
= CPU_R4700
;
353 c
->isa_level
= MIPS_CPU_ISA_III
;
354 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
359 c
->cputype
= CPU_TX49XX
;
360 c
->isa_level
= MIPS_CPU_ISA_III
;
361 c
->options
= R4K_OPTS
| MIPS_CPU_LLSC
;
362 if (!(c
->processor_id
& 0x08))
363 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
367 c
->cputype
= CPU_R5000
;
368 c
->isa_level
= MIPS_CPU_ISA_IV
;
369 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
374 c
->cputype
= CPU_R5432
;
375 c
->isa_level
= MIPS_CPU_ISA_IV
;
376 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
377 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
381 c
->cputype
= CPU_R5500
;
382 c
->isa_level
= MIPS_CPU_ISA_IV
;
383 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
384 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
387 case PRID_IMP_NEVADA
:
388 c
->cputype
= CPU_NEVADA
;
389 c
->isa_level
= MIPS_CPU_ISA_IV
;
390 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
391 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
;
395 c
->cputype
= CPU_R6000
;
396 c
->isa_level
= MIPS_CPU_ISA_II
;
397 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
401 case PRID_IMP_R6000A
:
402 c
->cputype
= CPU_R6000A
;
403 c
->isa_level
= MIPS_CPU_ISA_II
;
404 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
408 case PRID_IMP_RM7000
:
409 c
->cputype
= CPU_RM7000
;
410 c
->isa_level
= MIPS_CPU_ISA_IV
;
411 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
414 * Undocumented RM7000: Bit 29 in the info register of
415 * the RM7000 v2.0 indicates if the TLB has 48 or 64
418 * 29 1 => 64 entry JTLB
421 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
423 case PRID_IMP_RM9000
:
424 c
->cputype
= CPU_RM9000
;
425 c
->isa_level
= MIPS_CPU_ISA_IV
;
426 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
429 * Bit 29 in the info register of the RM9000
430 * indicates if the TLB has 48 or 64 entries.
432 * 29 1 => 64 entry JTLB
435 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
438 c
->cputype
= CPU_R8000
;
439 c
->isa_level
= MIPS_CPU_ISA_IV
;
440 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
441 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
443 c
->tlbsize
= 384; /* has weird TLB: 3-way x 128 */
445 case PRID_IMP_R10000
:
446 c
->cputype
= CPU_R10000
;
447 c
->isa_level
= MIPS_CPU_ISA_IV
;
448 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
449 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
450 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
454 case PRID_IMP_R12000
:
455 c
->cputype
= CPU_R12000
;
456 c
->isa_level
= MIPS_CPU_ISA_IV
;
457 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
458 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
459 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
463 case PRID_IMP_R14000
:
464 c
->cputype
= CPU_R14000
;
465 c
->isa_level
= MIPS_CPU_ISA_IV
;
466 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
467 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
468 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
475 static char unknown_isa
[] __initdata
= KERN_ERR \
476 "Unsupported ISA type, c0.config0: %d.";
478 static inline unsigned int decode_config0(struct cpuinfo_mips
*c
)
480 unsigned int config0
;
483 config0
= read_c0_config();
485 if (((config0
& MIPS_CONF_MT
) >> 7) == 1)
486 c
->options
|= MIPS_CPU_TLB
;
487 isa
= (config0
& MIPS_CONF_AT
) >> 13;
490 switch ((config0
& MIPS_CONF_AR
) >> 10) {
492 c
->isa_level
= MIPS_CPU_ISA_M32R1
;
495 c
->isa_level
= MIPS_CPU_ISA_M32R2
;
502 switch ((config0
& MIPS_CONF_AR
) >> 10) {
504 c
->isa_level
= MIPS_CPU_ISA_M64R1
;
507 c
->isa_level
= MIPS_CPU_ISA_M64R2
;
517 return config0
& MIPS_CONF_M
;
520 panic(unknown_isa
, config0
);
523 static inline unsigned int decode_config1(struct cpuinfo_mips
*c
)
525 unsigned int config1
;
527 config1
= read_c0_config1();
529 if (config1
& MIPS_CONF1_MD
)
530 c
->ases
|= MIPS_ASE_MDMX
;
531 if (config1
& MIPS_CONF1_WR
)
532 c
->options
|= MIPS_CPU_WATCH
;
533 if (config1
& MIPS_CONF1_CA
)
534 c
->ases
|= MIPS_ASE_MIPS16
;
535 if (config1
& MIPS_CONF1_EP
)
536 c
->options
|= MIPS_CPU_EJTAG
;
537 if (config1
& MIPS_CONF1_FP
) {
538 c
->options
|= MIPS_CPU_FPU
;
539 c
->options
|= MIPS_CPU_32FPR
;
542 c
->tlbsize
= ((config1
& MIPS_CONF1_TLBS
) >> 25) + 1;
544 return config1
& MIPS_CONF_M
;
547 static inline unsigned int decode_config2(struct cpuinfo_mips
*c
)
549 unsigned int config2
;
551 config2
= read_c0_config2();
553 if (config2
& MIPS_CONF2_SL
)
554 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
556 return config2
& MIPS_CONF_M
;
559 static inline unsigned int decode_config3(struct cpuinfo_mips
*c
)
561 unsigned int config3
;
563 config3
= read_c0_config3();
565 if (config3
& MIPS_CONF3_SM
)
566 c
->ases
|= MIPS_ASE_SMARTMIPS
;
567 if (config3
& MIPS_CONF3_DSP
)
568 c
->ases
|= MIPS_ASE_DSP
;
569 if (config3
& MIPS_CONF3_VINT
)
570 c
->options
|= MIPS_CPU_VINT
;
571 if (config3
& MIPS_CONF3_VEIC
)
572 c
->options
|= MIPS_CPU_VEIC
;
573 if (config3
& MIPS_CONF3_MT
)
574 c
->ases
|= MIPS_ASE_MIPSMT
;
576 return config3
& MIPS_CONF_M
;
579 static void __init
decode_configs(struct cpuinfo_mips
*c
)
581 /* MIPS32 or MIPS64 compliant CPU. */
582 c
->options
= MIPS_CPU_4KEX
| MIPS_CPU_4K_CACHE
| MIPS_CPU_COUNTER
|
583 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
| MIPS_CPU_MCHECK
;
585 c
->scache
.flags
= MIPS_CACHE_NOT_PRESENT
;
587 /* Read Config registers. */
588 if (!decode_config0(c
))
589 return; /* actually worth a panic() */
590 if (!decode_config1(c
))
592 if (!decode_config2(c
))
594 if (!decode_config3(c
))
598 static inline void cpu_probe_mips(struct cpuinfo_mips
*c
)
601 switch (c
->processor_id
& 0xff00) {
603 c
->cputype
= CPU_4KC
;
606 c
->cputype
= CPU_4KEC
;
608 case PRID_IMP_4KECR2
:
609 c
->cputype
= CPU_4KEC
;
613 c
->cputype
= CPU_4KSC
;
616 c
->cputype
= CPU_5KC
;
619 c
->cputype
= CPU_20KC
;
623 c
->cputype
= CPU_24K
;
626 c
->cputype
= CPU_25KF
;
629 c
->cputype
= CPU_34K
;
632 c
->cputype
= CPU_74K
;
637 static inline void cpu_probe_alchemy(struct cpuinfo_mips
*c
)
640 switch (c
->processor_id
& 0xff00) {
641 case PRID_IMP_AU1_REV1
:
642 case PRID_IMP_AU1_REV2
:
643 switch ((c
->processor_id
>> 24) & 0xff) {
645 c
->cputype
= CPU_AU1000
;
648 c
->cputype
= CPU_AU1500
;
651 c
->cputype
= CPU_AU1100
;
654 c
->cputype
= CPU_AU1550
;
657 c
->cputype
= CPU_AU1200
;
660 panic("Unknown Au Core!");
667 static inline void cpu_probe_sibyte(struct cpuinfo_mips
*c
)
672 * For historical reasons the SB1 comes with it's own variant of
673 * cache code which eventually will be folded into c-r4k.c. Until
674 * then we pretend it's got it's own cache architecture.
676 c
->options
&= ~MIPS_CPU_4K_CACHE
;
677 c
->options
|= MIPS_CPU_SB1_CACHE
;
679 switch (c
->processor_id
& 0xff00) {
681 c
->cputype
= CPU_SB1
;
682 /* FPU in pass1 is known to have issues. */
683 if ((c
->processor_id
& 0xff) < 0x02)
684 c
->options
&= ~(MIPS_CPU_FPU
| MIPS_CPU_32FPR
);
687 c
->cputype
= CPU_SB1A
;
692 static inline void cpu_probe_sandcraft(struct cpuinfo_mips
*c
)
695 switch (c
->processor_id
& 0xff00) {
696 case PRID_IMP_SR71000
:
697 c
->cputype
= CPU_SR71000
;
704 static inline void cpu_probe_philips(struct cpuinfo_mips
*c
)
707 switch (c
->processor_id
& 0xff00) {
708 case PRID_IMP_PR4450
:
709 c
->cputype
= CPU_PR4450
;
710 c
->isa_level
= MIPS_CPU_ISA_M32R1
;
713 panic("Unknown Philips Core!"); /* REVISIT: die? */
719 __init
void cpu_probe(void)
721 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
723 c
->processor_id
= PRID_IMP_UNKNOWN
;
724 c
->fpu_id
= FPIR_IMP_NONE
;
725 c
->cputype
= CPU_UNKNOWN
;
727 c
->processor_id
= read_c0_prid();
728 switch (c
->processor_id
& 0xff0000) {
729 case PRID_COMP_LEGACY
:
735 case PRID_COMP_ALCHEMY
:
736 cpu_probe_alchemy(c
);
738 case PRID_COMP_SIBYTE
:
741 case PRID_COMP_SANDCRAFT
:
742 cpu_probe_sandcraft(c
);
744 case PRID_COMP_PHILIPS
:
745 cpu_probe_philips(c
);
748 c
->cputype
= CPU_UNKNOWN
;
750 if (c
->options
& MIPS_CPU_FPU
) {
751 c
->fpu_id
= cpu_get_fpu_id();
753 if (c
->isa_level
== MIPS_CPU_ISA_M32R1
||
754 c
->isa_level
== MIPS_CPU_ISA_M32R2
||
755 c
->isa_level
== MIPS_CPU_ISA_M64R1
||
756 c
->isa_level
== MIPS_CPU_ISA_M64R2
) {
757 if (c
->fpu_id
& MIPS_FPIR_3D
)
758 c
->ases
|= MIPS_ASE_MIPS3D
;
763 __init
void cpu_report(void)
765 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
767 printk("CPU revision is: %08x\n", c
->processor_id
);
768 if (c
->options
& MIPS_CPU_FPU
)
769 printk("FPU revision is: %08x\n", c
->fpu_id
);