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drm: Propagate failure from setting crtc base.
[linux-2.6/linux-2.6-openrd.git] / drivers / gpu / drm / i915 / intel_display.c
blobac92799fa8a15e762c74de5fb299e216c373aae4
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/i2c.h>
28 #include "drmP.h"
29 #include "intel_drv.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32
33 #include "drm_crtc_helper.h"
34
35 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
36
37 typedef struct {
38 /* given values */
39 int n;
40 int m1, m2;
41 int p1, p2;
42 /* derived values */
43 int dot;
44 int vco;
45 int m;
46 int p;
47 } intel_clock_t;
48
49 typedef struct {
50 int min, max;
51 } intel_range_t;
52
53 typedef struct {
54 int dot_limit;
55 int p2_slow, p2_fast;
56 } intel_p2_t;
57
58 #define INTEL_P2_NUM 2
59
60 typedef struct {
61 intel_range_t dot, vco, n, m, m1, m2, p, p1;
62 intel_p2_t p2;
63 } intel_limit_t;
64
65 #define I8XX_DOT_MIN 25000
66 #define I8XX_DOT_MAX 350000
67 #define I8XX_VCO_MIN 930000
68 #define I8XX_VCO_MAX 1400000
69 #define I8XX_N_MIN 3
70 #define I8XX_N_MAX 16
71 #define I8XX_M_MIN 96
72 #define I8XX_M_MAX 140
73 #define I8XX_M1_MIN 18
74 #define I8XX_M1_MAX 26
75 #define I8XX_M2_MIN 6
76 #define I8XX_M2_MAX 16
77 #define I8XX_P_MIN 4
78 #define I8XX_P_MAX 128
79 #define I8XX_P1_MIN 2
80 #define I8XX_P1_MAX 33
81 #define I8XX_P1_LVDS_MIN 1
82 #define I8XX_P1_LVDS_MAX 6
83 #define I8XX_P2_SLOW 4
84 #define I8XX_P2_FAST 2
85 #define I8XX_P2_LVDS_SLOW 14
86 #define I8XX_P2_LVDS_FAST 14 /* No fast option */
87 #define I8XX_P2_SLOW_LIMIT 165000
88
89 #define I9XX_DOT_MIN 20000
90 #define I9XX_DOT_MAX 400000
91 #define I9XX_VCO_MIN 1400000
92 #define I9XX_VCO_MAX 2800000
93 #define I9XX_N_MIN 3
94 #define I9XX_N_MAX 8
95 #define I9XX_M_MIN 70
96 #define I9XX_M_MAX 120
97 #define I9XX_M1_MIN 10
98 #define I9XX_M1_MAX 20
99 #define I9XX_M2_MIN 5
100 #define I9XX_M2_MAX 9
101 #define I9XX_P_SDVO_DAC_MIN 5
102 #define I9XX_P_SDVO_DAC_MAX 80
103 #define I9XX_P_LVDS_MIN 7
104 #define I9XX_P_LVDS_MAX 98
105 #define I9XX_P1_MIN 1
106 #define I9XX_P1_MAX 8
107 #define I9XX_P2_SDVO_DAC_SLOW 10
108 #define I9XX_P2_SDVO_DAC_FAST 5
109 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
110 #define I9XX_P2_LVDS_SLOW 14
111 #define I9XX_P2_LVDS_FAST 7
112 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
113
114 #define INTEL_LIMIT_I8XX_DVO_DAC 0
115 #define INTEL_LIMIT_I8XX_LVDS 1
116 #define INTEL_LIMIT_I9XX_SDVO_DAC 2
117 #define INTEL_LIMIT_I9XX_LVDS 3
118
119 static const intel_limit_t intel_limits[] = {
120 { /* INTEL_LIMIT_I8XX_DVO_DAC */
121 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
122 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
123 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
124 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
125 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
126 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
127 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
128 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
129 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
130 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
131 },
132 { /* INTEL_LIMIT_I8XX_LVDS */
133 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
134 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
135 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
136 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
137 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
138 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
139 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
140 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
141 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
142 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
143 },
144 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
145 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
146 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
147 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
148 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
149 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
150 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
151 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
152 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
153 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
154 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
155 },
156 { /* INTEL_LIMIT_I9XX_LVDS */
157 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
158 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
159 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
160 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
161 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
162 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
163 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
164 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
165 /* The single-channel range is 25-112Mhz, and dual-channel
166 * is 80-224Mhz. Prefer single channel as much as possible.
167 */
168 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
169 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
170 },
171 };
172
173 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
174 {
175 struct drm_device *dev = crtc->dev;
176 const intel_limit_t *limit;
177
178 if (IS_I9XX(dev)) {
179 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
180 limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
181 else
182 limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
183 } else {
184 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
185 limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
186 else
187 limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC];
188 }
189 return limit;
190 }
191
192 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
193
194 static void i8xx_clock(int refclk, intel_clock_t *clock)
195 {
196 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
197 clock->p = clock->p1 * clock->p2;
198 clock->vco = refclk * clock->m / (clock->n + 2);
199 clock->dot = clock->vco / clock->p;
200 }
201
202 /** Derive the pixel clock for the given refclk and divisors for 9xx chips. */
203
204 static void i9xx_clock(int refclk, intel_clock_t *clock)
205 {
206 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
207 clock->p = clock->p1 * clock->p2;
208 clock->vco = refclk * clock->m / (clock->n + 2);
209 clock->dot = clock->vco / clock->p;
210 }
211
212 static void intel_clock(struct drm_device *dev, int refclk,
213 intel_clock_t *clock)
214 {
215 if (IS_I9XX(dev))
216 i9xx_clock (refclk, clock);
217 else
218 i8xx_clock (refclk, clock);
219 }
220
221 /**
222 * Returns whether any output on the specified pipe is of the specified type
223 */
224 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
225 {
226 struct drm_device *dev = crtc->dev;
227 struct drm_mode_config *mode_config = &dev->mode_config;
228 struct drm_connector *l_entry;
229
230 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
231 if (l_entry->encoder &&
232 l_entry->encoder->crtc == crtc) {
233 struct intel_output *intel_output = to_intel_output(l_entry);
234 if (intel_output->type == type)
235 return true;
236 }
237 }
238 return false;
239 }
240
241 #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
242 /**
243 * Returns whether the given set of divisors are valid for a given refclk with
244 * the given connectors.
245 */
246
247 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
248 {
249 const intel_limit_t *limit = intel_limit (crtc);
250
251 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
252 INTELPllInvalid ("p1 out of range\n");
253 if (clock->p < limit->p.min || limit->p.max < clock->p)
254 INTELPllInvalid ("p out of range\n");
255 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
256 INTELPllInvalid ("m2 out of range\n");
257 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
258 INTELPllInvalid ("m1 out of range\n");
259 if (clock->m1 <= clock->m2)
260 INTELPllInvalid ("m1 <= m2\n");
261 if (clock->m < limit->m.min || limit->m.max < clock->m)
262 INTELPllInvalid ("m out of range\n");
263 if (clock->n < limit->n.min || limit->n.max < clock->n)
264 INTELPllInvalid ("n out of range\n");
265 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
266 INTELPllInvalid ("vco out of range\n");
267 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
268 * connector, etc., rather than just a single range.
269 */
270 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
271 INTELPllInvalid ("dot out of range\n");
272
273 return true;
274 }
275
276 /**
277 * Returns a set of divisors for the desired target clock with the given
278 * refclk, or FALSE. The returned values represent the clock equation:
279 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
280 */
281 static bool intel_find_best_PLL(struct drm_crtc *crtc, int target,
282 int refclk, intel_clock_t *best_clock)
283 {
284 struct drm_device *dev = crtc->dev;
285 struct drm_i915_private *dev_priv = dev->dev_private;
286 intel_clock_t clock;
287 const intel_limit_t *limit = intel_limit(crtc);
288 int err = target;
289
290 if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
291 (I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
292 /*
293 * For LVDS, if the panel is on, just rely on its current
294 * settings for dual-channel. We haven't figured out how to
295 * reliably set up different single/dual channel state, if we
296 * even can.
297 */
298 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
299 LVDS_CLKB_POWER_UP)
300 clock.p2 = limit->p2.p2_fast;
301 else
302 clock.p2 = limit->p2.p2_slow;
303 } else {
304 if (target < limit->p2.dot_limit)
305 clock.p2 = limit->p2.p2_slow;
306 else
307 clock.p2 = limit->p2.p2_fast;
308 }
309
310 memset (best_clock, 0, sizeof (*best_clock));
311
312 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
313 for (clock.m2 = limit->m2.min; clock.m2 < clock.m1 &&
314 clock.m2 <= limit->m2.max; clock.m2++) {
315 for (clock.n = limit->n.min; clock.n <= limit->n.max;
316 clock.n++) {
317 for (clock.p1 = limit->p1.min;
318 clock.p1 <= limit->p1.max; clock.p1++) {
319 int this_err;
320
321 intel_clock(dev, refclk, &clock);
322
323 if (!intel_PLL_is_valid(crtc, &clock))
324 continue;
325
326 this_err = abs(clock.dot - target);
327 if (this_err < err) {
328 *best_clock = clock;
329 err = this_err;
330 }
331 }
332 }
333 }
334 }
335
336 return (err != target);
337 }
338
339 void
340 intel_wait_for_vblank(struct drm_device *dev)
341 {
342 /* Wait for 20ms, i.e. one cycle at 50hz. */
343 udelay(20000);
344 }
345
346 static int
347 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
348 struct drm_framebuffer *old_fb)
349 {
350 struct drm_device *dev = crtc->dev;
351 struct drm_i915_private *dev_priv = dev->dev_private;
352 struct drm_i915_master_private *master_priv;
353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
354 struct intel_framebuffer *intel_fb;
355 struct drm_i915_gem_object *obj_priv;
356 struct drm_gem_object *obj;
357 int pipe = intel_crtc->pipe;
358 unsigned long Start, Offset;
359 int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
360 int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
361 int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
362 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
363 u32 dspcntr, alignment;
364 int ret;
365
366 /* no fb bound */
367 if (!crtc->fb) {
368 DRM_DEBUG("No FB bound\n");
369 return 0;
370 }
371
372 switch (pipe) {
373 case 0:
374 case 1:
375 break;
376 default:
377 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
378 return -EINVAL;
379 }
380
381 intel_fb = to_intel_framebuffer(crtc->fb);
382 obj = intel_fb->obj;
383 obj_priv = obj->driver_private;
384
385 switch (obj_priv->tiling_mode) {
386 case I915_TILING_NONE:
387 alignment = 64 * 1024;
388 break;
389 case I915_TILING_X:
390 /* pin() will align the object as required by fence */
391 alignment = 0;
392 break;
393 case I915_TILING_Y:
394 /* FIXME: Is this true? */
395 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
396 return -EINVAL;
397 default:
398 BUG();
399 }
400
401 mutex_lock(&dev->struct_mutex);
402 ret = i915_gem_object_pin(intel_fb->obj, alignment);
403 if (ret != 0) {
404 mutex_unlock(&dev->struct_mutex);
405 return ret;
406 }
407
408 ret = i915_gem_object_set_to_gtt_domain(intel_fb->obj, 1);
409 if (ret != 0) {
410 i915_gem_object_unpin(intel_fb->obj);
411 mutex_unlock(&dev->struct_mutex);
412 return ret;
413 }
414
415 dspcntr = I915_READ(dspcntr_reg);
416 /* Mask out pixel format bits in case we change it */
417 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
418 switch (crtc->fb->bits_per_pixel) {
419 case 8:
420 dspcntr |= DISPPLANE_8BPP;
421 break;
422 case 16:
423 if (crtc->fb->depth == 15)
424 dspcntr |= DISPPLANE_15_16BPP;
425 else
426 dspcntr |= DISPPLANE_16BPP;
427 break;
428 case 24:
429 case 32:
430 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
431 break;
432 default:
433 DRM_ERROR("Unknown color depth\n");
434 i915_gem_object_unpin(intel_fb->obj);
435 mutex_unlock(&dev->struct_mutex);
436 return -EINVAL;
437 }
438 I915_WRITE(dspcntr_reg, dspcntr);
439
440 Start = obj_priv->gtt_offset;
441 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
442
443 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
444 I915_WRITE(dspstride, crtc->fb->pitch);
445 if (IS_I965G(dev)) {
446 I915_WRITE(dspbase, Offset);
447 I915_READ(dspbase);
448 I915_WRITE(dspsurf, Start);
449 I915_READ(dspsurf);
450 } else {
451 I915_WRITE(dspbase, Start + Offset);
452 I915_READ(dspbase);
453 }
454
455 intel_wait_for_vblank(dev);
456
457 if (old_fb) {
458 intel_fb = to_intel_framebuffer(old_fb);
459 i915_gem_object_unpin(intel_fb->obj);
460 }
461 mutex_unlock(&dev->struct_mutex);
462
463 if (!dev->primary->master)
464 return 0;
465
466 master_priv = dev->primary->master->driver_priv;
467 if (!master_priv->sarea_priv)
468 return 0;
469
470 if (pipe) {
471 master_priv->sarea_priv->pipeB_x = x;
472 master_priv->sarea_priv->pipeB_y = y;
473 } else {
474 master_priv->sarea_priv->pipeA_x = x;
475 master_priv->sarea_priv->pipeA_y = y;
476 }
477
478 return 0;
479 }
480
481
482
483 /**
484 * Sets the power management mode of the pipe and plane.
485 *
486 * This code should probably grow support for turning the cursor off and back
487 * on appropriately at the same time as we're turning the pipe off/on.
488 */
489 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
490 {
491 struct drm_device *dev = crtc->dev;
492 struct drm_i915_master_private *master_priv;
493 struct drm_i915_private *dev_priv = dev->dev_private;
494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
495 int pipe = intel_crtc->pipe;
496 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
497 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
498 int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
499 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
500 u32 temp;
501 bool enabled;
502
503 /* XXX: When our outputs are all unaware of DPMS modes other than off
504 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
505 */
506 switch (mode) {
507 case DRM_MODE_DPMS_ON:
508 case DRM_MODE_DPMS_STANDBY:
509 case DRM_MODE_DPMS_SUSPEND:
510 /* Enable the DPLL */
511 temp = I915_READ(dpll_reg);
512 if ((temp & DPLL_VCO_ENABLE) == 0) {
513 I915_WRITE(dpll_reg, temp);
514 I915_READ(dpll_reg);
515 /* Wait for the clocks to stabilize. */
516 udelay(150);
517 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
518 I915_READ(dpll_reg);
519 /* Wait for the clocks to stabilize. */
520 udelay(150);
521 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
522 I915_READ(dpll_reg);
523 /* Wait for the clocks to stabilize. */
524 udelay(150);
525 }
526
527 /* Enable the pipe */
528 temp = I915_READ(pipeconf_reg);
529 if ((temp & PIPEACONF_ENABLE) == 0)
530 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
531
532 /* Enable the plane */
533 temp = I915_READ(dspcntr_reg);
534 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
535 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
536 /* Flush the plane changes */
537 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
538 }
539
540 intel_crtc_load_lut(crtc);
541
542 /* Give the overlay scaler a chance to enable if it's on this pipe */
543 //intel_crtc_dpms_video(crtc, true); TODO
544 break;
545 case DRM_MODE_DPMS_OFF:
546 /* Give the overlay scaler a chance to disable if it's on this pipe */
547 //intel_crtc_dpms_video(crtc, FALSE); TODO
548
549 /* Disable the VGA plane that we never use */
550 I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
551
552 /* Disable display plane */
553 temp = I915_READ(dspcntr_reg);
554 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
555 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
556 /* Flush the plane changes */
557 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
558 I915_READ(dspbase_reg);
559 }
560
561 if (!IS_I9XX(dev)) {
562 /* Wait for vblank for the disable to take effect */
563 intel_wait_for_vblank(dev);
564 }
565
566 /* Next, disable display pipes */
567 temp = I915_READ(pipeconf_reg);
568 if ((temp & PIPEACONF_ENABLE) != 0) {
569 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
570 I915_READ(pipeconf_reg);
571 }
572
573 /* Wait for vblank for the disable to take effect. */
574 intel_wait_for_vblank(dev);
575
576 temp = I915_READ(dpll_reg);
577 if ((temp & DPLL_VCO_ENABLE) != 0) {
578 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
579 I915_READ(dpll_reg);
580 }
581
582 /* Wait for the clocks to turn off. */
583 udelay(150);
584 break;
585 }
586
587 if (!dev->primary->master)
588 return;
589
590 master_priv = dev->primary->master->driver_priv;
591 if (!master_priv->sarea_priv)
592 return;
593
594 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
595
596 switch (pipe) {
597 case 0:
598 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
599 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
600 break;
601 case 1:
602 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
603 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
604 break;
605 default:
606 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
607 break;
608 }
609
610 intel_crtc->dpms_mode = mode;
611 }
612
613 static void intel_crtc_prepare (struct drm_crtc *crtc)
614 {
615 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
616 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
617 }
618
619 static void intel_crtc_commit (struct drm_crtc *crtc)
620 {
621 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
622 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
623 }
624
625 void intel_encoder_prepare (struct drm_encoder *encoder)
626 {
627 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
628 /* lvds has its own version of prepare see intel_lvds_prepare */
629 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
630 }
631
632 void intel_encoder_commit (struct drm_encoder *encoder)
633 {
634 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
635 /* lvds has its own version of commit see intel_lvds_commit */
636 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
637 }
638
639 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
640 struct drm_display_mode *mode,
641 struct drm_display_mode *adjusted_mode)
642 {
643 return true;
644 }
645
646
647 /** Returns the core display clock speed for i830 - i945 */
648 static int intel_get_core_clock_speed(struct drm_device *dev)
649 {
650
651 /* Core clock values taken from the published datasheets.
652 * The 830 may go up to 166 Mhz, which we should check.
653 */
654 if (IS_I945G(dev))
655 return 400000;
656 else if (IS_I915G(dev))
657 return 333000;
658 else if (IS_I945GM(dev) || IS_845G(dev))
659 return 200000;
660 else if (IS_I915GM(dev)) {
661 u16 gcfgc = 0;
662
663 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
664
665 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
666 return 133000;
667 else {
668 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
669 case GC_DISPLAY_CLOCK_333_MHZ:
670 return 333000;
671 default:
672 case GC_DISPLAY_CLOCK_190_200_MHZ:
673 return 190000;
674 }
675 }
676 } else if (IS_I865G(dev))
677 return 266000;
678 else if (IS_I855(dev)) {
679 u16 hpllcc = 0;
680 /* Assume that the hardware is in the high speed state. This
681 * should be the default.
682 */
683 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
684 case GC_CLOCK_133_200:
685 case GC_CLOCK_100_200:
686 return 200000;
687 case GC_CLOCK_166_250:
688 return 250000;
689 case GC_CLOCK_100_133:
690 return 133000;
691 }
692 } else /* 852, 830 */
693 return 133000;
694
695 return 0; /* Silence gcc warning */
696 }
697
698
699 /**
700 * Return the pipe currently connected to the panel fitter,
701 * or -1 if the panel fitter is not present or not in use
702 */
703 static int intel_panel_fitter_pipe (struct drm_device *dev)
704 {
705 struct drm_i915_private *dev_priv = dev->dev_private;
706 u32 pfit_control;
707
708 /* i830 doesn't have a panel fitter */
709 if (IS_I830(dev))
710 return -1;
711
712 pfit_control = I915_READ(PFIT_CONTROL);
713
714 /* See if the panel fitter is in use */
715 if ((pfit_control & PFIT_ENABLE) == 0)
716 return -1;
717
718 /* 965 can place panel fitter on either pipe */
719 if (IS_I965G(dev))
720 return (pfit_control >> 29) & 0x3;
721
722 /* older chips can only use pipe 1 */
723 return 1;
724 }
725
726 static int intel_crtc_mode_set(struct drm_crtc *crtc,
727 struct drm_display_mode *mode,
728 struct drm_display_mode *adjusted_mode,
729 int x, int y,
730 struct drm_framebuffer *old_fb)
731 {
732 struct drm_device *dev = crtc->dev;
733 struct drm_i915_private *dev_priv = dev->dev_private;
734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
735 int pipe = intel_crtc->pipe;
736 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
737 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
738 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
739 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
740 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
741 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
742 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
743 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
744 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
745 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
746 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
747 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
748 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
749 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
750 int refclk;
751 intel_clock_t clock;
752 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
753 bool ok, is_sdvo = false, is_dvo = false;
754 bool is_crt = false, is_lvds = false, is_tv = false;
755 struct drm_mode_config *mode_config = &dev->mode_config;
756 struct drm_connector *connector;
757 int ret;
758
759 drm_vblank_pre_modeset(dev, pipe);
760
761 list_for_each_entry(connector, &mode_config->connector_list, head) {
762 struct intel_output *intel_output = to_intel_output(connector);
763
764 if (!connector->encoder || connector->encoder->crtc != crtc)
765 continue;
766
767 switch (intel_output->type) {
768 case INTEL_OUTPUT_LVDS:
769 is_lvds = true;
770 break;
771 case INTEL_OUTPUT_SDVO:
772 case INTEL_OUTPUT_HDMI:
773 is_sdvo = true;
774 if (intel_output->needs_tv_clock)
775 is_tv = true;
776 break;
777 case INTEL_OUTPUT_DVO:
778 is_dvo = true;
779 break;
780 case INTEL_OUTPUT_TVOUT:
781 is_tv = true;
782 break;
783 case INTEL_OUTPUT_ANALOG:
784 is_crt = true;
785 break;
786 }
787 }
788
789 if (IS_I9XX(dev)) {
790 refclk = 96000;
791 } else {
792 refclk = 48000;
793 }
794
795 ok = intel_find_best_PLL(crtc, adjusted_mode->clock, refclk, &clock);
796 if (!ok) {
797 DRM_ERROR("Couldn't find PLL settings for mode!\n");
798 return -EINVAL;
799 }
800
801 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
802
803 dpll = DPLL_VGA_MODE_DIS;
804 if (IS_I9XX(dev)) {
805 if (is_lvds)
806 dpll |= DPLLB_MODE_LVDS;
807 else
808 dpll |= DPLLB_MODE_DAC_SERIAL;
809 if (is_sdvo) {
810 dpll |= DPLL_DVO_HIGH_SPEED;
811 if (IS_I945G(dev) || IS_I945GM(dev)) {
812 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
813 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
814 }
815 }
816
817 /* compute bitmask from p1 value */
818 dpll |= (1 << (clock.p1 - 1)) << 16;
819 switch (clock.p2) {
820 case 5:
821 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
822 break;
823 case 7:
824 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
825 break;
826 case 10:
827 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
828 break;
829 case 14:
830 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
831 break;
832 }
833 if (IS_I965G(dev))
834 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
835 } else {
836 if (is_lvds) {
837 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
838 } else {
839 if (clock.p1 == 2)
840 dpll |= PLL_P1_DIVIDE_BY_TWO;
841 else
842 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
843 if (clock.p2 == 4)
844 dpll |= PLL_P2_DIVIDE_BY_4;
845 }
846 }
847
848 if (is_tv) {
849 /* XXX: just matching BIOS for now */
850 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
851 dpll |= 3;
852 }
853 else
854 dpll |= PLL_REF_INPUT_DREFCLK;
855
856 /* setup pipeconf */
857 pipeconf = I915_READ(pipeconf_reg);
858
859 /* Set up the display plane register */
860 dspcntr = DISPPLANE_GAMMA_ENABLE;
861
862 if (pipe == 0)
863 dspcntr |= DISPPLANE_SEL_PIPE_A;
864 else
865 dspcntr |= DISPPLANE_SEL_PIPE_B;
866
867 if (pipe == 0 && !IS_I965G(dev)) {
868 /* Enable pixel doubling when the dot clock is > 90% of the (display)
869 * core speed.
870 *
871 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
872 * pipe == 0 check?
873 */
874 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
875 pipeconf |= PIPEACONF_DOUBLE_WIDE;
876 else
877 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
878 }
879
880 dspcntr |= DISPLAY_PLANE_ENABLE;
881 pipeconf |= PIPEACONF_ENABLE;
882 dpll |= DPLL_VCO_ENABLE;
883
884
885 /* Disable the panel fitter if it was on our pipe */
886 if (intel_panel_fitter_pipe(dev) == pipe)
887 I915_WRITE(PFIT_CONTROL, 0);
888
889 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
890 drm_mode_debug_printmodeline(mode);
891
892
893 if (dpll & DPLL_VCO_ENABLE) {
894 I915_WRITE(fp_reg, fp);
895 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
896 I915_READ(dpll_reg);
897 udelay(150);
898 }
899
900 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
901 * This is an exception to the general rule that mode_set doesn't turn
902 * things on.
903 */
904 if (is_lvds) {
905 u32 lvds = I915_READ(LVDS);
906
907 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
908 /* Set the B0-B3 data pairs corresponding to whether we're going to
909 * set the DPLLs for dual-channel mode or not.
910 */
911 if (clock.p2 == 7)
912 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
913 else
914 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
915
916 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
917 * appropriately here, but we need to look more thoroughly into how
918 * panels behave in the two modes.
919 */
920
921 I915_WRITE(LVDS, lvds);
922 I915_READ(LVDS);
923 }
924
925 I915_WRITE(fp_reg, fp);
926 I915_WRITE(dpll_reg, dpll);
927 I915_READ(dpll_reg);
928 /* Wait for the clocks to stabilize. */
929 udelay(150);
930
931 if (IS_I965G(dev)) {
932 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
933 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
934 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
935 } else {
936 /* write it again -- the BIOS does, after all */
937 I915_WRITE(dpll_reg, dpll);
938 }
939 I915_READ(dpll_reg);
940 /* Wait for the clocks to stabilize. */
941 udelay(150);
942
943 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
944 ((adjusted_mode->crtc_htotal - 1) << 16));
945 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
946 ((adjusted_mode->crtc_hblank_end - 1) << 16));
947 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
948 ((adjusted_mode->crtc_hsync_end - 1) << 16));
949 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
950 ((adjusted_mode->crtc_vtotal - 1) << 16));
951 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
952 ((adjusted_mode->crtc_vblank_end - 1) << 16));
953 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
954 ((adjusted_mode->crtc_vsync_end - 1) << 16));
955 /* pipesrc and dspsize control the size that is scaled from, which should
956 * always be the user's requested size.
957 */
958 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
959 I915_WRITE(dsppos_reg, 0);
960 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
961 I915_WRITE(pipeconf_reg, pipeconf);
962 I915_READ(pipeconf_reg);
963
964 intel_wait_for_vblank(dev);
965
966 I915_WRITE(dspcntr_reg, dspcntr);
967
968 /* Flush the plane changes */
969 ret = intel_pipe_set_base(crtc, x, y, old_fb);
970 if (ret != 0)
971 return ret;
972
973 drm_vblank_post_modeset(dev, pipe);
974
975 return 0;
976 }
977
978 /** Loads the palette/gamma unit for the CRTC with the prepared values */
979 void intel_crtc_load_lut(struct drm_crtc *crtc)
980 {
981 struct drm_device *dev = crtc->dev;
982 struct drm_i915_private *dev_priv = dev->dev_private;
983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
984 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
985 int i;
986
987 /* The clocks have to be on to load the palette. */
988 if (!crtc->enabled)
989 return;
990
991 for (i = 0; i < 256; i++) {
992 I915_WRITE(palreg + 4 * i,
993 (intel_crtc->lut_r[i] << 16) |
994 (intel_crtc->lut_g[i] << 8) |
995 intel_crtc->lut_b[i]);
996 }
997 }
998
999 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
1000 struct drm_file *file_priv,
1001 uint32_t handle,
1002 uint32_t width, uint32_t height)
1003 {
1004 struct drm_device *dev = crtc->dev;
1005 struct drm_i915_private *dev_priv = dev->dev_private;
1006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007 struct drm_gem_object *bo;
1008 struct drm_i915_gem_object *obj_priv;
1009 int pipe = intel_crtc->pipe;
1010 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
1011 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
1012 uint32_t temp;
1013 size_t addr;
1014 int ret;
1015
1016 DRM_DEBUG("\n");
1017
1018 /* if we want to turn off the cursor ignore width and height */
1019 if (!handle) {
1020 DRM_DEBUG("cursor off\n");
1021 temp = CURSOR_MODE_DISABLE;
1022 addr = 0;
1023 bo = NULL;
1024 goto finish;
1025 }
1026
1027 /* Currently we only support 64x64 cursors */
1028 if (width != 64 || height != 64) {
1029 DRM_ERROR("we currently only support 64x64 cursors\n");
1030 return -EINVAL;
1031 }
1032
1033 bo = drm_gem_object_lookup(dev, file_priv, handle);
1034 if (!bo)
1035 return -ENOENT;
1036
1037 obj_priv = bo->driver_private;
1038
1039 if (bo->size < width * height * 4) {
1040 DRM_ERROR("buffer is to small\n");
1041 ret = -ENOMEM;
1042 goto fail;
1043 }
1044
1045 /* we only need to pin inside GTT if cursor is non-phy */
1046 if (!dev_priv->cursor_needs_physical) {
1047 ret = i915_gem_object_pin(bo, PAGE_SIZE);
1048 if (ret) {
1049 DRM_ERROR("failed to pin cursor bo\n");
1050 goto fail;
1051 }
1052 addr = obj_priv->gtt_offset;
1053 } else {
1054 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
1055 if (ret) {
1056 DRM_ERROR("failed to attach phys object\n");
1057 goto fail;
1058 }
1059 addr = obj_priv->phys_obj->handle->busaddr;
1060 }
1061
1062 temp = 0;
1063 /* set the pipe for the cursor */
1064 temp |= (pipe << 28);
1065 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1066
1067 finish:
1068 I915_WRITE(control, temp);
1069 I915_WRITE(base, addr);
1070
1071 if (intel_crtc->cursor_bo) {
1072 if (dev_priv->cursor_needs_physical) {
1073 if (intel_crtc->cursor_bo != bo)
1074 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
1075 } else
1076 i915_gem_object_unpin(intel_crtc->cursor_bo);
1077 mutex_lock(&dev->struct_mutex);
1078 drm_gem_object_unreference(intel_crtc->cursor_bo);
1079 mutex_unlock(&dev->struct_mutex);
1080 }
1081
1082 intel_crtc->cursor_addr = addr;
1083 intel_crtc->cursor_bo = bo;
1084
1085 return 0;
1086 fail:
1087 mutex_lock(&dev->struct_mutex);
1088 drm_gem_object_unreference(bo);
1089 mutex_unlock(&dev->struct_mutex);
1090 return ret;
1091 }
1092
1093 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1094 {
1095 struct drm_device *dev = crtc->dev;
1096 struct drm_i915_private *dev_priv = dev->dev_private;
1097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1098 int pipe = intel_crtc->pipe;
1099 uint32_t temp = 0;
1100 uint32_t adder;
1101
1102 if (x < 0) {
1103 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
1104 x = -x;
1105 }
1106 if (y < 0) {
1107 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
1108 y = -y;
1109 }
1110
1111 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
1112 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1113
1114 adder = intel_crtc->cursor_addr;
1115 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
1116 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
1117
1118 return 0;
1119 }
1120
1121 /** Sets the color ramps on behalf of RandR */
1122 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1123 u16 blue, int regno)
1124 {
1125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1126
1127 intel_crtc->lut_r[regno] = red >> 8;
1128 intel_crtc->lut_g[regno] = green >> 8;
1129 intel_crtc->lut_b[regno] = blue >> 8;
1130 }
1131
1132 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1133 u16 *blue, uint32_t size)
1134 {
1135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1136 int i;
1137
1138 if (size != 256)
1139 return;
1140
1141 for (i = 0; i < 256; i++) {
1142 intel_crtc->lut_r[i] = red[i] >> 8;
1143 intel_crtc->lut_g[i] = green[i] >> 8;
1144 intel_crtc->lut_b[i] = blue[i] >> 8;
1145 }
1146
1147 intel_crtc_load_lut(crtc);
1148 }
1149
1150 /**
1151 * Get a pipe with a simple mode set on it for doing load-based monitor
1152 * detection.
1153 *
1154 * It will be up to the load-detect code to adjust the pipe as appropriate for
1155 * its requirements. The pipe will be connected to no other outputs.
1156 *
1157 * Currently this code will only succeed if there is a pipe with no outputs
1158 * configured for it. In the future, it could choose to temporarily disable
1159 * some outputs to free up a pipe for its use.
1160 *
1161 * \return crtc, or NULL if no pipes are available.
1162 */
1163
1164 /* VESA 640x480x72Hz mode to set on the pipe */
1165 static struct drm_display_mode load_detect_mode = {
1166 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
1167 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1168 };
1169
1170 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
1171 struct drm_display_mode *mode,
1172 int *dpms_mode)
1173 {
1174 struct intel_crtc *intel_crtc;
1175 struct drm_crtc *possible_crtc;
1176 struct drm_crtc *supported_crtc =NULL;
1177 struct drm_encoder *encoder = &intel_output->enc;
1178 struct drm_crtc *crtc = NULL;
1179 struct drm_device *dev = encoder->dev;
1180 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1181 struct drm_crtc_helper_funcs *crtc_funcs;
1182 int i = -1;
1183
1184 /*
1185 * Algorithm gets a little messy:
1186 * - if the connector already has an assigned crtc, use it (but make
1187 * sure it's on first)
1188 * - try to find the first unused crtc that can drive this connector,
1189 * and use that if we find one
1190 * - if there are no unused crtcs available, try to use the first
1191 * one we found that supports the connector
1192 */
1193
1194 /* See if we already have a CRTC for this connector */
1195 if (encoder->crtc) {
1196 crtc = encoder->crtc;
1197 /* Make sure the crtc and connector are running */
1198 intel_crtc = to_intel_crtc(crtc);
1199 *dpms_mode = intel_crtc->dpms_mode;
1200 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
1201 crtc_funcs = crtc->helper_private;
1202 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1203 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1204 }
1205 return crtc;
1206 }
1207
1208 /* Find an unused one (if possible) */
1209 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
1210 i++;
1211 if (!(encoder->possible_crtcs & (1 << i)))
1212 continue;
1213 if (!possible_crtc->enabled) {
1214 crtc = possible_crtc;
1215 break;
1216 }
1217 if (!supported_crtc)
1218 supported_crtc = possible_crtc;
1219 }
1220
1221 /*
1222 * If we didn't find an unused CRTC, don't use any.
1223 */
1224 if (!crtc) {
1225 return NULL;
1226 }
1227
1228 encoder->crtc = crtc;
1229 intel_output->load_detect_temp = true;
1230
1231 intel_crtc = to_intel_crtc(crtc);
1232 *dpms_mode = intel_crtc->dpms_mode;
1233
1234 if (!crtc->enabled) {
1235 if (!mode)
1236 mode = &load_detect_mode;
1237 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
1238 } else {
1239 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
1240 crtc_funcs = crtc->helper_private;
1241 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1242 }
1243
1244 /* Add this connector to the crtc */
1245 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
1246 encoder_funcs->commit(encoder);
1247 }
1248 /* let the connector get through one full cycle before testing */
1249 intel_wait_for_vblank(dev);
1250
1251 return crtc;
1252 }
1253
1254 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
1255 {
1256 struct drm_encoder *encoder = &intel_output->enc;
1257 struct drm_device *dev = encoder->dev;
1258 struct drm_crtc *crtc = encoder->crtc;
1259 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1260 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1261
1262 if (intel_output->load_detect_temp) {
1263 encoder->crtc = NULL;
1264 intel_output->load_detect_temp = false;
1265 crtc->enabled = drm_helper_crtc_in_use(crtc);
1266 drm_helper_disable_unused_functions(dev);
1267 }
1268
1269 /* Switch crtc and output back off if necessary */
1270 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
1271 if (encoder->crtc == crtc)
1272 encoder_funcs->dpms(encoder, dpms_mode);
1273 crtc_funcs->dpms(crtc, dpms_mode);
1274 }
1275 }
1276
1277 /* Returns the clock of the currently programmed mode of the given pipe. */
1278 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
1279 {
1280 struct drm_i915_private *dev_priv = dev->dev_private;
1281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1282 int pipe = intel_crtc->pipe;
1283 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
1284 u32 fp;
1285 intel_clock_t clock;
1286
1287 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1288 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
1289 else
1290 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
1291
1292 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1293 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1294 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1295 if (IS_I9XX(dev)) {
1296 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
1297 DPLL_FPA01_P1_POST_DIV_SHIFT);
1298
1299 switch (dpll & DPLL_MODE_MASK) {
1300 case DPLLB_MODE_DAC_SERIAL:
1301 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
1302 5 : 10;
1303 break;
1304 case DPLLB_MODE_LVDS:
1305 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
1306 7 : 14;
1307 break;
1308 default:
1309 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
1310 "mode\n", (int)(dpll & DPLL_MODE_MASK));
1311 return 0;
1312 }
1313
1314 /* XXX: Handle the 100Mhz refclk */
1315 i9xx_clock(96000, &clock);
1316 } else {
1317 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
1318
1319 if (is_lvds) {
1320 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1321 DPLL_FPA01_P1_POST_DIV_SHIFT);
1322 clock.p2 = 14;
1323
1324 if ((dpll & PLL_REF_INPUT_MASK) ==
1325 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1326 /* XXX: might not be 66MHz */
1327 i8xx_clock(66000, &clock);
1328 } else
1329 i8xx_clock(48000, &clock);
1330 } else {
1331 if (dpll & PLL_P1_DIVIDE_BY_TWO)
1332 clock.p1 = 2;
1333 else {
1334 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1335 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1336 }
1337 if (dpll & PLL_P2_DIVIDE_BY_4)
1338 clock.p2 = 4;
1339 else
1340 clock.p2 = 2;
1341
1342 i8xx_clock(48000, &clock);
1343 }
1344 }
1345
1346 /* XXX: It would be nice to validate the clocks, but we can't reuse
1347 * i830PllIsValid() because it relies on the xf86_config connector
1348 * configuration being accurate, which it isn't necessarily.
1349 */
1350
1351 return clock.dot;
1352 }
1353
1354 /** Returns the currently programmed mode of the given pipe. */
1355 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1356 struct drm_crtc *crtc)
1357 {
1358 struct drm_i915_private *dev_priv = dev->dev_private;
1359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1360 int pipe = intel_crtc->pipe;
1361 struct drm_display_mode *mode;
1362 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
1363 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
1364 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
1365 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
1366
1367 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1368 if (!mode)
1369 return NULL;
1370
1371 mode->clock = intel_crtc_clock_get(dev, crtc);
1372 mode->hdisplay = (htot & 0xffff) + 1;
1373 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1374 mode->hsync_start = (hsync & 0xffff) + 1;
1375 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1376 mode->vdisplay = (vtot & 0xffff) + 1;
1377 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1378 mode->vsync_start = (vsync & 0xffff) + 1;
1379 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1380
1381 drm_mode_set_name(mode);
1382 drm_mode_set_crtcinfo(mode, 0);
1383
1384 return mode;
1385 }
1386
1387 static void intel_crtc_destroy(struct drm_crtc *crtc)
1388 {
1389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1390
1391 drm_crtc_cleanup(crtc);
1392 kfree(intel_crtc);
1393 }
1394
1395 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
1396 .dpms = intel_crtc_dpms,
1397 .mode_fixup = intel_crtc_mode_fixup,
1398 .mode_set = intel_crtc_mode_set,
1399 .mode_set_base = intel_pipe_set_base,
1400 .prepare = intel_crtc_prepare,
1401 .commit = intel_crtc_commit,
1402 };
1403
1404 static const struct drm_crtc_funcs intel_crtc_funcs = {
1405 .cursor_set = intel_crtc_cursor_set,
1406 .cursor_move = intel_crtc_cursor_move,
1407 .gamma_set = intel_crtc_gamma_set,
1408 .set_config = drm_crtc_helper_set_config,
1409 .destroy = intel_crtc_destroy,
1410 };
1411
1412
1413 static void intel_crtc_init(struct drm_device *dev, int pipe)
1414 {
1415 struct intel_crtc *intel_crtc;
1416 int i;
1417
1418 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
1419 if (intel_crtc == NULL)
1420 return;
1421
1422 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
1423
1424 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
1425 intel_crtc->pipe = pipe;
1426 for (i = 0; i < 256; i++) {
1427 intel_crtc->lut_r[i] = i;
1428 intel_crtc->lut_g[i] = i;
1429 intel_crtc->lut_b[i] = i;
1430 }
1431
1432 intel_crtc->cursor_addr = 0;
1433 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
1434 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
1435
1436 intel_crtc->mode_set.crtc = &intel_crtc->base;
1437 intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
1438 intel_crtc->mode_set.num_connectors = 0;
1439
1440 if (i915_fbpercrtc) {
1441
1442
1443
1444 }
1445 }
1446
1447 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
1448 {
1449 struct drm_crtc *crtc = NULL;
1450
1451 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1453 if (intel_crtc->pipe == pipe)
1454 break;
1455 }
1456 return crtc;
1457 }
1458
1459 static int intel_connector_clones(struct drm_device *dev, int type_mask)
1460 {
1461 int index_mask = 0;
1462 struct drm_connector *connector;
1463 int entry = 0;
1464
1465 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1466 struct intel_output *intel_output = to_intel_output(connector);
1467 if (type_mask & (1 << intel_output->type))
1468 index_mask |= (1 << entry);
1469 entry++;
1470 }
1471 return index_mask;
1472 }
1473
1474
1475 static void intel_setup_outputs(struct drm_device *dev)
1476 {
1477 struct drm_i915_private *dev_priv = dev->dev_private;
1478 struct drm_connector *connector;
1479
1480 intel_crt_init(dev);
1481
1482 /* Set up integrated LVDS */
1483 if (IS_MOBILE(dev) && !IS_I830(dev))
1484 intel_lvds_init(dev);
1485
1486 if (IS_I9XX(dev)) {
1487 int found;
1488
1489 if (I915_READ(SDVOB) & SDVO_DETECTED) {
1490 found = intel_sdvo_init(dev, SDVOB);
1491 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1492 intel_hdmi_init(dev, SDVOB);
1493 }
1494 if (!IS_G4X(dev) || (I915_READ(SDVOB) & SDVO_DETECTED)) {
1495 found = intel_sdvo_init(dev, SDVOC);
1496 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1497 intel_hdmi_init(dev, SDVOC);
1498 }
1499 } else
1500 intel_dvo_init(dev);
1501
1502 if (IS_I9XX(dev) && IS_MOBILE(dev))
1503 intel_tv_init(dev);
1504
1505 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1506 struct intel_output *intel_output = to_intel_output(connector);
1507 struct drm_encoder *encoder = &intel_output->enc;
1508 int crtc_mask = 0, clone_mask = 0;
1509
1510 /* valid crtcs */
1511 switch(intel_output->type) {
1512 case INTEL_OUTPUT_HDMI:
1513 crtc_mask = ((1 << 0)|
1514 (1 << 1));
1515 clone_mask = ((1 << INTEL_OUTPUT_HDMI));
1516 break;
1517 case INTEL_OUTPUT_DVO:
1518 case INTEL_OUTPUT_SDVO:
1519 crtc_mask = ((1 << 0)|
1520 (1 << 1));
1521 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
1522 (1 << INTEL_OUTPUT_DVO) |
1523 (1 << INTEL_OUTPUT_SDVO));
1524 break;
1525 case INTEL_OUTPUT_ANALOG:
1526 crtc_mask = ((1 << 0)|
1527 (1 << 1));
1528 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
1529 (1 << INTEL_OUTPUT_DVO) |
1530 (1 << INTEL_OUTPUT_SDVO));
1531 break;
1532 case INTEL_OUTPUT_LVDS:
1533 crtc_mask = (1 << 1);
1534 clone_mask = (1 << INTEL_OUTPUT_LVDS);
1535 break;
1536 case INTEL_OUTPUT_TVOUT:
1537 crtc_mask = ((1 << 0) |
1538 (1 << 1));
1539 clone_mask = (1 << INTEL_OUTPUT_TVOUT);
1540 break;
1541 }
1542 encoder->possible_crtcs = crtc_mask;
1543 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
1544 }
1545 }
1546
1547 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
1548 {
1549 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1550 struct drm_device *dev = fb->dev;
1551
1552 if (fb->fbdev)
1553 intelfb_remove(dev, fb);
1554
1555 drm_framebuffer_cleanup(fb);
1556 mutex_lock(&dev->struct_mutex);
1557 drm_gem_object_unreference(intel_fb->obj);
1558 mutex_unlock(&dev->struct_mutex);
1559
1560 kfree(intel_fb);
1561 }
1562
1563 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1564 struct drm_file *file_priv,
1565 unsigned int *handle)
1566 {
1567 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1568 struct drm_gem_object *object = intel_fb->obj;
1569
1570 return drm_gem_handle_create(file_priv, object, handle);
1571 }
1572
1573 static const struct drm_framebuffer_funcs intel_fb_funcs = {
1574 .destroy = intel_user_framebuffer_destroy,
1575 .create_handle = intel_user_framebuffer_create_handle,
1576 };
1577
1578 int intel_framebuffer_create(struct drm_device *dev,
1579 struct drm_mode_fb_cmd *mode_cmd,
1580 struct drm_framebuffer **fb,
1581 struct drm_gem_object *obj)
1582 {
1583 struct intel_framebuffer *intel_fb;
1584 int ret;
1585
1586 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1587 if (!intel_fb)
1588 return -ENOMEM;
1589
1590 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
1591 if (ret) {
1592 DRM_ERROR("framebuffer init failed %d\n", ret);
1593 return ret;
1594 }
1595
1596 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
1597
1598 intel_fb->obj = obj;
1599
1600 *fb = &intel_fb->base;
1601
1602 return 0;
1603 }
1604
1605
1606 static struct drm_framebuffer *
1607 intel_user_framebuffer_create(struct drm_device *dev,
1608 struct drm_file *filp,
1609 struct drm_mode_fb_cmd *mode_cmd)
1610 {
1611 struct drm_gem_object *obj;
1612 struct drm_framebuffer *fb;
1613 int ret;
1614
1615 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
1616 if (!obj)
1617 return NULL;
1618
1619 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
1620 if (ret) {
1621 drm_gem_object_unreference(obj);
1622 return NULL;
1623 }
1624
1625 return fb;
1626 }
1627
1628 static const struct drm_mode_config_funcs intel_mode_funcs = {
1629 .fb_create = intel_user_framebuffer_create,
1630 .fb_changed = intelfb_probe,
1631 };
1632
1633 void intel_modeset_init(struct drm_device *dev)
1634 {
1635 int num_pipe;
1636 int i;
1637
1638 drm_mode_config_init(dev);
1639
1640 dev->mode_config.min_width = 0;
1641 dev->mode_config.min_height = 0;
1642
1643 dev->mode_config.funcs = (void *)&intel_mode_funcs;
1644
1645 if (IS_I965G(dev)) {
1646 dev->mode_config.max_width = 8192;
1647 dev->mode_config.max_height = 8192;
1648 } else {
1649 dev->mode_config.max_width = 2048;
1650 dev->mode_config.max_height = 2048;
1651 }
1652
1653 /* set memory base */
1654 if (IS_I9XX(dev))
1655 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
1656 else
1657 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
1658
1659 if (IS_MOBILE(dev) || IS_I9XX(dev))
1660 num_pipe = 2;
1661 else
1662 num_pipe = 1;
1663 DRM_DEBUG("%d display pipe%s available.\n",
1664 num_pipe, num_pipe > 1 ? "s" : "");
1665
1666 for (i = 0; i < num_pipe; i++) {
1667 intel_crtc_init(dev, i);
1668 }
1669
1670 intel_setup_outputs(dev);
1671 }
1672
1673 void intel_modeset_cleanup(struct drm_device *dev)
1674 {
1675 drm_mode_config_cleanup(dev);
1676 }
1677
1678
1679 /* current intel driver doesn't take advantage of encoders
1680 always give back the encoder for the connector
1681 */
1682 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
1683 {
1684 struct intel_output *intel_output = to_intel_output(connector);
1685
1686 return &intel_output->enc;
1687 }
linux 2.6 git repository for openrd