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[PATCH] tick management: make broadcast dependent on local APIC
[linux-2.6/linux-2.6-openrd.git] / drivers / mmc / sdhci.c
blob7522f76b15ec48db85c9c3091dfb4a933d2ca3ab
1 /*
2 * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 */
11
12 #include <linux/delay.h>
13 #include <linux/highmem.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
16
17 #include <linux/mmc/host.h>
18 #include <linux/mmc/protocol.h>
19
20 #include <asm/scatterlist.h>
21
22 #include "sdhci.h"
23
24 #define DRIVER_NAME "sdhci"
25
26 #define DBG(f, x...) \
27 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
28
29 static unsigned int debug_nodma = 0;
30 static unsigned int debug_forcedma = 0;
31 static unsigned int debug_quirks = 0;
32
33 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
34 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
35 /* Controller doesn't like some resets when there is no card inserted. */
36 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
37 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
38
39 static const struct pci_device_id pci_ids[] __devinitdata = {
40 {
41 .vendor = PCI_VENDOR_ID_RICOH,
42 .device = PCI_DEVICE_ID_RICOH_R5C822,
43 .subvendor = PCI_VENDOR_ID_IBM,
44 .subdevice = PCI_ANY_ID,
45 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
46 SDHCI_QUIRK_FORCE_DMA,
47 },
48
49 {
50 .vendor = PCI_VENDOR_ID_RICOH,
51 .device = PCI_DEVICE_ID_RICOH_R5C822,
52 .subvendor = PCI_ANY_ID,
53 .subdevice = PCI_ANY_ID,
54 .driver_data = SDHCI_QUIRK_FORCE_DMA |
55 SDHCI_QUIRK_NO_CARD_NO_RESET,
56 },
57
58 {
59 .vendor = PCI_VENDOR_ID_TI,
60 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
61 .subvendor = PCI_ANY_ID,
62 .subdevice = PCI_ANY_ID,
63 .driver_data = SDHCI_QUIRK_FORCE_DMA,
64 },
65
66 {
67 .vendor = PCI_VENDOR_ID_ENE,
68 .device = PCI_DEVICE_ID_ENE_CB712_SD,
69 .subvendor = PCI_ANY_ID,
70 .subdevice = PCI_ANY_ID,
71 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE,
72 },
73
74 { /* Generic SD host controller */
75 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
76 },
77
78 { /* end: all zeroes */ },
79 };
80
81 MODULE_DEVICE_TABLE(pci, pci_ids);
82
83 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
84 static void sdhci_finish_data(struct sdhci_host *);
85
86 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
87 static void sdhci_finish_command(struct sdhci_host *);
88
89 static void sdhci_dumpregs(struct sdhci_host *host)
90 {
91 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
92
93 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
94 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
95 readw(host->ioaddr + SDHCI_HOST_VERSION));
96 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
97 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
98 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
99 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
100 readl(host->ioaddr + SDHCI_ARGUMENT),
101 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
102 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
103 readl(host->ioaddr + SDHCI_PRESENT_STATE),
104 readb(host->ioaddr + SDHCI_HOST_CONTROL));
105 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
106 readb(host->ioaddr + SDHCI_POWER_CONTROL),
107 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
108 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
109 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
110 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
111 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
112 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
113 readl(host->ioaddr + SDHCI_INT_STATUS));
114 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
115 readl(host->ioaddr + SDHCI_INT_ENABLE),
116 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
117 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
118 readw(host->ioaddr + SDHCI_ACMD12_ERR),
119 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
120 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
121 readl(host->ioaddr + SDHCI_CAPABILITIES),
122 readl(host->ioaddr + SDHCI_MAX_CURRENT));
123
124 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
125 }
126
127 /*****************************************************************************\
128 * *
129 * Low level functions *
130 * *
131 \*****************************************************************************/
132
133 static void sdhci_reset(struct sdhci_host *host, u8 mask)
134 {
135 unsigned long timeout;
136
137 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
138 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
139 SDHCI_CARD_PRESENT))
140 return;
141 }
142
143 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
144
145 if (mask & SDHCI_RESET_ALL)
146 host->clock = 0;
147
148 /* Wait max 100 ms */
149 timeout = 100;
150
151 /* hw clears the bit when it's done */
152 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
153 if (timeout == 0) {
154 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
155 mmc_hostname(host->mmc), (int)mask);
156 sdhci_dumpregs(host);
157 return;
158 }
159 timeout--;
160 mdelay(1);
161 }
162 }
163
164 static void sdhci_init(struct sdhci_host *host)
165 {
166 u32 intmask;
167
168 sdhci_reset(host, SDHCI_RESET_ALL);
169
170 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
171 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
172 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
173 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
174 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
175 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
176
177 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
178 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
179 }
180
181 static void sdhci_activate_led(struct sdhci_host *host)
182 {
183 u8 ctrl;
184
185 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
186 ctrl |= SDHCI_CTRL_LED;
187 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
188 }
189
190 static void sdhci_deactivate_led(struct sdhci_host *host)
191 {
192 u8 ctrl;
193
194 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
195 ctrl &= ~SDHCI_CTRL_LED;
196 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
197 }
198
199 /*****************************************************************************\
200 * *
201 * Core functions *
202 * *
203 \*****************************************************************************/
204
205 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
206 {
207 return page_address(host->cur_sg->page) + host->cur_sg->offset;
208 }
209
210 static inline int sdhci_next_sg(struct sdhci_host* host)
211 {
212 /*
213 * Skip to next SG entry.
214 */
215 host->cur_sg++;
216 host->num_sg--;
217
218 /*
219 * Any entries left?
220 */
221 if (host->num_sg > 0) {
222 host->offset = 0;
223 host->remain = host->cur_sg->length;
224 }
225
226 return host->num_sg;
227 }
228
229 static void sdhci_read_block_pio(struct sdhci_host *host)
230 {
231 int blksize, chunk_remain;
232 u32 data;
233 char *buffer;
234 int size;
235
236 DBG("PIO reading\n");
237
238 blksize = host->data->blksz;
239 chunk_remain = 0;
240 data = 0;
241
242 buffer = sdhci_sg_to_buffer(host) + host->offset;
243
244 while (blksize) {
245 if (chunk_remain == 0) {
246 data = readl(host->ioaddr + SDHCI_BUFFER);
247 chunk_remain = min(blksize, 4);
248 }
249
250 size = min(host->size, host->remain);
251 size = min(size, chunk_remain);
252
253 chunk_remain -= size;
254 blksize -= size;
255 host->offset += size;
256 host->remain -= size;
257 host->size -= size;
258 while (size) {
259 *buffer = data & 0xFF;
260 buffer++;
261 data >>= 8;
262 size--;
263 }
264
265 if (host->remain == 0) {
266 if (sdhci_next_sg(host) == 0) {
267 BUG_ON(blksize != 0);
268 return;
269 }
270 buffer = sdhci_sg_to_buffer(host);
271 }
272 }
273 }
274
275 static void sdhci_write_block_pio(struct sdhci_host *host)
276 {
277 int blksize, chunk_remain;
278 u32 data;
279 char *buffer;
280 int bytes, size;
281
282 DBG("PIO writing\n");
283
284 blksize = host->data->blksz;
285 chunk_remain = 4;
286 data = 0;
287
288 bytes = 0;
289 buffer = sdhci_sg_to_buffer(host) + host->offset;
290
291 while (blksize) {
292 size = min(host->size, host->remain);
293 size = min(size, chunk_remain);
294
295 chunk_remain -= size;
296 blksize -= size;
297 host->offset += size;
298 host->remain -= size;
299 host->size -= size;
300 while (size) {
301 data >>= 8;
302 data |= (u32)*buffer << 24;
303 buffer++;
304 size--;
305 }
306
307 if (chunk_remain == 0) {
308 writel(data, host->ioaddr + SDHCI_BUFFER);
309 chunk_remain = min(blksize, 4);
310 }
311
312 if (host->remain == 0) {
313 if (sdhci_next_sg(host) == 0) {
314 BUG_ON(blksize != 0);
315 return;
316 }
317 buffer = sdhci_sg_to_buffer(host);
318 }
319 }
320 }
321
322 static void sdhci_transfer_pio(struct sdhci_host *host)
323 {
324 u32 mask;
325
326 BUG_ON(!host->data);
327
328 if (host->size == 0)
329 return;
330
331 if (host->data->flags & MMC_DATA_READ)
332 mask = SDHCI_DATA_AVAILABLE;
333 else
334 mask = SDHCI_SPACE_AVAILABLE;
335
336 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
337 if (host->data->flags & MMC_DATA_READ)
338 sdhci_read_block_pio(host);
339 else
340 sdhci_write_block_pio(host);
341
342 if (host->size == 0)
343 break;
344
345 BUG_ON(host->num_sg == 0);
346 }
347
348 DBG("PIO transfer complete.\n");
349 }
350
351 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
352 {
353 u8 count;
354 unsigned target_timeout, current_timeout;
355
356 WARN_ON(host->data);
357
358 if (data == NULL)
359 return;
360
361 DBG("blksz %04x blks %04x flags %08x\n",
362 data->blksz, data->blocks, data->flags);
363 DBG("tsac %d ms nsac %d clk\n",
364 data->timeout_ns / 1000000, data->timeout_clks);
365
366 /* Sanity checks */
367 BUG_ON(data->blksz * data->blocks > 524288);
368 BUG_ON(data->blksz > host->mmc->max_blk_size);
369 BUG_ON(data->blocks > 65535);
370
371 /* timeout in us */
372 target_timeout = data->timeout_ns / 1000 +
373 data->timeout_clks / host->clock;
374
375 /*
376 * Figure out needed cycles.
377 * We do this in steps in order to fit inside a 32 bit int.
378 * The first step is the minimum timeout, which will have a
379 * minimum resolution of 6 bits:
380 * (1) 2^13*1000 > 2^22,
381 * (2) host->timeout_clk < 2^16
382 * =>
383 * (1) / (2) > 2^6
384 */
385 count = 0;
386 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
387 while (current_timeout < target_timeout) {
388 count++;
389 current_timeout <<= 1;
390 if (count >= 0xF)
391 break;
392 }
393
394 if (count >= 0xF) {
395 printk(KERN_WARNING "%s: Too large timeout requested!\n",
396 mmc_hostname(host->mmc));
397 count = 0xE;
398 }
399
400 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
401
402 if (host->flags & SDHCI_USE_DMA) {
403 int count;
404
405 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
406 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
407 BUG_ON(count != 1);
408
409 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
410 } else {
411 host->size = data->blksz * data->blocks;
412
413 host->cur_sg = data->sg;
414 host->num_sg = data->sg_len;
415
416 host->offset = 0;
417 host->remain = host->cur_sg->length;
418 }
419
420 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
421 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
422 host->ioaddr + SDHCI_BLOCK_SIZE);
423 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
424 }
425
426 static void sdhci_set_transfer_mode(struct sdhci_host *host,
427 struct mmc_data *data)
428 {
429 u16 mode;
430
431 WARN_ON(host->data);
432
433 if (data == NULL)
434 return;
435
436 mode = SDHCI_TRNS_BLK_CNT_EN;
437 if (data->blocks > 1)
438 mode |= SDHCI_TRNS_MULTI;
439 if (data->flags & MMC_DATA_READ)
440 mode |= SDHCI_TRNS_READ;
441 if (host->flags & SDHCI_USE_DMA)
442 mode |= SDHCI_TRNS_DMA;
443
444 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
445 }
446
447 static void sdhci_finish_data(struct sdhci_host *host)
448 {
449 struct mmc_data *data;
450 u16 blocks;
451
452 BUG_ON(!host->data);
453
454 data = host->data;
455 host->data = NULL;
456
457 if (host->flags & SDHCI_USE_DMA) {
458 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
459 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
460 }
461
462 /*
463 * Controller doesn't count down when in single block mode.
464 */
465 if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
466 blocks = 0;
467 else
468 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
469 data->bytes_xfered = data->blksz * (data->blocks - blocks);
470
471 if ((data->error == MMC_ERR_NONE) && blocks) {
472 printk(KERN_ERR "%s: Controller signalled completion even "
473 "though there were blocks left.\n",
474 mmc_hostname(host->mmc));
475 data->error = MMC_ERR_FAILED;
476 } else if (host->size != 0) {
477 printk(KERN_ERR "%s: %d bytes were left untransferred.\n",
478 mmc_hostname(host->mmc), host->size);
479 data->error = MMC_ERR_FAILED;
480 }
481
482 DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
483
484 if (data->stop) {
485 /*
486 * The controller needs a reset of internal state machines
487 * upon error conditions.
488 */
489 if (data->error != MMC_ERR_NONE) {
490 sdhci_reset(host, SDHCI_RESET_CMD);
491 sdhci_reset(host, SDHCI_RESET_DATA);
492 }
493
494 sdhci_send_command(host, data->stop);
495 } else
496 tasklet_schedule(&host->finish_tasklet);
497 }
498
499 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
500 {
501 int flags;
502 u32 mask;
503 unsigned long timeout;
504
505 WARN_ON(host->cmd);
506
507 DBG("Sending cmd (%x)\n", cmd->opcode);
508
509 /* Wait max 10 ms */
510 timeout = 10;
511
512 mask = SDHCI_CMD_INHIBIT;
513 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
514 mask |= SDHCI_DATA_INHIBIT;
515
516 /* We shouldn't wait for data inihibit for stop commands, even
517 though they might use busy signaling */
518 if (host->mrq->data && (cmd == host->mrq->data->stop))
519 mask &= ~SDHCI_DATA_INHIBIT;
520
521 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
522 if (timeout == 0) {
523 printk(KERN_ERR "%s: Controller never released "
524 "inhibit bit(s).\n", mmc_hostname(host->mmc));
525 sdhci_dumpregs(host);
526 cmd->error = MMC_ERR_FAILED;
527 tasklet_schedule(&host->finish_tasklet);
528 return;
529 }
530 timeout--;
531 mdelay(1);
532 }
533
534 mod_timer(&host->timer, jiffies + 10 * HZ);
535
536 host->cmd = cmd;
537
538 sdhci_prepare_data(host, cmd->data);
539
540 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
541
542 sdhci_set_transfer_mode(host, cmd->data);
543
544 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
545 printk(KERN_ERR "%s: Unsupported response type!\n",
546 mmc_hostname(host->mmc));
547 cmd->error = MMC_ERR_INVALID;
548 tasklet_schedule(&host->finish_tasklet);
549 return;
550 }
551
552 if (!(cmd->flags & MMC_RSP_PRESENT))
553 flags = SDHCI_CMD_RESP_NONE;
554 else if (cmd->flags & MMC_RSP_136)
555 flags = SDHCI_CMD_RESP_LONG;
556 else if (cmd->flags & MMC_RSP_BUSY)
557 flags = SDHCI_CMD_RESP_SHORT_BUSY;
558 else
559 flags = SDHCI_CMD_RESP_SHORT;
560
561 if (cmd->flags & MMC_RSP_CRC)
562 flags |= SDHCI_CMD_CRC;
563 if (cmd->flags & MMC_RSP_OPCODE)
564 flags |= SDHCI_CMD_INDEX;
565 if (cmd->data)
566 flags |= SDHCI_CMD_DATA;
567
568 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
569 host->ioaddr + SDHCI_COMMAND);
570 }
571
572 static void sdhci_finish_command(struct sdhci_host *host)
573 {
574 int i;
575
576 BUG_ON(host->cmd == NULL);
577
578 if (host->cmd->flags & MMC_RSP_PRESENT) {
579 if (host->cmd->flags & MMC_RSP_136) {
580 /* CRC is stripped so we need to do some shifting. */
581 for (i = 0;i < 4;i++) {
582 host->cmd->resp[i] = readl(host->ioaddr +
583 SDHCI_RESPONSE + (3-i)*4) << 8;
584 if (i != 3)
585 host->cmd->resp[i] |=
586 readb(host->ioaddr +
587 SDHCI_RESPONSE + (3-i)*4-1);
588 }
589 } else {
590 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
591 }
592 }
593
594 host->cmd->error = MMC_ERR_NONE;
595
596 DBG("Ending cmd (%x)\n", host->cmd->opcode);
597
598 if (host->cmd->data)
599 host->data = host->cmd->data;
600 else
601 tasklet_schedule(&host->finish_tasklet);
602
603 host->cmd = NULL;
604 }
605
606 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
607 {
608 int div;
609 u8 ctrl;
610 u16 clk;
611 unsigned long timeout;
612
613 if (clock == host->clock)
614 return;
615
616 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
617
618 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
619 if (clock > 25000000)
620 ctrl |= SDHCI_CTRL_HISPD;
621 else
622 ctrl &= ~SDHCI_CTRL_HISPD;
623 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
624
625 if (clock == 0)
626 goto out;
627
628 for (div = 1;div < 256;div *= 2) {
629 if ((host->max_clk / div) <= clock)
630 break;
631 }
632 div >>= 1;
633
634 clk = div << SDHCI_DIVIDER_SHIFT;
635 clk |= SDHCI_CLOCK_INT_EN;
636 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
637
638 /* Wait max 10 ms */
639 timeout = 10;
640 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
641 & SDHCI_CLOCK_INT_STABLE)) {
642 if (timeout == 0) {
643 printk(KERN_ERR "%s: Internal clock never "
644 "stabilised.\n", mmc_hostname(host->mmc));
645 sdhci_dumpregs(host);
646 return;
647 }
648 timeout--;
649 mdelay(1);
650 }
651
652 clk |= SDHCI_CLOCK_CARD_EN;
653 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
654
655 out:
656 host->clock = clock;
657 }
658
659 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
660 {
661 u8 pwr;
662
663 if (host->power == power)
664 return;
665
666 if (power == (unsigned short)-1) {
667 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
668 goto out;
669 }
670
671 /*
672 * Spec says that we should clear the power reg before setting
673 * a new value. Some controllers don't seem to like this though.
674 */
675 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
676 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
677
678 pwr = SDHCI_POWER_ON;
679
680 switch (power) {
681 case MMC_VDD_170:
682 case MMC_VDD_180:
683 case MMC_VDD_190:
684 pwr |= SDHCI_POWER_180;
685 break;
686 case MMC_VDD_290:
687 case MMC_VDD_300:
688 case MMC_VDD_310:
689 pwr |= SDHCI_POWER_300;
690 break;
691 case MMC_VDD_320:
692 case MMC_VDD_330:
693 case MMC_VDD_340:
694 pwr |= SDHCI_POWER_330;
695 break;
696 default:
697 BUG();
698 }
699
700 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
701
702 out:
703 host->power = power;
704 }
705
706 /*****************************************************************************\
707 * *
708 * MMC callbacks *
709 * *
710 \*****************************************************************************/
711
712 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
713 {
714 struct sdhci_host *host;
715 unsigned long flags;
716
717 host = mmc_priv(mmc);
718
719 spin_lock_irqsave(&host->lock, flags);
720
721 WARN_ON(host->mrq != NULL);
722
723 sdhci_activate_led(host);
724
725 host->mrq = mrq;
726
727 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
728 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
729 tasklet_schedule(&host->finish_tasklet);
730 } else
731 sdhci_send_command(host, mrq->cmd);
732
733 mmiowb();
734 spin_unlock_irqrestore(&host->lock, flags);
735 }
736
737 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
738 {
739 struct sdhci_host *host;
740 unsigned long flags;
741 u8 ctrl;
742
743 host = mmc_priv(mmc);
744
745 spin_lock_irqsave(&host->lock, flags);
746
747 /*
748 * Reset the chip on each power off.
749 * Should clear out any weird states.
750 */
751 if (ios->power_mode == MMC_POWER_OFF) {
752 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
753 sdhci_init(host);
754 }
755
756 sdhci_set_clock(host, ios->clock);
757
758 if (ios->power_mode == MMC_POWER_OFF)
759 sdhci_set_power(host, -1);
760 else
761 sdhci_set_power(host, ios->vdd);
762
763 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
764 if (ios->bus_width == MMC_BUS_WIDTH_4)
765 ctrl |= SDHCI_CTRL_4BITBUS;
766 else
767 ctrl &= ~SDHCI_CTRL_4BITBUS;
768 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
769
770 mmiowb();
771 spin_unlock_irqrestore(&host->lock, flags);
772 }
773
774 static int sdhci_get_ro(struct mmc_host *mmc)
775 {
776 struct sdhci_host *host;
777 unsigned long flags;
778 int present;
779
780 host = mmc_priv(mmc);
781
782 spin_lock_irqsave(&host->lock, flags);
783
784 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
785
786 spin_unlock_irqrestore(&host->lock, flags);
787
788 return !(present & SDHCI_WRITE_PROTECT);
789 }
790
791 static const struct mmc_host_ops sdhci_ops = {
792 .request = sdhci_request,
793 .set_ios = sdhci_set_ios,
794 .get_ro = sdhci_get_ro,
795 };
796
797 /*****************************************************************************\
798 * *
799 * Tasklets *
800 * *
801 \*****************************************************************************/
802
803 static void sdhci_tasklet_card(unsigned long param)
804 {
805 struct sdhci_host *host;
806 unsigned long flags;
807
808 host = (struct sdhci_host*)param;
809
810 spin_lock_irqsave(&host->lock, flags);
811
812 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
813 if (host->mrq) {
814 printk(KERN_ERR "%s: Card removed during transfer!\n",
815 mmc_hostname(host->mmc));
816 printk(KERN_ERR "%s: Resetting controller.\n",
817 mmc_hostname(host->mmc));
818
819 sdhci_reset(host, SDHCI_RESET_CMD);
820 sdhci_reset(host, SDHCI_RESET_DATA);
821
822 host->mrq->cmd->error = MMC_ERR_FAILED;
823 tasklet_schedule(&host->finish_tasklet);
824 }
825 }
826
827 spin_unlock_irqrestore(&host->lock, flags);
828
829 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
830 }
831
832 static void sdhci_tasklet_finish(unsigned long param)
833 {
834 struct sdhci_host *host;
835 unsigned long flags;
836 struct mmc_request *mrq;
837
838 host = (struct sdhci_host*)param;
839
840 spin_lock_irqsave(&host->lock, flags);
841
842 del_timer(&host->timer);
843
844 mrq = host->mrq;
845
846 DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
847
848 /*
849 * The controller needs a reset of internal state machines
850 * upon error conditions.
851 */
852 if ((mrq->cmd->error != MMC_ERR_NONE) ||
853 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
854 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
855
856 /* Some controllers need this kick or reset won't work here */
857 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
858 unsigned int clock;
859
860 /* This is to force an update */
861 clock = host->clock;
862 host->clock = 0;
863 sdhci_set_clock(host, clock);
864 }
865
866 /* Spec says we should do both at the same time, but Ricoh
867 controllers do not like that. */
868 sdhci_reset(host, SDHCI_RESET_CMD);
869 sdhci_reset(host, SDHCI_RESET_DATA);
870 }
871
872 host->mrq = NULL;
873 host->cmd = NULL;
874 host->data = NULL;
875
876 sdhci_deactivate_led(host);
877
878 mmiowb();
879 spin_unlock_irqrestore(&host->lock, flags);
880
881 mmc_request_done(host->mmc, mrq);
882 }
883
884 static void sdhci_timeout_timer(unsigned long data)
885 {
886 struct sdhci_host *host;
887 unsigned long flags;
888
889 host = (struct sdhci_host*)data;
890
891 spin_lock_irqsave(&host->lock, flags);
892
893 if (host->mrq) {
894 printk(KERN_ERR "%s: Timeout waiting for hardware "
895 "interrupt.\n", mmc_hostname(host->mmc));
896 sdhci_dumpregs(host);
897
898 if (host->data) {
899 host->data->error = MMC_ERR_TIMEOUT;
900 sdhci_finish_data(host);
901 } else {
902 if (host->cmd)
903 host->cmd->error = MMC_ERR_TIMEOUT;
904 else
905 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
906
907 tasklet_schedule(&host->finish_tasklet);
908 }
909 }
910
911 mmiowb();
912 spin_unlock_irqrestore(&host->lock, flags);
913 }
914
915 /*****************************************************************************\
916 * *
917 * Interrupt handling *
918 * *
919 \*****************************************************************************/
920
921 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
922 {
923 BUG_ON(intmask == 0);
924
925 if (!host->cmd) {
926 printk(KERN_ERR "%s: Got command interrupt even though no "
927 "command operation was in progress.\n",
928 mmc_hostname(host->mmc));
929 sdhci_dumpregs(host);
930 return;
931 }
932
933 if (intmask & SDHCI_INT_RESPONSE)
934 sdhci_finish_command(host);
935 else {
936 if (intmask & SDHCI_INT_TIMEOUT)
937 host->cmd->error = MMC_ERR_TIMEOUT;
938 else if (intmask & SDHCI_INT_CRC)
939 host->cmd->error = MMC_ERR_BADCRC;
940 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
941 host->cmd->error = MMC_ERR_FAILED;
942 else
943 host->cmd->error = MMC_ERR_INVALID;
944
945 tasklet_schedule(&host->finish_tasklet);
946 }
947 }
948
949 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
950 {
951 BUG_ON(intmask == 0);
952
953 if (!host->data) {
954 /*
955 * A data end interrupt is sent together with the response
956 * for the stop command.
957 */
958 if (intmask & SDHCI_INT_DATA_END)
959 return;
960
961 printk(KERN_ERR "%s: Got data interrupt even though no "
962 "data operation was in progress.\n",
963 mmc_hostname(host->mmc));
964 sdhci_dumpregs(host);
965
966 return;
967 }
968
969 if (intmask & SDHCI_INT_DATA_TIMEOUT)
970 host->data->error = MMC_ERR_TIMEOUT;
971 else if (intmask & SDHCI_INT_DATA_CRC)
972 host->data->error = MMC_ERR_BADCRC;
973 else if (intmask & SDHCI_INT_DATA_END_BIT)
974 host->data->error = MMC_ERR_FAILED;
975
976 if (host->data->error != MMC_ERR_NONE)
977 sdhci_finish_data(host);
978 else {
979 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
980 sdhci_transfer_pio(host);
981
982 if (intmask & SDHCI_INT_DATA_END)
983 sdhci_finish_data(host);
984 }
985 }
986
987 static irqreturn_t sdhci_irq(int irq, void *dev_id)
988 {
989 irqreturn_t result;
990 struct sdhci_host* host = dev_id;
991 u32 intmask;
992
993 spin_lock(&host->lock);
994
995 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
996
997 if (!intmask) {
998 result = IRQ_NONE;
999 goto out;
1000 }
1001
1002 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1003
1004 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1005 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1006 host->ioaddr + SDHCI_INT_STATUS);
1007 tasklet_schedule(&host->card_tasklet);
1008 }
1009
1010 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1011
1012 if (intmask & SDHCI_INT_CMD_MASK) {
1013 writel(intmask & SDHCI_INT_CMD_MASK,
1014 host->ioaddr + SDHCI_INT_STATUS);
1015 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1016 }
1017
1018 if (intmask & SDHCI_INT_DATA_MASK) {
1019 writel(intmask & SDHCI_INT_DATA_MASK,
1020 host->ioaddr + SDHCI_INT_STATUS);
1021 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1022 }
1023
1024 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1025
1026 if (intmask & SDHCI_INT_BUS_POWER) {
1027 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1028 mmc_hostname(host->mmc));
1029 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1030 }
1031
1032 intmask &= SDHCI_INT_BUS_POWER;
1033
1034 if (intmask) {
1035 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1036 mmc_hostname(host->mmc), intmask);
1037 sdhci_dumpregs(host);
1038
1039 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1040 }
1041
1042 result = IRQ_HANDLED;
1043
1044 mmiowb();
1045 out:
1046 spin_unlock(&host->lock);
1047
1048 return result;
1049 }
1050
1051 /*****************************************************************************\
1052 * *
1053 * Suspend/resume *
1054 * *
1055 \*****************************************************************************/
1056
1057 #ifdef CONFIG_PM
1058
1059 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1060 {
1061 struct sdhci_chip *chip;
1062 int i, ret;
1063
1064 chip = pci_get_drvdata(pdev);
1065 if (!chip)
1066 return 0;
1067
1068 DBG("Suspending...\n");
1069
1070 for (i = 0;i < chip->num_slots;i++) {
1071 if (!chip->hosts[i])
1072 continue;
1073 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1074 if (ret) {
1075 for (i--;i >= 0;i--)
1076 mmc_resume_host(chip->hosts[i]->mmc);
1077 return ret;
1078 }
1079 }
1080
1081 pci_save_state(pdev);
1082 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1083 pci_disable_device(pdev);
1084 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1085
1086 return 0;
1087 }
1088
1089 static int sdhci_resume (struct pci_dev *pdev)
1090 {
1091 struct sdhci_chip *chip;
1092 int i, ret;
1093
1094 chip = pci_get_drvdata(pdev);
1095 if (!chip)
1096 return 0;
1097
1098 DBG("Resuming...\n");
1099
1100 pci_set_power_state(pdev, PCI_D0);
1101 pci_restore_state(pdev);
1102 ret = pci_enable_device(pdev);
1103 if (ret)
1104 return ret;
1105
1106 for (i = 0;i < chip->num_slots;i++) {
1107 if (!chip->hosts[i])
1108 continue;
1109 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1110 pci_set_master(pdev);
1111 sdhci_init(chip->hosts[i]);
1112 mmiowb();
1113 ret = mmc_resume_host(chip->hosts[i]->mmc);
1114 if (ret)
1115 return ret;
1116 }
1117
1118 return 0;
1119 }
1120
1121 #else /* CONFIG_PM */
1122
1123 #define sdhci_suspend NULL
1124 #define sdhci_resume NULL
1125
1126 #endif /* CONFIG_PM */
1127
1128 /*****************************************************************************\
1129 * *
1130 * Device probing/removal *
1131 * *
1132 \*****************************************************************************/
1133
1134 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1135 {
1136 int ret;
1137 unsigned int version;
1138 struct sdhci_chip *chip;
1139 struct mmc_host *mmc;
1140 struct sdhci_host *host;
1141
1142 u8 first_bar;
1143 unsigned int caps;
1144
1145 chip = pci_get_drvdata(pdev);
1146 BUG_ON(!chip);
1147
1148 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1149 if (ret)
1150 return ret;
1151
1152 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1153
1154 if (first_bar > 5) {
1155 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1156 return -ENODEV;
1157 }
1158
1159 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1160 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1161 return -ENODEV;
1162 }
1163
1164 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1165 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1166 "You may experience problems.\n");
1167 }
1168
1169 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1170 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1171 return -ENODEV;
1172 }
1173
1174 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1175 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1176 return -ENODEV;
1177 }
1178
1179 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1180 if (!mmc)
1181 return -ENOMEM;
1182
1183 host = mmc_priv(mmc);
1184 host->mmc = mmc;
1185
1186 host->chip = chip;
1187 chip->hosts[slot] = host;
1188
1189 host->bar = first_bar + slot;
1190
1191 host->addr = pci_resource_start(pdev, host->bar);
1192 host->irq = pdev->irq;
1193
1194 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1195
1196 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1197
1198 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1199 if (ret)
1200 goto free;
1201
1202 host->ioaddr = ioremap_nocache(host->addr,
1203 pci_resource_len(pdev, host->bar));
1204 if (!host->ioaddr) {
1205 ret = -ENOMEM;
1206 goto release;
1207 }
1208
1209 sdhci_reset(host, SDHCI_RESET_ALL);
1210
1211 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1212 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1213 if (version != 0) {
1214 printk(KERN_ERR "%s: Unknown controller version (%d). "
1215 "You may experience problems.\n", host->slot_descr,
1216 version);
1217 }
1218
1219 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1220
1221 if (debug_nodma)
1222 DBG("DMA forced off\n");
1223 else if (debug_forcedma) {
1224 DBG("DMA forced on\n");
1225 host->flags |= SDHCI_USE_DMA;
1226 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1227 host->flags |= SDHCI_USE_DMA;
1228 else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
1229 DBG("Controller doesn't have DMA interface\n");
1230 else if (!(caps & SDHCI_CAN_DO_DMA))
1231 DBG("Controller doesn't have DMA capability\n");
1232 else
1233 host->flags |= SDHCI_USE_DMA;
1234
1235 if (host->flags & SDHCI_USE_DMA) {
1236 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1237 printk(KERN_WARNING "%s: No suitable DMA available. "
1238 "Falling back to PIO.\n", host->slot_descr);
1239 host->flags &= ~SDHCI_USE_DMA;
1240 }
1241 }
1242
1243 if (host->flags & SDHCI_USE_DMA)
1244 pci_set_master(pdev);
1245 else /* XXX: Hack to get MMC layer to avoid highmem */
1246 pdev->dma_mask = 0;
1247
1248 host->max_clk =
1249 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1250 if (host->max_clk == 0) {
1251 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1252 "frequency.\n", host->slot_descr);
1253 ret = -ENODEV;
1254 goto unmap;
1255 }
1256 host->max_clk *= 1000000;
1257
1258 host->timeout_clk =
1259 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1260 if (host->timeout_clk == 0) {
1261 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1262 "frequency.\n", host->slot_descr);
1263 ret = -ENODEV;
1264 goto unmap;
1265 }
1266 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1267 host->timeout_clk *= 1000;
1268
1269 /*
1270 * Set host parameters.
1271 */
1272 mmc->ops = &sdhci_ops;
1273 mmc->f_min = host->max_clk / 256;
1274 mmc->f_max = host->max_clk;
1275 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1276
1277 mmc->ocr_avail = 0;
1278 if (caps & SDHCI_CAN_VDD_330)
1279 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1280 if (caps & SDHCI_CAN_VDD_300)
1281 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1282 if (caps & SDHCI_CAN_VDD_180)
1283 mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
1284
1285 if ((host->max_clk > 25000000) && !(caps & SDHCI_CAN_DO_HISPD)) {
1286 printk(KERN_ERR "%s: Controller reports > 25 MHz base clock,"
1287 " but no high speed support.\n",
1288 host->slot_descr);
1289 mmc->f_max = 25000000;
1290 }
1291
1292 if (mmc->ocr_avail == 0) {
1293 printk(KERN_ERR "%s: Hardware doesn't report any "
1294 "support voltages.\n", host->slot_descr);
1295 ret = -ENODEV;
1296 goto unmap;
1297 }
1298
1299 spin_lock_init(&host->lock);
1300
1301 /*
1302 * Maximum number of segments. Hardware cannot do scatter lists.
1303 */
1304 if (host->flags & SDHCI_USE_DMA)
1305 mmc->max_hw_segs = 1;
1306 else
1307 mmc->max_hw_segs = 16;
1308 mmc->max_phys_segs = 16;
1309
1310 /*
1311 * Maximum number of sectors in one transfer. Limited by DMA boundary
1312 * size (512KiB).
1313 */
1314 mmc->max_req_size = 524288;
1315
1316 /*
1317 * Maximum segment size. Could be one segment with the maximum number
1318 * of bytes.
1319 */
1320 mmc->max_seg_size = mmc->max_req_size;
1321
1322 /*
1323 * Maximum block size. This varies from controller to controller and
1324 * is specified in the capabilities register.
1325 */
1326 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1327 if (mmc->max_blk_size >= 3) {
1328 printk(KERN_ERR "%s: Invalid maximum block size.\n",
1329 host->slot_descr);
1330 ret = -ENODEV;
1331 goto unmap;
1332 }
1333 mmc->max_blk_size = 512 << mmc->max_blk_size;
1334
1335 /*
1336 * Maximum block count.
1337 */
1338 mmc->max_blk_count = 65535;
1339
1340 /*
1341 * Init tasklets.
1342 */
1343 tasklet_init(&host->card_tasklet,
1344 sdhci_tasklet_card, (unsigned long)host);
1345 tasklet_init(&host->finish_tasklet,
1346 sdhci_tasklet_finish, (unsigned long)host);
1347
1348 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1349
1350 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1351 host->slot_descr, host);
1352 if (ret)
1353 goto untasklet;
1354
1355 sdhci_init(host);
1356
1357 #ifdef CONFIG_MMC_DEBUG
1358 sdhci_dumpregs(host);
1359 #endif
1360
1361 mmiowb();
1362
1363 mmc_add_host(mmc);
1364
1365 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1366 host->addr, host->irq,
1367 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1368
1369 return 0;
1370
1371 untasklet:
1372 tasklet_kill(&host->card_tasklet);
1373 tasklet_kill(&host->finish_tasklet);
1374 unmap:
1375 iounmap(host->ioaddr);
1376 release:
1377 pci_release_region(pdev, host->bar);
1378 free:
1379 mmc_free_host(mmc);
1380
1381 return ret;
1382 }
1383
1384 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1385 {
1386 struct sdhci_chip *chip;
1387 struct mmc_host *mmc;
1388 struct sdhci_host *host;
1389
1390 chip = pci_get_drvdata(pdev);
1391 host = chip->hosts[slot];
1392 mmc = host->mmc;
1393
1394 chip->hosts[slot] = NULL;
1395
1396 mmc_remove_host(mmc);
1397
1398 sdhci_reset(host, SDHCI_RESET_ALL);
1399
1400 free_irq(host->irq, host);
1401
1402 del_timer_sync(&host->timer);
1403
1404 tasklet_kill(&host->card_tasklet);
1405 tasklet_kill(&host->finish_tasklet);
1406
1407 iounmap(host->ioaddr);
1408
1409 pci_release_region(pdev, host->bar);
1410
1411 mmc_free_host(mmc);
1412 }
1413
1414 static int __devinit sdhci_probe(struct pci_dev *pdev,
1415 const struct pci_device_id *ent)
1416 {
1417 int ret, i;
1418 u8 slots, rev;
1419 struct sdhci_chip *chip;
1420
1421 BUG_ON(pdev == NULL);
1422 BUG_ON(ent == NULL);
1423
1424 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1425
1426 printk(KERN_INFO DRIVER_NAME
1427 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1428 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1429 (int)rev);
1430
1431 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1432 if (ret)
1433 return ret;
1434
1435 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1436 DBG("found %d slot(s)\n", slots);
1437 if (slots == 0)
1438 return -ENODEV;
1439
1440 ret = pci_enable_device(pdev);
1441 if (ret)
1442 return ret;
1443
1444 chip = kzalloc(sizeof(struct sdhci_chip) +
1445 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1446 if (!chip) {
1447 ret = -ENOMEM;
1448 goto err;
1449 }
1450
1451 chip->pdev = pdev;
1452 chip->quirks = ent->driver_data;
1453
1454 if (debug_quirks)
1455 chip->quirks = debug_quirks;
1456
1457 chip->num_slots = slots;
1458 pci_set_drvdata(pdev, chip);
1459
1460 for (i = 0;i < slots;i++) {
1461 ret = sdhci_probe_slot(pdev, i);
1462 if (ret) {
1463 for (i--;i >= 0;i--)
1464 sdhci_remove_slot(pdev, i);
1465 goto free;
1466 }
1467 }
1468
1469 return 0;
1470
1471 free:
1472 pci_set_drvdata(pdev, NULL);
1473 kfree(chip);
1474
1475 err:
1476 pci_disable_device(pdev);
1477 return ret;
1478 }
1479
1480 static void __devexit sdhci_remove(struct pci_dev *pdev)
1481 {
1482 int i;
1483 struct sdhci_chip *chip;
1484
1485 chip = pci_get_drvdata(pdev);
1486
1487 if (chip) {
1488 for (i = 0;i < chip->num_slots;i++)
1489 sdhci_remove_slot(pdev, i);
1490
1491 pci_set_drvdata(pdev, NULL);
1492
1493 kfree(chip);
1494 }
1495
1496 pci_disable_device(pdev);
1497 }
1498
1499 static struct pci_driver sdhci_driver = {
1500 .name = DRIVER_NAME,
1501 .id_table = pci_ids,
1502 .probe = sdhci_probe,
1503 .remove = __devexit_p(sdhci_remove),
1504 .suspend = sdhci_suspend,
1505 .resume = sdhci_resume,
1506 };
1507
1508 /*****************************************************************************\
1509 * *
1510 * Driver init/exit *
1511 * *
1512 \*****************************************************************************/
1513
1514 static int __init sdhci_drv_init(void)
1515 {
1516 printk(KERN_INFO DRIVER_NAME
1517 ": Secure Digital Host Controller Interface driver\n");
1518 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1519
1520 return pci_register_driver(&sdhci_driver);
1521 }
1522
1523 static void __exit sdhci_drv_exit(void)
1524 {
1525 DBG("Exiting\n");
1526
1527 pci_unregister_driver(&sdhci_driver);
1528 }
1529
1530 module_init(sdhci_drv_init);
1531 module_exit(sdhci_drv_exit);
1532
1533 module_param(debug_nodma, uint, 0444);
1534 module_param(debug_forcedma, uint, 0444);
1535 module_param(debug_quirks, uint, 0444);
1536
1537 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1538 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1539 MODULE_LICENSE("GPL");
1540
1541 MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1542 MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
1543 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
linux 2.6 git repository for openrd