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[PATCH] tick management: make broadcast dependent on local APIC
[linux-2.6/linux-2.6-openrd.git] / drivers / mmc / pxamci.c
blob9774fc68b61a0c56cae19d96276aab5bd18e56cc
1 /*
2 * linux/drivers/mmc/pxa.c - PXA MMCI driver
3 *
4 * Copyright (C) 2003 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This hardware is really sick:
11 * - No way to clear interrupts.
12 * - Have to turn off the clock whenever we touch the device.
13 * - Doesn't tell you how many data blocks were transferred.
14 * Yuck!
15 *
16 * 1 and 3 byte data transfers not supported
17 * max block length up to 1023
18 */
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/ioport.h>
22 #include <linux/platform_device.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/protocol.h>
28
29 #include <asm/dma.h>
30 #include <asm/io.h>
31 #include <asm/scatterlist.h>
32 #include <asm/sizes.h>
33
34 #include <asm/arch/pxa-regs.h>
35 #include <asm/arch/mmc.h>
36
37 #include "pxamci.h"
38
39 #define DRIVER_NAME "pxa2xx-mci"
40
41 #define NR_SG 1
42
43 struct pxamci_host {
44 struct mmc_host *mmc;
45 spinlock_t lock;
46 struct resource *res;
47 void __iomem *base;
48 int irq;
49 int dma;
50 unsigned int clkrt;
51 unsigned int cmdat;
52 unsigned int imask;
53 unsigned int power_mode;
54 struct pxamci_platform_data *pdata;
55
56 struct mmc_request *mrq;
57 struct mmc_command *cmd;
58 struct mmc_data *data;
59
60 dma_addr_t sg_dma;
61 struct pxa_dma_desc *sg_cpu;
62 unsigned int dma_len;
63
64 unsigned int dma_dir;
65 };
66
67 static void pxamci_stop_clock(struct pxamci_host *host)
68 {
69 if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
70 unsigned long timeout = 10000;
71 unsigned int v;
72
73 writel(STOP_CLOCK, host->base + MMC_STRPCL);
74
75 do {
76 v = readl(host->base + MMC_STAT);
77 if (!(v & STAT_CLK_EN))
78 break;
79 udelay(1);
80 } while (timeout--);
81
82 if (v & STAT_CLK_EN)
83 dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
84 }
85 }
86
87 static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
88 {
89 unsigned long flags;
90
91 spin_lock_irqsave(&host->lock, flags);
92 host->imask &= ~mask;
93 writel(host->imask, host->base + MMC_I_MASK);
94 spin_unlock_irqrestore(&host->lock, flags);
95 }
96
97 static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
98 {
99 unsigned long flags;
100
101 spin_lock_irqsave(&host->lock, flags);
102 host->imask |= mask;
103 writel(host->imask, host->base + MMC_I_MASK);
104 spin_unlock_irqrestore(&host->lock, flags);
105 }
106
107 static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
108 {
109 unsigned int nob = data->blocks;
110 unsigned long long clks;
111 unsigned int timeout;
112 u32 dcmd;
113 int i;
114
115 host->data = data;
116
117 if (data->flags & MMC_DATA_STREAM)
118 nob = 0xffff;
119
120 writel(nob, host->base + MMC_NOB);
121 writel(data->blksz, host->base + MMC_BLKLEN);
122
123 clks = (unsigned long long)data->timeout_ns * CLOCKRATE;
124 do_div(clks, 1000000000UL);
125 timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
126 writel((timeout + 255) / 256, host->base + MMC_RDTO);
127
128 if (data->flags & MMC_DATA_READ) {
129 host->dma_dir = DMA_FROM_DEVICE;
130 dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
131 DRCMRTXMMC = 0;
132 DRCMRRXMMC = host->dma | DRCMR_MAPVLD;
133 } else {
134 host->dma_dir = DMA_TO_DEVICE;
135 dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
136 DRCMRRXMMC = 0;
137 DRCMRTXMMC = host->dma | DRCMR_MAPVLD;
138 }
139
140 dcmd |= DCMD_BURST32 | DCMD_WIDTH1;
141
142 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
143 host->dma_dir);
144
145 for (i = 0; i < host->dma_len; i++) {
146 if (data->flags & MMC_DATA_READ) {
147 host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
148 host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
149 } else {
150 host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
151 host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
152 }
153 host->sg_cpu[i].dcmd = dcmd | sg_dma_len(&data->sg[i]);
154 host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
155 sizeof(struct pxa_dma_desc);
156 }
157 host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
158 wmb();
159
160 DDADR(host->dma) = host->sg_dma;
161 DCSR(host->dma) = DCSR_RUN;
162 }
163
164 static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
165 {
166 WARN_ON(host->cmd != NULL);
167 host->cmd = cmd;
168
169 if (cmd->flags & MMC_RSP_BUSY)
170 cmdat |= CMDAT_BUSY;
171
172 #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
173 switch (RSP_TYPE(mmc_resp_type(cmd))) {
174 case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
175 cmdat |= CMDAT_RESP_SHORT;
176 break;
177 case RSP_TYPE(MMC_RSP_R3):
178 cmdat |= CMDAT_RESP_R3;
179 break;
180 case RSP_TYPE(MMC_RSP_R2):
181 cmdat |= CMDAT_RESP_R2;
182 break;
183 default:
184 break;
185 }
186
187 writel(cmd->opcode, host->base + MMC_CMD);
188 writel(cmd->arg >> 16, host->base + MMC_ARGH);
189 writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
190 writel(cmdat, host->base + MMC_CMDAT);
191 writel(host->clkrt, host->base + MMC_CLKRT);
192
193 writel(START_CLOCK, host->base + MMC_STRPCL);
194
195 pxamci_enable_irq(host, END_CMD_RES);
196 }
197
198 static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
199 {
200 host->mrq = NULL;
201 host->cmd = NULL;
202 host->data = NULL;
203 mmc_request_done(host->mmc, mrq);
204 }
205
206 static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
207 {
208 struct mmc_command *cmd = host->cmd;
209 int i;
210 u32 v;
211
212 if (!cmd)
213 return 0;
214
215 host->cmd = NULL;
216
217 /*
218 * Did I mention this is Sick. We always need to
219 * discard the upper 8 bits of the first 16-bit word.
220 */
221 v = readl(host->base + MMC_RES) & 0xffff;
222 for (i = 0; i < 4; i++) {
223 u32 w1 = readl(host->base + MMC_RES) & 0xffff;
224 u32 w2 = readl(host->base + MMC_RES) & 0xffff;
225 cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
226 v = w2;
227 }
228
229 if (stat & STAT_TIME_OUT_RESPONSE) {
230 cmd->error = MMC_ERR_TIMEOUT;
231 } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
232 #ifdef CONFIG_PXA27x
233 /*
234 * workaround for erratum #42:
235 * Intel PXA27x Family Processor Specification Update Rev 001
236 */
237 if (cmd->opcode == MMC_ALL_SEND_CID ||
238 cmd->opcode == MMC_SEND_CSD ||
239 cmd->opcode == MMC_SEND_CID) {
240 /* a bogus CRC error can appear if the msb of
241 the 15 byte response is a one */
242 if ((cmd->resp[0] & 0x80000000) == 0)
243 cmd->error = MMC_ERR_BADCRC;
244 } else {
245 pr_debug("ignoring CRC from command %d - *risky*\n",cmd->opcode);
246 }
247 #else
248 cmd->error = MMC_ERR_BADCRC;
249 #endif
250 }
251
252 pxamci_disable_irq(host, END_CMD_RES);
253 if (host->data && cmd->error == MMC_ERR_NONE) {
254 pxamci_enable_irq(host, DATA_TRAN_DONE);
255 } else {
256 pxamci_finish_request(host, host->mrq);
257 }
258
259 return 1;
260 }
261
262 static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
263 {
264 struct mmc_data *data = host->data;
265
266 if (!data)
267 return 0;
268
269 DCSR(host->dma) = 0;
270 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
271 host->dma_dir);
272
273 if (stat & STAT_READ_TIME_OUT)
274 data->error = MMC_ERR_TIMEOUT;
275 else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
276 data->error = MMC_ERR_BADCRC;
277
278 /*
279 * There appears to be a hardware design bug here. There seems to
280 * be no way to find out how much data was transferred to the card.
281 * This means that if there was an error on any block, we mark all
282 * data blocks as being in error.
283 */
284 if (data->error == MMC_ERR_NONE)
285 data->bytes_xfered = data->blocks * data->blksz;
286 else
287 data->bytes_xfered = 0;
288
289 pxamci_disable_irq(host, DATA_TRAN_DONE);
290
291 host->data = NULL;
292 if (host->mrq->stop) {
293 pxamci_stop_clock(host);
294 pxamci_start_cmd(host, host->mrq->stop, 0);
295 } else {
296 pxamci_finish_request(host, host->mrq);
297 }
298
299 return 1;
300 }
301
302 static irqreturn_t pxamci_irq(int irq, void *devid)
303 {
304 struct pxamci_host *host = devid;
305 unsigned int ireg;
306 int handled = 0;
307
308 ireg = readl(host->base + MMC_I_REG);
309
310 if (ireg) {
311 unsigned stat = readl(host->base + MMC_STAT);
312
313 pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
314
315 if (ireg & END_CMD_RES)
316 handled |= pxamci_cmd_done(host, stat);
317 if (ireg & DATA_TRAN_DONE)
318 handled |= pxamci_data_done(host, stat);
319 }
320
321 return IRQ_RETVAL(handled);
322 }
323
324 static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
325 {
326 struct pxamci_host *host = mmc_priv(mmc);
327 unsigned int cmdat;
328
329 WARN_ON(host->mrq != NULL);
330
331 host->mrq = mrq;
332
333 pxamci_stop_clock(host);
334
335 cmdat = host->cmdat;
336 host->cmdat &= ~CMDAT_INIT;
337
338 if (mrq->data) {
339 pxamci_setup_data(host, mrq->data);
340
341 cmdat &= ~CMDAT_BUSY;
342 cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
343 if (mrq->data->flags & MMC_DATA_WRITE)
344 cmdat |= CMDAT_WRITE;
345
346 if (mrq->data->flags & MMC_DATA_STREAM)
347 cmdat |= CMDAT_STREAM;
348 }
349
350 pxamci_start_cmd(host, mrq->cmd, cmdat);
351 }
352
353 static int pxamci_get_ro(struct mmc_host *mmc)
354 {
355 struct pxamci_host *host = mmc_priv(mmc);
356
357 if (host->pdata && host->pdata->get_ro)
358 return host->pdata->get_ro(mmc_dev(mmc));
359 /* Host doesn't support read only detection so assume writeable */
360 return 0;
361 }
362
363 static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
364 {
365 struct pxamci_host *host = mmc_priv(mmc);
366
367 if (ios->clock) {
368 unsigned int clk = CLOCKRATE / ios->clock;
369 if (CLOCKRATE / clk > ios->clock)
370 clk <<= 1;
371 host->clkrt = fls(clk) - 1;
372 pxa_set_cken(CKEN12_MMC, 1);
373
374 /*
375 * we write clkrt on the next command
376 */
377 } else {
378 pxamci_stop_clock(host);
379 pxa_set_cken(CKEN12_MMC, 0);
380 }
381
382 if (host->power_mode != ios->power_mode) {
383 host->power_mode = ios->power_mode;
384
385 if (host->pdata && host->pdata->setpower)
386 host->pdata->setpower(mmc_dev(mmc), ios->vdd);
387
388 if (ios->power_mode == MMC_POWER_ON)
389 host->cmdat |= CMDAT_INIT;
390 }
391
392 pr_debug("PXAMCI: clkrt = %x cmdat = %x\n",
393 host->clkrt, host->cmdat);
394 }
395
396 static const struct mmc_host_ops pxamci_ops = {
397 .request = pxamci_request,
398 .get_ro = pxamci_get_ro,
399 .set_ios = pxamci_set_ios,
400 };
401
402 static void pxamci_dma_irq(int dma, void *devid)
403 {
404 printk(KERN_ERR "DMA%d: IRQ???\n", dma);
405 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
406 }
407
408 static irqreturn_t pxamci_detect_irq(int irq, void *devid)
409 {
410 struct pxamci_host *host = mmc_priv(devid);
411
412 mmc_detect_change(devid, host->pdata->detect_delay);
413 return IRQ_HANDLED;
414 }
415
416 static int pxamci_probe(struct platform_device *pdev)
417 {
418 struct mmc_host *mmc;
419 struct pxamci_host *host = NULL;
420 struct resource *r;
421 int ret, irq;
422
423 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
424 irq = platform_get_irq(pdev, 0);
425 if (!r || irq < 0)
426 return -ENXIO;
427
428 r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
429 if (!r)
430 return -EBUSY;
431
432 mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
433 if (!mmc) {
434 ret = -ENOMEM;
435 goto out;
436 }
437
438 mmc->ops = &pxamci_ops;
439 mmc->f_min = CLOCKRATE_MIN;
440 mmc->f_max = CLOCKRATE_MAX;
441
442 /*
443 * We can do SG-DMA, but we don't because we never know how much
444 * data we successfully wrote to the card.
445 */
446 mmc->max_phys_segs = NR_SG;
447
448 /*
449 * Our hardware DMA can handle a maximum of one page per SG entry.
450 */
451 mmc->max_seg_size = PAGE_SIZE;
452
453 /*
454 * Block length register is 10 bits.
455 */
456 mmc->max_blk_size = 1023;
457
458 /*
459 * Block count register is 16 bits.
460 */
461 mmc->max_blk_count = 65535;
462
463 host = mmc_priv(mmc);
464 host->mmc = mmc;
465 host->dma = -1;
466 host->pdata = pdev->dev.platform_data;
467 mmc->ocr_avail = host->pdata ?
468 host->pdata->ocr_mask :
469 MMC_VDD_32_33|MMC_VDD_33_34;
470
471 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
472 if (!host->sg_cpu) {
473 ret = -ENOMEM;
474 goto out;
475 }
476
477 spin_lock_init(&host->lock);
478 host->res = r;
479 host->irq = irq;
480 host->imask = MMC_I_MASK_ALL;
481
482 host->base = ioremap(r->start, SZ_4K);
483 if (!host->base) {
484 ret = -ENOMEM;
485 goto out;
486 }
487
488 /*
489 * Ensure that the host controller is shut down, and setup
490 * with our defaults.
491 */
492 pxamci_stop_clock(host);
493 writel(0, host->base + MMC_SPI);
494 writel(64, host->base + MMC_RESTO);
495 writel(host->imask, host->base + MMC_I_MASK);
496
497 host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
498 pxamci_dma_irq, host);
499 if (host->dma < 0) {
500 ret = -EBUSY;
501 goto out;
502 }
503
504 ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
505 if (ret)
506 goto out;
507
508 platform_set_drvdata(pdev, mmc);
509
510 if (host->pdata && host->pdata->init)
511 host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
512
513 mmc_add_host(mmc);
514
515 return 0;
516
517 out:
518 if (host) {
519 if (host->dma >= 0)
520 pxa_free_dma(host->dma);
521 if (host->base)
522 iounmap(host->base);
523 if (host->sg_cpu)
524 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
525 }
526 if (mmc)
527 mmc_free_host(mmc);
528 release_resource(r);
529 return ret;
530 }
531
532 static int pxamci_remove(struct platform_device *pdev)
533 {
534 struct mmc_host *mmc = platform_get_drvdata(pdev);
535
536 platform_set_drvdata(pdev, NULL);
537
538 if (mmc) {
539 struct pxamci_host *host = mmc_priv(mmc);
540
541 if (host->pdata && host->pdata->exit)
542 host->pdata->exit(&pdev->dev, mmc);
543
544 mmc_remove_host(mmc);
545
546 pxamci_stop_clock(host);
547 writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
548 END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
549 host->base + MMC_I_MASK);
550
551 DRCMRRXMMC = 0;
552 DRCMRTXMMC = 0;
553
554 free_irq(host->irq, host);
555 pxa_free_dma(host->dma);
556 iounmap(host->base);
557 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
558
559 release_resource(host->res);
560
561 mmc_free_host(mmc);
562 }
563 return 0;
564 }
565
566 #ifdef CONFIG_PM
567 static int pxamci_suspend(struct platform_device *dev, pm_message_t state)
568 {
569 struct mmc_host *mmc = platform_get_drvdata(dev);
570 int ret = 0;
571
572 if (mmc)
573 ret = mmc_suspend_host(mmc, state);
574
575 return ret;
576 }
577
578 static int pxamci_resume(struct platform_device *dev)
579 {
580 struct mmc_host *mmc = platform_get_drvdata(dev);
581 int ret = 0;
582
583 if (mmc)
584 ret = mmc_resume_host(mmc);
585
586 return ret;
587 }
588 #else
589 #define pxamci_suspend NULL
590 #define pxamci_resume NULL
591 #endif
592
593 static struct platform_driver pxamci_driver = {
594 .probe = pxamci_probe,
595 .remove = pxamci_remove,
596 .suspend = pxamci_suspend,
597 .resume = pxamci_resume,
598 .driver = {
599 .name = DRIVER_NAME,
600 },
601 };
602
603 static int __init pxamci_init(void)
604 {
605 return platform_driver_register(&pxamci_driver);
606 }
607
608 static void __exit pxamci_exit(void)
609 {
610 platform_driver_unregister(&pxamci_driver);
611 }
612
613 module_init(pxamci_init);
614 module_exit(pxamci_exit);
615
616 MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
617 MODULE_LICENSE("GPL");
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