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mfd: fix undefined twl4030-power resconfig value checks
[linux-2.6/linux-2.6-openrd.git] / include / linux / i2c / twl4030.h
blob8a4a58ff8dadc82f30ed01c22b6a90c829b5d894
1 /*
2 * twl4030.h - header for TWL4030 PM and audio CODEC device
3 *
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
5 *
6 * Based on tlv320aic23.c:
7 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25 #ifndef __TWL4030_H_
26 #define __TWL4030_H_
27
28 #include <linux/types.h>
29 #include <linux/input/matrix_keypad.h>
30
31 /*
32 * Using the twl4030 core we address registers using a pair
33 * { module id, relative register offset }
34 * which that core then maps to the relevant
35 * { i2c slave, absolute register address }
36 *
37 * The module IDs are meaningful only to the twl4030 core code,
38 * which uses them as array indices to look up the first register
39 * address each module uses within a given i2c slave.
40 */
41
42 /* Slave 0 (i2c address 0x48) */
43 #define TWL4030_MODULE_USB 0x00
44
45 /* Slave 1 (i2c address 0x49) */
46 #define TWL4030_MODULE_AUDIO_VOICE 0x01
47 #define TWL4030_MODULE_GPIO 0x02
48 #define TWL4030_MODULE_INTBR 0x03
49 #define TWL4030_MODULE_PIH 0x04
50 #define TWL4030_MODULE_TEST 0x05
51
52 /* Slave 2 (i2c address 0x4a) */
53 #define TWL4030_MODULE_KEYPAD 0x06
54 #define TWL4030_MODULE_MADC 0x07
55 #define TWL4030_MODULE_INTERRUPTS 0x08
56 #define TWL4030_MODULE_LED 0x09
57 #define TWL4030_MODULE_MAIN_CHARGE 0x0A
58 #define TWL4030_MODULE_PRECHARGE 0x0B
59 #define TWL4030_MODULE_PWM0 0x0C
60 #define TWL4030_MODULE_PWM1 0x0D
61 #define TWL4030_MODULE_PWMA 0x0E
62 #define TWL4030_MODULE_PWMB 0x0F
63
64 /* Slave 3 (i2c address 0x4b) */
65 #define TWL4030_MODULE_BACKUP 0x10
66 #define TWL4030_MODULE_INT 0x11
67 #define TWL4030_MODULE_PM_MASTER 0x12
68 #define TWL4030_MODULE_PM_RECEIVER 0x13
69 #define TWL4030_MODULE_RTC 0x14
70 #define TWL4030_MODULE_SECURED_REG 0x15
71
72 /*
73 * Read and write single 8-bit registers
74 */
75 int twl4030_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
76 int twl4030_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
77
78 /*
79 * Read and write several 8-bit registers at once.
80 *
81 * IMPORTANT: For twl4030_i2c_write(), allocate num_bytes + 1
82 * for the value, and populate your data starting at offset 1.
83 */
84 int twl4030_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
85 int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
86
87 /*----------------------------------------------------------------------*/
88
89 /*
90 * NOTE: at up to 1024 registers, this is a big chip.
91 *
92 * Avoid putting register declarations in this file, instead of into
93 * a driver-private file, unless some of the registers in a block
94 * need to be shared with other drivers. One example is blocks that
95 * have Secondary IRQ Handler (SIH) registers.
96 */
97
98 #define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0)
99 #define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1)
100 #define TWL4030_SIH_CTRL_COR_MASK BIT(2)
101
102 /*----------------------------------------------------------------------*/
103
104 /*
105 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
106 */
107
108 #define REG_GPIODATAIN1 0x0
109 #define REG_GPIODATAIN2 0x1
110 #define REG_GPIODATAIN3 0x2
111 #define REG_GPIODATADIR1 0x3
112 #define REG_GPIODATADIR2 0x4
113 #define REG_GPIODATADIR3 0x5
114 #define REG_GPIODATAOUT1 0x6
115 #define REG_GPIODATAOUT2 0x7
116 #define REG_GPIODATAOUT3 0x8
117 #define REG_CLEARGPIODATAOUT1 0x9
118 #define REG_CLEARGPIODATAOUT2 0xA
119 #define REG_CLEARGPIODATAOUT3 0xB
120 #define REG_SETGPIODATAOUT1 0xC
121 #define REG_SETGPIODATAOUT2 0xD
122 #define REG_SETGPIODATAOUT3 0xE
123 #define REG_GPIO_DEBEN1 0xF
124 #define REG_GPIO_DEBEN2 0x10
125 #define REG_GPIO_DEBEN3 0x11
126 #define REG_GPIO_CTRL 0x12
127 #define REG_GPIOPUPDCTR1 0x13
128 #define REG_GPIOPUPDCTR2 0x14
129 #define REG_GPIOPUPDCTR3 0x15
130 #define REG_GPIOPUPDCTR4 0x16
131 #define REG_GPIOPUPDCTR5 0x17
132 #define REG_GPIO_ISR1A 0x19
133 #define REG_GPIO_ISR2A 0x1A
134 #define REG_GPIO_ISR3A 0x1B
135 #define REG_GPIO_IMR1A 0x1C
136 #define REG_GPIO_IMR2A 0x1D
137 #define REG_GPIO_IMR3A 0x1E
138 #define REG_GPIO_ISR1B 0x1F
139 #define REG_GPIO_ISR2B 0x20
140 #define REG_GPIO_ISR3B 0x21
141 #define REG_GPIO_IMR1B 0x22
142 #define REG_GPIO_IMR2B 0x23
143 #define REG_GPIO_IMR3B 0x24
144 #define REG_GPIO_EDR1 0x28
145 #define REG_GPIO_EDR2 0x29
146 #define REG_GPIO_EDR3 0x2A
147 #define REG_GPIO_EDR4 0x2B
148 #define REG_GPIO_EDR5 0x2C
149 #define REG_GPIO_SIH_CTRL 0x2D
150
151 /* Up to 18 signals are available as GPIOs, when their
152 * pins are not assigned to another use (such as ULPI/USB).
153 */
154 #define TWL4030_GPIO_MAX 18
155
156 /*----------------------------------------------------------------------*/
157
158 /*
159 * Keypad register offsets (use TWL4030_MODULE_KEYPAD)
160 * ... SIH/interrupt only
161 */
162
163 #define TWL4030_KEYPAD_KEYP_ISR1 0x11
164 #define TWL4030_KEYPAD_KEYP_IMR1 0x12
165 #define TWL4030_KEYPAD_KEYP_ISR2 0x13
166 #define TWL4030_KEYPAD_KEYP_IMR2 0x14
167 #define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */
168 #define TWL4030_KEYPAD_KEYP_EDR 0x16
169 #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
170
171 /*----------------------------------------------------------------------*/
172
173 /*
174 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
175 * ... SIH/interrupt only
176 */
177
178 #define TWL4030_MADC_ISR1 0x61
179 #define TWL4030_MADC_IMR1 0x62
180 #define TWL4030_MADC_ISR2 0x63
181 #define TWL4030_MADC_IMR2 0x64
182 #define TWL4030_MADC_SIR 0x65 /* test register */
183 #define TWL4030_MADC_EDR 0x66
184 #define TWL4030_MADC_SIH_CTRL 0x67
185
186 /*----------------------------------------------------------------------*/
187
188 /*
189 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
190 */
191
192 #define TWL4030_INTERRUPTS_BCIISR1A 0x0
193 #define TWL4030_INTERRUPTS_BCIISR2A 0x1
194 #define TWL4030_INTERRUPTS_BCIIMR1A 0x2
195 #define TWL4030_INTERRUPTS_BCIIMR2A 0x3
196 #define TWL4030_INTERRUPTS_BCIISR1B 0x4
197 #define TWL4030_INTERRUPTS_BCIISR2B 0x5
198 #define TWL4030_INTERRUPTS_BCIIMR1B 0x6
199 #define TWL4030_INTERRUPTS_BCIIMR2B 0x7
200 #define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */
201 #define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */
202 #define TWL4030_INTERRUPTS_BCIEDR1 0xa
203 #define TWL4030_INTERRUPTS_BCIEDR2 0xb
204 #define TWL4030_INTERRUPTS_BCIEDR3 0xc
205 #define TWL4030_INTERRUPTS_BCISIHCTRL 0xd
206
207 /*----------------------------------------------------------------------*/
208
209 /*
210 * Power Interrupt block register offsets (use TWL4030_MODULE_INT)
211 */
212
213 #define TWL4030_INT_PWR_ISR1 0x0
214 #define TWL4030_INT_PWR_IMR1 0x1
215 #define TWL4030_INT_PWR_ISR2 0x2
216 #define TWL4030_INT_PWR_IMR2 0x3
217 #define TWL4030_INT_PWR_SIR 0x4 /* test register */
218 #define TWL4030_INT_PWR_EDR1 0x5
219 #define TWL4030_INT_PWR_EDR2 0x6
220 #define TWL4030_INT_PWR_SIH_CTRL 0x7
221
222 /*----------------------------------------------------------------------*/
223
224 /* Power bus message definitions */
225
226 /* The TWL4030/5030 splits its power-management resources (the various
227 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
228 * P3. These groups can then be configured to transition between sleep, wait-on
229 * and active states by sending messages to the power bus. See Section 5.4.2
230 * Power Resources of TWL4030 TRM
231 */
232
233 /* Processor groups */
234 #define DEV_GRP_NULL 0x0
235 #define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
236 #define DEV_GRP_P2 0x2 /* P2: all Modem devices */
237 #define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
238
239 /* Resource groups */
240 #define RES_GRP_RES 0x0 /* Reserved */
241 #define RES_GRP_PP 0x1 /* Power providers */
242 #define RES_GRP_RC 0x2 /* Reset and control */
243 #define RES_GRP_PP_RC 0x3
244 #define RES_GRP_PR 0x4 /* Power references */
245 #define RES_GRP_PP_PR 0x5
246 #define RES_GRP_RC_PR 0x6
247 #define RES_GRP_ALL 0x7 /* All resource groups */
248
249 #define RES_TYPE2_R0 0x0
250
251 #define RES_TYPE_ALL 0x7
252
253 /* Resource states */
254 #define RES_STATE_WRST 0xF
255 #define RES_STATE_ACTIVE 0xE
256 #define RES_STATE_SLEEP 0x8
257 #define RES_STATE_OFF 0x0
258
259 /* Power resources */
260
261 /* Power providers */
262 #define RES_VAUX1 1
263 #define RES_VAUX2 2
264 #define RES_VAUX3 3
265 #define RES_VAUX4 4
266 #define RES_VMMC1 5
267 #define RES_VMMC2 6
268 #define RES_VPLL1 7
269 #define RES_VPLL2 8
270 #define RES_VSIM 9
271 #define RES_VDAC 10
272 #define RES_VINTANA1 11
273 #define RES_VINTANA2 12
274 #define RES_VINTDIG 13
275 #define RES_VIO 14
276 #define RES_VDD1 15
277 #define RES_VDD2 16
278 #define RES_VUSB_1V5 17
279 #define RES_VUSB_1V8 18
280 #define RES_VUSB_3V1 19
281 #define RES_VUSBCP 20
282 #define RES_REGEN 21
283 /* Reset and control */
284 #define RES_NRES_PWRON 22
285 #define RES_CLKEN 23
286 #define RES_SYSEN 24
287 #define RES_HFCLKOUT 25
288 #define RES_32KCLKOUT 26
289 #define RES_RESET 27
290 /* Power Reference */
291 #define RES_Main_Ref 28
292
293 #define TOTAL_RESOURCES 28
294 /*
295 * Power Bus Message Format ... these can be sent individually by Linux,
296 * but are usually part of downloaded scripts that are run when various
297 * power events are triggered.
298 *
299 * Broadcast Message (16 Bits):
300 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
301 * RES_STATE[3:0]
302 *
303 * Singular Message (16 Bits):
304 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
305 */
306
307 #define MSG_BROADCAST(devgrp, grp, type, type2, state) \
308 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
309 | (type) << 4 | (state))
310
311 #define MSG_SINGULAR(devgrp, id, state) \
312 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
313
314 /*----------------------------------------------------------------------*/
315
316 struct twl4030_bci_platform_data {
317 int *battery_tmp_tbl;
318 unsigned int tblsize;
319 };
320
321 /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
322 struct twl4030_gpio_platform_data {
323 int gpio_base;
324 unsigned irq_base, irq_end;
325
326 /* package the two LED signals as output-only GPIOs? */
327 bool use_leds;
328
329 /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
330 u8 mmc_cd;
331
332 /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
333 u32 debounce;
334
335 /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
336 * should be enabled. Else, if that bit is set in "pulldowns",
337 * that pulldown is enabled. Don't waste power by letting any
338 * digital inputs float...
339 */
340 u32 pullups;
341 u32 pulldowns;
342
343 int (*setup)(struct device *dev,
344 unsigned gpio, unsigned ngpio);
345 int (*teardown)(struct device *dev,
346 unsigned gpio, unsigned ngpio);
347 };
348
349 struct twl4030_madc_platform_data {
350 int irq_line;
351 };
352
353 /* Boards have uniqe mappings of {row, col} --> keycode.
354 * Column and row are 8 bits each, but range only from 0..7.
355 * a PERSISTENT_KEY is "always on" and never reported.
356 */
357 #define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED)
358
359 struct twl4030_keypad_data {
360 const struct matrix_keymap_data *keymap_data;
361 unsigned rows;
362 unsigned cols;
363 bool rep;
364 };
365
366 enum twl4030_usb_mode {
367 T2_USB_MODE_ULPI = 1,
368 T2_USB_MODE_CEA2011_3PIN = 2,
369 };
370
371 struct twl4030_usb_data {
372 enum twl4030_usb_mode usb_mode;
373 };
374
375 struct twl4030_ins {
376 u16 pmb_message;
377 u8 delay;
378 };
379
380 struct twl4030_script {
381 struct twl4030_ins *script;
382 unsigned size;
383 u8 flags;
384 #define TWL4030_WRST_SCRIPT (1<<0)
385 #define TWL4030_WAKEUP12_SCRIPT (1<<1)
386 #define TWL4030_WAKEUP3_SCRIPT (1<<2)
387 #define TWL4030_SLEEP_SCRIPT (1<<3)
388 };
389
390 struct twl4030_resconfig {
391 u8 resource;
392 u8 devgroup; /* Processor group that Power resource belongs to */
393 u8 type; /* Power resource addressed, 6 / broadcast message */
394 u8 type2; /* Power resource addressed, 3 / broadcast message */
395 u8 remap_off; /* off state remapping */
396 u8 remap_sleep; /* sleep state remapping */
397 };
398
399 struct twl4030_power_data {
400 struct twl4030_script **scripts;
401 unsigned num;
402 struct twl4030_resconfig *resource_config;
403 #define TWL4030_RESCONFIG_UNDEF ((u8)-1)
404 };
405
406 extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
407
408 struct twl4030_codec_audio_data {
409 unsigned int audio_mclk;
410 unsigned int ramp_delay_value;
411 unsigned int hs_extmute:1;
412 void (*set_hs_extmute)(int mute);
413 };
414
415 struct twl4030_codec_vibra_data {
416 unsigned int audio_mclk;
417 unsigned int coexist;
418 };
419
420 struct twl4030_codec_data {
421 unsigned int audio_mclk;
422 struct twl4030_codec_audio_data *audio;
423 struct twl4030_codec_vibra_data *vibra;
424 };
425
426 struct twl4030_platform_data {
427 unsigned irq_base, irq_end;
428 struct twl4030_bci_platform_data *bci;
429 struct twl4030_gpio_platform_data *gpio;
430 struct twl4030_madc_platform_data *madc;
431 struct twl4030_keypad_data *keypad;
432 struct twl4030_usb_data *usb;
433 struct twl4030_power_data *power;
434 struct twl4030_codec_data *codec;
435
436 /* LDO regulators */
437 struct regulator_init_data *vdac;
438 struct regulator_init_data *vpll1;
439 struct regulator_init_data *vpll2;
440 struct regulator_init_data *vmmc1;
441 struct regulator_init_data *vmmc2;
442 struct regulator_init_data *vsim;
443 struct regulator_init_data *vaux1;
444 struct regulator_init_data *vaux2;
445 struct regulator_init_data *vaux3;
446 struct regulator_init_data *vaux4;
447
448 /* REVISIT more to come ... _nothing_ should be hard-wired */
449 };
450
451 /*----------------------------------------------------------------------*/
452
453 int twl4030_sih_setup(int module);
454
455 /* Offsets to Power Registers */
456 #define TWL4030_VDAC_DEV_GRP 0x3B
457 #define TWL4030_VDAC_DEDICATED 0x3E
458 #define TWL4030_VAUX1_DEV_GRP 0x17
459 #define TWL4030_VAUX1_DEDICATED 0x1A
460 #define TWL4030_VAUX2_DEV_GRP 0x1B
461 #define TWL4030_VAUX2_DEDICATED 0x1E
462 #define TWL4030_VAUX3_DEV_GRP 0x1F
463 #define TWL4030_VAUX3_DEDICATED 0x22
464
465 #if defined(CONFIG_TWL4030_BCI_BATTERY) || \
466 defined(CONFIG_TWL4030_BCI_BATTERY_MODULE)
467 extern int twl4030charger_usb_en(int enable);
468 #else
469 static inline int twl4030charger_usb_en(int enable) { return 0; }
470 #endif
471
472 /*----------------------------------------------------------------------*/
473
474 /* Linux-specific regulator identifiers ... for now, we only support
475 * the LDOs, and leave the three buck converters alone. VDD1 and VDD2
476 * need to tie into hardware based voltage scaling (cpufreq etc), while
477 * VIO is generally fixed.
478 */
479
480 /* EXTERNAL dc-to-dc buck converters */
481 #define TWL4030_REG_VDD1 0
482 #define TWL4030_REG_VDD2 1
483 #define TWL4030_REG_VIO 2
484
485 /* EXTERNAL LDOs */
486 #define TWL4030_REG_VDAC 3
487 #define TWL4030_REG_VPLL1 4
488 #define TWL4030_REG_VPLL2 5 /* not on all chips */
489 #define TWL4030_REG_VMMC1 6
490 #define TWL4030_REG_VMMC2 7 /* not on all chips */
491 #define TWL4030_REG_VSIM 8 /* not on all chips */
492 #define TWL4030_REG_VAUX1 9 /* not on all chips */
493 #define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */
494 #define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */
495 #define TWL4030_REG_VAUX3 12 /* not on all chips */
496 #define TWL4030_REG_VAUX4 13 /* not on all chips */
497
498 /* INTERNAL LDOs */
499 #define TWL4030_REG_VINTANA1 14
500 #define TWL4030_REG_VINTANA2 15
501 #define TWL4030_REG_VINTDIG 16
502 #define TWL4030_REG_VUSB1V5 17
503 #define TWL4030_REG_VUSB1V8 18
504 #define TWL4030_REG_VUSB3V1 19
505
506 #endif /* End of __TWL4030_H */
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