2 * Copyright (C) 1995 Linus Torvalds
3 * Adapted from 'alpha' version by Gary Thomas
4 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 #include <linux/errno.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
15 #include <linux/stddef.h>
16 #include <linux/unistd.h>
17 #include <linux/ptrace.h>
18 #include <linux/slab.h>
19 #include <linux/user.h>
20 #include <linux/a.out.h>
21 #include <linux/tty.h>
22 #include <linux/major.h>
23 #include <linux/interrupt.h>
24 #include <linux/reboot.h>
25 #include <linux/init.h>
26 #include <linux/pci.h>
27 #include <linux/utsrelease.h>
28 #include <linux/adb.h>
29 #include <linux/module.h>
30 #include <linux/delay.h>
31 #include <linux/ide.h>
32 #include <linux/console.h>
33 #include <linux/seq_file.h>
34 #include <linux/root_dev.h>
35 #include <linux/initrd.h>
36 #include <linux/module.h>
37 #include <linux/timer.h>
40 #include <asm/pgtable.h>
43 #include <asm/pci-bridge.h>
45 #include <asm/machdep.h>
47 #include <asm/hydra.h>
48 #include <asm/sections.h>
50 #include <asm/i8259.h>
57 void rtas_indicator_progress(char *, unsigned short);
60 EXPORT_SYMBOL(_chrp_type
);
62 static struct mpic
*chrp_mpic
;
64 /* Used for doing CHRP event-scans */
65 DEFINE_PER_CPU(struct timer_list
, heartbeat_timer
);
66 unsigned long event_scan_interval
;
69 * XXX this should be in xmon.h, but putting it there means xmon.h
70 * has to include <linux/interrupt.h> (to get irqreturn_t), which
71 * causes all sorts of problems. -- paulus
73 extern irqreturn_t
xmon_irq(int, void *, struct pt_regs
*);
75 extern unsigned long loops_per_jiffy
;
78 extern struct smp_ops_t chrp_smp_ops
;
81 static const char *gg2_memtypes
[4] = {
82 "FPM", "SDRAM", "EDO", "BEDO"
84 static const char *gg2_cachesizes
[4] = {
85 "256 KB", "512 KB", "1 MB", "Reserved"
87 static const char *gg2_cachetypes
[4] = {
88 "Asynchronous", "Reserved", "Flow-Through Synchronous",
89 "Pipelined Synchronous"
91 static const char *gg2_cachemodes
[4] = {
92 "Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
95 void chrp_show_cpuinfo(struct seq_file
*m
)
99 struct device_node
*root
;
100 const char *model
= "";
102 root
= find_path_device("/");
104 model
= get_property(root
, "model", NULL
);
105 seq_printf(m
, "machine\t\t: CHRP %s\n", model
);
107 /* longtrail (goldengate) stuff */
108 if (!strncmp(model
, "IBM,LongTrail", 13)) {
109 /* VLSI VAS96011/12 `Golden Gate 2' */
111 sdramen
= (in_le32(gg2_pci_config_base
+ GG2_PCI_DRAM_CTRL
)
113 for (i
= 0; i
< (sdramen
? 4 : 6); i
++) {
114 t
= in_le32(gg2_pci_config_base
+
119 switch ((t
>>8) & 0x1f) {
142 seq_printf(m
, "memory bank %d\t: %s %s\n", i
, model
,
143 gg2_memtypes
[sdramen
? 1 : ((t
>>1) & 3)]);
146 t
= in_le32(gg2_pci_config_base
+GG2_PCI_CC_CTRL
);
147 seq_printf(m
, "board l2\t: %s %s (%s)\n",
148 gg2_cachesizes
[(t
>>7) & 3],
149 gg2_cachetypes
[(t
>>2) & 3],
150 gg2_cachemodes
[t
& 3]);
155 * Fixes for the National Semiconductor PC78308VUL SuperI/O
157 * Some versions of Open Firmware incorrectly initialize the IRQ settings
158 * for keyboard and mouse
160 static inline void __init
sio_write(u8 val
, u8 index
)
166 static inline u8 __init
sio_read(u8 index
)
172 static void __init
sio_fixup_irq(const char *name
, u8 device
, u8 level
,
175 u8 level0
, type0
, active
;
177 /* select logical device */
178 sio_write(device
, 0x07);
179 active
= sio_read(0x30);
180 level0
= sio_read(0x70);
181 type0
= sio_read(0x71);
182 if (level0
!= level
|| type0
!= type
|| !active
) {
183 printk(KERN_WARNING
"sio: %s irq level %d, type %d, %sactive: "
184 "remapping to level %d, type %d, active\n",
185 name
, level0
, type0
, !active
? "in" : "", level
, type
);
186 sio_write(0x01, 0x30);
187 sio_write(level
, 0x70);
188 sio_write(type
, 0x71);
192 static void __init
sio_init(void)
194 struct device_node
*root
;
196 if ((root
= find_path_device("/")) &&
197 !strncmp(get_property(root
, "model", NULL
), "IBM,LongTrail", 13)) {
198 /* logical device 0 (KBC/Keyboard) */
199 sio_fixup_irq("keyboard", 0, 1, 2);
200 /* select logical device 1 (KBC/Mouse) */
201 sio_fixup_irq("mouse", 1, 12, 2);
206 static void __init
pegasos_set_l2cr(void)
208 struct device_node
*np
;
210 /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
211 if (_chrp_type
!= _CHRP_Pegasos
)
214 /* Enable L2 cache if needed */
215 np
= find_type_devices("cpu");
217 unsigned int *l2cr
= (unsigned int *)
218 get_property (np
, "l2cr", NULL
);
220 printk ("Pegasos l2cr : no cpu l2cr property found\n");
223 if (!((*l2cr
) & 0x80000000)) {
224 printk ("Pegasos l2cr : L2 cache was not active, "
227 _set_L2CR((*l2cr
) | 0x80000000);
232 void __init
chrp_setup_arch(void)
234 struct device_node
*root
= find_path_device ("/");
235 char *machine
= NULL
;
237 /* init to some ~sane value until calibrate_delay() runs */
238 loops_per_jiffy
= 50000000/HZ
;
241 machine
= get_property(root
, "model", NULL
);
242 if (machine
&& strncmp(machine
, "Pegasos", 7) == 0) {
243 _chrp_type
= _CHRP_Pegasos
;
244 } else if (machine
&& strncmp(machine
, "IBM", 3) == 0) {
245 _chrp_type
= _CHRP_IBM
;
246 } else if (machine
&& strncmp(machine
, "MOT", 3) == 0) {
247 _chrp_type
= _CHRP_Motorola
;
249 /* Let's assume it is an IBM chrp if all else fails */
250 _chrp_type
= _CHRP_IBM
;
252 printk("chrp type = %x\n", _chrp_type
);
255 if (rtas_token("display-character") >= 0)
256 ppc_md
.progress
= rtas_progress
;
258 /* use RTAS time-of-day routines if available */
259 if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE
) {
260 ppc_md
.get_boot_time
= rtas_get_boot_time
;
261 ppc_md
.get_rtc_time
= rtas_get_rtc_time
;
262 ppc_md
.set_rtc_time
= rtas_set_rtc_time
;
265 #ifdef CONFIG_BLK_DEV_INITRD
266 /* this is fine for chrp */
267 initrd_below_start_ok
= 1;
270 ROOT_DEV
= Root_RAM0
;
273 ROOT_DEV
= Root_SDA2
; /* sda2 (sda1 is for the kernel) */
275 /* On pegasos, enable the L2 cache if not already done by OF */
278 /* Lookup PCI host bridges */
282 * Temporary fixes for PCI devices.
285 hydra_init(); /* Mac I/O */
288 * Fix the Super I/O configuration
292 pci_create_OF_bus_map();
295 smp_ops
= &chrp_smp_ops
;
296 #endif /* CONFIG_SMP */
299 * Print the banner, then scroll down so boot progress
300 * can be printed. -- Cort
302 if (ppc_md
.progress
) ppc_md
.progress("Linux/PPC "UTS_RELEASE
"\n", 0x0);
306 chrp_event_scan(unsigned long unused
)
308 unsigned char log
[1024];
311 /* XXX: we should loop until the hardware says no more error logs -- Cort */
312 rtas_call(rtas_token("event-scan"), 4, 1, &ret
, 0xffffffff, 0,
314 mod_timer(&__get_cpu_var(heartbeat_timer
),
315 jiffies
+ event_scan_interval
);
318 static void chrp_8259_cascade(unsigned int irq
, struct irq_desc
*desc
,
319 struct pt_regs
*regs
)
321 unsigned int cascade_irq
= i8259_irq(regs
);
322 if (cascade_irq
!= NO_IRQ
)
323 generic_handle_irq(cascade_irq
, regs
);
324 desc
->chip
->eoi(irq
);
328 * Finds the open-pic node and sets up the mpic driver.
330 static void __init
chrp_find_openpic(void)
332 struct device_node
*np
, *root
;
334 int isu_size
, idu_size
;
335 unsigned int *iranges
, *opprop
= NULL
;
337 unsigned long opaddr
;
340 np
= of_find_node_by_type(NULL
, "open-pic");
343 root
= of_find_node_by_path("/");
345 opprop
= (unsigned int *) get_property
346 (root
, "platform-open-pic", &oplen
);
347 na
= prom_n_addr_cells(root
);
349 if (opprop
&& oplen
>= na
* sizeof(unsigned int)) {
350 opaddr
= opprop
[na
-1]; /* assume 32-bit */
351 oplen
/= na
* sizeof(unsigned int);
354 if (of_address_to_resource(np
, 0, &r
)) {
361 printk(KERN_INFO
"OpenPIC at %lx\n", opaddr
);
363 iranges
= (unsigned int *) get_property(np
, "interrupt-ranges", &len
);
365 len
= 0; /* non-distributed mpic */
367 len
/= 2 * sizeof(unsigned int);
370 * The first pair of cells in interrupt-ranges refers to the
371 * IDU; subsequent pairs refer to the ISUs.
374 printk(KERN_ERR
"Insufficient addresses for distributed"
375 " OpenPIC (%d < %d)\n", oplen
, len
);
381 if (len
> 0 && iranges
[1] != 0) {
382 printk(KERN_INFO
"OpenPIC irqs %d..%d in IDU\n",
383 iranges
[0], iranges
[0] + iranges
[1] - 1);
384 idu_size
= iranges
[1];
387 isu_size
= iranges
[3];
389 chrp_mpic
= mpic_alloc(np
, opaddr
, MPIC_PRIMARY
,
390 isu_size
, 0, " MPIC ");
391 if (chrp_mpic
== NULL
) {
392 printk(KERN_ERR
"Failed to allocate MPIC structure\n");
396 for (i
= 1; i
< len
; ++i
) {
399 printk(KERN_INFO
"OpenPIC irqs %d..%d in ISU at %x\n",
400 iranges
[0], iranges
[0] + iranges
[1] - 1,
402 mpic_assign_isu(chrp_mpic
, i
- 1, opprop
[j
]);
405 mpic_init(chrp_mpic
);
406 ppc_md
.get_irq
= mpic_get_irq
;
412 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
413 static struct irqaction xmon_irqaction
= {
415 .mask
= CPU_MASK_NONE
,
416 .name
= "XMON break",
420 static void __init
chrp_find_8259(void)
422 struct device_node
*np
, *pic
= NULL
;
423 unsigned long chrp_int_ack
= 0;
424 unsigned int cascade_irq
;
426 /* Look for cascade */
427 for_each_node_by_type(np
, "interrupt-controller")
428 if (device_is_compatible(np
, "chrp,iic")) {
432 /* Ok, 8259 wasn't found. We need to handle the case where
433 * we have a pegasos that claims to be chrp but doesn't have
434 * a proper interrupt tree
436 if (pic
== NULL
&& chrp_mpic
!= NULL
) {
437 printk(KERN_ERR
"i8259: Not found in device-tree"
438 " assuming no legacy interrupts\n");
442 /* Look for intack. In a perfect world, we would look for it on
443 * the ISA bus that holds the 8259 but heh... Works that way. If
444 * we ever see a problem, we can try to re-use the pSeries code here.
445 * Also, Pegasos-type platforms don't have a proper node to start
448 for (np
= find_devices("pci"); np
!= NULL
; np
= np
->next
) {
449 unsigned int *addrp
= (unsigned int *)
450 get_property(np
, "8259-interrupt-acknowledge", NULL
);
454 chrp_int_ack
= addrp
[prom_n_addr_cells(np
)-1];
458 printk(KERN_WARNING
"Cannot find PCI interrupt acknowledge"
459 " address, polling\n");
461 i8259_init(pic
, chrp_int_ack
);
462 if (ppc_md
.get_irq
== NULL
)
463 ppc_md
.get_irq
= i8259_irq
;
464 if (chrp_mpic
!= NULL
) {
465 cascade_irq
= irq_of_parse_and_map(pic
, 0);
466 if (cascade_irq
== NO_IRQ
)
467 printk(KERN_ERR
"i8259: failed to map cascade irq\n");
469 set_irq_chained_handler(cascade_irq
,
474 void __init
chrp_init_IRQ(void)
476 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
477 struct device_node
*kbd
;
482 if (_chrp_type
== _CHRP_Pegasos
)
483 ppc_md
.get_irq
= i8259_irq
;
485 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
486 /* see if there is a keyboard in the device tree
487 with a parent of type "adb" */
488 for (kbd
= find_devices("keyboard"); kbd
; kbd
= kbd
->next
)
489 if (kbd
->parent
&& kbd
->parent
->type
490 && strcmp(kbd
->parent
->type
, "adb") == 0)
493 setup_irq(HYDRA_INT_ADB_NMI
, &xmon_irqaction
);
500 struct device_node
*device
;
501 unsigned int *p
= NULL
;
507 request_region(0x20,0x20,"pic1");
508 request_region(0xa0,0x20,"pic2");
509 request_region(0x00,0x20,"dma1");
510 request_region(0x40,0x20,"timer");
511 request_region(0x80,0x10,"dma page reg");
512 request_region(0xc0,0x20,"dma2");
514 /* Get the event scan rate for the rtas so we know how
515 * often it expects a heartbeat. -- Cort
517 device
= find_devices("rtas");
519 p
= (unsigned int *) get_property
520 (device
, "rtas-event-scan-rate", NULL
);
523 * Arrange to call chrp_event_scan at least *p times
524 * per minute. We use 59 rather than 60 here so that
525 * the rate will be slightly higher than the minimum.
526 * This all assumes we don't do hotplug CPU on any
527 * machine that needs the event scans done.
529 unsigned long interval
, offset
;
531 struct timer_list
*timer
;
533 interval
= HZ
* 59 / *p
;
535 ncpus
= num_online_cpus();
536 event_scan_interval
= ncpus
* interval
;
537 for (cpu
= 0; cpu
< ncpus
; ++cpu
) {
538 timer
= &per_cpu(heartbeat_timer
, cpu
);
539 setup_timer(timer
, chrp_event_scan
, 0);
540 timer
->expires
= jiffies
+ offset
;
541 add_timer_on(timer
, cpu
);
544 printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
549 ppc_md
.progress(" Have fun! ", 0x7777);
552 static int __init
chrp_probe(void)
554 char *dtype
= of_get_flat_dt_prop(of_get_flat_dt_root(),
555 "device_type", NULL
);
558 if (strcmp(dtype
, "chrp"))
561 ISA_DMA_THRESHOLD
= ~0L;
562 DMA_MODE_READ
= 0x44;
563 DMA_MODE_WRITE
= 0x48;
564 isa_io_base
= CHRP_ISA_IO_BASE
; /* default value */
569 define_machine(chrp
) {
572 .setup_arch
= chrp_setup_arch
,
574 .show_cpuinfo
= chrp_show_cpuinfo
,
575 .init_IRQ
= chrp_init_IRQ
,
576 .pcibios_fixup
= chrp_pcibios_fixup
,
577 .restart
= rtas_restart
,
578 .power_off
= rtas_power_off
,
580 .time_init
= chrp_time_init
,
581 .set_rtc_time
= chrp_set_rtc_time
,
582 .get_rtc_time
= chrp_get_rtc_time
,
583 .calibrate_decr
= generic_calibrate_decr
,
584 .phys_mem_access_prot
= pci_phys_mem_access_prot
,