2 * OmniVision OV96xx Camera Driver
4 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
6 * Based on ov772x camera driver:
8 * Copyright (C) 2008 Renesas Solutions Corp.
9 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
11 * Based on ov7670 and soc_camera_platform driver,
13 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
14 * Copyright (C) 2008 Magnus Damm
15 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/videodev2.h>
28 #include <media/v4l2-chip-ident.h>
29 #include <media/v4l2-common.h>
30 #include <media/soc_camera.h>
34 /* default register setup */
35 static const struct ov9640_reg ov9640_regs_dflt
[] = {
36 { OV9640_COM5
, OV9640_COM5_SYSCLK
| OV9640_COM5_LONGEXP
},
37 { OV9640_COM6
, OV9640_COM6_OPT_BLC
| OV9640_COM6_ADBLC_BIAS
|
38 OV9640_COM6_FMT_RST
| OV9640_COM6_ADBLC_OPTEN
},
39 { OV9640_PSHFT
, OV9640_PSHFT_VAL(0x01) },
40 { OV9640_ACOM
, OV9640_ACOM_2X_ANALOG
| OV9640_ACOM_RSVD
},
41 { OV9640_TSLB
, OV9640_TSLB_YUYV_UYVY
},
42 { OV9640_COM16
, OV9640_COM16_RB_AVG
},
45 { 0x6c, 0x40 }, { 0x6d, 0x30 }, { 0x6e, 0x4b }, { 0x6f, 0x60 },
46 { 0x70, 0x70 }, { 0x71, 0x70 }, { 0x72, 0x70 }, { 0x73, 0x70 },
47 { 0x74, 0x60 }, { 0x75, 0x60 }, { 0x76, 0x50 }, { 0x77, 0x48 },
48 { 0x78, 0x3a }, { 0x79, 0x2e }, { 0x7a, 0x28 }, { 0x7b, 0x22 },
51 { 0x7c, 0x04 }, { 0x7d, 0x07 }, { 0x7e, 0x10 }, { 0x7f, 0x28 },
52 { 0x80, 0x36 }, { 0x81, 0x44 }, { 0x82, 0x52 }, { 0x83, 0x60 },
53 { 0x84, 0x6c }, { 0x85, 0x78 }, { 0x86, 0x8c }, { 0x87, 0x9e },
54 { 0x88, 0xbb }, { 0x89, 0xd2 }, { 0x8a, 0xe6 },
58 * NOTE: for YUV, alter the following registers:
59 * COM12 |= OV9640_COM12_YUV_AVG
61 * for RGB, alter the following registers:
62 * COM7 |= OV9640_COM7_RGB
63 * COM13 |= OV9640_COM13_RGB_AVG
64 * COM15 |= proper RGB color encoding mode
66 static const struct ov9640_reg ov9640_regs_qqcif
[] = {
67 { OV9640_CLKRC
, OV9640_CLKRC_DPLL_EN
| OV9640_CLKRC_DIV(0x0f) },
68 { OV9640_COM1
, OV9640_COM1_QQFMT
| OV9640_COM1_HREF_2SKIP
},
69 { OV9640_COM4
, OV9640_COM4_QQ_VP
| OV9640_COM4_RSVD
},
70 { OV9640_COM7
, OV9640_COM7_QCIF
},
71 { OV9640_COM12
, OV9640_COM12_RSVD
},
72 { OV9640_COM13
, OV9640_COM13_GAMMA_RAW
| OV9640_COM13_MATRIX_EN
},
73 { OV9640_COM15
, OV9640_COM15_OR_10F0
},
76 static const struct ov9640_reg ov9640_regs_qqvga
[] = {
77 { OV9640_CLKRC
, OV9640_CLKRC_DPLL_EN
| OV9640_CLKRC_DIV(0x07) },
78 { OV9640_COM1
, OV9640_COM1_QQFMT
| OV9640_COM1_HREF_2SKIP
},
79 { OV9640_COM4
, OV9640_COM4_QQ_VP
| OV9640_COM4_RSVD
},
80 { OV9640_COM7
, OV9640_COM7_QVGA
},
81 { OV9640_COM12
, OV9640_COM12_RSVD
},
82 { OV9640_COM13
, OV9640_COM13_GAMMA_RAW
| OV9640_COM13_MATRIX_EN
},
83 { OV9640_COM15
, OV9640_COM15_OR_10F0
},
86 static const struct ov9640_reg ov9640_regs_qcif
[] = {
87 { OV9640_CLKRC
, OV9640_CLKRC_DPLL_EN
| OV9640_CLKRC_DIV(0x07) },
88 { OV9640_COM4
, OV9640_COM4_QQ_VP
| OV9640_COM4_RSVD
},
89 { OV9640_COM7
, OV9640_COM7_QCIF
},
90 { OV9640_COM12
, OV9640_COM12_RSVD
},
91 { OV9640_COM13
, OV9640_COM13_GAMMA_RAW
| OV9640_COM13_MATRIX_EN
},
92 { OV9640_COM15
, OV9640_COM15_OR_10F0
},
95 static const struct ov9640_reg ov9640_regs_qvga
[] = {
96 { OV9640_CLKRC
, OV9640_CLKRC_DPLL_EN
| OV9640_CLKRC_DIV(0x03) },
97 { OV9640_COM4
, OV9640_COM4_QQ_VP
| OV9640_COM4_RSVD
},
98 { OV9640_COM7
, OV9640_COM7_QVGA
},
99 { OV9640_COM12
, OV9640_COM12_RSVD
},
100 { OV9640_COM13
, OV9640_COM13_GAMMA_RAW
| OV9640_COM13_MATRIX_EN
},
101 { OV9640_COM15
, OV9640_COM15_OR_10F0
},
104 static const struct ov9640_reg ov9640_regs_cif
[] = {
105 { OV9640_CLKRC
, OV9640_CLKRC_DPLL_EN
| OV9640_CLKRC_DIV(0x03) },
106 { OV9640_COM3
, OV9640_COM3_VP
},
107 { OV9640_COM7
, OV9640_COM7_CIF
},
108 { OV9640_COM12
, OV9640_COM12_RSVD
},
109 { OV9640_COM13
, OV9640_COM13_GAMMA_RAW
| OV9640_COM13_MATRIX_EN
},
110 { OV9640_COM15
, OV9640_COM15_OR_10F0
},
113 static const struct ov9640_reg ov9640_regs_vga
[] = {
114 { OV9640_CLKRC
, OV9640_CLKRC_DPLL_EN
| OV9640_CLKRC_DIV(0x01) },
115 { OV9640_COM3
, OV9640_COM3_VP
},
116 { OV9640_COM7
, OV9640_COM7_VGA
},
117 { OV9640_COM12
, OV9640_COM12_RSVD
},
118 { OV9640_COM13
, OV9640_COM13_GAMMA_RAW
| OV9640_COM13_MATRIX_EN
},
119 { OV9640_COM15
, OV9640_COM15_OR_10F0
},
122 static const struct ov9640_reg ov9640_regs_sxga
[] = {
123 { OV9640_CLKRC
, OV9640_CLKRC_DPLL_EN
| OV9640_CLKRC_DIV(0x01) },
124 { OV9640_COM3
, OV9640_COM3_VP
},
126 { OV9640_COM12
, OV9640_COM12_RSVD
},
127 { OV9640_COM13
, OV9640_COM13_GAMMA_RAW
| OV9640_COM13_MATRIX_EN
},
128 { OV9640_COM15
, OV9640_COM15_OR_10F0
},
131 static const struct ov9640_reg ov9640_regs_yuv
[] = {
132 { OV9640_MTX1
, 0x58 },
133 { OV9640_MTX2
, 0x48 },
134 { OV9640_MTX3
, 0x10 },
135 { OV9640_MTX4
, 0x28 },
136 { OV9640_MTX5
, 0x48 },
137 { OV9640_MTX6
, 0x70 },
138 { OV9640_MTX7
, 0x40 },
139 { OV9640_MTX8
, 0x40 },
140 { OV9640_MTX9
, 0x40 },
141 { OV9640_MTXS
, 0x0f },
144 static const struct ov9640_reg ov9640_regs_rgb
[] = {
145 { OV9640_MTX1
, 0x71 },
146 { OV9640_MTX2
, 0x3e },
147 { OV9640_MTX3
, 0x0c },
148 { OV9640_MTX4
, 0x33 },
149 { OV9640_MTX5
, 0x72 },
150 { OV9640_MTX6
, 0x00 },
151 { OV9640_MTX7
, 0x2b },
152 { OV9640_MTX8
, 0x66 },
153 { OV9640_MTX9
, 0xd2 },
154 { OV9640_MTXS
, 0x65 },
158 * TODO: this sensor also supports RGB555 and RGB565 formats, but support for
159 * them has not yet been sufficiently tested and so it is not included with
160 * this version of the driver. To test and debug these formats add two entries
161 * to the below array, see ov722x.c for an example.
163 static const struct soc_camera_data_format ov9640_fmt_lists
[] = {
166 .fourcc
= V4L2_PIX_FMT_UYVY
,
168 .colorspace
= V4L2_COLORSPACE_JPEG
,
172 static const struct v4l2_queryctrl ov9640_controls
[] = {
174 .id
= V4L2_CID_VFLIP
,
175 .type
= V4L2_CTRL_TYPE_BOOLEAN
,
176 .name
= "Flip Vertically",
183 .id
= V4L2_CID_HFLIP
,
184 .type
= V4L2_CTRL_TYPE_BOOLEAN
,
185 .name
= "Flip Horizontally",
193 /* read a register */
194 static int ov9640_reg_read(struct i2c_client
*client
, u8 reg
, u8
*val
)
198 struct i2c_msg msg
= {
199 .addr
= client
->addr
,
205 ret
= i2c_transfer(client
->adapter
, &msg
, 1);
209 msg
.flags
= I2C_M_RD
;
210 ret
= i2c_transfer(client
->adapter
, &msg
, 1);
218 dev_err(&client
->dev
, "Failed reading register 0x%02x!\n", reg
);
222 /* write a register */
223 static int ov9640_reg_write(struct i2c_client
*client
, u8 reg
, u8 val
)
227 unsigned char data
[2] = { reg
, val
};
228 struct i2c_msg msg
= {
229 .addr
= client
->addr
,
235 ret
= i2c_transfer(client
->adapter
, &msg
, 1);
237 dev_err(&client
->dev
, "Failed writing register 0x%02x!\n", reg
);
241 /* we have to read the register back ... no idea why, maybe HW bug */
242 ret
= ov9640_reg_read(client
, reg
, &_val
);
244 dev_err(&client
->dev
,
245 "Failed reading back register 0x%02x!\n", reg
);
251 /* Read a register, alter its bits, write it back */
252 static int ov9640_reg_rmw(struct i2c_client
*client
, u8 reg
, u8 set
, u8 unset
)
257 ret
= ov9640_reg_read(client
, reg
, &val
);
259 dev_err(&client
->dev
,
260 "[Read]-Modify-Write of register %02x failed!\n", reg
);
267 ret
= ov9640_reg_write(client
, reg
, val
);
269 dev_err(&client
->dev
,
270 "Read-Modify-[Write] of register %02x failed!\n", reg
);
275 /* Soft reset the camera. This has nothing to do with the RESET pin! */
276 static int ov9640_reset(struct i2c_client
*client
)
280 ret
= ov9640_reg_write(client
, OV9640_COM7
, OV9640_COM7_SCCB_RESET
);
282 dev_err(&client
->dev
,
283 "An error occured while entering soft reset!\n");
288 /* Start/Stop streaming from the device */
289 static int ov9640_s_stream(struct v4l2_subdev
*sd
, int enable
)
294 /* Alter bus settings on camera side */
295 static int ov9640_set_bus_param(struct soc_camera_device
*icd
,
301 /* Request bus settings on camera side */
302 static unsigned long ov9640_query_bus_param(struct soc_camera_device
*icd
)
304 struct soc_camera_link
*icl
= to_soc_camera_link(icd
);
307 * REVISIT: the camera probably can do 10 bit transfers, but I don't
308 * have those pins connected on my hardware.
310 unsigned long flags
= SOCAM_PCLK_SAMPLE_RISING
| SOCAM_MASTER
|
311 SOCAM_VSYNC_ACTIVE_HIGH
| SOCAM_HSYNC_ACTIVE_HIGH
|
312 SOCAM_DATA_ACTIVE_HIGH
| SOCAM_DATAWIDTH_8
;
314 return soc_camera_apply_sensor_flags(icl
, flags
);
317 /* Get status of additional camera capabilities */
318 static int ov9640_g_ctrl(struct v4l2_subdev
*sd
, struct v4l2_control
*ctrl
)
320 struct i2c_client
*client
= sd
->priv
;
321 struct ov9640_priv
*priv
= container_of(i2c_get_clientdata(client
),
322 struct ov9640_priv
, subdev
);
326 ctrl
->value
= priv
->flag_vflip
;
329 ctrl
->value
= priv
->flag_hflip
;
335 /* Set status of additional camera capabilities */
336 static int ov9640_s_ctrl(struct v4l2_subdev
*sd
, struct v4l2_control
*ctrl
)
338 struct i2c_client
*client
= sd
->priv
;
339 struct ov9640_priv
*priv
= container_of(i2c_get_clientdata(client
),
340 struct ov9640_priv
, subdev
);
346 priv
->flag_vflip
= ctrl
->value
;
348 ret
= ov9640_reg_rmw(client
, OV9640_MVFP
,
351 ret
= ov9640_reg_rmw(client
, OV9640_MVFP
,
355 priv
->flag_hflip
= ctrl
->value
;
357 ret
= ov9640_reg_rmw(client
, OV9640_MVFP
,
360 ret
= ov9640_reg_rmw(client
, OV9640_MVFP
,
368 /* Get chip identification */
369 static int ov9640_g_chip_ident(struct v4l2_subdev
*sd
,
370 struct v4l2_dbg_chip_ident
*id
)
372 struct i2c_client
*client
= sd
->priv
;
373 struct ov9640_priv
*priv
= container_of(i2c_get_clientdata(client
),
374 struct ov9640_priv
, subdev
);
376 id
->ident
= priv
->model
;
377 id
->revision
= priv
->revision
;
382 #ifdef CONFIG_VIDEO_ADV_DEBUG
383 static int ov9640_get_register(struct v4l2_subdev
*sd
,
384 struct v4l2_dbg_register
*reg
)
386 struct i2c_client
*client
= sd
->priv
;
390 if (reg
->reg
& ~0xff)
395 ret
= ov9640_reg_read(client
, reg
->reg
, &val
);
399 reg
->val
= (__u64
)val
;
404 static int ov9640_set_register(struct v4l2_subdev
*sd
,
405 struct v4l2_dbg_register
*reg
)
407 struct i2c_client
*client
= sd
->priv
;
409 if (reg
->reg
& ~0xff || reg
->val
& ~0xff)
412 return ov9640_reg_write(client
, reg
->reg
, reg
->val
);
416 /* select nearest higher resolution for capture */
417 static void ov9640_res_roundup(u32
*width
, u32
*height
)
420 enum { QQCIF
, QQVGA
, QCIF
, QVGA
, CIF
, VGA
, SXGA
};
421 int res_x
[] = { 88, 160, 176, 320, 352, 640, 1280 };
422 int res_y
[] = { 72, 120, 144, 240, 288, 480, 960 };
424 for (i
= 0; i
< ARRAY_SIZE(res_x
); i
++) {
425 if (res_x
[i
] >= *width
&& res_y
[i
] >= *height
) {
432 *width
= res_x
[SXGA
];
433 *height
= res_y
[SXGA
];
436 /* Prepare necessary register changes depending on color encoding */
437 static void ov9640_alter_regs(u32 pixfmt
, struct ov9640_reg_alt
*alt
)
440 case V4L2_PIX_FMT_UYVY
:
441 alt
->com12
= OV9640_COM12_YUV_AVG
;
442 alt
->com13
= OV9640_COM13_Y_DELAY_EN
|
443 OV9640_COM13_YUV_DLY(0x01);
445 case V4L2_PIX_FMT_RGB555
:
446 alt
->com7
= OV9640_COM7_RGB
;
447 alt
->com13
= OV9640_COM13_RGB_AVG
;
448 alt
->com15
= OV9640_COM15_RGB_555
;
450 case V4L2_PIX_FMT_RGB565
:
451 alt
->com7
= OV9640_COM7_RGB
;
452 alt
->com13
= OV9640_COM13_RGB_AVG
;
453 alt
->com15
= OV9640_COM15_RGB_565
;
458 /* Setup registers according to resolution and color encoding */
459 static int ov9640_write_regs(struct i2c_client
*client
,
460 u32 width
, u32 pixfmt
, struct ov9640_reg_alt
*alts
)
462 const struct ov9640_reg
*ov9640_regs
, *matrix_regs
;
463 int ov9640_regs_len
, matrix_regs_len
;
467 /* select register configuration for given resolution */
470 ov9640_regs
= ov9640_regs_qqcif
;
471 ov9640_regs_len
= ARRAY_SIZE(ov9640_regs_qqcif
);
474 ov9640_regs
= ov9640_regs_qqvga
;
475 ov9640_regs_len
= ARRAY_SIZE(ov9640_regs_qqvga
);
478 ov9640_regs
= ov9640_regs_qcif
;
479 ov9640_regs_len
= ARRAY_SIZE(ov9640_regs_qcif
);
482 ov9640_regs
= ov9640_regs_qvga
;
483 ov9640_regs_len
= ARRAY_SIZE(ov9640_regs_qvga
);
486 ov9640_regs
= ov9640_regs_cif
;
487 ov9640_regs_len
= ARRAY_SIZE(ov9640_regs_cif
);
490 ov9640_regs
= ov9640_regs_vga
;
491 ov9640_regs_len
= ARRAY_SIZE(ov9640_regs_vga
);
494 ov9640_regs
= ov9640_regs_sxga
;
495 ov9640_regs_len
= ARRAY_SIZE(ov9640_regs_sxga
);
498 dev_err(&client
->dev
, "Failed to select resolution!\n");
502 /* select color matrix configuration for given color encoding */
503 if (pixfmt
== V4L2_PIX_FMT_UYVY
) {
504 matrix_regs
= ov9640_regs_yuv
;
505 matrix_regs_len
= ARRAY_SIZE(ov9640_regs_yuv
);
507 matrix_regs
= ov9640_regs_rgb
;
508 matrix_regs_len
= ARRAY_SIZE(ov9640_regs_rgb
);
511 /* write register settings into the module */
512 for (i
= 0; i
< ov9640_regs_len
; i
++) {
513 val
= ov9640_regs
[i
].val
;
515 switch (ov9640_regs
[i
].reg
) {
530 ret
= ov9640_reg_write(client
, ov9640_regs
[i
].reg
, val
);
535 /* write color matrix configuration into the module */
536 for (i
= 0; i
< matrix_regs_len
; i
++) {
537 ret
= ov9640_reg_write(client
, matrix_regs
[i
].reg
,
546 /* program default register values */
547 static int ov9640_prog_dflt(struct i2c_client
*client
)
551 for (i
= 0; i
< ARRAY_SIZE(ov9640_regs_dflt
); i
++) {
552 ret
= ov9640_reg_write(client
, ov9640_regs_dflt
[i
].reg
,
553 ov9640_regs_dflt
[i
].val
);
558 /* wait for the changes to actually happen, 140ms are not enough yet */
564 /* set the format we will capture in */
565 static int ov9640_s_fmt(struct v4l2_subdev
*sd
, struct v4l2_format
*f
)
567 struct i2c_client
*client
= sd
->priv
;
568 struct v4l2_pix_format
*pix
= &f
->fmt
.pix
;
569 struct ov9640_reg_alt alts
= {0};
572 ov9640_res_roundup(&pix
->width
, &pix
->height
);
573 ov9640_alter_regs(pix
->pixelformat
, &alts
);
575 ov9640_reset(client
);
577 ret
= ov9640_prog_dflt(client
);
581 return ov9640_write_regs(client
, pix
->width
, pix
->pixelformat
, &alts
);
584 static int ov9640_try_fmt(struct v4l2_subdev
*sd
, struct v4l2_format
*f
)
586 struct v4l2_pix_format
*pix
= &f
->fmt
.pix
;
588 ov9640_res_roundup(&pix
->width
, &pix
->height
);
589 pix
->field
= V4L2_FIELD_NONE
;
594 static int ov9640_g_crop(struct v4l2_subdev
*sd
, struct v4l2_crop
*a
)
599 a
->c
.height
= H_SXGA
;
600 a
->type
= V4L2_BUF_TYPE_VIDEO_CAPTURE
;
605 static int ov9640_cropcap(struct v4l2_subdev
*sd
, struct v4l2_cropcap
*a
)
609 a
->bounds
.width
= W_SXGA
;
610 a
->bounds
.height
= H_SXGA
;
611 a
->defrect
= a
->bounds
;
612 a
->type
= V4L2_BUF_TYPE_VIDEO_CAPTURE
;
613 a
->pixelaspect
.numerator
= 1;
614 a
->pixelaspect
.denominator
= 1;
621 static int ov9640_video_probe(struct soc_camera_device
*icd
,
622 struct i2c_client
*client
)
624 struct ov9640_priv
*priv
= i2c_get_clientdata(client
);
625 u8 pid
, ver
, midh
, midl
;
630 * We must have a parent by now. And it cannot be a wrong one.
631 * So this entire test is completely redundant.
633 if (!icd
->dev
.parent
||
634 to_soc_camera_host(icd
->dev
.parent
)->nr
!= icd
->iface
) {
635 dev_err(&client
->dev
, "Parent missing or invalid!\n");
640 icd
->formats
= ov9640_fmt_lists
;
641 icd
->num_formats
= ARRAY_SIZE(ov9640_fmt_lists
);
644 * check and show product ID and manufacturer ID
647 ret
= ov9640_reg_read(client
, OV9640_PID
, &pid
);
651 ret
= ov9640_reg_read(client
, OV9640_VER
, &ver
);
655 ret
= ov9640_reg_read(client
, OV9640_MIDH
, &midh
);
659 ret
= ov9640_reg_read(client
, OV9640_MIDL
, &midl
);
663 switch (VERSION(pid
, ver
)) {
666 priv
->model
= V4L2_IDENT_OV9640
;
670 priv
->model
= V4L2_IDENT_OV9640
;
674 dev_err(&client
->dev
, "Product ID error %x:%x\n", pid
, ver
);
679 dev_info(&client
->dev
, "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
680 devname
, pid
, ver
, midh
, midl
);
686 static struct soc_camera_ops ov9640_ops
= {
687 .set_bus_param
= ov9640_set_bus_param
,
688 .query_bus_param
= ov9640_query_bus_param
,
689 .controls
= ov9640_controls
,
690 .num_controls
= ARRAY_SIZE(ov9640_controls
),
693 static struct v4l2_subdev_core_ops ov9640_core_ops
= {
694 .g_ctrl
= ov9640_g_ctrl
,
695 .s_ctrl
= ov9640_s_ctrl
,
696 .g_chip_ident
= ov9640_g_chip_ident
,
697 #ifdef CONFIG_VIDEO_ADV_DEBUG
698 .g_register
= ov9640_get_register
,
699 .s_register
= ov9640_set_register
,
704 static struct v4l2_subdev_video_ops ov9640_video_ops
= {
705 .s_stream
= ov9640_s_stream
,
706 .s_fmt
= ov9640_s_fmt
,
707 .try_fmt
= ov9640_try_fmt
,
708 .cropcap
= ov9640_cropcap
,
709 .g_crop
= ov9640_g_crop
,
713 static struct v4l2_subdev_ops ov9640_subdev_ops
= {
714 .core
= &ov9640_core_ops
,
715 .video
= &ov9640_video_ops
,
719 * i2c_driver function
721 static int ov9640_probe(struct i2c_client
*client
,
722 const struct i2c_device_id
*did
)
724 struct ov9640_priv
*priv
;
725 struct soc_camera_device
*icd
= client
->dev
.platform_data
;
726 struct soc_camera_link
*icl
;
730 dev_err(&client
->dev
, "Missing soc-camera data!\n");
734 icl
= to_soc_camera_link(icd
);
736 dev_err(&client
->dev
, "Missing platform_data for driver\n");
740 priv
= kzalloc(sizeof(struct ov9640_priv
), GFP_KERNEL
);
742 dev_err(&client
->dev
,
743 "Failed to allocate memory for private data!\n");
747 v4l2_i2c_subdev_init(&priv
->subdev
, client
, &ov9640_subdev_ops
);
749 icd
->ops
= &ov9640_ops
;
751 ret
= ov9640_video_probe(icd
, client
);
755 i2c_set_clientdata(client
, NULL
);
762 static int ov9640_remove(struct i2c_client
*client
)
764 struct ov9640_priv
*priv
= i2c_get_clientdata(client
);
766 i2c_set_clientdata(client
, NULL
);
771 static const struct i2c_device_id ov9640_id
[] = {
775 MODULE_DEVICE_TABLE(i2c
, ov9640_id
);
777 static struct i2c_driver ov9640_i2c_driver
= {
781 .probe
= ov9640_probe
,
782 .remove
= ov9640_remove
,
783 .id_table
= ov9640_id
,
786 static int __init
ov9640_module_init(void)
788 return i2c_add_driver(&ov9640_i2c_driver
);
791 static void __exit
ov9640_module_exit(void)
793 i2c_del_driver(&ov9640_i2c_driver
);
796 module_init(ov9640_module_init
);
797 module_exit(ov9640_module_exit
);
799 MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV96xx");
800 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
801 MODULE_LICENSE("GPL v2");