USB: EHCI: add need_io_watchdog flag to ehci_hcd
[linux-2.6/linux-2.6-openrd.git] / drivers / usb / host / ehci-hcd.c
blob2dc15f3ad14386ad0708c1173410f45b201625c4
1 /*
2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/dmapool.h>
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/slab.h>
27 #include <linux/vmalloc.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/timer.h>
31 #include <linux/list.h>
32 #include <linux/interrupt.h>
33 #include <linux/reboot.h>
34 #include <linux/usb.h>
35 #include <linux/moduleparam.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/debugfs.h>
39 #include "../core/hcd.h"
41 #include <asm/byteorder.h>
42 #include <asm/io.h>
43 #include <asm/irq.h>
44 #include <asm/system.h>
45 #include <asm/unaligned.h>
47 /*-------------------------------------------------------------------------*/
50 * EHCI hc_driver implementation ... experimental, incomplete.
51 * Based on the final 1.0 register interface specification.
53 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
54 * First was PCMCIA, like ISA; then CardBus, which is PCI.
55 * Next comes "CardBay", using USB 2.0 signals.
57 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
58 * Special thanks to Intel and VIA for providing host controllers to
59 * test this driver on, and Cypress (including In-System Design) for
60 * providing early devices for those host controllers to talk to!
63 #define DRIVER_AUTHOR "David Brownell"
64 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
66 static const char hcd_name [] = "ehci_hcd";
69 #undef VERBOSE_DEBUG
70 #undef EHCI_URB_TRACE
72 #ifdef DEBUG
73 #define EHCI_STATS
74 #endif
76 /* magic numbers that can affect system performance */
77 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
78 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
79 #define EHCI_TUNE_RL_TT 0
80 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
81 #define EHCI_TUNE_MULT_TT 1
82 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
84 #define EHCI_IAA_MSECS 10 /* arbitrary */
85 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
86 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
87 #define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */
89 /* Initial IRQ latency: faster than hw default */
90 static int log2_irq_thresh = 0; // 0 to 6
91 module_param (log2_irq_thresh, int, S_IRUGO);
92 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
94 /* initial park setting: slower than hw default */
95 static unsigned park = 0;
96 module_param (park, uint, S_IRUGO);
97 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
99 /* for flakey hardware, ignore overcurrent indicators */
100 static int ignore_oc = 0;
101 module_param (ignore_oc, bool, S_IRUGO);
102 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
104 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
106 /*-------------------------------------------------------------------------*/
108 #include "ehci.h"
109 #include "ehci-dbg.c"
111 /*-------------------------------------------------------------------------*/
113 static void
114 timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action)
116 /* Don't override timeouts which shrink or (later) disable
117 * the async ring; just the I/O watchdog. Note that if a
118 * SHRINK were pending, OFF would never be requested.
120 if (timer_pending(&ehci->watchdog)
121 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
122 & ehci->actions))
123 return;
125 if (!test_and_set_bit(action, &ehci->actions)) {
126 unsigned long t;
128 switch (action) {
129 case TIMER_IO_WATCHDOG:
130 if (!ehci->need_io_watchdog)
131 return;
132 t = EHCI_IO_JIFFIES;
133 break;
134 case TIMER_ASYNC_OFF:
135 t = EHCI_ASYNC_JIFFIES;
136 break;
137 /* case TIMER_ASYNC_SHRINK: */
138 default:
139 /* add a jiffie since we synch against the
140 * 8 KHz uframe counter.
142 t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1;
143 break;
145 mod_timer(&ehci->watchdog, t + jiffies);
149 /*-------------------------------------------------------------------------*/
152 * handshake - spin reading hc until handshake completes or fails
153 * @ptr: address of hc register to be read
154 * @mask: bits to look at in result of read
155 * @done: value of those bits when handshake succeeds
156 * @usec: timeout in microseconds
158 * Returns negative errno, or zero on success
160 * Success happens when the "mask" bits have the specified value (hardware
161 * handshake done). There are two failure modes: "usec" have passed (major
162 * hardware flakeout), or the register reads as all-ones (hardware removed).
164 * That last failure should_only happen in cases like physical cardbus eject
165 * before driver shutdown. But it also seems to be caused by bugs in cardbus
166 * bridge shutdown: shutting down the bridge before the devices using it.
168 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
169 u32 mask, u32 done, int usec)
171 u32 result;
173 do {
174 result = ehci_readl(ehci, ptr);
175 if (result == ~(u32)0) /* card removed */
176 return -ENODEV;
177 result &= mask;
178 if (result == done)
179 return 0;
180 udelay (1);
181 usec--;
182 } while (usec > 0);
183 return -ETIMEDOUT;
186 /* force HC to halt state from unknown (EHCI spec section 2.3) */
187 static int ehci_halt (struct ehci_hcd *ehci)
189 u32 temp = ehci_readl(ehci, &ehci->regs->status);
191 /* disable any irqs left enabled by previous code */
192 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
194 if ((temp & STS_HALT) != 0)
195 return 0;
197 temp = ehci_readl(ehci, &ehci->regs->command);
198 temp &= ~CMD_RUN;
199 ehci_writel(ehci, temp, &ehci->regs->command);
200 return handshake (ehci, &ehci->regs->status,
201 STS_HALT, STS_HALT, 16 * 125);
204 static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
205 u32 mask, u32 done, int usec)
207 int error;
209 error = handshake(ehci, ptr, mask, done, usec);
210 if (error) {
211 ehci_halt(ehci);
212 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
213 ehci_err(ehci, "force halt; handhake %p %08x %08x -> %d\n",
214 ptr, mask, done, error);
217 return error;
220 /* put TDI/ARC silicon into EHCI mode */
221 static void tdi_reset (struct ehci_hcd *ehci)
223 u32 __iomem *reg_ptr;
224 u32 tmp;
226 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
227 tmp = ehci_readl(ehci, reg_ptr);
228 tmp |= USBMODE_CM_HC;
229 /* The default byte access to MMR space is LE after
230 * controller reset. Set the required endian mode
231 * for transfer buffers to match the host microprocessor
233 if (ehci_big_endian_mmio(ehci))
234 tmp |= USBMODE_BE;
235 ehci_writel(ehci, tmp, reg_ptr);
238 /* reset a non-running (STS_HALT == 1) controller */
239 static int ehci_reset (struct ehci_hcd *ehci)
241 int retval;
242 u32 command = ehci_readl(ehci, &ehci->regs->command);
244 command |= CMD_RESET;
245 dbg_cmd (ehci, "reset", command);
246 ehci_writel(ehci, command, &ehci->regs->command);
247 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
248 ehci->next_statechange = jiffies;
249 retval = handshake (ehci, &ehci->regs->command,
250 CMD_RESET, 0, 250 * 1000);
252 if (retval)
253 return retval;
255 if (ehci_is_TDI(ehci))
256 tdi_reset (ehci);
258 return retval;
261 /* idle the controller (from running) */
262 static void ehci_quiesce (struct ehci_hcd *ehci)
264 u32 temp;
266 #ifdef DEBUG
267 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
268 BUG ();
269 #endif
271 /* wait for any schedule enables/disables to take effect */
272 temp = ehci_readl(ehci, &ehci->regs->command) << 10;
273 temp &= STS_ASS | STS_PSS;
274 if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
275 STS_ASS | STS_PSS, temp, 16 * 125))
276 return;
278 /* then disable anything that's still active */
279 temp = ehci_readl(ehci, &ehci->regs->command);
280 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
281 ehci_writel(ehci, temp, &ehci->regs->command);
283 /* hardware can take 16 microframes to turn off ... */
284 handshake_on_error_set_halt(ehci, &ehci->regs->status,
285 STS_ASS | STS_PSS, 0, 16 * 125);
288 /*-------------------------------------------------------------------------*/
290 static void end_unlink_async(struct ehci_hcd *ehci);
291 static void ehci_work(struct ehci_hcd *ehci);
293 #include "ehci-hub.c"
294 #include "ehci-mem.c"
295 #include "ehci-q.c"
296 #include "ehci-sched.c"
298 /*-------------------------------------------------------------------------*/
300 static void ehci_iaa_watchdog(unsigned long param)
302 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
303 unsigned long flags;
305 spin_lock_irqsave (&ehci->lock, flags);
307 /* Lost IAA irqs wedge things badly; seen first with a vt8235.
308 * So we need this watchdog, but must protect it against both
309 * (a) SMP races against real IAA firing and retriggering, and
310 * (b) clean HC shutdown, when IAA watchdog was pending.
312 if (ehci->reclaim
313 && !timer_pending(&ehci->iaa_watchdog)
314 && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
315 u32 cmd, status;
317 /* If we get here, IAA is *REALLY* late. It's barely
318 * conceivable that the system is so busy that CMD_IAAD
319 * is still legitimately set, so let's be sure it's
320 * clear before we read STS_IAA. (The HC should clear
321 * CMD_IAAD when it sets STS_IAA.)
323 cmd = ehci_readl(ehci, &ehci->regs->command);
324 if (cmd & CMD_IAAD)
325 ehci_writel(ehci, cmd & ~CMD_IAAD,
326 &ehci->regs->command);
328 /* If IAA is set here it either legitimately triggered
329 * before we cleared IAAD above (but _way_ late, so we'll
330 * still count it as lost) ... or a silicon erratum:
331 * - VIA seems to set IAA without triggering the IRQ;
332 * - IAAD potentially cleared without setting IAA.
334 status = ehci_readl(ehci, &ehci->regs->status);
335 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
336 COUNT (ehci->stats.lost_iaa);
337 ehci_writel(ehci, STS_IAA, &ehci->regs->status);
340 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
341 status, cmd);
342 end_unlink_async(ehci);
345 spin_unlock_irqrestore(&ehci->lock, flags);
348 static void ehci_watchdog(unsigned long param)
350 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
351 unsigned long flags;
353 spin_lock_irqsave(&ehci->lock, flags);
355 /* stop async processing after it's idled a bit */
356 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
357 start_unlink_async (ehci, ehci->async);
359 /* ehci could run by timer, without IRQs ... */
360 ehci_work (ehci);
362 spin_unlock_irqrestore (&ehci->lock, flags);
365 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
366 * The firmware seems to think that powering off is a wakeup event!
367 * This routine turns off remote wakeup and everything else, on all ports.
369 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
371 int port = HCS_N_PORTS(ehci->hcs_params);
373 while (port--)
374 ehci_writel(ehci, PORT_RWC_BITS,
375 &ehci->regs->port_status[port]);
379 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
380 * Should be called with ehci->lock held.
382 static void ehci_silence_controller(struct ehci_hcd *ehci)
384 ehci_halt(ehci);
385 ehci_turn_off_all_ports(ehci);
387 /* make BIOS/etc use companion controller during reboot */
388 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
390 /* unblock posted writes */
391 ehci_readl(ehci, &ehci->regs->configured_flag);
394 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
395 * This forcibly disables dma and IRQs, helping kexec and other cases
396 * where the next system software may expect clean state.
398 static void ehci_shutdown(struct usb_hcd *hcd)
400 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
402 del_timer_sync(&ehci->watchdog);
403 del_timer_sync(&ehci->iaa_watchdog);
405 spin_lock_irq(&ehci->lock);
406 ehci_silence_controller(ehci);
407 spin_unlock_irq(&ehci->lock);
410 static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
412 unsigned port;
414 if (!HCS_PPC (ehci->hcs_params))
415 return;
417 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
418 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
419 (void) ehci_hub_control(ehci_to_hcd(ehci),
420 is_on ? SetPortFeature : ClearPortFeature,
421 USB_PORT_FEAT_POWER,
422 port--, NULL, 0);
423 /* Flush those writes */
424 ehci_readl(ehci, &ehci->regs->command);
425 msleep(20);
428 /*-------------------------------------------------------------------------*/
431 * ehci_work is called from some interrupts, timers, and so on.
432 * it calls driver completion functions, after dropping ehci->lock.
434 static void ehci_work (struct ehci_hcd *ehci)
436 timer_action_done (ehci, TIMER_IO_WATCHDOG);
438 /* another CPU may drop ehci->lock during a schedule scan while
439 * it reports urb completions. this flag guards against bogus
440 * attempts at re-entrant schedule scanning.
442 if (ehci->scanning)
443 return;
444 ehci->scanning = 1;
445 scan_async (ehci);
446 if (ehci->next_uframe != -1)
447 scan_periodic (ehci);
448 ehci->scanning = 0;
450 /* the IO watchdog guards against hardware or driver bugs that
451 * misplace IRQs, and should let us run completely without IRQs.
452 * such lossage has been observed on both VT6202 and VT8235.
454 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
455 (ehci->async->qh_next.ptr != NULL ||
456 ehci->periodic_sched != 0))
457 timer_action (ehci, TIMER_IO_WATCHDOG);
461 * Called when the ehci_hcd module is removed.
463 static void ehci_stop (struct usb_hcd *hcd)
465 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
467 ehci_dbg (ehci, "stop\n");
469 /* no more interrupts ... */
470 del_timer_sync (&ehci->watchdog);
471 del_timer_sync(&ehci->iaa_watchdog);
473 spin_lock_irq(&ehci->lock);
474 if (HC_IS_RUNNING (hcd->state))
475 ehci_quiesce (ehci);
477 ehci_silence_controller(ehci);
478 ehci_reset (ehci);
479 spin_unlock_irq(&ehci->lock);
481 remove_companion_file(ehci);
482 remove_debug_files (ehci);
484 /* root hub is shut down separately (first, when possible) */
485 spin_lock_irq (&ehci->lock);
486 if (ehci->async)
487 ehci_work (ehci);
488 spin_unlock_irq (&ehci->lock);
489 ehci_mem_cleanup (ehci);
491 #ifdef EHCI_STATS
492 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
493 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
494 ehci->stats.lost_iaa);
495 ehci_dbg (ehci, "complete %ld unlink %ld\n",
496 ehci->stats.complete, ehci->stats.unlink);
497 #endif
499 dbg_status (ehci, "ehci_stop completed",
500 ehci_readl(ehci, &ehci->regs->status));
503 /* one-time init, only for memory state */
504 static int ehci_init(struct usb_hcd *hcd)
506 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
507 u32 temp;
508 int retval;
509 u32 hcc_params;
511 spin_lock_init(&ehci->lock);
514 * keep io watchdog by default, those good HCDs could turn off it later
516 ehci->need_io_watchdog = 1;
517 init_timer(&ehci->watchdog);
518 ehci->watchdog.function = ehci_watchdog;
519 ehci->watchdog.data = (unsigned long) ehci;
521 init_timer(&ehci->iaa_watchdog);
522 ehci->iaa_watchdog.function = ehci_iaa_watchdog;
523 ehci->iaa_watchdog.data = (unsigned long) ehci;
526 * hw default: 1K periodic list heads, one per frame.
527 * periodic_size can shrink by USBCMD update if hcc_params allows.
529 ehci->periodic_size = DEFAULT_I_TDPS;
530 INIT_LIST_HEAD(&ehci->cached_itd_list);
531 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
532 return retval;
534 /* controllers may cache some of the periodic schedule ... */
535 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
536 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
537 ehci->i_thresh = 8;
538 else // N microframes cached
539 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
541 ehci->reclaim = NULL;
542 ehci->next_uframe = -1;
543 ehci->clock_frame = -1;
546 * dedicate a qh for the async ring head, since we couldn't unlink
547 * a 'real' qh without stopping the async schedule [4.8]. use it
548 * as the 'reclamation list head' too.
549 * its dummy is used in hw_alt_next of many tds, to prevent the qh
550 * from automatically advancing to the next td after short reads.
552 ehci->async->qh_next.qh = NULL;
553 ehci->async->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
554 ehci->async->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
555 ehci->async->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
556 ehci->async->hw_qtd_next = EHCI_LIST_END(ehci);
557 ehci->async->qh_state = QH_STATE_LINKED;
558 ehci->async->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
560 /* clear interrupt enables, set irq latency */
561 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
562 log2_irq_thresh = 0;
563 temp = 1 << (16 + log2_irq_thresh);
564 if (HCC_CANPARK(hcc_params)) {
565 /* HW default park == 3, on hardware that supports it (like
566 * NVidia and ALI silicon), maximizes throughput on the async
567 * schedule by avoiding QH fetches between transfers.
569 * With fast usb storage devices and NForce2, "park" seems to
570 * make problems: throughput reduction (!), data errors...
572 if (park) {
573 park = min(park, (unsigned) 3);
574 temp |= CMD_PARK;
575 temp |= park << 8;
577 ehci_dbg(ehci, "park %d\n", park);
579 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
580 /* periodic schedule size can be smaller than default */
581 temp &= ~(3 << 2);
582 temp |= (EHCI_TUNE_FLS << 2);
583 switch (EHCI_TUNE_FLS) {
584 case 0: ehci->periodic_size = 1024; break;
585 case 1: ehci->periodic_size = 512; break;
586 case 2: ehci->periodic_size = 256; break;
587 default: BUG();
590 ehci->command = temp;
592 return 0;
595 /* start HC running; it's halted, ehci_init() has been run (once) */
596 static int ehci_run (struct usb_hcd *hcd)
598 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
599 int retval;
600 u32 temp;
601 u32 hcc_params;
603 hcd->uses_new_polling = 1;
604 hcd->poll_rh = 0;
606 /* EHCI spec section 4.1 */
607 if ((retval = ehci_reset(ehci)) != 0) {
608 ehci_mem_cleanup(ehci);
609 return retval;
611 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
612 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
615 * hcc_params controls whether ehci->regs->segment must (!!!)
616 * be used; it constrains QH/ITD/SITD and QTD locations.
617 * pci_pool consistent memory always uses segment zero.
618 * streaming mappings for I/O buffers, like pci_map_single(),
619 * can return segments above 4GB, if the device allows.
621 * NOTE: the dma mask is visible through dma_supported(), so
622 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
623 * Scsi_Host.highmem_io, and so forth. It's readonly to all
624 * host side drivers though.
626 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
627 if (HCC_64BIT_ADDR(hcc_params)) {
628 ehci_writel(ehci, 0, &ehci->regs->segment);
629 #if 0
630 // this is deeply broken on almost all architectures
631 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
632 ehci_info(ehci, "enabled 64bit DMA\n");
633 #endif
637 // Philips, Intel, and maybe others need CMD_RUN before the
638 // root hub will detect new devices (why?); NEC doesn't
639 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
640 ehci->command |= CMD_RUN;
641 ehci_writel(ehci, ehci->command, &ehci->regs->command);
642 dbg_cmd (ehci, "init", ehci->command);
645 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
646 * are explicitly handed to companion controller(s), so no TT is
647 * involved with the root hub. (Except where one is integrated,
648 * and there's no companion controller unless maybe for USB OTG.)
650 * Turning on the CF flag will transfer ownership of all ports
651 * from the companions to the EHCI controller. If any of the
652 * companions are in the middle of a port reset at the time, it
653 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
654 * guarantees that no resets are in progress. After we set CF,
655 * a short delay lets the hardware catch up; new resets shouldn't
656 * be started before the port switching actions could complete.
658 down_write(&ehci_cf_port_reset_rwsem);
659 hcd->state = HC_STATE_RUNNING;
660 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
661 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
662 msleep(5);
663 up_write(&ehci_cf_port_reset_rwsem);
665 temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
666 ehci_info (ehci,
667 "USB %x.%x started, EHCI %x.%02x%s\n",
668 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
669 temp >> 8, temp & 0xff,
670 ignore_oc ? ", overcurrent ignored" : "");
672 ehci_writel(ehci, INTR_MASK,
673 &ehci->regs->intr_enable); /* Turn On Interrupts */
675 /* GRR this is run-once init(), being done every time the HC starts.
676 * So long as they're part of class devices, we can't do it init()
677 * since the class device isn't created that early.
679 create_debug_files(ehci);
680 create_companion_file(ehci);
682 return 0;
685 /*-------------------------------------------------------------------------*/
687 static irqreturn_t ehci_irq (struct usb_hcd *hcd)
689 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
690 u32 status, masked_status, pcd_status = 0, cmd;
691 int bh;
693 spin_lock (&ehci->lock);
695 status = ehci_readl(ehci, &ehci->regs->status);
697 /* e.g. cardbus physical eject */
698 if (status == ~(u32) 0) {
699 ehci_dbg (ehci, "device removed\n");
700 goto dead;
703 masked_status = status & INTR_MASK;
704 if (!masked_status) { /* irq sharing? */
705 spin_unlock(&ehci->lock);
706 return IRQ_NONE;
709 /* clear (just) interrupts */
710 ehci_writel(ehci, masked_status, &ehci->regs->status);
711 cmd = ehci_readl(ehci, &ehci->regs->command);
712 bh = 0;
714 #ifdef VERBOSE_DEBUG
715 /* unrequested/ignored: Frame List Rollover */
716 dbg_status (ehci, "irq", status);
717 #endif
719 /* INT, ERR, and IAA interrupt rates can be throttled */
721 /* normal [4.15.1.2] or error [4.15.1.1] completion */
722 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
723 if (likely ((status & STS_ERR) == 0))
724 COUNT (ehci->stats.normal);
725 else
726 COUNT (ehci->stats.error);
727 bh = 1;
730 /* complete the unlinking of some qh [4.15.2.3] */
731 if (status & STS_IAA) {
732 /* guard against (alleged) silicon errata */
733 if (cmd & CMD_IAAD) {
734 ehci_writel(ehci, cmd & ~CMD_IAAD,
735 &ehci->regs->command);
736 ehci_dbg(ehci, "IAA with IAAD still set?\n");
738 if (ehci->reclaim) {
739 COUNT(ehci->stats.reclaim);
740 end_unlink_async(ehci);
741 } else
742 ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
745 /* remote wakeup [4.3.1] */
746 if (status & STS_PCD) {
747 unsigned i = HCS_N_PORTS (ehci->hcs_params);
749 /* kick root hub later */
750 pcd_status = status;
752 /* resume root hub? */
753 if (!(cmd & CMD_RUN))
754 usb_hcd_resume_root_hub(hcd);
756 while (i--) {
757 int pstatus = ehci_readl(ehci,
758 &ehci->regs->port_status [i]);
760 if (pstatus & PORT_OWNER)
761 continue;
762 if (!(test_bit(i, &ehci->suspended_ports) &&
763 ((pstatus & PORT_RESUME) ||
764 !(pstatus & PORT_SUSPEND)) &&
765 (pstatus & PORT_PE) &&
766 ehci->reset_done[i] == 0))
767 continue;
769 /* start 20 msec resume signaling from this port,
770 * and make khubd collect PORT_STAT_C_SUSPEND to
771 * stop that signaling.
773 ehci->reset_done [i] = jiffies + msecs_to_jiffies (20);
774 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
775 mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
779 /* PCI errors [4.15.2.4] */
780 if (unlikely ((status & STS_FATAL) != 0)) {
781 ehci_err(ehci, "fatal error\n");
782 dbg_cmd(ehci, "fatal", cmd);
783 dbg_status(ehci, "fatal", status);
784 ehci_halt(ehci);
785 dead:
786 ehci_reset(ehci);
787 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
788 /* generic layer kills/unlinks all urbs, then
789 * uses ehci_stop to clean up the rest
791 bh = 1;
794 if (bh)
795 ehci_work (ehci);
796 spin_unlock (&ehci->lock);
797 if (pcd_status)
798 usb_hcd_poll_rh_status(hcd);
799 return IRQ_HANDLED;
802 /*-------------------------------------------------------------------------*/
805 * non-error returns are a promise to giveback() the urb later
806 * we drop ownership so next owner (or urb unlink) can get it
808 * urb + dev is in hcd.self.controller.urb_list
809 * we're queueing TDs onto software and hardware lists
811 * hcd-specific init for hcpriv hasn't been done yet
813 * NOTE: control, bulk, and interrupt share the same code to append TDs
814 * to a (possibly active) QH, and the same QH scanning code.
816 static int ehci_urb_enqueue (
817 struct usb_hcd *hcd,
818 struct urb *urb,
819 gfp_t mem_flags
821 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
822 struct list_head qtd_list;
824 INIT_LIST_HEAD (&qtd_list);
826 switch (usb_pipetype (urb->pipe)) {
827 case PIPE_CONTROL:
828 /* qh_completions() code doesn't handle all the fault cases
829 * in multi-TD control transfers. Even 1KB is rare anyway.
831 if (urb->transfer_buffer_length > (16 * 1024))
832 return -EMSGSIZE;
833 /* FALLTHROUGH */
834 /* case PIPE_BULK: */
835 default:
836 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
837 return -ENOMEM;
838 return submit_async(ehci, urb, &qtd_list, mem_flags);
840 case PIPE_INTERRUPT:
841 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
842 return -ENOMEM;
843 return intr_submit(ehci, urb, &qtd_list, mem_flags);
845 case PIPE_ISOCHRONOUS:
846 if (urb->dev->speed == USB_SPEED_HIGH)
847 return itd_submit (ehci, urb, mem_flags);
848 else
849 return sitd_submit (ehci, urb, mem_flags);
853 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
855 /* failfast */
856 if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim)
857 end_unlink_async(ehci);
859 /* if it's not linked then there's nothing to do */
860 if (qh->qh_state != QH_STATE_LINKED)
863 /* defer till later if busy */
864 else if (ehci->reclaim) {
865 struct ehci_qh *last;
867 for (last = ehci->reclaim;
868 last->reclaim;
869 last = last->reclaim)
870 continue;
871 qh->qh_state = QH_STATE_UNLINK_WAIT;
872 last->reclaim = qh;
874 /* start IAA cycle */
875 } else
876 start_unlink_async (ehci, qh);
879 /* remove from hardware lists
880 * completions normally happen asynchronously
883 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
885 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
886 struct ehci_qh *qh;
887 unsigned long flags;
888 int rc;
890 spin_lock_irqsave (&ehci->lock, flags);
891 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
892 if (rc)
893 goto done;
895 switch (usb_pipetype (urb->pipe)) {
896 // case PIPE_CONTROL:
897 // case PIPE_BULK:
898 default:
899 qh = (struct ehci_qh *) urb->hcpriv;
900 if (!qh)
901 break;
902 switch (qh->qh_state) {
903 case QH_STATE_LINKED:
904 case QH_STATE_COMPLETING:
905 unlink_async(ehci, qh);
906 break;
907 case QH_STATE_UNLINK:
908 case QH_STATE_UNLINK_WAIT:
909 /* already started */
910 break;
911 case QH_STATE_IDLE:
912 /* QH might be waiting for a Clear-TT-Buffer */
913 qh_completions(ehci, qh);
914 break;
916 break;
918 case PIPE_INTERRUPT:
919 qh = (struct ehci_qh *) urb->hcpriv;
920 if (!qh)
921 break;
922 switch (qh->qh_state) {
923 case QH_STATE_LINKED:
924 intr_deschedule (ehci, qh);
925 /* FALL THROUGH */
926 case QH_STATE_IDLE:
927 qh_completions (ehci, qh);
928 break;
929 default:
930 ehci_dbg (ehci, "bogus qh %p state %d\n",
931 qh, qh->qh_state);
932 goto done;
935 /* reschedule QH iff another request is queued */
936 if (!list_empty (&qh->qtd_list)
937 && HC_IS_RUNNING (hcd->state)) {
938 rc = qh_schedule(ehci, qh);
940 /* An error here likely indicates handshake failure
941 * or no space left in the schedule. Neither fault
942 * should happen often ...
944 * FIXME kill the now-dysfunctional queued urbs
946 if (rc != 0)
947 ehci_err(ehci,
948 "can't reschedule qh %p, err %d",
949 qh, rc);
951 break;
953 case PIPE_ISOCHRONOUS:
954 // itd or sitd ...
956 // wait till next completion, do it then.
957 // completion irqs can wait up to 1024 msec,
958 break;
960 done:
961 spin_unlock_irqrestore (&ehci->lock, flags);
962 return rc;
965 /*-------------------------------------------------------------------------*/
967 // bulk qh holds the data toggle
969 static void
970 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
972 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
973 unsigned long flags;
974 struct ehci_qh *qh, *tmp;
976 /* ASSERT: any requests/urbs are being unlinked */
977 /* ASSERT: nobody can be submitting urbs for this any more */
979 rescan:
980 spin_lock_irqsave (&ehci->lock, flags);
981 qh = ep->hcpriv;
982 if (!qh)
983 goto done;
985 /* endpoints can be iso streams. for now, we don't
986 * accelerate iso completions ... so spin a while.
988 if (qh->hw_info1 == 0) {
989 ehci_vdbg (ehci, "iso delay\n");
990 goto idle_timeout;
993 if (!HC_IS_RUNNING (hcd->state))
994 qh->qh_state = QH_STATE_IDLE;
995 switch (qh->qh_state) {
996 case QH_STATE_LINKED:
997 for (tmp = ehci->async->qh_next.qh;
998 tmp && tmp != qh;
999 tmp = tmp->qh_next.qh)
1000 continue;
1001 /* periodic qh self-unlinks on empty */
1002 if (!tmp)
1003 goto nogood;
1004 unlink_async (ehci, qh);
1005 /* FALL THROUGH */
1006 case QH_STATE_UNLINK: /* wait for hw to finish? */
1007 case QH_STATE_UNLINK_WAIT:
1008 idle_timeout:
1009 spin_unlock_irqrestore (&ehci->lock, flags);
1010 schedule_timeout_uninterruptible(1);
1011 goto rescan;
1012 case QH_STATE_IDLE: /* fully unlinked */
1013 if (qh->clearing_tt)
1014 goto idle_timeout;
1015 if (list_empty (&qh->qtd_list)) {
1016 qh_put (qh);
1017 break;
1019 /* else FALL THROUGH */
1020 default:
1021 nogood:
1022 /* caller was supposed to have unlinked any requests;
1023 * that's not our job. just leak this memory.
1025 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1026 qh, ep->desc.bEndpointAddress, qh->qh_state,
1027 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1028 break;
1030 ep->hcpriv = NULL;
1031 done:
1032 spin_unlock_irqrestore (&ehci->lock, flags);
1033 return;
1036 static void
1037 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1039 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1040 struct ehci_qh *qh;
1041 int eptype = usb_endpoint_type(&ep->desc);
1042 int epnum = usb_endpoint_num(&ep->desc);
1043 int is_out = usb_endpoint_dir_out(&ep->desc);
1044 unsigned long flags;
1046 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1047 return;
1049 spin_lock_irqsave(&ehci->lock, flags);
1050 qh = ep->hcpriv;
1052 /* For Bulk and Interrupt endpoints we maintain the toggle state
1053 * in the hardware; the toggle bits in udev aren't used at all.
1054 * When an endpoint is reset by usb_clear_halt() we must reset
1055 * the toggle bit in the QH.
1057 if (qh) {
1058 usb_settoggle(qh->dev, epnum, is_out, 0);
1059 if (!list_empty(&qh->qtd_list)) {
1060 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1061 } else if (qh->qh_state == QH_STATE_LINKED) {
1063 /* The toggle value in the QH can't be updated
1064 * while the QH is active. Unlink it now;
1065 * re-linking will call qh_refresh().
1067 if (eptype == USB_ENDPOINT_XFER_BULK) {
1068 unlink_async(ehci, qh);
1069 } else {
1070 intr_deschedule(ehci, qh);
1071 (void) qh_schedule(ehci, qh);
1075 spin_unlock_irqrestore(&ehci->lock, flags);
1078 static int ehci_get_frame (struct usb_hcd *hcd)
1080 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1081 return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) %
1082 ehci->periodic_size;
1085 /*-------------------------------------------------------------------------*/
1087 MODULE_DESCRIPTION(DRIVER_DESC);
1088 MODULE_AUTHOR (DRIVER_AUTHOR);
1089 MODULE_LICENSE ("GPL");
1091 #ifdef CONFIG_PCI
1092 #include "ehci-pci.c"
1093 #define PCI_DRIVER ehci_pci_driver
1094 #endif
1096 #ifdef CONFIG_USB_EHCI_FSL
1097 #include "ehci-fsl.c"
1098 #define PLATFORM_DRIVER ehci_fsl_driver
1099 #endif
1101 #ifdef CONFIG_SOC_AU1200
1102 #include "ehci-au1xxx.c"
1103 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1104 #endif
1106 #ifdef CONFIG_PPC_PS3
1107 #include "ehci-ps3.c"
1108 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1109 #endif
1111 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1112 #include "ehci-ppc-of.c"
1113 #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1114 #endif
1116 #ifdef CONFIG_PLAT_ORION
1117 #include "ehci-orion.c"
1118 #define PLATFORM_DRIVER ehci_orion_driver
1119 #endif
1121 #ifdef CONFIG_ARCH_IXP4XX
1122 #include "ehci-ixp4xx.c"
1123 #define PLATFORM_DRIVER ixp4xx_ehci_driver
1124 #endif
1126 #ifdef CONFIG_USB_W90X900_EHCI
1127 #include "ehci-w90x900.c"
1128 #define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1129 #endif
1131 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1132 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
1133 #error "missing bus glue for ehci-hcd"
1134 #endif
1136 static int __init ehci_hcd_init(void)
1138 int retval = 0;
1140 if (usb_disabled())
1141 return -ENODEV;
1143 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1144 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1145 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1146 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1147 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1148 " before uhci_hcd and ohci_hcd, not after\n");
1150 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1151 hcd_name,
1152 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1153 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1155 #ifdef DEBUG
1156 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1157 if (!ehci_debug_root) {
1158 retval = -ENOENT;
1159 goto err_debug;
1161 #endif
1163 #ifdef PLATFORM_DRIVER
1164 retval = platform_driver_register(&PLATFORM_DRIVER);
1165 if (retval < 0)
1166 goto clean0;
1167 #endif
1169 #ifdef PCI_DRIVER
1170 retval = pci_register_driver(&PCI_DRIVER);
1171 if (retval < 0)
1172 goto clean1;
1173 #endif
1175 #ifdef PS3_SYSTEM_BUS_DRIVER
1176 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1177 if (retval < 0)
1178 goto clean2;
1179 #endif
1181 #ifdef OF_PLATFORM_DRIVER
1182 retval = of_register_platform_driver(&OF_PLATFORM_DRIVER);
1183 if (retval < 0)
1184 goto clean3;
1185 #endif
1186 return retval;
1188 #ifdef OF_PLATFORM_DRIVER
1189 /* of_unregister_platform_driver(&OF_PLATFORM_DRIVER); */
1190 clean3:
1191 #endif
1192 #ifdef PS3_SYSTEM_BUS_DRIVER
1193 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1194 clean2:
1195 #endif
1196 #ifdef PCI_DRIVER
1197 pci_unregister_driver(&PCI_DRIVER);
1198 clean1:
1199 #endif
1200 #ifdef PLATFORM_DRIVER
1201 platform_driver_unregister(&PLATFORM_DRIVER);
1202 clean0:
1203 #endif
1204 #ifdef DEBUG
1205 debugfs_remove(ehci_debug_root);
1206 ehci_debug_root = NULL;
1207 err_debug:
1208 #endif
1209 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1210 return retval;
1212 module_init(ehci_hcd_init);
1214 static void __exit ehci_hcd_cleanup(void)
1216 #ifdef OF_PLATFORM_DRIVER
1217 of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1218 #endif
1219 #ifdef PLATFORM_DRIVER
1220 platform_driver_unregister(&PLATFORM_DRIVER);
1221 #endif
1222 #ifdef PCI_DRIVER
1223 pci_unregister_driver(&PCI_DRIVER);
1224 #endif
1225 #ifdef PS3_SYSTEM_BUS_DRIVER
1226 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1227 #endif
1228 #ifdef DEBUG
1229 debugfs_remove(ehci_debug_root);
1230 #endif
1231 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1233 module_exit(ehci_hcd_cleanup);