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[SPARC64]: SMP build fix.
[linux-2.6/linux-2.6-openrd.git] / arch / sparc64 / kernel / irq.c
blob8cb3358674f5257fcaff2ee83448592b1732e3dd
1 /* irq.c: UltraSparc IRQ handling/init/registry.
2 *
3 * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
6 */
7
8 #include <linux/module.h>
9 #include <linux/sched.h>
10 #include <linux/ptrace.h>
11 #include <linux/errno.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/signal.h>
14 #include <linux/mm.h>
15 #include <linux/interrupt.h>
16 #include <linux/slab.h>
17 #include <linux/random.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/proc_fs.h>
21 #include <linux/seq_file.h>
22 #include <linux/bootmem.h>
23 #include <linux/irq.h>
24 #include <linux/msi.h>
25
26 #include <asm/ptrace.h>
27 #include <asm/processor.h>
28 #include <asm/atomic.h>
29 #include <asm/system.h>
30 #include <asm/irq.h>
31 #include <asm/io.h>
32 #include <asm/sbus.h>
33 #include <asm/iommu.h>
34 #include <asm/upa.h>
35 #include <asm/oplib.h>
36 #include <asm/prom.h>
37 #include <asm/timer.h>
38 #include <asm/smp.h>
39 #include <asm/starfire.h>
40 #include <asm/uaccess.h>
41 #include <asm/cache.h>
42 #include <asm/cpudata.h>
43 #include <asm/auxio.h>
44 #include <asm/head.h>
45 #include <asm/hypervisor.h>
46
47 /* UPA nodes send interrupt packet to UltraSparc with first data reg
48 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
49 * delivered. We must translate this into a non-vector IRQ so we can
50 * set the softint on this cpu.
51 *
52 * To make processing these packets efficient and race free we use
53 * an array of irq buckets below. The interrupt vector handler in
54 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
55 * The IVEC handler does not need to act atomically, the PIL dispatch
56 * code uses CAS to get an atomic snapshot of the list and clear it
57 * at the same time.
58 *
59 * If you make changes to ino_bucket, please update hand coded assembler
60 * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
61 */
62 struct ino_bucket {
63 /* Next handler in per-CPU IRQ worklist. We know that
64 * bucket pointers have the high 32-bits clear, so to
65 * save space we only store the bits we need.
66 */
67 /*0x00*/unsigned int irq_chain;
68
69 /* Virtual interrupt number assigned to this INO. */
70 /*0x04*/unsigned int virt_irq;
71 };
72
73 #define NUM_IVECS (IMAP_INR + 1)
74 struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
75
76 #define __irq_ino(irq) \
77 (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
78 #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
79 #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
80
81 /* This has to be in the main kernel image, it cannot be
82 * turned into per-cpu data. The reason is that the main
83 * kernel image is locked into the TLB and this structure
84 * is accessed from the vectored interrupt trap handler. If
85 * access to this structure takes a TLB miss it could cause
86 * the 5-level sparc v9 trap stack to overflow.
87 */
88 #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist)
89
90 static unsigned int virt_to_real_irq_table[NR_IRQS];
91
92 static unsigned char virt_irq_alloc(unsigned int real_irq)
93 {
94 unsigned char ent;
95
96 BUILD_BUG_ON(NR_IRQS >= 256);
97
98 for (ent = 1; ent < NR_IRQS; ent++) {
99 if (!virt_to_real_irq_table[ent])
100 break;
101 }
102 if (ent >= NR_IRQS) {
103 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
104 return 0;
105 }
106
107 virt_to_real_irq_table[ent] = real_irq;
108
109 return ent;
110 }
111
112 #ifdef CONFIG_PCI_MSI
113 static void virt_irq_free(unsigned int virt_irq)
114 {
115 unsigned int real_irq;
116
117 if (virt_irq >= NR_IRQS)
118 return;
119
120 real_irq = virt_to_real_irq_table[virt_irq];
121 virt_to_real_irq_table[virt_irq] = 0;
122
123 __bucket(real_irq)->virt_irq = 0;
124 }
125 #endif
126
127 static unsigned int virt_to_real_irq(unsigned char virt_irq)
128 {
129 return virt_to_real_irq_table[virt_irq];
130 }
131
132 /*
133 * /proc/interrupts printing:
134 */
135
136 int show_interrupts(struct seq_file *p, void *v)
137 {
138 int i = *(loff_t *) v, j;
139 struct irqaction * action;
140 unsigned long flags;
141
142 if (i == 0) {
143 seq_printf(p, " ");
144 for_each_online_cpu(j)
145 seq_printf(p, "CPU%d ",j);
146 seq_putc(p, '\n');
147 }
148
149 if (i < NR_IRQS) {
150 spin_lock_irqsave(&irq_desc[i].lock, flags);
151 action = irq_desc[i].action;
152 if (!action)
153 goto skip;
154 seq_printf(p, "%3d: ",i);
155 #ifndef CONFIG_SMP
156 seq_printf(p, "%10u ", kstat_irqs(i));
157 #else
158 for_each_online_cpu(j)
159 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
160 #endif
161 seq_printf(p, " %9s", irq_desc[i].chip->typename);
162 seq_printf(p, " %s", action->name);
163
164 for (action=action->next; action; action = action->next)
165 seq_printf(p, ", %s", action->name);
166
167 seq_putc(p, '\n');
168 skip:
169 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
170 }
171 return 0;
172 }
173
174 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
175 {
176 unsigned int tid;
177
178 if (this_is_starfire) {
179 tid = starfire_translate(imap, cpuid);
180 tid <<= IMAP_TID_SHIFT;
181 tid &= IMAP_TID_UPA;
182 } else {
183 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
184 unsigned long ver;
185
186 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
187 if ((ver >> 32UL) == __JALAPENO_ID ||
188 (ver >> 32UL) == __SERRANO_ID) {
189 tid = cpuid << IMAP_TID_SHIFT;
190 tid &= IMAP_TID_JBUS;
191 } else {
192 unsigned int a = cpuid & 0x1f;
193 unsigned int n = (cpuid >> 5) & 0x1f;
194
195 tid = ((a << IMAP_AID_SHIFT) |
196 (n << IMAP_NID_SHIFT));
197 tid &= (IMAP_AID_SAFARI |
198 IMAP_NID_SAFARI);;
199 }
200 } else {
201 tid = cpuid << IMAP_TID_SHIFT;
202 tid &= IMAP_TID_UPA;
203 }
204 }
205
206 return tid;
207 }
208
209 struct irq_handler_data {
210 unsigned long iclr;
211 unsigned long imap;
212
213 void (*pre_handler)(unsigned int, void *, void *);
214 void *pre_handler_arg1;
215 void *pre_handler_arg2;
216 };
217
218 static inline struct ino_bucket *virt_irq_to_bucket(unsigned int virt_irq)
219 {
220 unsigned int real_irq = virt_to_real_irq(virt_irq);
221 struct ino_bucket *bucket = NULL;
222
223 if (likely(real_irq))
224 bucket = __bucket(real_irq);
225
226 return bucket;
227 }
228
229 #ifdef CONFIG_SMP
230 static int irq_choose_cpu(unsigned int virt_irq)
231 {
232 cpumask_t mask = irq_desc[virt_irq].affinity;
233 int cpuid;
234
235 if (cpus_equal(mask, CPU_MASK_ALL)) {
236 static int irq_rover;
237 static DEFINE_SPINLOCK(irq_rover_lock);
238 unsigned long flags;
239
240 /* Round-robin distribution... */
241 do_round_robin:
242 spin_lock_irqsave(&irq_rover_lock, flags);
243
244 while (!cpu_online(irq_rover)) {
245 if (++irq_rover >= NR_CPUS)
246 irq_rover = 0;
247 }
248 cpuid = irq_rover;
249 do {
250 if (++irq_rover >= NR_CPUS)
251 irq_rover = 0;
252 } while (!cpu_online(irq_rover));
253
254 spin_unlock_irqrestore(&irq_rover_lock, flags);
255 } else {
256 cpumask_t tmp;
257
258 cpus_and(tmp, cpu_online_map, mask);
259
260 if (cpus_empty(tmp))
261 goto do_round_robin;
262
263 cpuid = first_cpu(tmp);
264 }
265
266 return cpuid;
267 }
268 #else
269 static int irq_choose_cpu(unsigned int virt_irq)
270 {
271 return real_hard_smp_processor_id();
272 }
273 #endif
274
275 static void sun4u_irq_enable(unsigned int virt_irq)
276 {
277 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
278
279 if (likely(data)) {
280 unsigned long cpuid, imap, val;
281 unsigned int tid;
282
283 cpuid = irq_choose_cpu(virt_irq);
284 imap = data->imap;
285
286 tid = sun4u_compute_tid(imap, cpuid);
287
288 val = upa_readq(imap);
289 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
290 IMAP_AID_SAFARI | IMAP_NID_SAFARI);
291 val |= tid | IMAP_VALID;
292 upa_writeq(val, imap);
293 }
294 }
295
296 static void sun4u_set_affinity(unsigned int virt_irq, cpumask_t mask)
297 {
298 sun4u_irq_enable(virt_irq);
299 }
300
301 static void sun4u_irq_disable(unsigned int virt_irq)
302 {
303 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
304
305 if (likely(data)) {
306 unsigned long imap = data->imap;
307 u32 tmp = upa_readq(imap);
308
309 tmp &= ~IMAP_VALID;
310 upa_writeq(tmp, imap);
311 }
312 }
313
314 static void sun4u_irq_end(unsigned int virt_irq)
315 {
316 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
317 struct irq_desc *desc = irq_desc + virt_irq;
318
319 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
320 return;
321
322 if (likely(data))
323 upa_writeq(ICLR_IDLE, data->iclr);
324 }
325
326 static void sun4v_irq_enable(unsigned int virt_irq)
327 {
328 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
329 unsigned int ino = bucket - &ivector_table[0];
330
331 if (likely(bucket)) {
332 unsigned long cpuid;
333 int err;
334
335 cpuid = irq_choose_cpu(virt_irq);
336
337 err = sun4v_intr_settarget(ino, cpuid);
338 if (err != HV_EOK)
339 printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
340 ino, cpuid, err);
341 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
342 if (err != HV_EOK)
343 printk("sun4v_intr_setstate(%x): "
344 "err(%d)\n", ino, err);
345 err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
346 if (err != HV_EOK)
347 printk("sun4v_intr_setenabled(%x): err(%d)\n",
348 ino, err);
349 }
350 }
351
352 static void sun4v_set_affinity(unsigned int virt_irq, cpumask_t mask)
353 {
354 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
355 unsigned int ino = bucket - &ivector_table[0];
356
357 if (likely(bucket)) {
358 unsigned long cpuid;
359 int err;
360
361 cpuid = irq_choose_cpu(virt_irq);
362
363 err = sun4v_intr_settarget(ino, cpuid);
364 if (err != HV_EOK)
365 printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
366 ino, cpuid, err);
367 }
368 }
369
370 static void sun4v_irq_disable(unsigned int virt_irq)
371 {
372 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
373 unsigned int ino = bucket - &ivector_table[0];
374
375 if (likely(bucket)) {
376 int err;
377
378 err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
379 if (err != HV_EOK)
380 printk("sun4v_intr_setenabled(%x): "
381 "err(%d)\n", ino, err);
382 }
383 }
384
385 #ifdef CONFIG_PCI_MSI
386 static void sun4v_msi_enable(unsigned int virt_irq)
387 {
388 sun4v_irq_enable(virt_irq);
389 unmask_msi_irq(virt_irq);
390 }
391
392 static void sun4v_msi_disable(unsigned int virt_irq)
393 {
394 mask_msi_irq(virt_irq);
395 sun4v_irq_disable(virt_irq);
396 }
397 #endif
398
399 static void sun4v_irq_end(unsigned int virt_irq)
400 {
401 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
402 unsigned int ino = bucket - &ivector_table[0];
403 struct irq_desc *desc = irq_desc + virt_irq;
404
405 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
406 return;
407
408 if (likely(bucket)) {
409 int err;
410
411 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
412 if (err != HV_EOK)
413 printk("sun4v_intr_setstate(%x): "
414 "err(%d)\n", ino, err);
415 }
416 }
417
418 static void sun4v_virq_enable(unsigned int virt_irq)
419 {
420 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
421 unsigned int ino = bucket - &ivector_table[0];
422
423 if (likely(bucket)) {
424 unsigned long cpuid, dev_handle, dev_ino;
425 int err;
426
427 cpuid = irq_choose_cpu(virt_irq);
428
429 dev_handle = ino & IMAP_IGN;
430 dev_ino = ino & IMAP_INO;
431
432 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
433 if (err != HV_EOK)
434 printk("sun4v_vintr_set_target(%lx,%lx,%lu): "
435 "err(%d)\n",
436 dev_handle, dev_ino, cpuid, err);
437 err = sun4v_vintr_set_state(dev_handle, dev_ino,
438 HV_INTR_STATE_IDLE);
439 if (err != HV_EOK)
440 printk("sun4v_vintr_set_state(%lx,%lx,"
441 "HV_INTR_STATE_IDLE): err(%d)\n",
442 dev_handle, dev_ino, err);
443 err = sun4v_vintr_set_valid(dev_handle, dev_ino,
444 HV_INTR_ENABLED);
445 if (err != HV_EOK)
446 printk("sun4v_vintr_set_state(%lx,%lx,"
447 "HV_INTR_ENABLED): err(%d)\n",
448 dev_handle, dev_ino, err);
449 }
450 }
451
452 static void sun4v_virt_set_affinity(unsigned int virt_irq, cpumask_t mask)
453 {
454 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
455 unsigned int ino = bucket - &ivector_table[0];
456
457 if (likely(bucket)) {
458 unsigned long cpuid, dev_handle, dev_ino;
459 int err;
460
461 cpuid = irq_choose_cpu(virt_irq);
462
463 dev_handle = ino & IMAP_IGN;
464 dev_ino = ino & IMAP_INO;
465
466 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
467 if (err != HV_EOK)
468 printk("sun4v_vintr_set_target(%lx,%lx,%lu): "
469 "err(%d)\n",
470 dev_handle, dev_ino, cpuid, err);
471 }
472 }
473
474 static void sun4v_virq_disable(unsigned int virt_irq)
475 {
476 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
477 unsigned int ino = bucket - &ivector_table[0];
478
479 if (likely(bucket)) {
480 unsigned long dev_handle, dev_ino;
481 int err;
482
483 dev_handle = ino & IMAP_IGN;
484 dev_ino = ino & IMAP_INO;
485
486 err = sun4v_vintr_set_valid(dev_handle, dev_ino,
487 HV_INTR_DISABLED);
488 if (err != HV_EOK)
489 printk("sun4v_vintr_set_state(%lx,%lx,"
490 "HV_INTR_DISABLED): err(%d)\n",
491 dev_handle, dev_ino, err);
492 }
493 }
494
495 static void sun4v_virq_end(unsigned int virt_irq)
496 {
497 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
498 unsigned int ino = bucket - &ivector_table[0];
499 struct irq_desc *desc = irq_desc + virt_irq;
500
501 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
502 return;
503
504 if (likely(bucket)) {
505 unsigned long dev_handle, dev_ino;
506 int err;
507
508 dev_handle = ino & IMAP_IGN;
509 dev_ino = ino & IMAP_INO;
510
511 err = sun4v_vintr_set_state(dev_handle, dev_ino,
512 HV_INTR_STATE_IDLE);
513 if (err != HV_EOK)
514 printk("sun4v_vintr_set_state(%lx,%lx,"
515 "HV_INTR_STATE_IDLE): err(%d)\n",
516 dev_handle, dev_ino, err);
517 }
518 }
519
520 static void run_pre_handler(unsigned int virt_irq)
521 {
522 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
523 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
524
525 if (likely(data->pre_handler)) {
526 data->pre_handler(__irq_ino(__irq(bucket)),
527 data->pre_handler_arg1,
528 data->pre_handler_arg2);
529 }
530 }
531
532 static struct irq_chip sun4u_irq = {
533 .typename = "sun4u",
534 .enable = sun4u_irq_enable,
535 .disable = sun4u_irq_disable,
536 .end = sun4u_irq_end,
537 .set_affinity = sun4u_set_affinity,
538 };
539
540 static struct irq_chip sun4u_irq_ack = {
541 .typename = "sun4u+ack",
542 .enable = sun4u_irq_enable,
543 .disable = sun4u_irq_disable,
544 .ack = run_pre_handler,
545 .end = sun4u_irq_end,
546 .set_affinity = sun4u_set_affinity,
547 };
548
549 static struct irq_chip sun4v_irq = {
550 .typename = "sun4v",
551 .enable = sun4v_irq_enable,
552 .disable = sun4v_irq_disable,
553 .end = sun4v_irq_end,
554 .set_affinity = sun4v_set_affinity,
555 };
556
557 static struct irq_chip sun4v_irq_ack = {
558 .typename = "sun4v+ack",
559 .enable = sun4v_irq_enable,
560 .disable = sun4v_irq_disable,
561 .ack = run_pre_handler,
562 .end = sun4v_irq_end,
563 .set_affinity = sun4v_set_affinity,
564 };
565
566 #ifdef CONFIG_PCI_MSI
567 static struct irq_chip sun4v_msi = {
568 .typename = "sun4v+msi",
569 .mask = mask_msi_irq,
570 .unmask = unmask_msi_irq,
571 .enable = sun4v_msi_enable,
572 .disable = sun4v_msi_disable,
573 .ack = run_pre_handler,
574 .end = sun4v_irq_end,
575 .set_affinity = sun4v_set_affinity,
576 };
577 #endif
578
579 static struct irq_chip sun4v_virq = {
580 .typename = "vsun4v",
581 .enable = sun4v_virq_enable,
582 .disable = sun4v_virq_disable,
583 .end = sun4v_virq_end,
584 .set_affinity = sun4v_virt_set_affinity,
585 };
586
587 static struct irq_chip sun4v_virq_ack = {
588 .typename = "vsun4v+ack",
589 .enable = sun4v_virq_enable,
590 .disable = sun4v_virq_disable,
591 .ack = run_pre_handler,
592 .end = sun4v_virq_end,
593 .set_affinity = sun4v_virt_set_affinity,
594 };
595
596 void irq_install_pre_handler(int virt_irq,
597 void (*func)(unsigned int, void *, void *),
598 void *arg1, void *arg2)
599 {
600 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
601 struct irq_chip *chip;
602
603 data->pre_handler = func;
604 data->pre_handler_arg1 = arg1;
605 data->pre_handler_arg2 = arg2;
606
607 chip = get_irq_chip(virt_irq);
608 if (chip == &sun4u_irq_ack ||
609 chip == &sun4v_irq_ack ||
610 chip == &sun4v_virq_ack
611 #ifdef CONFIG_PCI_MSI
612 || chip == &sun4v_msi
613 #endif
614 )
615 return;
616
617 chip = (chip == &sun4u_irq ?
618 &sun4u_irq_ack :
619 (chip == &sun4v_irq ?
620 &sun4v_irq_ack : &sun4v_virq_ack));
621 set_irq_chip(virt_irq, chip);
622 }
623
624 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
625 {
626 struct ino_bucket *bucket;
627 struct irq_handler_data *data;
628 int ino;
629
630 BUG_ON(tlb_type == hypervisor);
631
632 ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
633 bucket = &ivector_table[ino];
634 if (!bucket->virt_irq) {
635 bucket->virt_irq = virt_irq_alloc(__irq(bucket));
636 set_irq_chip(bucket->virt_irq, &sun4u_irq);
637 }
638
639 data = get_irq_chip_data(bucket->virt_irq);
640 if (unlikely(data))
641 goto out;
642
643 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
644 if (unlikely(!data)) {
645 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
646 prom_halt();
647 }
648 set_irq_chip_data(bucket->virt_irq, data);
649
650 data->imap = imap;
651 data->iclr = iclr;
652
653 out:
654 return bucket->virt_irq;
655 }
656
657 static unsigned int sun4v_build_common(unsigned long sysino,
658 struct irq_chip *chip)
659 {
660 struct ino_bucket *bucket;
661 struct irq_handler_data *data;
662
663 BUG_ON(tlb_type != hypervisor);
664
665 bucket = &ivector_table[sysino];
666 if (!bucket->virt_irq) {
667 bucket->virt_irq = virt_irq_alloc(__irq(bucket));
668 set_irq_chip(bucket->virt_irq, chip);
669 }
670
671 data = get_irq_chip_data(bucket->virt_irq);
672 if (unlikely(data))
673 goto out;
674
675 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
676 if (unlikely(!data)) {
677 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
678 prom_halt();
679 }
680 set_irq_chip_data(bucket->virt_irq, data);
681
682 /* Catch accidental accesses to these things. IMAP/ICLR handling
683 * is done by hypervisor calls on sun4v platforms, not by direct
684 * register accesses.
685 */
686 data->imap = ~0UL;
687 data->iclr = ~0UL;
688
689 out:
690 return bucket->virt_irq;
691 }
692
693 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
694 {
695 unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
696
697 return sun4v_build_common(sysino, &sun4v_irq);
698 }
699
700 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
701 {
702 unsigned long sysino, hv_err;
703
704 BUG_ON(devhandle & ~IMAP_IGN);
705 BUG_ON(devino & ~IMAP_INO);
706
707 sysino = devhandle | devino;
708
709 hv_err = sun4v_vintr_set_cookie(devhandle, devino, sysino);
710 if (hv_err) {
711 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
712 "err=%lu\n", devhandle, devino, hv_err);
713 prom_halt();
714 }
715
716 return sun4v_build_common(sysino, &sun4v_virq);
717 }
718
719 #ifdef CONFIG_PCI_MSI
720 unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p,
721 unsigned int msi_start, unsigned int msi_end)
722 {
723 struct ino_bucket *bucket;
724 struct irq_handler_data *data;
725 unsigned long sysino;
726 unsigned int devino;
727
728 BUG_ON(tlb_type != hypervisor);
729
730 /* Find a free devino in the given range. */
731 for (devino = msi_start; devino < msi_end; devino++) {
732 sysino = sun4v_devino_to_sysino(devhandle, devino);
733 bucket = &ivector_table[sysino];
734 if (!bucket->virt_irq)
735 break;
736 }
737 if (devino >= msi_end)
738 return 0;
739
740 sysino = sun4v_devino_to_sysino(devhandle, devino);
741 bucket = &ivector_table[sysino];
742 bucket->virt_irq = virt_irq_alloc(__irq(bucket));
743 *virt_irq_p = bucket->virt_irq;
744 set_irq_chip(bucket->virt_irq, &sun4v_msi);
745
746 data = get_irq_chip_data(bucket->virt_irq);
747 if (unlikely(data))
748 return devino;
749
750 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
751 if (unlikely(!data)) {
752 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
753 prom_halt();
754 }
755 set_irq_chip_data(bucket->virt_irq, data);
756
757 data->imap = ~0UL;
758 data->iclr = ~0UL;
759
760 return devino;
761 }
762
763 void sun4v_destroy_msi(unsigned int virt_irq)
764 {
765 virt_irq_free(virt_irq);
766 }
767 #endif
768
769 void ack_bad_irq(unsigned int virt_irq)
770 {
771 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
772 unsigned int ino = 0xdeadbeef;
773
774 if (bucket)
775 ino = bucket - &ivector_table[0];
776
777 printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
778 ino, virt_irq);
779 }
780
781 void handler_irq(int irq, struct pt_regs *regs)
782 {
783 struct ino_bucket *bucket;
784 struct pt_regs *old_regs;
785
786 clear_softint(1 << irq);
787
788 old_regs = set_irq_regs(regs);
789 irq_enter();
790
791 /* Sliiiick... */
792 bucket = __bucket(xchg32(irq_work(smp_processor_id()), 0));
793 while (bucket) {
794 struct ino_bucket *next = __bucket(bucket->irq_chain);
795
796 bucket->irq_chain = 0;
797 __do_IRQ(bucket->virt_irq);
798
799 bucket = next;
800 }
801
802 irq_exit();
803 set_irq_regs(old_regs);
804 }
805
806 #ifdef CONFIG_HOTPLUG_CPU
807 void fixup_irqs(void)
808 {
809 unsigned int irq;
810
811 for (irq = 0; irq < NR_IRQS; irq++) {
812 unsigned long flags;
813
814 spin_lock_irqsave(&irq_desc[irq].lock, flags);
815 if (irq_desc[irq].action &&
816 !(irq_desc[irq].status & IRQ_PER_CPU)) {
817 if (irq_desc[irq].chip->set_affinity)
818 irq_desc[irq].chip->set_affinity(irq,
819 irq_desc[irq].affinity);
820 }
821 spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
822 }
823 }
824 #endif
825
826 struct sun5_timer {
827 u64 count0;
828 u64 limit0;
829 u64 count1;
830 u64 limit1;
831 };
832
833 static struct sun5_timer *prom_timers;
834 static u64 prom_limit0, prom_limit1;
835
836 static void map_prom_timers(void)
837 {
838 struct device_node *dp;
839 const unsigned int *addr;
840
841 /* PROM timer node hangs out in the top level of device siblings... */
842 dp = of_find_node_by_path("/");
843 dp = dp->child;
844 while (dp) {
845 if (!strcmp(dp->name, "counter-timer"))
846 break;
847 dp = dp->sibling;
848 }
849
850 /* Assume if node is not present, PROM uses different tick mechanism
851 * which we should not care about.
852 */
853 if (!dp) {
854 prom_timers = (struct sun5_timer *) 0;
855 return;
856 }
857
858 /* If PROM is really using this, it must be mapped by him. */
859 addr = of_get_property(dp, "address", NULL);
860 if (!addr) {
861 prom_printf("PROM does not have timer mapped, trying to continue.\n");
862 prom_timers = (struct sun5_timer *) 0;
863 return;
864 }
865 prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
866 }
867
868 static void kill_prom_timer(void)
869 {
870 if (!prom_timers)
871 return;
872
873 /* Save them away for later. */
874 prom_limit0 = prom_timers->limit0;
875 prom_limit1 = prom_timers->limit1;
876
877 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
878 * We turn both off here just to be paranoid.
879 */
880 prom_timers->limit0 = 0;
881 prom_timers->limit1 = 0;
882
883 /* Wheee, eat the interrupt packet too... */
884 __asm__ __volatile__(
885 " mov 0x40, %%g2\n"
886 " ldxa [%%g0] %0, %%g1\n"
887 " ldxa [%%g2] %1, %%g1\n"
888 " stxa %%g0, [%%g0] %0\n"
889 " membar #Sync\n"
890 : /* no outputs */
891 : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
892 : "g1", "g2");
893 }
894
895 void init_irqwork_curcpu(void)
896 {
897 int cpu = hard_smp_processor_id();
898
899 trap_block[cpu].irq_worklist = 0;
900 }
901
902 /* Please be very careful with register_one_mondo() and
903 * sun4v_register_mondo_queues().
904 *
905 * On SMP this gets invoked from the CPU trampoline before
906 * the cpu has fully taken over the trap table from OBP,
907 * and it's kernel stack + %g6 thread register state is
908 * not fully cooked yet.
909 *
910 * Therefore you cannot make any OBP calls, not even prom_printf,
911 * from these two routines.
912 */
913 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask)
914 {
915 unsigned long num_entries = (qmask + 1) / 64;
916 unsigned long status;
917
918 status = sun4v_cpu_qconf(type, paddr, num_entries);
919 if (status != HV_EOK) {
920 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
921 "err %lu\n", type, paddr, num_entries, status);
922 prom_halt();
923 }
924 }
925
926 static void __cpuinit sun4v_register_mondo_queues(int this_cpu)
927 {
928 struct trap_per_cpu *tb = &trap_block[this_cpu];
929
930 register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
931 tb->cpu_mondo_qmask);
932 register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
933 tb->dev_mondo_qmask);
934 register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
935 tb->resum_qmask);
936 register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
937 tb->nonresum_qmask);
938 }
939
940 static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask, int use_bootmem)
941 {
942 unsigned long size = PAGE_ALIGN(qmask + 1);
943 unsigned long order = get_order(size);
944 void *p = NULL;
945
946 if (use_bootmem) {
947 p = __alloc_bootmem_low(size, size, 0);
948 } else {
949 struct page *page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, order);
950 if (page)
951 p = page_address(page);
952 }
953
954 if (!p) {
955 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
956 prom_halt();
957 }
958
959 *pa_ptr = __pa(p);
960 }
961
962 static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask, int use_bootmem)
963 {
964 unsigned long size = PAGE_ALIGN(qmask + 1);
965 unsigned long order = get_order(size);
966 void *p = NULL;
967
968 if (use_bootmem) {
969 p = __alloc_bootmem_low(size, size, 0);
970 } else {
971 struct page *page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, order);
972 if (page)
973 p = page_address(page);
974 }
975
976 if (!p) {
977 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
978 prom_halt();
979 }
980
981 *pa_ptr = __pa(p);
982 }
983
984 static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem)
985 {
986 #ifdef CONFIG_SMP
987 void *page;
988
989 BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
990
991 if (use_bootmem)
992 page = alloc_bootmem_low_pages(PAGE_SIZE);
993 else
994 page = (void *) get_zeroed_page(GFP_ATOMIC);
995
996 if (!page) {
997 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
998 prom_halt();
999 }
1000
1001 tb->cpu_mondo_block_pa = __pa(page);
1002 tb->cpu_list_pa = __pa(page + 64);
1003 #endif
1004 }
1005
1006 /* Allocate and register the mondo and error queues for this cpu. */
1007 void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load)
1008 {
1009 struct trap_per_cpu *tb = &trap_block[cpu];
1010
1011 if (alloc) {
1012 alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask, use_bootmem);
1013 alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask, use_bootmem);
1014 alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask, use_bootmem);
1015 alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask, use_bootmem);
1016 alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask, use_bootmem);
1017 alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, tb->nonresum_qmask, use_bootmem);
1018
1019 init_cpu_send_mondo_info(tb, use_bootmem);
1020 }
1021
1022 if (load) {
1023 if (cpu != hard_smp_processor_id()) {
1024 prom_printf("SUN4V: init mondo on cpu %d not %d\n",
1025 cpu, hard_smp_processor_id());
1026 prom_halt();
1027 }
1028 sun4v_register_mondo_queues(cpu);
1029 }
1030 }
1031
1032 static struct irqaction timer_irq_action = {
1033 .name = "timer",
1034 };
1035
1036 /* Only invoked on boot processor. */
1037 void __init init_IRQ(void)
1038 {
1039 map_prom_timers();
1040 kill_prom_timer();
1041 memset(&ivector_table[0], 0, sizeof(ivector_table));
1042
1043 if (tlb_type == hypervisor)
1044 sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
1045
1046 /* We need to clear any IRQ's pending in the soft interrupt
1047 * registers, a spurious one could be left around from the
1048 * PROM timer which we just disabled.
1049 */
1050 clear_softint(get_softint());
1051
1052 /* Now that ivector table is initialized, it is safe
1053 * to receive IRQ vector traps. We will normally take
1054 * one or two right now, in case some device PROM used
1055 * to boot us wants to speak to us. We just ignore them.
1056 */
1057 __asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
1058 "or %%g1, %0, %%g1\n\t"
1059 "wrpr %%g1, 0x0, %%pstate"
1060 : /* No outputs */
1061 : "i" (PSTATE_IE)
1062 : "g1");
1063
1064 irq_desc[0].action = &timer_irq_action;
1065 }
linux 2.6 git repository for openrd