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[MIPS] rbtx4938: Add generic GPIO support
[linux-2.6/linux-2.6-openrd.git] / arch / mips / tx4938 / toshiba_rbtx4938 / setup.c
blob12b9f4f9c3a207312da410add926ff6a4bedb22e
1 /*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c
3 *
4 * Setup pointers to hardware-dependent routines.
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/ioport.h>
17 #include <linux/proc_fs.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/console.h>
21 #include <linux/pci.h>
22 #include <linux/pm.h>
23 #include <linux/platform_device.h>
24
25 #include <asm/wbflush.h>
26 #include <asm/reboot.h>
27 #include <asm/irq.h>
28 #include <asm/time.h>
29 #include <asm/uaccess.h>
30 #include <asm/io.h>
31 #include <asm/bootinfo.h>
32 #include <asm/gpio.h>
33 #include <asm/tx4938/rbtx4938.h>
34 #ifdef CONFIG_SERIAL_TXX9
35 #include <linux/tty.h>
36 #include <linux/serial.h>
37 #include <linux/serial_core.h>
38 #endif
39
40 extern void rbtx4938_time_init(void) __init;
41 extern char * __init prom_getcmdline(void);
42 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
43
44 /* These functions are used for rebooting or halting the machine*/
45 extern void rbtx4938_machine_restart(char *command);
46 extern void rbtx4938_machine_halt(void);
47 extern void rbtx4938_machine_power_off(void);
48
49 /* clocks */
50 unsigned int txx9_master_clock;
51 unsigned int txx9_cpu_clock;
52 unsigned int txx9_gbus_clock;
53
54 unsigned long rbtx4938_ce_base[8];
55 unsigned long rbtx4938_ce_size[8];
56 int txboard_pci66_mode;
57 static int tx4938_pcic_trdyto; /* default: disabled */
58 static int tx4938_pcic_retryto; /* default: disabled */
59 static int tx4938_ccfg_toeon = 1;
60
61 struct tx4938_pcic_reg *pcicptrs[4] = {
62 tx4938_pcicptr /* default setting for TX4938 */
63 };
64
65 static struct {
66 unsigned long base;
67 unsigned long size;
68 } phys_regions[16] __initdata;
69 static int num_phys_regions __initdata;
70
71 #define PHYS_REGION_MINSIZE 0x10000
72
73 void rbtx4938_machine_halt(void)
74 {
75 printk(KERN_NOTICE "System Halted\n");
76 local_irq_disable();
77
78 while (1)
79 __asm__(".set\tmips3\n\t"
80 "wait\n\t"
81 ".set\tmips0");
82 }
83
84 void rbtx4938_machine_power_off(void)
85 {
86 rbtx4938_machine_halt();
87 /* no return */
88 }
89
90 void rbtx4938_machine_restart(char *command)
91 {
92 local_irq_disable();
93
94 printk("Rebooting...");
95 *rbtx4938_softresetlock_ptr = 1;
96 *rbtx4938_sfvol_ptr = 1;
97 *rbtx4938_softreset_ptr = 1;
98 wbflush();
99
100 while(1);
101 }
102
103 void __init
104 txboard_add_phys_region(unsigned long base, unsigned long size)
105 {
106 if (num_phys_regions >= ARRAY_SIZE(phys_regions)) {
107 printk("phys_region overflow\n");
108 return;
109 }
110 phys_regions[num_phys_regions].base = base;
111 phys_regions[num_phys_regions].size = size;
112 num_phys_regions++;
113 }
114 unsigned long __init
115 txboard_find_free_phys_region(unsigned long begin, unsigned long end,
116 unsigned long size)
117 {
118 unsigned long base;
119 int i;
120
121 for (base = begin / size * size; base < end; base += size) {
122 for (i = 0; i < num_phys_regions; i++) {
123 if (phys_regions[i].size &&
124 base <= phys_regions[i].base + (phys_regions[i].size - 1) &&
125 base + (size - 1) >= phys_regions[i].base)
126 break;
127 }
128 if (i == num_phys_regions)
129 return base;
130 }
131 return 0;
132 }
133 unsigned long __init
134 txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end,
135 unsigned long *size)
136 {
137 unsigned long sz, base;
138 for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) {
139 base = txboard_find_free_phys_region(begin, end, sz);
140 if (base) {
141 *size = sz;
142 return base;
143 }
144 }
145 return 0;
146 }
147 unsigned long __init
148 txboard_request_phys_region_range(unsigned long begin, unsigned long end,
149 unsigned long size)
150 {
151 unsigned long base;
152 base = txboard_find_free_phys_region(begin, end, size);
153 if (base)
154 txboard_add_phys_region(base, size);
155 return base;
156 }
157 unsigned long __init
158 txboard_request_phys_region(unsigned long size)
159 {
160 unsigned long base;
161 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
162 base = txboard_find_free_phys_region(begin, end, size);
163 if (base)
164 txboard_add_phys_region(base, size);
165 return base;
166 }
167 unsigned long __init
168 txboard_request_phys_region_shrink(unsigned long *size)
169 {
170 unsigned long base;
171 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
172 base = txboard_find_free_phys_region_shrink(begin, end, size);
173 if (base)
174 txboard_add_phys_region(base, *size);
175 return base;
176 }
177
178 #ifdef CONFIG_PCI
179 void __init
180 tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr,
181 struct pci_controller *channel,
182 unsigned long pci_io_base,
183 int extarb)
184 {
185 int i;
186
187 /* Disable All Initiator Space */
188 pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)|
189 TX4938_PCIC_PCICCFG_G2PMEN(1)|
190 TX4938_PCIC_PCICCFG_G2PMEN(2)|
191 TX4938_PCIC_PCICCFG_G2PIOEN);
192
193 /* GB->PCI mappings */
194 pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4;
195 pcicptr->g2piogbase = pci_io_base |
196 #ifdef __BIG_ENDIAN
197 TX4938_PCIC_G2PIOGBASE_ECHG
198 #else
199 TX4938_PCIC_G2PIOGBASE_BSDIS
200 #endif
201 ;
202 pcicptr->g2piopbase = 0;
203 for (i = 0; i < 3; i++) {
204 pcicptr->g2pmmask[i] = 0;
205 pcicptr->g2pmgbase[i] = 0;
206 pcicptr->g2pmpbase[i] = 0;
207 }
208 if (channel->mem_resource->end) {
209 pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4;
210 pcicptr->g2pmgbase[0] = channel->mem_resource->start |
211 #ifdef __BIG_ENDIAN
212 TX4938_PCIC_G2PMnGBASE_ECHG
213 #else
214 TX4938_PCIC_G2PMnGBASE_BSDIS
215 #endif
216 ;
217 pcicptr->g2pmpbase[0] = channel->mem_resource->start;
218 }
219 /* PCI->GB mappings (I/O 256B) */
220 pcicptr->p2giopbase = 0; /* 256B */
221 pcicptr->p2giogbase = 0;
222 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
223 pcicptr->p2gm0plbase = 0;
224 pcicptr->p2gm0pubase = 0;
225 pcicptr->p2gmgbase[0] = 0 |
226 TX4938_PCIC_P2GMnGBASE_TMEMEN |
227 #ifdef __BIG_ENDIAN
228 TX4938_PCIC_P2GMnGBASE_TECHG
229 #else
230 TX4938_PCIC_P2GMnGBASE_TBSDIS
231 #endif
232 ;
233 /* PCI->GB mappings (MEM 16MB) */
234 pcicptr->p2gm1plbase = 0xffffffff;
235 pcicptr->p2gm1pubase = 0xffffffff;
236 pcicptr->p2gmgbase[1] = 0;
237 /* PCI->GB mappings (MEM 1MB) */
238 pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */
239 pcicptr->p2gmgbase[2] = 0;
240
241 pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK;
242 /* Enable Initiator Memory Space */
243 if (channel->mem_resource->end)
244 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0);
245 /* Enable Initiator I/O Space */
246 if (channel->io_resource->end)
247 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN;
248 /* Enable Initiator Config */
249 pcicptr->pciccfg |=
250 TX4938_PCIC_PCICCFG_ICAEN |
251 TX4938_PCIC_PCICCFG_TCAR;
252
253 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
254 pcicptr->pcicfg1 = 0;
255
256 pcicptr->g2ptocnt &= ~0xffff;
257
258 if (tx4938_pcic_trdyto >= 0) {
259 pcicptr->g2ptocnt &= ~0xff;
260 pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff);
261 }
262
263 if (tx4938_pcic_retryto >= 0) {
264 pcicptr->g2ptocnt &= ~0xff00;
265 pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00);
266 }
267
268 /* Clear All Local Bus Status */
269 pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL;
270 /* Enable All Local Bus Interrupts */
271 pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL;
272 /* Clear All Initiator Status */
273 pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL;
274 /* Enable All Initiator Interrupts */
275 pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL;
276 /* Clear All PCI Status Error */
277 pcicptr->pcistatus =
278 (pcicptr->pcistatus & 0x0000ffff) |
279 (TX4938_PCIC_PCISTATUS_ALL << 16);
280 /* Enable All PCI Status Error Interrupts */
281 pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL;
282
283 if (!extarb) {
284 /* Reset Bus Arbiter */
285 pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA;
286 pcicptr->pbabm = 0;
287 /* Enable Bus Arbiter */
288 pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN;
289 }
290
291 /* PCIC Int => IRC IRQ16 */
292 pcicptr->pcicfg2 =
293 (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC;
294
295 pcicptr->pcistatus = PCI_COMMAND_MASTER |
296 PCI_COMMAND_MEMORY |
297 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
298 }
299
300 int __init
301 tx4938_report_pciclk(void)
302 {
303 unsigned long pcode = TX4938_REV_PCODE();
304 int pciclk = 0;
305 printk("TX%lx PCIC --%s PCICLK:",
306 pcode,
307 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : "");
308 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
309
310 switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) {
311 case TX4938_CCFG_PCIDIVMODE_4:
312 pciclk = txx9_cpu_clock / 4; break;
313 case TX4938_CCFG_PCIDIVMODE_4_5:
314 pciclk = txx9_cpu_clock * 2 / 9; break;
315 case TX4938_CCFG_PCIDIVMODE_5:
316 pciclk = txx9_cpu_clock / 5; break;
317 case TX4938_CCFG_PCIDIVMODE_5_5:
318 pciclk = txx9_cpu_clock * 2 / 11; break;
319 case TX4938_CCFG_PCIDIVMODE_8:
320 pciclk = txx9_cpu_clock / 8; break;
321 case TX4938_CCFG_PCIDIVMODE_9:
322 pciclk = txx9_cpu_clock / 9; break;
323 case TX4938_CCFG_PCIDIVMODE_10:
324 pciclk = txx9_cpu_clock / 10; break;
325 case TX4938_CCFG_PCIDIVMODE_11:
326 pciclk = txx9_cpu_clock / 11; break;
327 }
328 printk("Internal(%dMHz)", pciclk / 1000000);
329 } else {
330 printk("External");
331 pciclk = -1;
332 }
333 printk("\n");
334 return pciclk;
335 }
336
337 void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr)
338 {
339 pcicptrs[ch] = pcicptr;
340 }
341
342 struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch)
343 {
344 return pcicptrs[ch];
345 }
346
347 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
348 int top_bus, int busnr, int devfn)
349 {
350 static struct pci_dev dev;
351 static struct pci_bus bus;
352
353 dev.sysdata = (void *)hose;
354 dev.devfn = devfn;
355 bus.number = busnr;
356 bus.ops = hose->pci_ops;
357 bus.parent = NULL;
358 dev.bus = &bus;
359
360 return &dev;
361 }
362
363 #define EARLY_PCI_OP(rw, size, type) \
364 static int early_##rw##_config_##size(struct pci_controller *hose, \
365 int top_bus, int bus, int devfn, int offset, type value) \
366 { \
367 return pci_##rw##_config_##size( \
368 fake_pci_dev(hose, top_bus, bus, devfn), \
369 offset, value); \
370 }
371
372 EARLY_PCI_OP(read, word, u16 *)
373
374 int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus)
375 {
376 u32 pci_devfn;
377 unsigned short vid;
378 int devfn_start = 0;
379 int devfn_stop = 0xff;
380 int cap66 = -1;
381 u16 stat;
382
383 printk("PCI: Checking 66MHz capabilities...\n");
384
385 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
386 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
387 PCI_VENDOR_ID, &vid);
388
389 if (vid == 0xffff) continue;
390
391 /* check 66MHz capability */
392 if (cap66 < 0)
393 cap66 = 1;
394 if (cap66) {
395 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
396 PCI_STATUS, &stat);
397 if (!(stat & PCI_STATUS_66MHZ)) {
398 printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n",
399 current_bus, pci_devfn);
400 cap66 = 0;
401 break;
402 }
403 }
404 }
405 return cap66 > 0;
406 }
407
408 int __init
409 tx4938_pciclk66_setup(void)
410 {
411 int pciclk;
412
413 /* Assert M66EN */
414 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66;
415 /* Double PCICLK (if possible) */
416 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
417 unsigned int pcidivmode =
418 tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK;
419 switch (pcidivmode) {
420 case TX4938_CCFG_PCIDIVMODE_8:
421 case TX4938_CCFG_PCIDIVMODE_4:
422 pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
423 pciclk = txx9_cpu_clock / 4;
424 break;
425 case TX4938_CCFG_PCIDIVMODE_9:
426 case TX4938_CCFG_PCIDIVMODE_4_5:
427 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
428 pciclk = txx9_cpu_clock * 2 / 9;
429 break;
430 case TX4938_CCFG_PCIDIVMODE_10:
431 case TX4938_CCFG_PCIDIVMODE_5:
432 pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
433 pciclk = txx9_cpu_clock / 5;
434 break;
435 case TX4938_CCFG_PCIDIVMODE_11:
436 case TX4938_CCFG_PCIDIVMODE_5_5:
437 default:
438 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
439 pciclk = txx9_cpu_clock * 2 / 11;
440 break;
441 }
442 tx4938_ccfgptr->ccfg =
443 (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK)
444 | pcidivmode;
445 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
446 (unsigned long)tx4938_ccfgptr->ccfg);
447 } else {
448 pciclk = -1;
449 }
450 return pciclk;
451 }
452
453 extern struct pci_controller tx4938_pci_controller[];
454 static int __init tx4938_pcibios_init(void)
455 {
456 unsigned long mem_base[2];
457 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
458 unsigned long io_base[2];
459 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
460 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
461 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
462
463 PCIBIOS_MIN_IO = 0x00001000UL;
464 PCIBIOS_MIN_MEM = 0x01000000UL;
465
466 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
467 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
468
469 printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
470 (unsigned short)(tx4938_pcicptr->pciid >> 16),
471 (unsigned short)(tx4938_pcicptr->pciid & 0xffff),
472 (unsigned short)(tx4938_pcicptr->pciccrev & 0xff),
473 extarb ? "External" : "Internal");
474
475 /* setup PCI area */
476 tx4938_pci_controller[0].io_resource->start = io_base[0];
477 tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1;
478 tx4938_pci_controller[0].mem_resource->start = mem_base[0];
479 tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1;
480
481 set_tx4938_pcicptr(0, tx4938_pcicptr);
482
483 register_pci_controller(&tx4938_pci_controller[0]);
484
485 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) {
486 printk("TX4938_CCFG_PCI66 already configured\n");
487 txboard_pci66_mode = -1; /* already configured */
488 }
489
490 /* Reset PCI Bus */
491 *rbtx4938_pcireset_ptr = 0;
492 /* Reset PCIC */
493 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
494 if (txboard_pci66_mode > 0)
495 tx4938_pciclk66_setup();
496 mdelay(10);
497 /* clear PCIC reset */
498 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
499 *rbtx4938_pcireset_ptr = 1;
500 wbflush();
501 tx4938_report_pcic_status1(tx4938_pcicptr);
502
503 tx4938_report_pciclk();
504 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
505 if (txboard_pci66_mode == 0 &&
506 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {
507 /* Reset PCI Bus */
508 *rbtx4938_pcireset_ptr = 0;
509 /* Reset PCIC */
510 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
511 tx4938_pciclk66_setup();
512 mdelay(10);
513 /* clear PCIC reset */
514 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
515 *rbtx4938_pcireset_ptr = 1;
516 wbflush();
517 /* Reinitialize PCIC */
518 tx4938_report_pciclk();
519 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
520 }
521
522 mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]);
523 io_base[1] = txboard_request_phys_region_shrink(&io_size[1]);
524 /* Reset PCIC1 */
525 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST;
526 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
527 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD))
528 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66;
529 else
530 tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66;
531 mdelay(10);
532 /* clear PCIC1 reset */
533 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
534 tx4938_report_pcic_status1(tx4938_pcic1ptr);
535
536 printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x",
537 (unsigned short)(tx4938_pcic1ptr->pciid >> 16),
538 (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff),
539 (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff));
540 printk("%s PCICLK:%dMHz\n",
541 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "",
542 txx9_gbus_clock /
543 ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) /
544 1000000);
545
546 /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */
547 tx4938_pci_controller[1].io_resource->start =
548 io_base[1] - io_base[0];
549 tx4938_pci_controller[1].io_resource->end =
550 io_base[1] - io_base[0] + io_size[1] - 1;
551 tx4938_pci_controller[1].mem_resource->start = mem_base[1];
552 tx4938_pci_controller[1].mem_resource->end =
553 mem_base[1] + mem_size[1] - 1;
554 set_tx4938_pcicptr(1, tx4938_pcic1ptr);
555
556 register_pci_controller(&tx4938_pci_controller[1]);
557
558 tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb);
559
560 /* map ioport 0 to PCI I/O space address 0 */
561 set_io_port_base(KSEG1 + io_base[0]);
562
563 return 0;
564 }
565
566 arch_initcall(tx4938_pcibios_init);
567
568 #endif /* CONFIG_PCI */
569
570 /* SPI support */
571
572 /* chip select for SPI devices */
573 #define SEEPROM1_CS 7 /* PIO7 */
574 #define SEEPROM2_CS 0 /* IOC */
575 #define SEEPROM3_CS 1 /* IOC */
576 #define SRTC_CS 2 /* IOC */
577
578 static int rbtx4938_spi_cs_func(int chipid, int on)
579 {
580 unsigned char bit;
581 switch (chipid) {
582 case RBTX4938_SEEPROM1_CHIPID:
583 if (on)
584 tx4938_pioptr->dout &= ~(1 << SEEPROM1_CS);
585 else
586 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
587 return 0;
588 break;
589 case RBTX4938_SEEPROM2_CHIPID:
590 bit = (1 << SEEPROM2_CS);
591 break;
592 case RBTX4938_SEEPROM3_CHIPID:
593 bit = (1 << SEEPROM3_CS);
594 break;
595 case RBTX4938_SRTC_CHIPID:
596 bit = (1 << SRTC_CS);
597 break;
598 default:
599 return -ENODEV;
600 }
601 /* bit1,2,4 are low active, bit3 is high active */
602 *rbtx4938_spics_ptr =
603 (*rbtx4938_spics_ptr & ~bit) |
604 ((on ? (bit ^ 0x0b) : ~(bit ^ 0x0b)) & bit);
605 return 0;
606 }
607
608 #ifdef CONFIG_PCI
609 extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
610
611 int rbtx4938_get_tx4938_ethaddr(struct pci_dev *dev, unsigned char *addr)
612 {
613 struct pci_controller *channel = (struct pci_controller *)dev->bus->sysdata;
614 static unsigned char dat[17];
615 static int read_dat = 0;
616 int ch = 0;
617
618 if (channel != &tx4938_pci_controller[1])
619 return -ENODEV;
620 /* TX4938 PCIC1 */
621 switch (PCI_SLOT(dev->devfn)) {
622 case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
623 ch = 0;
624 break;
625 case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
626 ch = 1;
627 break;
628 default:
629 return -ENODEV;
630 }
631 if (!read_dat) {
632 unsigned char sum;
633 int i;
634 read_dat = 1;
635 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
636 if (spi_eeprom_read(RBTX4938_SEEPROM1_CHIPID,
637 0, dat, sizeof(dat))) {
638 printk(KERN_ERR "seeprom: read error.\n");
639 } else {
640 if (strcmp(dat, "MAC") != 0)
641 printk(KERN_WARNING "seeprom: bad signature.\n");
642 for (i = 0, sum = 0; i < sizeof(dat); i++)
643 sum += dat[i];
644 if (sum)
645 printk(KERN_WARNING "seeprom: bad checksum.\n");
646 }
647 }
648 memcpy(addr, &dat[4 + 6 * ch], 6);
649 return 0;
650 }
651 #endif /* CONFIG_PCI */
652
653 extern void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on));
654 static void __init rbtx4938_spi_setup(void)
655 {
656 /* set SPI_SEL */
657 tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL;
658 /* chip selects for SPI devices */
659 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
660 tx4938_pioptr->dir |= (1 << SEEPROM1_CS);
661 txx9_spi_init(TX4938_SPI_REG, rbtx4938_spi_cs_func);
662 }
663
664 static struct resource rbtx4938_fpga_resource;
665
666 static char pcode_str[8];
667 static struct resource tx4938_reg_resource = {
668 .start = TX4938_REG_BASE,
669 .end = TX4938_REG_BASE + TX4938_REG_SIZE,
670 .name = pcode_str,
671 .flags = IORESOURCE_MEM
672 };
673
674 void __init tx4938_board_setup(void)
675 {
676 int i;
677 unsigned long divmode;
678 int cpuclk = 0;
679 unsigned long pcode = TX4938_REV_PCODE();
680
681 ioport_resource.start = 0x1000;
682 ioport_resource.end = 0xffffffff;
683 iomem_resource.start = 0x1000;
684 iomem_resource.end = 0xffffffff; /* expand to 4GB */
685
686 sprintf(pcode_str, "TX%lx", pcode);
687 /* SDRAMC,EBUSC are configured by PROM */
688 for (i = 0; i < 8; i++) {
689 if (!(tx4938_ebuscptr->cr[i] & 0x8))
690 continue; /* disabled */
691 rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i);
692 txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i));
693 }
694
695 /* clocks */
696 if (txx9_master_clock) {
697 /* calculate gbus_clock and cpu_clock from master_clock */
698 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
699 switch (divmode) {
700 case TX4938_CCFG_DIVMODE_8:
701 case TX4938_CCFG_DIVMODE_10:
702 case TX4938_CCFG_DIVMODE_12:
703 case TX4938_CCFG_DIVMODE_16:
704 case TX4938_CCFG_DIVMODE_18:
705 txx9_gbus_clock = txx9_master_clock * 4; break;
706 default:
707 txx9_gbus_clock = txx9_master_clock;
708 }
709 switch (divmode) {
710 case TX4938_CCFG_DIVMODE_2:
711 case TX4938_CCFG_DIVMODE_8:
712 cpuclk = txx9_gbus_clock * 2; break;
713 case TX4938_CCFG_DIVMODE_2_5:
714 case TX4938_CCFG_DIVMODE_10:
715 cpuclk = txx9_gbus_clock * 5 / 2; break;
716 case TX4938_CCFG_DIVMODE_3:
717 case TX4938_CCFG_DIVMODE_12:
718 cpuclk = txx9_gbus_clock * 3; break;
719 case TX4938_CCFG_DIVMODE_4:
720 case TX4938_CCFG_DIVMODE_16:
721 cpuclk = txx9_gbus_clock * 4; break;
722 case TX4938_CCFG_DIVMODE_4_5:
723 case TX4938_CCFG_DIVMODE_18:
724 cpuclk = txx9_gbus_clock * 9 / 2; break;
725 }
726 txx9_cpu_clock = cpuclk;
727 } else {
728 if (txx9_cpu_clock == 0) {
729 txx9_cpu_clock = 300000000; /* 300MHz */
730 }
731 /* calculate gbus_clock and master_clock from cpu_clock */
732 cpuclk = txx9_cpu_clock;
733 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
734 switch (divmode) {
735 case TX4938_CCFG_DIVMODE_2:
736 case TX4938_CCFG_DIVMODE_8:
737 txx9_gbus_clock = cpuclk / 2; break;
738 case TX4938_CCFG_DIVMODE_2_5:
739 case TX4938_CCFG_DIVMODE_10:
740 txx9_gbus_clock = cpuclk * 2 / 5; break;
741 case TX4938_CCFG_DIVMODE_3:
742 case TX4938_CCFG_DIVMODE_12:
743 txx9_gbus_clock = cpuclk / 3; break;
744 case TX4938_CCFG_DIVMODE_4:
745 case TX4938_CCFG_DIVMODE_16:
746 txx9_gbus_clock = cpuclk / 4; break;
747 case TX4938_CCFG_DIVMODE_4_5:
748 case TX4938_CCFG_DIVMODE_18:
749 txx9_gbus_clock = cpuclk * 2 / 9; break;
750 }
751 switch (divmode) {
752 case TX4938_CCFG_DIVMODE_8:
753 case TX4938_CCFG_DIVMODE_10:
754 case TX4938_CCFG_DIVMODE_12:
755 case TX4938_CCFG_DIVMODE_16:
756 case TX4938_CCFG_DIVMODE_18:
757 txx9_master_clock = txx9_gbus_clock / 4; break;
758 default:
759 txx9_master_clock = txx9_gbus_clock;
760 }
761 }
762 /* change default value to udelay/mdelay take reasonable time */
763 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
764
765 /* CCFG */
766 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
767 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW;
768 /* clear PCIC1 reset */
769 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST)
770 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
771
772 /* enable Timeout BusError */
773 if (tx4938_ccfg_toeon)
774 tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE;
775
776 /* DMA selection */
777 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL;
778
779 /* Use external clock for external arbiter */
780 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB))
781 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL;
782
783 printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n",
784 pcode_str,
785 cpuclk / 1000000, txx9_master_clock / 1000000,
786 (unsigned long)tx4938_ccfgptr->crir,
787 tx4938_ccfgptr->ccfg,
788 tx4938_ccfgptr->pcfg);
789
790 printk("%s SDRAMC --", pcode_str);
791 for (i = 0; i < 4; i++) {
792 unsigned long long cr = tx4938_sdramcptr->cr[i];
793 unsigned long ram_base, ram_size;
794 if (!((unsigned long)cr & 0x00000400))
795 continue; /* disabled */
796 ram_base = (unsigned long)(cr >> 49) << 21;
797 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
798 if (ram_base >= 0x20000000)
799 continue; /* high memory (ignore) */
800 printk(" CR%d:%016Lx", i, cr);
801 txboard_add_phys_region(ram_base, ram_size);
802 }
803 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
804
805 /* SRAM */
806 if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) {
807 unsigned int size = 0x800;
808 unsigned long base =
809 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
810 txboard_add_phys_region(base, size);
811 }
812
813 /* IRC */
814 /* disable interrupt control */
815 tx4938_ircptr->cer = 0;
816
817 /* TMR */
818 /* disable all timers */
819 for (i = 0; i < TX4938_NR_TMR; i++) {
820 tx4938_tmrptr(i)->tcr = 0x00000020;
821 tx4938_tmrptr(i)->tisr = 0;
822 tx4938_tmrptr(i)->cpra = 0xffffffff;
823 tx4938_tmrptr(i)->itmr = 0;
824 tx4938_tmrptr(i)->ccdr = 0;
825 tx4938_tmrptr(i)->pgmr = 0;
826 }
827
828 /* enable DMA */
829 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
830 TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);
831
832 /* PIO */
833 tx4938_pioptr->maskcpu = 0;
834 tx4938_pioptr->maskext = 0;
835
836 /* TX4938 internal registers */
837 if (request_resource(&iomem_resource, &tx4938_reg_resource))
838 printk("request resource for internal registers failed\n");
839 }
840
841 #ifdef CONFIG_PCI
842 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr)
843 {
844 unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16);
845 unsigned long g2pstatus = pcicptr->g2pstatus;
846 unsigned long pcicstatus = pcicptr->pcicstatus;
847 static struct {
848 unsigned long flag;
849 const char *str;
850 } pcistat_tbl[] = {
851 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
852 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
853 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
854 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
855 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
856 { PCI_STATUS_PARITY, "MasterParityError" },
857 }, g2pstat_tbl[] = {
858 { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" },
859 { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" },
860 }, pcicstat_tbl[] = {
861 { TX4938_PCIC_PCICSTATUS_PME, "PME" },
862 { TX4938_PCIC_PCICSTATUS_TLB, "TLB" },
863 { TX4938_PCIC_PCICSTATUS_NIB, "NIB" },
864 { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" },
865 { TX4938_PCIC_PCICSTATUS_PERR, "PERR" },
866 { TX4938_PCIC_PCICSTATUS_SERR, "SERR" },
867 { TX4938_PCIC_PCICSTATUS_GBE, "GBE" },
868 { TX4938_PCIC_PCICSTATUS_IWB, "IWB" },
869 };
870 int i;
871
872 printk("pcistat:%04x(", pcistatus);
873 for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
874 if (pcistatus & pcistat_tbl[i].flag)
875 printk("%s ", pcistat_tbl[i].str);
876 printk("), g2pstatus:%08lx(", g2pstatus);
877 for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
878 if (g2pstatus & g2pstat_tbl[i].flag)
879 printk("%s ", g2pstat_tbl[i].str);
880 printk("), pcicstatus:%08lx(", pcicstatus);
881 for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
882 if (pcicstatus & pcicstat_tbl[i].flag)
883 printk("%s ", pcicstat_tbl[i].str);
884 printk(")\n");
885 }
886
887 void tx4938_report_pcic_status(void)
888 {
889 int i;
890 struct tx4938_pcic_reg *pcicptr;
891 for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++)
892 tx4938_report_pcic_status1(pcicptr);
893 }
894
895 #endif /* CONFIG_PCI */
896
897 /* We use onchip r4k counter or TMR timer as our system wide timer
898 * interrupt running at 100HZ. */
899
900 extern void __init rtc_rx5c348_init(int chipid);
901 void __init rbtx4938_time_init(void)
902 {
903 rtc_rx5c348_init(RBTX4938_SRTC_CHIPID);
904 mips_hpt_frequency = txx9_cpu_clock / 2;
905 }
906
907 void __init toshiba_rbtx4938_setup(void)
908 {
909 unsigned long long pcfg;
910 char *argptr;
911
912 iomem_resource.end = 0xffffffff; /* 4GB */
913
914 if (txx9_master_clock == 0)
915 txx9_master_clock = 25000000; /* 25MHz */
916 tx4938_board_setup();
917 /* setup irq stuff */
918 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000000); /* irq trigger */
919 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM1), 0x00000000); /* irq trigger */
920 /* setup serial stuff */
921 TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
922 TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
923
924 #ifndef CONFIG_PCI
925 set_io_port_base(RBTX4938_ETHER_BASE);
926 #endif
927
928 #ifdef CONFIG_SERIAL_TXX9
929 {
930 extern int early_serial_txx9_setup(struct uart_port *port);
931 int i;
932 struct uart_port req;
933 for(i = 0; i < 2; i++) {
934 memset(&req, 0, sizeof(req));
935 req.line = i;
936 req.iotype = UPIO_MEM;
937 req.membase = (char *)(0xff1ff300 + i * 0x100);
938 req.mapbase = 0xff1ff300 + i * 0x100;
939 req.irq = 32 + i;
940 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
941 req.uartclk = 50000000;
942 early_serial_txx9_setup(&req);
943 }
944 }
945 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
946 argptr = prom_getcmdline();
947 if (strstr(argptr, "console=") == NULL) {
948 strcat(argptr, " console=ttyS0,38400");
949 }
950 #endif
951 #endif
952
953 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
954 printk("PIOSEL: disabling both ata and nand selection\n");
955 local_irq_disable();
956 tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
957 #endif
958
959 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
960 printk("PIOSEL: enabling nand selection\n");
961 tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL;
962 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL;
963 #endif
964
965 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
966 printk("PIOSEL: enabling ata selection\n");
967 tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL;
968 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL;
969 #endif
970
971 #ifdef CONFIG_IP_PNP
972 argptr = prom_getcmdline();
973 if (strstr(argptr, "ip=") == NULL) {
974 strcat(argptr, " ip=any");
975 }
976 #endif
977
978
979 #ifdef CONFIG_FB
980 {
981 conswitchp = &dummy_con;
982 }
983 #endif
984
985 rbtx4938_spi_setup();
986 pcfg = tx4938_ccfgptr->pcfg; /* updated */
987 /* fixup piosel */
988 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
989 TX4938_PCFG_ATA_SEL) {
990 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04;
991 }
992 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
993 TX4938_PCFG_NDF_SEL) {
994 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08;
995 }
996 else {
997 *rbtx4938_piosel_ptr &= ~(0x08 | 0x04);
998 }
999
1000 rbtx4938_fpga_resource.name = "FPGA Registers";
1001 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
1002 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
1003 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
1004 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
1005 printk("request resource for fpga failed\n");
1006
1007 /* disable all OnBoard I/O interrupts */
1008 *rbtx4938_imask_ptr = 0;
1009
1010 _machine_restart = rbtx4938_machine_restart;
1011 _machine_halt = rbtx4938_machine_halt;
1012 pm_power_off = rbtx4938_machine_power_off;
1013
1014 *rbtx4938_led_ptr = 0xff;
1015 printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);
1016 printk(" DIPSW:%02x,%02x\n",
1017 *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
1018 }
1019
1020 #ifdef CONFIG_PROC_FS
1021 extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid);
1022 static int __init tx4938_spi_proc_setup(void)
1023 {
1024 struct proc_dir_entry *tx4938_spi_eeprom_dir;
1025
1026 tx4938_spi_eeprom_dir = proc_mkdir("spi_eeprom", 0);
1027
1028 if (!tx4938_spi_eeprom_dir)
1029 return -ENOMEM;
1030
1031 /* don't allow user access to RBTX4938_SEEPROM1_CHIPID
1032 * as it contains eth0 and eth1 MAC addresses
1033 */
1034 spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM2_CHIPID);
1035 spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM3_CHIPID);
1036
1037 return 0;
1038 }
1039
1040 __initcall(tx4938_spi_proc_setup);
1041 #endif
1042
1043 static int __init rbtx4938_ne_init(void)
1044 {
1045 struct resource res[] = {
1046 {
1047 .start = RBTX4938_RTL_8019_BASE,
1048 .end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
1049 .flags = IORESOURCE_IO,
1050 }, {
1051 .start = RBTX4938_RTL_8019_IRQ,
1052 .flags = IORESOURCE_IRQ,
1053 }
1054 };
1055 struct platform_device *dev =
1056 platform_device_register_simple("ne", -1,
1057 res, ARRAY_SIZE(res));
1058 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
1059 }
1060 device_initcall(rbtx4938_ne_init);
1061
1062 /* GPIO support */
1063
1064 static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
1065
1066 static void rbtx4938_spi_gpio_set(unsigned gpio, int value)
1067 {
1068 u8 val;
1069 unsigned long flags;
1070 gpio -= 16;
1071 spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
1072 val = *rbtx4938_spics_ptr;
1073 if (value)
1074 val |= 1 << gpio;
1075 else
1076 val &= ~(1 << gpio);
1077 *rbtx4938_spics_ptr = val;
1078 mmiowb();
1079 spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
1080 }
1081
1082 static int rbtx4938_spi_gpio_dir_out(unsigned gpio, int value)
1083 {
1084 rbtx4938_spi_gpio_set(gpio, value);
1085 return 0;
1086 }
1087
1088 static DEFINE_SPINLOCK(tx4938_gpio_lock);
1089
1090 static int tx4938_gpio_get(unsigned gpio)
1091 {
1092 return tx4938_pioptr->din & (1 << gpio);
1093 }
1094
1095 static void tx4938_gpio_set_raw(unsigned gpio, int value)
1096 {
1097 u32 val;
1098 val = tx4938_pioptr->dout;
1099 if (value)
1100 val |= 1 << gpio;
1101 else
1102 val &= ~(1 << gpio);
1103 tx4938_pioptr->dout = val;
1104 }
1105
1106 static void tx4938_gpio_set(unsigned gpio, int value)
1107 {
1108 unsigned long flags;
1109 spin_lock_irqsave(&tx4938_gpio_lock, flags);
1110 tx4938_gpio_set_raw(gpio, value);
1111 mmiowb();
1112 spin_unlock_irqrestore(&tx4938_gpio_lock, flags);
1113 }
1114
1115 static int tx4938_gpio_dir_in(unsigned gpio)
1116 {
1117 spin_lock_irq(&tx4938_gpio_lock);
1118 tx4938_pioptr->dir &= ~(1 << gpio);
1119 mmiowb();
1120 spin_unlock_irq(&tx4938_gpio_lock);
1121 return 0;
1122 }
1123
1124 static int tx4938_gpio_dir_out(unsigned int gpio, int value)
1125 {
1126 spin_lock_irq(&tx4938_gpio_lock);
1127 tx4938_gpio_set_raw(gpio, value);
1128 tx4938_pioptr->dir |= 1 << gpio;
1129 mmiowb();
1130 spin_unlock_irq(&tx4938_gpio_lock);
1131 return 0;
1132 }
1133
1134 int gpio_direction_input(unsigned gpio)
1135 {
1136 if (gpio < 16)
1137 return tx4938_gpio_dir_in(gpio);
1138 return -EINVAL;
1139 }
1140
1141 int gpio_direction_output(unsigned gpio, int value)
1142 {
1143 if (gpio < 16)
1144 return tx4938_gpio_dir_out(gpio, value);
1145 if (gpio < 16 + 3)
1146 return rbtx4938_spi_gpio_dir_out(gpio, value);
1147 return -EINVAL;
1148 }
1149
1150 int gpio_get_value(unsigned gpio)
1151 {
1152 if (gpio < 16)
1153 return tx4938_gpio_get(gpio);
1154 return 0;
1155 }
1156
1157 void gpio_set_value(unsigned gpio, int value)
1158 {
1159 if (gpio < 16)
1160 tx4938_gpio_set(gpio, value);
1161 else
1162 rbtx4938_spi_gpio_set(gpio, value);
1163 }
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