drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34
  35 /* General customization:
  36  */
  37
  38 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  39
  40 #define DRIVER_NAME             "i915"
  41 #define DRIVER_DESC             "Intel Graphics"
  42 #define DRIVER_DATE             "20060119"
  43
  44 enum pipe {
  45         PIPE_A = 0,
  46         PIPE_B,
  47 };
  48
  49 /* Interface history:
  50  *
  51  * 1.1: Original.
  52  * 1.2: Add Power Management
  53  * 1.3: Add vblank support
  54  * 1.4: Fix cmdbuffer path, add heap destroy
  55  * 1.5: Add vblank pipe configuration
  56  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  57  *      - Support vertical blank on secondary display pipe
  58  */
  59 #define DRIVER_MAJOR            1
  60 #define DRIVER_MINOR            6
  61 #define DRIVER_PATCHLEVEL       0
  62
  63 typedef struct _drm_i915_ring_buffer {
  64         int tail_mask;
  65         unsigned long Start;
  66         unsigned long End;
  67         unsigned long Size;
  68         u8 *virtual_start;
  69         int head;
  70         int tail;
  71         int space;
  72         drm_local_map_t map;
  73 } drm_i915_ring_buffer_t;
  74
  75 struct mem_block {
  76         struct mem_block *next;
  77         struct mem_block *prev;
  78         int start;
  79         int size;
  80         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
  81 };
  82
  83 typedef struct _drm_i915_vbl_swap {
  84         struct list_head head;
  85         drm_drawable_t drw_id;
  86         unsigned int pipe;
  87         unsigned int sequence;
  88 } drm_i915_vbl_swap_t;
  89
  90 struct intel_opregion {
  91         struct opregion_header *header;
  92         struct opregion_acpi *acpi;
  93         struct opregion_swsci *swsci;
  94         struct opregion_asle *asle;
  95         int enabled;
  96 };
  97
  98 typedef struct drm_i915_private {
  99         drm_local_map_t *sarea;
 100         drm_local_map_t *mmio_map;
 101
 102         drm_i915_sarea_t *sarea_priv;
 103         drm_i915_ring_buffer_t ring;
 104
 105         drm_dma_handle_t *status_page_dmah;
 106         void *hw_status_page;
 107         dma_addr_t dma_status_page;
 108         unsigned long counter;
 109         unsigned int status_gfx_addr;
 110         drm_local_map_t hws_map;
 111
 112         unsigned int cpp;
 113         int back_offset;
 114         int front_offset;
 115         int current_page;
 116         int page_flipping;
 117
 118         wait_queue_head_t irq_queue;
 119         atomic_t irq_received;
 120         atomic_t irq_emitted;
 121         /** Protects user_irq_refcount and irq_mask_reg */
 122         spinlock_t user_irq_lock;
 123         /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
 124         int user_irq_refcount;
 125         /** Cached value of IMR to avoid reads in updating the bitfield */
 126         u32 irq_mask_reg;
 127
 128         int tex_lru_log_granularity;
 129         int allow_batchbuffer;
 130         struct mem_block *agp_heap;
 131         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 132         int vblank_pipe;
 133
 134         spinlock_t swaps_lock;
 135         drm_i915_vbl_swap_t vbl_swaps;
 136         unsigned int swaps_pending;
 137
 138         struct intel_opregion opregion;
 139
 140         /* Register state */
 141         u8 saveLBB;
 142         u32 saveDSPACNTR;
 143         u32 saveDSPBCNTR;
 144         u32 saveDSPARB;
 145         u32 savePIPEACONF;
 146         u32 savePIPEBCONF;
 147         u32 savePIPEASRC;
 148         u32 savePIPEBSRC;
 149         u32 saveFPA0;
 150         u32 saveFPA1;
 151         u32 saveDPLL_A;
 152         u32 saveDPLL_A_MD;
 153         u32 saveHTOTAL_A;
 154         u32 saveHBLANK_A;
 155         u32 saveHSYNC_A;
 156         u32 saveVTOTAL_A;
 157         u32 saveVBLANK_A;
 158         u32 saveVSYNC_A;
 159         u32 saveBCLRPAT_A;
 160         u32 savePIPEASTAT;
 161         u32 saveDSPASTRIDE;
 162         u32 saveDSPASIZE;
 163         u32 saveDSPAPOS;
 164         u32 saveDSPAADDR;
 165         u32 saveDSPASURF;
 166         u32 saveDSPATILEOFF;
 167         u32 savePFIT_PGM_RATIOS;
 168         u32 saveBLC_PWM_CTL;
 169         u32 saveBLC_PWM_CTL2;
 170         u32 saveFPB0;
 171         u32 saveFPB1;
 172         u32 saveDPLL_B;
 173         u32 saveDPLL_B_MD;
 174         u32 saveHTOTAL_B;
 175         u32 saveHBLANK_B;
 176         u32 saveHSYNC_B;
 177         u32 saveVTOTAL_B;
 178         u32 saveVBLANK_B;
 179         u32 saveVSYNC_B;
 180         u32 saveBCLRPAT_B;
 181         u32 savePIPEBSTAT;
 182         u32 saveDSPBSTRIDE;
 183         u32 saveDSPBSIZE;
 184         u32 saveDSPBPOS;
 185         u32 saveDSPBADDR;
 186         u32 saveDSPBSURF;
 187         u32 saveDSPBTILEOFF;
 188         u32 saveVGA0;
 189         u32 saveVGA1;
 190         u32 saveVGA_PD;
 191         u32 saveVGACNTRL;
 192         u32 saveADPA;
 193         u32 saveLVDS;
 194         u32 savePP_ON_DELAYS;
 195         u32 savePP_OFF_DELAYS;
 196         u32 saveDVOA;
 197         u32 saveDVOB;
 198         u32 saveDVOC;
 199         u32 savePP_ON;
 200         u32 savePP_OFF;
 201         u32 savePP_CONTROL;
 202         u32 savePP_DIVISOR;
 203         u32 savePFIT_CONTROL;
 204         u32 save_palette_a[256];
 205         u32 save_palette_b[256];
 206         u32 saveFBC_CFB_BASE;
 207         u32 saveFBC_LL_BASE;
 208         u32 saveFBC_CONTROL;
 209         u32 saveFBC_CONTROL2;
 210         u32 saveIER;
 211         u32 saveIIR;
 212         u32 saveIMR;
 213         u32 saveCACHE_MODE_0;
 214         u32 saveD_STATE;
 215         u32 saveCG_2D_DIS;
 216         u32 saveMI_ARB_STATE;
 217         u32 saveSWF0[16];
 218         u32 saveSWF1[16];
 219         u32 saveSWF2[3];
 220         u8 saveMSR;
 221         u8 saveSR[8];
 222         u8 saveGR[25];
 223         u8 saveAR_INDEX;
 224         u8 saveAR[21];
 225         u8 saveDACMASK;
 226         u8 saveDACDATA[256*3]; /* 256 3-byte colors */
 227         u8 saveCR[37];
 228 } drm_i915_private_t;
 229
 230 extern struct drm_ioctl_desc i915_ioctls[];
 231 extern int i915_max_ioctl;
 232
 233                                 /* i915_dma.c */
 234 extern void i915_kernel_lost_context(struct drm_device * dev);
 235 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 236 extern int i915_driver_unload(struct drm_device *);
 237 extern void i915_driver_lastclose(struct drm_device * dev);
 238 extern void i915_driver_preclose(struct drm_device *dev,
 239                                  struct drm_file *file_priv);
 240 extern int i915_driver_device_is_agp(struct drm_device * dev);
 241 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 242                               unsigned long arg);
 243
 244 /* i915_irq.c */
 245 extern int i915_irq_emit(struct drm_device *dev, void *data,
 246                          struct drm_file *file_priv);
 247 extern int i915_irq_wait(struct drm_device *dev, void *data,
 248                          struct drm_file *file_priv);
 249
 250 extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
 251 extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
 252 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 253 extern void i915_driver_irq_preinstall(struct drm_device * dev);
 254 extern void i915_driver_irq_postinstall(struct drm_device * dev);
 255 extern void i915_driver_irq_uninstall(struct drm_device * dev);
 256 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 257                                 struct drm_file *file_priv);
 258 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 259                                 struct drm_file *file_priv);
 260 extern int i915_vblank_swap(struct drm_device *dev, void *data,
 261                             struct drm_file *file_priv);
 262 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
 263
 264 /* i915_mem.c */
 265 extern int i915_mem_alloc(struct drm_device *dev, void *data,
 266                           struct drm_file *file_priv);
 267 extern int i915_mem_free(struct drm_device *dev, void *data,
 268                          struct drm_file *file_priv);
 269 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
 270                               struct drm_file *file_priv);
 271 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
 272                                  struct drm_file *file_priv);
 273 extern void i915_mem_takedown(struct mem_block **heap);
 274 extern void i915_mem_release(struct drm_device * dev,
 275                              struct drm_file *file_priv, struct mem_block *heap);
 276
 277 /* i915_suspend.c */
 278 extern int i915_save_state(struct drm_device *dev);
 279 extern int i915_restore_state(struct drm_device *dev);
 280
 281 /* i915_opregion.c */
 282 extern int intel_opregion_init(struct drm_device *dev);
 283 extern void intel_opregion_free(struct drm_device *dev);
 284 extern void opregion_asle_intr(struct drm_device *dev);
 285 extern void opregion_enable_asle(struct drm_device *dev);
 286
 287 #define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, (reg))
 288 #define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
 289 #define I915_READ16(reg)        DRM_READ16(dev_priv->mmio_map, (reg))
 290 #define I915_WRITE16(reg,val)   DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
 291 #define I915_READ8(reg)         DRM_READ8(dev_priv->mmio_map, (reg))
 292 #define I915_WRITE8(reg,val)    DRM_WRITE8(dev_priv->mmio_map, (reg), (val))
 293
 294 #define I915_VERBOSE 0
 295
 296 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 297                         volatile char *virt;
 298
 299 #define BEGIN_LP_RING(n) do {                           \
 300         if (I915_VERBOSE)                               \
 301                 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));  \
 302         if (dev_priv->ring.space < (n)*4)               \
 303                 i915_wait_ring(dev, (n)*4, __func__);           \
 304         outcount = 0;                                   \
 305         outring = dev_priv->ring.tail;                  \
 306         ringmask = dev_priv->ring.tail_mask;            \
 307         virt = dev_priv->ring.virtual_start;            \
 308 } while (0)
 309
 310 #define OUT_RING(n) do {                                        \
 311         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 312         *(volatile unsigned int *)(virt + outring) = (n);       \
 313         outcount++;                                             \
 314         outring += 4;                                           \
 315         outring &= ringmask;                                    \
 316 } while (0)
 317
 318 #define ADVANCE_LP_RING() do {                                          \
 319         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 320         dev_priv->ring.tail = outring;                                  \
 321         dev_priv->ring.space -= outcount * 4;                           \
 322         I915_WRITE(PRB0_TAIL, outring);                 \
 323 } while(0)
 324
 325 /**
 326  * Reads a dword out of the status page, which is written to from the command
 327  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 328  * MI_STORE_DATA_IMM.
 329  *
 330  * The following dwords have a reserved meaning:
 331  * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 332  * 4: ring 0 head pointer
 333  * 5: ring 1 head pointer (915-class)
 334  * 6: ring 2 head pointer (915-class)
 335  *
 336  * The area from dword 0x10 to 0x3ff is available for driver usage.
 337  */
 338 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
 339 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)
 340
 341 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 342
 343 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
 344 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
 345 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
 346 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
 347 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
 348
 349 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
 350 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
 351 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
 352 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
 353                         (dev)->pci_device == 0x27AE)
 354 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
 355                        (dev)->pci_device == 0x2982 || \
 356                        (dev)->pci_device == 0x2992 || \
 357                        (dev)->pci_device == 0x29A2 || \
 358                        (dev)->pci_device == 0x2A02 || \
 359                        (dev)->pci_device == 0x2A12 || \
 360                        (dev)->pci_device == 0x2A42 || \
 361                        (dev)->pci_device == 0x2E02 || \
 362                        (dev)->pci_device == 0x2E12 || \
 363                        (dev)->pci_device == 0x2E22)
 364
 365 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
 366
 367 #define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
 368
 369 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
 370                      (dev)->pci_device == 0x2E12 || \
 371                      (dev)->pci_device == 0x2E22)
 372
 373 #define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||  \
 374                         (dev)->pci_device == 0x29B2 ||  \
 375                         (dev)->pci_device == 0x29D2)
 376
 377 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
 378                       IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
 379
 380 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
 381                         IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))
 382
 383 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev))
 384
 385 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 386
 387 #endif