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e1000e: provide family-specific PHY power up/down operations
[linux-2.6/linux-2.6-openrd.git] / drivers / net / e1000e / ich8lan.c
blob9c3895598923e7a64b8d5ddcdfc913f9e0f1de53
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 */
56
57 #include "e1000.h"
58
59 #define ICH_FLASH_GFPREG 0x0000
60 #define ICH_FLASH_HSFSTS 0x0004
61 #define ICH_FLASH_HSFCTL 0x0006
62 #define ICH_FLASH_FADDR 0x0008
63 #define ICH_FLASH_FDATA0 0x0010
64 #define ICH_FLASH_PR0 0x0074
65
66 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
67 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
68 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
69 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
70 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
71
72 #define ICH_CYCLE_READ 0
73 #define ICH_CYCLE_WRITE 2
74 #define ICH_CYCLE_ERASE 3
75
76 #define FLASH_GFPREG_BASE_MASK 0x1FFF
77 #define FLASH_SECTOR_ADDR_SHIFT 12
78
79 #define ICH_FLASH_SEG_SIZE_256 256
80 #define ICH_FLASH_SEG_SIZE_4K 4096
81 #define ICH_FLASH_SEG_SIZE_8K 8192
82 #define ICH_FLASH_SEG_SIZE_64K 65536
83
84
85 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
86
87 #define E1000_ICH_MNG_IAMT_MODE 0x2
88
89 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
90 (ID_LED_DEF1_OFF2 << 8) | \
91 (ID_LED_DEF1_ON2 << 4) | \
92 (ID_LED_DEF1_DEF2))
93
94 #define E1000_ICH_NVM_SIG_WORD 0x13
95 #define E1000_ICH_NVM_SIG_MASK 0xC000
96 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
97 #define E1000_ICH_NVM_SIG_VALUE 0x80
98
99 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
100
101 #define E1000_FEXTNVM_SW_CONFIG 1
102 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
103
104 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
105
106 #define E1000_ICH_RAR_ENTRIES 7
107
108 #define PHY_PAGE_SHIFT 5
109 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
110 ((reg) & MAX_PHY_REG_ADDRESS))
111 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
112 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
113
114 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
115 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
116 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
117
118 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
119
120 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
121
122 /* SMBus Address Phy Register */
123 #define HV_SMB_ADDR PHY_REG(768, 26)
124 #define HV_SMB_ADDR_PEC_EN 0x0200
125 #define HV_SMB_ADDR_VALID 0x0080
126
127 /* Strapping Option Register - RO */
128 #define E1000_STRAP 0x0000C
129 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
130 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
131
132 /* OEM Bits Phy Register */
133 #define HV_OEM_BITS PHY_REG(768, 25)
134 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
135 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
136 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
137
138 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
139 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
140
141 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
142 /* Offset 04h HSFSTS */
143 union ich8_hws_flash_status {
144 struct ich8_hsfsts {
145 u16 flcdone :1; /* bit 0 Flash Cycle Done */
146 u16 flcerr :1; /* bit 1 Flash Cycle Error */
147 u16 dael :1; /* bit 2 Direct Access error Log */
148 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
149 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
150 u16 reserved1 :2; /* bit 13:6 Reserved */
151 u16 reserved2 :6; /* bit 13:6 Reserved */
152 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
153 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
154 } hsf_status;
155 u16 regval;
156 };
157
158 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
159 /* Offset 06h FLCTL */
160 union ich8_hws_flash_ctrl {
161 struct ich8_hsflctl {
162 u16 flcgo :1; /* 0 Flash Cycle Go */
163 u16 flcycle :2; /* 2:1 Flash Cycle */
164 u16 reserved :5; /* 7:3 Reserved */
165 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
166 u16 flockdn :6; /* 15:10 Reserved */
167 } hsf_ctrl;
168 u16 regval;
169 };
170
171 /* ICH Flash Region Access Permissions */
172 union ich8_hws_flash_regacc {
173 struct ich8_flracc {
174 u32 grra :8; /* 0:7 GbE region Read Access */
175 u32 grwa :8; /* 8:15 GbE region Write Access */
176 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
177 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
178 } hsf_flregacc;
179 u16 regval;
180 };
181
182 /* ICH Flash Protected Region */
183 union ich8_flash_protected_range {
184 struct ich8_pr {
185 u32 base:13; /* 0:12 Protected Range Base */
186 u32 reserved1:2; /* 13:14 Reserved */
187 u32 rpe:1; /* 15 Read Protection Enable */
188 u32 limit:13; /* 16:28 Protected Range Limit */
189 u32 reserved2:2; /* 29:30 Reserved */
190 u32 wpe:1; /* 31 Write Protection Enable */
191 } range;
192 u32 regval;
193 };
194
195 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
196 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
197 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
198 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
199 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
200 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
201 u32 offset, u8 byte);
202 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
203 u8 *data);
204 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
205 u16 *data);
206 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
207 u8 size, u16 *data);
208 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
209 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
210 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
211 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
212 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
213 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
214 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
215 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
216 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
217 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
218 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
219 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
220 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
221 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
222 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
223
224 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
225 {
226 return readw(hw->flash_address + reg);
227 }
228
229 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
230 {
231 return readl(hw->flash_address + reg);
232 }
233
234 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
235 {
236 writew(val, hw->flash_address + reg);
237 }
238
239 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
240 {
241 writel(val, hw->flash_address + reg);
242 }
243
244 #define er16flash(reg) __er16flash(hw, (reg))
245 #define er32flash(reg) __er32flash(hw, (reg))
246 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
247 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
248
249 /**
250 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
251 * @hw: pointer to the HW structure
252 *
253 * Initialize family-specific PHY parameters and function pointers.
254 **/
255 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
256 {
257 struct e1000_phy_info *phy = &hw->phy;
258 s32 ret_val = 0;
259
260 phy->addr = 1;
261 phy->reset_delay_us = 100;
262
263 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
264 phy->ops.read_reg = e1000_read_phy_reg_hv;
265 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
266 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
267 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
268 phy->ops.write_reg = e1000_write_phy_reg_hv;
269 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
270 phy->ops.power_up = e1000_power_up_phy_copper;
271 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
272 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
273
274 phy->id = e1000_phy_unknown;
275 e1000e_get_phy_id(hw);
276 phy->type = e1000e_get_phy_type_from_id(phy->id);
277
278 if (phy->type == e1000_phy_82577) {
279 phy->ops.check_polarity = e1000_check_polarity_82577;
280 phy->ops.force_speed_duplex =
281 e1000_phy_force_speed_duplex_82577;
282 phy->ops.get_cable_length = e1000_get_cable_length_82577;
283 phy->ops.get_info = e1000_get_phy_info_82577;
284 phy->ops.commit = e1000e_phy_sw_reset;
285 }
286
287 return ret_val;
288 }
289
290 /**
291 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
292 * @hw: pointer to the HW structure
293 *
294 * Initialize family-specific PHY parameters and function pointers.
295 **/
296 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
297 {
298 struct e1000_phy_info *phy = &hw->phy;
299 s32 ret_val;
300 u16 i = 0;
301
302 phy->addr = 1;
303 phy->reset_delay_us = 100;
304
305 phy->ops.power_up = e1000_power_up_phy_copper;
306 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
307
308 /*
309 * We may need to do this twice - once for IGP and if that fails,
310 * we'll set BM func pointers and try again
311 */
312 ret_val = e1000e_determine_phy_address(hw);
313 if (ret_val) {
314 phy->ops.write_reg = e1000e_write_phy_reg_bm;
315 phy->ops.read_reg = e1000e_read_phy_reg_bm;
316 ret_val = e1000e_determine_phy_address(hw);
317 if (ret_val)
318 return ret_val;
319 }
320
321 phy->id = 0;
322 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
323 (i++ < 100)) {
324 msleep(1);
325 ret_val = e1000e_get_phy_id(hw);
326 if (ret_val)
327 return ret_val;
328 }
329
330 /* Verify phy id */
331 switch (phy->id) {
332 case IGP03E1000_E_PHY_ID:
333 phy->type = e1000_phy_igp_3;
334 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
335 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
336 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
337 break;
338 case IFE_E_PHY_ID:
339 case IFE_PLUS_E_PHY_ID:
340 case IFE_C_E_PHY_ID:
341 phy->type = e1000_phy_ife;
342 phy->autoneg_mask = E1000_ALL_NOT_GIG;
343 break;
344 case BME1000_E_PHY_ID:
345 phy->type = e1000_phy_bm;
346 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
347 phy->ops.read_reg = e1000e_read_phy_reg_bm;
348 phy->ops.write_reg = e1000e_write_phy_reg_bm;
349 phy->ops.commit = e1000e_phy_sw_reset;
350 break;
351 default:
352 return -E1000_ERR_PHY;
353 break;
354 }
355
356 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
357
358 return 0;
359 }
360
361 /**
362 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
363 * @hw: pointer to the HW structure
364 *
365 * Initialize family-specific NVM parameters and function
366 * pointers.
367 **/
368 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
369 {
370 struct e1000_nvm_info *nvm = &hw->nvm;
371 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
372 u32 gfpreg, sector_base_addr, sector_end_addr;
373 u16 i;
374
375 /* Can't read flash registers if the register set isn't mapped. */
376 if (!hw->flash_address) {
377 e_dbg("ERROR: Flash registers not mapped\n");
378 return -E1000_ERR_CONFIG;
379 }
380
381 nvm->type = e1000_nvm_flash_sw;
382
383 gfpreg = er32flash(ICH_FLASH_GFPREG);
384
385 /*
386 * sector_X_addr is a "sector"-aligned address (4096 bytes)
387 * Add 1 to sector_end_addr since this sector is included in
388 * the overall size.
389 */
390 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
391 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
392
393 /* flash_base_addr is byte-aligned */
394 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
395
396 /*
397 * find total size of the NVM, then cut in half since the total
398 * size represents two separate NVM banks.
399 */
400 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
401 << FLASH_SECTOR_ADDR_SHIFT;
402 nvm->flash_bank_size /= 2;
403 /* Adjust to word count */
404 nvm->flash_bank_size /= sizeof(u16);
405
406 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
407
408 /* Clear shadow ram */
409 for (i = 0; i < nvm->word_size; i++) {
410 dev_spec->shadow_ram[i].modified = false;
411 dev_spec->shadow_ram[i].value = 0xFFFF;
412 }
413
414 return 0;
415 }
416
417 /**
418 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
419 * @hw: pointer to the HW structure
420 *
421 * Initialize family-specific MAC parameters and function
422 * pointers.
423 **/
424 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
425 {
426 struct e1000_hw *hw = &adapter->hw;
427 struct e1000_mac_info *mac = &hw->mac;
428
429 /* Set media type function pointer */
430 hw->phy.media_type = e1000_media_type_copper;
431
432 /* Set mta register count */
433 mac->mta_reg_count = 32;
434 /* Set rar entry count */
435 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
436 if (mac->type == e1000_ich8lan)
437 mac->rar_entry_count--;
438 /* Set if manageability features are enabled. */
439 mac->arc_subsystem_valid = true;
440
441 /* LED operations */
442 switch (mac->type) {
443 case e1000_ich8lan:
444 case e1000_ich9lan:
445 case e1000_ich10lan:
446 /* ID LED init */
447 mac->ops.id_led_init = e1000e_id_led_init;
448 /* setup LED */
449 mac->ops.setup_led = e1000e_setup_led_generic;
450 /* cleanup LED */
451 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
452 /* turn on/off LED */
453 mac->ops.led_on = e1000_led_on_ich8lan;
454 mac->ops.led_off = e1000_led_off_ich8lan;
455 break;
456 case e1000_pchlan:
457 /* ID LED init */
458 mac->ops.id_led_init = e1000_id_led_init_pchlan;
459 /* setup LED */
460 mac->ops.setup_led = e1000_setup_led_pchlan;
461 /* cleanup LED */
462 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
463 /* turn on/off LED */
464 mac->ops.led_on = e1000_led_on_pchlan;
465 mac->ops.led_off = e1000_led_off_pchlan;
466 break;
467 default:
468 break;
469 }
470
471 /* Enable PCS Lock-loss workaround for ICH8 */
472 if (mac->type == e1000_ich8lan)
473 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
474
475 return 0;
476 }
477
478 /**
479 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
480 * @hw: pointer to the HW structure
481 *
482 * Checks to see of the link status of the hardware has changed. If a
483 * change in link status has been detected, then we read the PHY registers
484 * to get the current speed/duplex if link exists.
485 **/
486 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
487 {
488 struct e1000_mac_info *mac = &hw->mac;
489 s32 ret_val;
490 bool link;
491
492 /*
493 * We only want to go out to the PHY registers to see if Auto-Neg
494 * has completed and/or if our link status has changed. The
495 * get_link_status flag is set upon receiving a Link Status
496 * Change or Rx Sequence Error interrupt.
497 */
498 if (!mac->get_link_status) {
499 ret_val = 0;
500 goto out;
501 }
502
503 /*
504 * First we want to see if the MII Status Register reports
505 * link. If so, then we want to get the current speed/duplex
506 * of the PHY.
507 */
508 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
509 if (ret_val)
510 goto out;
511
512 if (hw->mac.type == e1000_pchlan) {
513 ret_val = e1000_k1_gig_workaround_hv(hw, link);
514 if (ret_val)
515 goto out;
516 }
517
518 if (!link)
519 goto out; /* No link detected */
520
521 mac->get_link_status = false;
522
523 if (hw->phy.type == e1000_phy_82578) {
524 ret_val = e1000_link_stall_workaround_hv(hw);
525 if (ret_val)
526 goto out;
527 }
528
529 /*
530 * Check if there was DownShift, must be checked
531 * immediately after link-up
532 */
533 e1000e_check_downshift(hw);
534
535 /*
536 * If we are forcing speed/duplex, then we simply return since
537 * we have already determined whether we have link or not.
538 */
539 if (!mac->autoneg) {
540 ret_val = -E1000_ERR_CONFIG;
541 goto out;
542 }
543
544 /*
545 * Auto-Neg is enabled. Auto Speed Detection takes care
546 * of MAC speed/duplex configuration. So we only need to
547 * configure Collision Distance in the MAC.
548 */
549 e1000e_config_collision_dist(hw);
550
551 /*
552 * Configure Flow Control now that Auto-Neg has completed.
553 * First, we need to restore the desired flow control
554 * settings because we may have had to re-autoneg with a
555 * different link partner.
556 */
557 ret_val = e1000e_config_fc_after_link_up(hw);
558 if (ret_val)
559 e_dbg("Error configuring flow control\n");
560
561 out:
562 return ret_val;
563 }
564
565 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
566 {
567 struct e1000_hw *hw = &adapter->hw;
568 s32 rc;
569
570 rc = e1000_init_mac_params_ich8lan(adapter);
571 if (rc)
572 return rc;
573
574 rc = e1000_init_nvm_params_ich8lan(hw);
575 if (rc)
576 return rc;
577
578 if (hw->mac.type == e1000_pchlan)
579 rc = e1000_init_phy_params_pchlan(hw);
580 else
581 rc = e1000_init_phy_params_ich8lan(hw);
582 if (rc)
583 return rc;
584
585 if (adapter->hw.phy.type == e1000_phy_ife) {
586 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
587 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
588 }
589
590 if ((adapter->hw.mac.type == e1000_ich8lan) &&
591 (adapter->hw.phy.type == e1000_phy_igp_3))
592 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
593
594 return 0;
595 }
596
597 static DEFINE_MUTEX(nvm_mutex);
598
599 /**
600 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
601 * @hw: pointer to the HW structure
602 *
603 * Acquires the mutex for performing NVM operations.
604 **/
605 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
606 {
607 mutex_lock(&nvm_mutex);
608
609 return 0;
610 }
611
612 /**
613 * e1000_release_nvm_ich8lan - Release NVM mutex
614 * @hw: pointer to the HW structure
615 *
616 * Releases the mutex used while performing NVM operations.
617 **/
618 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
619 {
620 mutex_unlock(&nvm_mutex);
621
622 return;
623 }
624
625 static DEFINE_MUTEX(swflag_mutex);
626
627 /**
628 * e1000_acquire_swflag_ich8lan - Acquire software control flag
629 * @hw: pointer to the HW structure
630 *
631 * Acquires the software control flag for performing PHY and select
632 * MAC CSR accesses.
633 **/
634 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
635 {
636 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
637 s32 ret_val = 0;
638
639 mutex_lock(&swflag_mutex);
640
641 while (timeout) {
642 extcnf_ctrl = er32(EXTCNF_CTRL);
643 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
644 break;
645
646 mdelay(1);
647 timeout--;
648 }
649
650 if (!timeout) {
651 e_dbg("SW/FW/HW has locked the resource for too long.\n");
652 ret_val = -E1000_ERR_CONFIG;
653 goto out;
654 }
655
656 timeout = SW_FLAG_TIMEOUT;
657
658 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
659 ew32(EXTCNF_CTRL, extcnf_ctrl);
660
661 while (timeout) {
662 extcnf_ctrl = er32(EXTCNF_CTRL);
663 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
664 break;
665
666 mdelay(1);
667 timeout--;
668 }
669
670 if (!timeout) {
671 e_dbg("Failed to acquire the semaphore.\n");
672 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
673 ew32(EXTCNF_CTRL, extcnf_ctrl);
674 ret_val = -E1000_ERR_CONFIG;
675 goto out;
676 }
677
678 out:
679 if (ret_val)
680 mutex_unlock(&swflag_mutex);
681
682 return ret_val;
683 }
684
685 /**
686 * e1000_release_swflag_ich8lan - Release software control flag
687 * @hw: pointer to the HW structure
688 *
689 * Releases the software control flag for performing PHY and select
690 * MAC CSR accesses.
691 **/
692 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
693 {
694 u32 extcnf_ctrl;
695
696 extcnf_ctrl = er32(EXTCNF_CTRL);
697 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
698 ew32(EXTCNF_CTRL, extcnf_ctrl);
699
700 mutex_unlock(&swflag_mutex);
701
702 return;
703 }
704
705 /**
706 * e1000_check_mng_mode_ich8lan - Checks management mode
707 * @hw: pointer to the HW structure
708 *
709 * This checks if the adapter has manageability enabled.
710 * This is a function pointer entry point only called by read/write
711 * routines for the PHY and NVM parts.
712 **/
713 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
714 {
715 u32 fwsm;
716
717 fwsm = er32(FWSM);
718
719 return (fwsm & E1000_FWSM_MODE_MASK) ==
720 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
721 }
722
723 /**
724 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
725 * @hw: pointer to the HW structure
726 *
727 * Checks if firmware is blocking the reset of the PHY.
728 * This is a function pointer entry point only called by
729 * reset routines.
730 **/
731 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
732 {
733 u32 fwsm;
734
735 fwsm = er32(FWSM);
736
737 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
738 }
739
740 /**
741 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
742 * @hw: pointer to the HW structure
743 *
744 * Forces the speed and duplex settings of the PHY.
745 * This is a function pointer entry point only called by
746 * PHY setup routines.
747 **/
748 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
749 {
750 struct e1000_phy_info *phy = &hw->phy;
751 s32 ret_val;
752 u16 data;
753 bool link;
754
755 if (phy->type != e1000_phy_ife) {
756 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
757 return ret_val;
758 }
759
760 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
761 if (ret_val)
762 return ret_val;
763
764 e1000e_phy_force_speed_duplex_setup(hw, &data);
765
766 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
767 if (ret_val)
768 return ret_val;
769
770 /* Disable MDI-X support for 10/100 */
771 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
772 if (ret_val)
773 return ret_val;
774
775 data &= ~IFE_PMC_AUTO_MDIX;
776 data &= ~IFE_PMC_FORCE_MDIX;
777
778 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
779 if (ret_val)
780 return ret_val;
781
782 e_dbg("IFE PMC: %X\n", data);
783
784 udelay(1);
785
786 if (phy->autoneg_wait_to_complete) {
787 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
788
789 ret_val = e1000e_phy_has_link_generic(hw,
790 PHY_FORCE_LIMIT,
791 100000,
792 &link);
793 if (ret_val)
794 return ret_val;
795
796 if (!link)
797 e_dbg("Link taking longer than expected.\n");
798
799 /* Try once more */
800 ret_val = e1000e_phy_has_link_generic(hw,
801 PHY_FORCE_LIMIT,
802 100000,
803 &link);
804 if (ret_val)
805 return ret_val;
806 }
807
808 return 0;
809 }
810
811 /**
812 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
813 * @hw: pointer to the HW structure
814 *
815 * SW should configure the LCD from the NVM extended configuration region
816 * as a workaround for certain parts.
817 **/
818 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
819 {
820 struct e1000_phy_info *phy = &hw->phy;
821 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
822 s32 ret_val;
823 u16 word_addr, reg_data, reg_addr, phy_page = 0;
824
825 ret_val = hw->phy.ops.acquire(hw);
826 if (ret_val)
827 return ret_val;
828
829 /*
830 * Initialize the PHY from the NVM on ICH platforms. This
831 * is needed due to an issue where the NVM configuration is
832 * not properly autoloaded after power transitions.
833 * Therefore, after each PHY reset, we will load the
834 * configuration data out of the NVM manually.
835 */
836 if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
837 (hw->mac.type == e1000_pchlan)) {
838 struct e1000_adapter *adapter = hw->adapter;
839
840 /* Check if SW needs to configure the PHY */
841 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
842 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
843 (hw->mac.type == e1000_pchlan))
844 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
845 else
846 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
847
848 data = er32(FEXTNVM);
849 if (!(data & sw_cfg_mask))
850 goto out;
851
852 /* Wait for basic configuration completes before proceeding */
853 e1000_lan_init_done_ich8lan(hw);
854
855 /*
856 * Make sure HW does not configure LCD from PHY
857 * extended configuration before SW configuration
858 */
859 data = er32(EXTCNF_CTRL);
860 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
861 goto out;
862
863 cnf_size = er32(EXTCNF_SIZE);
864 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
865 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
866 if (!cnf_size)
867 goto out;
868
869 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
870 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
871
872 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
873 (hw->mac.type == e1000_pchlan)) {
874 /*
875 * HW configures the SMBus address and LEDs when the
876 * OEM and LCD Write Enable bits are set in the NVM.
877 * When both NVM bits are cleared, SW will configure
878 * them instead.
879 */
880 data = er32(STRAP);
881 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
882 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
883 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
884 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
885 reg_data);
886 if (ret_val)
887 goto out;
888
889 data = er32(LEDCTL);
890 ret_val = e1000_write_phy_reg_hv_locked(hw,
891 HV_LED_CONFIG,
892 (u16)data);
893 if (ret_val)
894 goto out;
895 }
896 /* Configure LCD from extended configuration region. */
897
898 /* cnf_base_addr is in DWORD */
899 word_addr = (u16)(cnf_base_addr << 1);
900
901 for (i = 0; i < cnf_size; i++) {
902 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
903 &reg_data);
904 if (ret_val)
905 goto out;
906
907 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
908 1, &reg_addr);
909 if (ret_val)
910 goto out;
911
912 /* Save off the PHY page for future writes. */
913 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
914 phy_page = reg_data;
915 continue;
916 }
917
918 reg_addr &= PHY_REG_MASK;
919 reg_addr |= phy_page;
920
921 ret_val = phy->ops.write_reg_locked(hw,
922 (u32)reg_addr,
923 reg_data);
924 if (ret_val)
925 goto out;
926 }
927 }
928
929 out:
930 hw->phy.ops.release(hw);
931 return ret_val;
932 }
933
934 /**
935 * e1000_k1_gig_workaround_hv - K1 Si workaround
936 * @hw: pointer to the HW structure
937 * @link: link up bool flag
938 *
939 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
940 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
941 * If link is down, the function will restore the default K1 setting located
942 * in the NVM.
943 **/
944 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
945 {
946 s32 ret_val = 0;
947 u16 status_reg = 0;
948 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
949
950 if (hw->mac.type != e1000_pchlan)
951 goto out;
952
953 /* Wrap the whole flow with the sw flag */
954 ret_val = hw->phy.ops.acquire(hw);
955 if (ret_val)
956 goto out;
957
958 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
959 if (link) {
960 if (hw->phy.type == e1000_phy_82578) {
961 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
962 &status_reg);
963 if (ret_val)
964 goto release;
965
966 status_reg &= BM_CS_STATUS_LINK_UP |
967 BM_CS_STATUS_RESOLVED |
968 BM_CS_STATUS_SPEED_MASK;
969
970 if (status_reg == (BM_CS_STATUS_LINK_UP |
971 BM_CS_STATUS_RESOLVED |
972 BM_CS_STATUS_SPEED_1000))
973 k1_enable = false;
974 }
975
976 if (hw->phy.type == e1000_phy_82577) {
977 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
978 &status_reg);
979 if (ret_val)
980 goto release;
981
982 status_reg &= HV_M_STATUS_LINK_UP |
983 HV_M_STATUS_AUTONEG_COMPLETE |
984 HV_M_STATUS_SPEED_MASK;
985
986 if (status_reg == (HV_M_STATUS_LINK_UP |
987 HV_M_STATUS_AUTONEG_COMPLETE |
988 HV_M_STATUS_SPEED_1000))
989 k1_enable = false;
990 }
991
992 /* Link stall fix for link up */
993 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
994 0x0100);
995 if (ret_val)
996 goto release;
997
998 } else {
999 /* Link stall fix for link down */
1000 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1001 0x4100);
1002 if (ret_val)
1003 goto release;
1004 }
1005
1006 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1007
1008 release:
1009 hw->phy.ops.release(hw);
1010 out:
1011 return ret_val;
1012 }
1013
1014 /**
1015 * e1000_configure_k1_ich8lan - Configure K1 power state
1016 * @hw: pointer to the HW structure
1017 * @enable: K1 state to configure
1018 *
1019 * Configure the K1 power state based on the provided parameter.
1020 * Assumes semaphore already acquired.
1021 *
1022 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1023 **/
1024 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1025 {
1026 s32 ret_val = 0;
1027 u32 ctrl_reg = 0;
1028 u32 ctrl_ext = 0;
1029 u32 reg = 0;
1030 u16 kmrn_reg = 0;
1031
1032 ret_val = e1000e_read_kmrn_reg_locked(hw,
1033 E1000_KMRNCTRLSTA_K1_CONFIG,
1034 &kmrn_reg);
1035 if (ret_val)
1036 goto out;
1037
1038 if (k1_enable)
1039 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1040 else
1041 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1042
1043 ret_val = e1000e_write_kmrn_reg_locked(hw,
1044 E1000_KMRNCTRLSTA_K1_CONFIG,
1045 kmrn_reg);
1046 if (ret_val)
1047 goto out;
1048
1049 udelay(20);
1050 ctrl_ext = er32(CTRL_EXT);
1051 ctrl_reg = er32(CTRL);
1052
1053 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1054 reg |= E1000_CTRL_FRCSPD;
1055 ew32(CTRL, reg);
1056
1057 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1058 udelay(20);
1059 ew32(CTRL, ctrl_reg);
1060 ew32(CTRL_EXT, ctrl_ext);
1061 udelay(20);
1062
1063 out:
1064 return ret_val;
1065 }
1066
1067 /**
1068 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1069 * @hw: pointer to the HW structure
1070 * @d0_state: boolean if entering d0 or d3 device state
1071 *
1072 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1073 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1074 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1075 **/
1076 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1077 {
1078 s32 ret_val = 0;
1079 u32 mac_reg;
1080 u16 oem_reg;
1081
1082 if (hw->mac.type != e1000_pchlan)
1083 return ret_val;
1084
1085 ret_val = hw->phy.ops.acquire(hw);
1086 if (ret_val)
1087 return ret_val;
1088
1089 mac_reg = er32(EXTCNF_CTRL);
1090 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1091 goto out;
1092
1093 mac_reg = er32(FEXTNVM);
1094 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1095 goto out;
1096
1097 mac_reg = er32(PHY_CTRL);
1098
1099 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1100 if (ret_val)
1101 goto out;
1102
1103 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1104
1105 if (d0_state) {
1106 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1107 oem_reg |= HV_OEM_BITS_GBE_DIS;
1108
1109 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1110 oem_reg |= HV_OEM_BITS_LPLU;
1111 } else {
1112 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1113 oem_reg |= HV_OEM_BITS_GBE_DIS;
1114
1115 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1116 oem_reg |= HV_OEM_BITS_LPLU;
1117 }
1118 /* Restart auto-neg to activate the bits */
1119 if (!e1000_check_reset_block(hw))
1120 oem_reg |= HV_OEM_BITS_RESTART_AN;
1121 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1122
1123 out:
1124 hw->phy.ops.release(hw);
1125
1126 return ret_val;
1127 }
1128
1129
1130 /**
1131 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1132 * done after every PHY reset.
1133 **/
1134 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1135 {
1136 s32 ret_val = 0;
1137
1138 if (hw->mac.type != e1000_pchlan)
1139 return ret_val;
1140
1141 if (((hw->phy.type == e1000_phy_82577) &&
1142 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1143 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1144 /* Disable generation of early preamble */
1145 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1146 if (ret_val)
1147 return ret_val;
1148
1149 /* Preamble tuning for SSC */
1150 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1151 if (ret_val)
1152 return ret_val;
1153 }
1154
1155 if (hw->phy.type == e1000_phy_82578) {
1156 /*
1157 * Return registers to default by doing a soft reset then
1158 * writing 0x3140 to the control register.
1159 */
1160 if (hw->phy.revision < 2) {
1161 e1000e_phy_sw_reset(hw);
1162 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1163 }
1164 }
1165
1166 /* Select page 0 */
1167 ret_val = hw->phy.ops.acquire(hw);
1168 if (ret_val)
1169 return ret_val;
1170
1171 hw->phy.addr = 1;
1172 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1173 if (ret_val)
1174 goto out;
1175 hw->phy.ops.release(hw);
1176
1177 /*
1178 * Configure the K1 Si workaround during phy reset assuming there is
1179 * link so that it disables K1 if link is in 1Gbps.
1180 */
1181 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1182
1183 out:
1184 return ret_val;
1185 }
1186
1187 /**
1188 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1189 * @hw: pointer to the HW structure
1190 *
1191 * Check the appropriate indication the MAC has finished configuring the
1192 * PHY after a software reset.
1193 **/
1194 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1195 {
1196 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1197
1198 /* Wait for basic configuration completes before proceeding */
1199 do {
1200 data = er32(STATUS);
1201 data &= E1000_STATUS_LAN_INIT_DONE;
1202 udelay(100);
1203 } while ((!data) && --loop);
1204
1205 /*
1206 * If basic configuration is incomplete before the above loop
1207 * count reaches 0, loading the configuration from NVM will
1208 * leave the PHY in a bad state possibly resulting in no link.
1209 */
1210 if (loop == 0)
1211 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1212
1213 /* Clear the Init Done bit for the next init event */
1214 data = er32(STATUS);
1215 data &= ~E1000_STATUS_LAN_INIT_DONE;
1216 ew32(STATUS, data);
1217 }
1218
1219 /**
1220 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1221 * @hw: pointer to the HW structure
1222 *
1223 * Resets the PHY
1224 * This is a function pointer entry point called by drivers
1225 * or other shared routines.
1226 **/
1227 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1228 {
1229 s32 ret_val = 0;
1230 u16 reg;
1231
1232 ret_val = e1000e_phy_hw_reset_generic(hw);
1233 if (ret_val)
1234 return ret_val;
1235
1236 /* Allow time for h/w to get to a quiescent state after reset */
1237 mdelay(10);
1238
1239 if (hw->mac.type == e1000_pchlan) {
1240 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1241 if (ret_val)
1242 return ret_val;
1243 }
1244
1245 /* Dummy read to clear the phy wakeup bit after lcd reset */
1246 if (hw->mac.type == e1000_pchlan)
1247 e1e_rphy(hw, BM_WUC, &reg);
1248
1249 /* Configure the LCD with the extended configuration region in NVM */
1250 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1251 if (ret_val)
1252 goto out;
1253
1254 /* Configure the LCD with the OEM bits in NVM */
1255 if (hw->mac.type == e1000_pchlan)
1256 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1257
1258 out:
1259 return 0;
1260 }
1261
1262 /**
1263 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
1264 * @hw: pointer to the HW structure
1265 *
1266 * Populates "phy" structure with various feature states.
1267 * This function is only called by other family-specific
1268 * routines.
1269 **/
1270 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
1271 {
1272 struct e1000_phy_info *phy = &hw->phy;
1273 s32 ret_val;
1274 u16 data;
1275 bool link;
1276
1277 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1278 if (ret_val)
1279 return ret_val;
1280
1281 if (!link) {
1282 e_dbg("Phy info is only valid if link is up\n");
1283 return -E1000_ERR_CONFIG;
1284 }
1285
1286 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
1287 if (ret_val)
1288 return ret_val;
1289 phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
1290
1291 if (phy->polarity_correction) {
1292 ret_val = phy->ops.check_polarity(hw);
1293 if (ret_val)
1294 return ret_val;
1295 } else {
1296 /* Polarity is forced */
1297 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
1298 ? e1000_rev_polarity_reversed
1299 : e1000_rev_polarity_normal;
1300 }
1301
1302 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1303 if (ret_val)
1304 return ret_val;
1305
1306 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
1307
1308 /* The following parameters are undefined for 10/100 operation. */
1309 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1310 phy->local_rx = e1000_1000t_rx_status_undefined;
1311 phy->remote_rx = e1000_1000t_rx_status_undefined;
1312
1313 return 0;
1314 }
1315
1316 /**
1317 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
1318 * @hw: pointer to the HW structure
1319 *
1320 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
1321 * This is a function pointer entry point called by drivers
1322 * or other shared routines.
1323 **/
1324 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
1325 {
1326 switch (hw->phy.type) {
1327 case e1000_phy_ife:
1328 return e1000_get_phy_info_ife_ich8lan(hw);
1329 break;
1330 case e1000_phy_igp_3:
1331 case e1000_phy_bm:
1332 case e1000_phy_82578:
1333 case e1000_phy_82577:
1334 return e1000e_get_phy_info_igp(hw);
1335 break;
1336 default:
1337 break;
1338 }
1339
1340 return -E1000_ERR_PHY_TYPE;
1341 }
1342
1343 /**
1344 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
1345 * @hw: pointer to the HW structure
1346 *
1347 * Polarity is determined on the polarity reversal feature being enabled.
1348 * This function is only called by other family-specific
1349 * routines.
1350 **/
1351 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
1352 {
1353 struct e1000_phy_info *phy = &hw->phy;
1354 s32 ret_val;
1355 u16 phy_data, offset, mask;
1356
1357 /*
1358 * Polarity is determined based on the reversal feature being enabled.
1359 */
1360 if (phy->polarity_correction) {
1361 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1362 mask = IFE_PESC_POLARITY_REVERSED;
1363 } else {
1364 offset = IFE_PHY_SPECIAL_CONTROL;
1365 mask = IFE_PSC_FORCE_POLARITY;
1366 }
1367
1368 ret_val = e1e_rphy(hw, offset, &phy_data);
1369
1370 if (!ret_val)
1371 phy->cable_polarity = (phy_data & mask)
1372 ? e1000_rev_polarity_reversed
1373 : e1000_rev_polarity_normal;
1374
1375 return ret_val;
1376 }
1377
1378 /**
1379 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1380 * @hw: pointer to the HW structure
1381 * @active: true to enable LPLU, false to disable
1382 *
1383 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1384 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1385 * the phy speed. This function will manually set the LPLU bit and restart
1386 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1387 * since it configures the same bit.
1388 **/
1389 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1390 {
1391 s32 ret_val = 0;
1392 u16 oem_reg;
1393
1394 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1395 if (ret_val)
1396 goto out;
1397
1398 if (active)
1399 oem_reg |= HV_OEM_BITS_LPLU;
1400 else
1401 oem_reg &= ~HV_OEM_BITS_LPLU;
1402
1403 oem_reg |= HV_OEM_BITS_RESTART_AN;
1404 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1405
1406 out:
1407 return ret_val;
1408 }
1409
1410 /**
1411 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1412 * @hw: pointer to the HW structure
1413 * @active: true to enable LPLU, false to disable
1414 *
1415 * Sets the LPLU D0 state according to the active flag. When
1416 * activating LPLU this function also disables smart speed
1417 * and vice versa. LPLU will not be activated unless the
1418 * device autonegotiation advertisement meets standards of
1419 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1420 * This is a function pointer entry point only called by
1421 * PHY setup routines.
1422 **/
1423 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1424 {
1425 struct e1000_phy_info *phy = &hw->phy;
1426 u32 phy_ctrl;
1427 s32 ret_val = 0;
1428 u16 data;
1429
1430 if (phy->type == e1000_phy_ife)
1431 return ret_val;
1432
1433 phy_ctrl = er32(PHY_CTRL);
1434
1435 if (active) {
1436 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1437 ew32(PHY_CTRL, phy_ctrl);
1438
1439 if (phy->type != e1000_phy_igp_3)
1440 return 0;
1441
1442 /*
1443 * Call gig speed drop workaround on LPLU before accessing
1444 * any PHY registers
1445 */
1446 if (hw->mac.type == e1000_ich8lan)
1447 e1000e_gig_downshift_workaround_ich8lan(hw);
1448
1449 /* When LPLU is enabled, we should disable SmartSpeed */
1450 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1451 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1452 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1453 if (ret_val)
1454 return ret_val;
1455 } else {
1456 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1457 ew32(PHY_CTRL, phy_ctrl);
1458
1459 if (phy->type != e1000_phy_igp_3)
1460 return 0;
1461
1462 /*
1463 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1464 * during Dx states where the power conservation is most
1465 * important. During driver activity we should enable
1466 * SmartSpeed, so performance is maintained.
1467 */
1468 if (phy->smart_speed == e1000_smart_speed_on) {
1469 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1470 &data);
1471 if (ret_val)
1472 return ret_val;
1473
1474 data |= IGP01E1000_PSCFR_SMART_SPEED;
1475 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1476 data);
1477 if (ret_val)
1478 return ret_val;
1479 } else if (phy->smart_speed == e1000_smart_speed_off) {
1480 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1481 &data);
1482 if (ret_val)
1483 return ret_val;
1484
1485 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1486 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1487 data);
1488 if (ret_val)
1489 return ret_val;
1490 }
1491 }
1492
1493 return 0;
1494 }
1495
1496 /**
1497 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1498 * @hw: pointer to the HW structure
1499 * @active: true to enable LPLU, false to disable
1500 *
1501 * Sets the LPLU D3 state according to the active flag. When
1502 * activating LPLU this function also disables smart speed
1503 * and vice versa. LPLU will not be activated unless the
1504 * device autonegotiation advertisement meets standards of
1505 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1506 * This is a function pointer entry point only called by
1507 * PHY setup routines.
1508 **/
1509 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1510 {
1511 struct e1000_phy_info *phy = &hw->phy;
1512 u32 phy_ctrl;
1513 s32 ret_val;
1514 u16 data;
1515
1516 phy_ctrl = er32(PHY_CTRL);
1517
1518 if (!active) {
1519 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1520 ew32(PHY_CTRL, phy_ctrl);
1521
1522 if (phy->type != e1000_phy_igp_3)
1523 return 0;
1524
1525 /*
1526 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1527 * during Dx states where the power conservation is most
1528 * important. During driver activity we should enable
1529 * SmartSpeed, so performance is maintained.
1530 */
1531 if (phy->smart_speed == e1000_smart_speed_on) {
1532 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1533 &data);
1534 if (ret_val)
1535 return ret_val;
1536
1537 data |= IGP01E1000_PSCFR_SMART_SPEED;
1538 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1539 data);
1540 if (ret_val)
1541 return ret_val;
1542 } else if (phy->smart_speed == e1000_smart_speed_off) {
1543 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1544 &data);
1545 if (ret_val)
1546 return ret_val;
1547
1548 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1549 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1550 data);
1551 if (ret_val)
1552 return ret_val;
1553 }
1554 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1555 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1556 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1557 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1558 ew32(PHY_CTRL, phy_ctrl);
1559
1560 if (phy->type != e1000_phy_igp_3)
1561 return 0;
1562
1563 /*
1564 * Call gig speed drop workaround on LPLU before accessing
1565 * any PHY registers
1566 */
1567 if (hw->mac.type == e1000_ich8lan)
1568 e1000e_gig_downshift_workaround_ich8lan(hw);
1569
1570 /* When LPLU is enabled, we should disable SmartSpeed */
1571 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1572 if (ret_val)
1573 return ret_val;
1574
1575 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1576 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1577 }
1578
1579 return 0;
1580 }
1581
1582 /**
1583 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1584 * @hw: pointer to the HW structure
1585 * @bank: pointer to the variable that returns the active bank
1586 *
1587 * Reads signature byte from the NVM using the flash access registers.
1588 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1589 **/
1590 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1591 {
1592 u32 eecd;
1593 struct e1000_nvm_info *nvm = &hw->nvm;
1594 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1595 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1596 u8 sig_byte = 0;
1597 s32 ret_val = 0;
1598
1599 switch (hw->mac.type) {
1600 case e1000_ich8lan:
1601 case e1000_ich9lan:
1602 eecd = er32(EECD);
1603 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1604 E1000_EECD_SEC1VAL_VALID_MASK) {
1605 if (eecd & E1000_EECD_SEC1VAL)
1606 *bank = 1;
1607 else
1608 *bank = 0;
1609
1610 return 0;
1611 }
1612 e_dbg("Unable to determine valid NVM bank via EEC - "
1613 "reading flash signature\n");
1614 /* fall-thru */
1615 default:
1616 /* set bank to 0 in case flash read fails */
1617 *bank = 0;
1618
1619 /* Check bank 0 */
1620 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1621 &sig_byte);
1622 if (ret_val)
1623 return ret_val;
1624 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1625 E1000_ICH_NVM_SIG_VALUE) {
1626 *bank = 0;
1627 return 0;
1628 }
1629
1630 /* Check bank 1 */
1631 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1632 bank1_offset,
1633 &sig_byte);
1634 if (ret_val)
1635 return ret_val;
1636 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1637 E1000_ICH_NVM_SIG_VALUE) {
1638 *bank = 1;
1639 return 0;
1640 }
1641
1642 e_dbg("ERROR: No valid NVM bank present\n");
1643 return -E1000_ERR_NVM;
1644 }
1645
1646 return 0;
1647 }
1648
1649 /**
1650 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1651 * @hw: pointer to the HW structure
1652 * @offset: The offset (in bytes) of the word(s) to read.
1653 * @words: Size of data to read in words
1654 * @data: Pointer to the word(s) to read at offset.
1655 *
1656 * Reads a word(s) from the NVM using the flash access registers.
1657 **/
1658 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1659 u16 *data)
1660 {
1661 struct e1000_nvm_info *nvm = &hw->nvm;
1662 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1663 u32 act_offset;
1664 s32 ret_val = 0;
1665 u32 bank = 0;
1666 u16 i, word;
1667
1668 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1669 (words == 0)) {
1670 e_dbg("nvm parameter(s) out of bounds\n");
1671 ret_val = -E1000_ERR_NVM;
1672 goto out;
1673 }
1674
1675 nvm->ops.acquire(hw);
1676
1677 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1678 if (ret_val) {
1679 e_dbg("Could not detect valid bank, assuming bank 0\n");
1680 bank = 0;
1681 }
1682
1683 act_offset = (bank) ? nvm->flash_bank_size : 0;
1684 act_offset += offset;
1685
1686 ret_val = 0;
1687 for (i = 0; i < words; i++) {
1688 if ((dev_spec->shadow_ram) &&
1689 (dev_spec->shadow_ram[offset+i].modified)) {
1690 data[i] = dev_spec->shadow_ram[offset+i].value;
1691 } else {
1692 ret_val = e1000_read_flash_word_ich8lan(hw,
1693 act_offset + i,
1694 &word);
1695 if (ret_val)
1696 break;
1697 data[i] = word;
1698 }
1699 }
1700
1701 nvm->ops.release(hw);
1702
1703 out:
1704 if (ret_val)
1705 e_dbg("NVM read error: %d\n", ret_val);
1706
1707 return ret_val;
1708 }
1709
1710 /**
1711 * e1000_flash_cycle_init_ich8lan - Initialize flash
1712 * @hw: pointer to the HW structure
1713 *
1714 * This function does initial flash setup so that a new read/write/erase cycle
1715 * can be started.
1716 **/
1717 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1718 {
1719 union ich8_hws_flash_status hsfsts;
1720 s32 ret_val = -E1000_ERR_NVM;
1721 s32 i = 0;
1722
1723 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1724
1725 /* Check if the flash descriptor is valid */
1726 if (hsfsts.hsf_status.fldesvalid == 0) {
1727 e_dbg("Flash descriptor invalid. "
1728 "SW Sequencing must be used.");
1729 return -E1000_ERR_NVM;
1730 }
1731
1732 /* Clear FCERR and DAEL in hw status by writing 1 */
1733 hsfsts.hsf_status.flcerr = 1;
1734 hsfsts.hsf_status.dael = 1;
1735
1736 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1737
1738 /*
1739 * Either we should have a hardware SPI cycle in progress
1740 * bit to check against, in order to start a new cycle or
1741 * FDONE bit should be changed in the hardware so that it
1742 * is 1 after hardware reset, which can then be used as an
1743 * indication whether a cycle is in progress or has been
1744 * completed.
1745 */
1746
1747 if (hsfsts.hsf_status.flcinprog == 0) {
1748 /*
1749 * There is no cycle running at present,
1750 * so we can start a cycle
1751 * Begin by setting Flash Cycle Done.
1752 */
1753 hsfsts.hsf_status.flcdone = 1;
1754 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1755 ret_val = 0;
1756 } else {
1757 /*
1758 * otherwise poll for sometime so the current
1759 * cycle has a chance to end before giving up.
1760 */
1761 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1762 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1763 if (hsfsts.hsf_status.flcinprog == 0) {
1764 ret_val = 0;
1765 break;
1766 }
1767 udelay(1);
1768 }
1769 if (ret_val == 0) {
1770 /*
1771 * Successful in waiting for previous cycle to timeout,
1772 * now set the Flash Cycle Done.
1773 */
1774 hsfsts.hsf_status.flcdone = 1;
1775 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1776 } else {
1777 e_dbg("Flash controller busy, cannot get access");
1778 }
1779 }
1780
1781 return ret_val;
1782 }
1783
1784 /**
1785 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1786 * @hw: pointer to the HW structure
1787 * @timeout: maximum time to wait for completion
1788 *
1789 * This function starts a flash cycle and waits for its completion.
1790 **/
1791 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1792 {
1793 union ich8_hws_flash_ctrl hsflctl;
1794 union ich8_hws_flash_status hsfsts;
1795 s32 ret_val = -E1000_ERR_NVM;
1796 u32 i = 0;
1797
1798 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1799 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1800 hsflctl.hsf_ctrl.flcgo = 1;
1801 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1802
1803 /* wait till FDONE bit is set to 1 */
1804 do {
1805 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1806 if (hsfsts.hsf_status.flcdone == 1)
1807 break;
1808 udelay(1);
1809 } while (i++ < timeout);
1810
1811 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1812 return 0;
1813
1814 return ret_val;
1815 }
1816
1817 /**
1818 * e1000_read_flash_word_ich8lan - Read word from flash
1819 * @hw: pointer to the HW structure
1820 * @offset: offset to data location
1821 * @data: pointer to the location for storing the data
1822 *
1823 * Reads the flash word at offset into data. Offset is converted
1824 * to bytes before read.
1825 **/
1826 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1827 u16 *data)
1828 {
1829 /* Must convert offset into bytes. */
1830 offset <<= 1;
1831
1832 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1833 }
1834
1835 /**
1836 * e1000_read_flash_byte_ich8lan - Read byte from flash
1837 * @hw: pointer to the HW structure
1838 * @offset: The offset of the byte to read.
1839 * @data: Pointer to a byte to store the value read.
1840 *
1841 * Reads a single byte from the NVM using the flash access registers.
1842 **/
1843 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1844 u8 *data)
1845 {
1846 s32 ret_val;
1847 u16 word = 0;
1848
1849 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1850 if (ret_val)
1851 return ret_val;
1852
1853 *data = (u8)word;
1854
1855 return 0;
1856 }
1857
1858 /**
1859 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1860 * @hw: pointer to the HW structure
1861 * @offset: The offset (in bytes) of the byte or word to read.
1862 * @size: Size of data to read, 1=byte 2=word
1863 * @data: Pointer to the word to store the value read.
1864 *
1865 * Reads a byte or word from the NVM using the flash access registers.
1866 **/
1867 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1868 u8 size, u16 *data)
1869 {
1870 union ich8_hws_flash_status hsfsts;
1871 union ich8_hws_flash_ctrl hsflctl;
1872 u32 flash_linear_addr;
1873 u32 flash_data = 0;
1874 s32 ret_val = -E1000_ERR_NVM;
1875 u8 count = 0;
1876
1877 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1878 return -E1000_ERR_NVM;
1879
1880 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1881 hw->nvm.flash_base_addr;
1882
1883 do {
1884 udelay(1);
1885 /* Steps */
1886 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1887 if (ret_val != 0)
1888 break;
1889
1890 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1891 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1892 hsflctl.hsf_ctrl.fldbcount = size - 1;
1893 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1894 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1895
1896 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1897
1898 ret_val = e1000_flash_cycle_ich8lan(hw,
1899 ICH_FLASH_READ_COMMAND_TIMEOUT);
1900
1901 /*
1902 * Check if FCERR is set to 1, if set to 1, clear it
1903 * and try the whole sequence a few more times, else
1904 * read in (shift in) the Flash Data0, the order is
1905 * least significant byte first msb to lsb
1906 */
1907 if (ret_val == 0) {
1908 flash_data = er32flash(ICH_FLASH_FDATA0);
1909 if (size == 1) {
1910 *data = (u8)(flash_data & 0x000000FF);
1911 } else if (size == 2) {
1912 *data = (u16)(flash_data & 0x0000FFFF);
1913 }
1914 break;
1915 } else {
1916 /*
1917 * If we've gotten here, then things are probably
1918 * completely hosed, but if the error condition is
1919 * detected, it won't hurt to give it another try...
1920 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1921 */
1922 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1923 if (hsfsts.hsf_status.flcerr == 1) {
1924 /* Repeat for some time before giving up. */
1925 continue;
1926 } else if (hsfsts.hsf_status.flcdone == 0) {
1927 e_dbg("Timeout error - flash cycle "
1928 "did not complete.");
1929 break;
1930 }
1931 }
1932 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1933
1934 return ret_val;
1935 }
1936
1937 /**
1938 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1939 * @hw: pointer to the HW structure
1940 * @offset: The offset (in bytes) of the word(s) to write.
1941 * @words: Size of data to write in words
1942 * @data: Pointer to the word(s) to write at offset.
1943 *
1944 * Writes a byte or word to the NVM using the flash access registers.
1945 **/
1946 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1947 u16 *data)
1948 {
1949 struct e1000_nvm_info *nvm = &hw->nvm;
1950 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1951 u16 i;
1952
1953 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1954 (words == 0)) {
1955 e_dbg("nvm parameter(s) out of bounds\n");
1956 return -E1000_ERR_NVM;
1957 }
1958
1959 nvm->ops.acquire(hw);
1960
1961 for (i = 0; i < words; i++) {
1962 dev_spec->shadow_ram[offset+i].modified = true;
1963 dev_spec->shadow_ram[offset+i].value = data[i];
1964 }
1965
1966 nvm->ops.release(hw);
1967
1968 return 0;
1969 }
1970
1971 /**
1972 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1973 * @hw: pointer to the HW structure
1974 *
1975 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1976 * which writes the checksum to the shadow ram. The changes in the shadow
1977 * ram are then committed to the EEPROM by processing each bank at a time
1978 * checking for the modified bit and writing only the pending changes.
1979 * After a successful commit, the shadow ram is cleared and is ready for
1980 * future writes.
1981 **/
1982 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1983 {
1984 struct e1000_nvm_info *nvm = &hw->nvm;
1985 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1986 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1987 s32 ret_val;
1988 u16 data;
1989
1990 ret_val = e1000e_update_nvm_checksum_generic(hw);
1991 if (ret_val)
1992 goto out;
1993
1994 if (nvm->type != e1000_nvm_flash_sw)
1995 goto out;
1996
1997 nvm->ops.acquire(hw);
1998
1999 /*
2000 * We're writing to the opposite bank so if we're on bank 1,
2001 * write to bank 0 etc. We also need to erase the segment that
2002 * is going to be written
2003 */
2004 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2005 if (ret_val) {
2006 e_dbg("Could not detect valid bank, assuming bank 0\n");
2007 bank = 0;
2008 }
2009
2010 if (bank == 0) {
2011 new_bank_offset = nvm->flash_bank_size;
2012 old_bank_offset = 0;
2013 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2014 if (ret_val) {
2015 nvm->ops.release(hw);
2016 goto out;
2017 }
2018 } else {
2019 old_bank_offset = nvm->flash_bank_size;
2020 new_bank_offset = 0;
2021 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2022 if (ret_val) {
2023 nvm->ops.release(hw);
2024 goto out;
2025 }
2026 }
2027
2028 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2029 /*
2030 * Determine whether to write the value stored
2031 * in the other NVM bank or a modified value stored
2032 * in the shadow RAM
2033 */
2034 if (dev_spec->shadow_ram[i].modified) {
2035 data = dev_spec->shadow_ram[i].value;
2036 } else {
2037 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2038 old_bank_offset,
2039 &data);
2040 if (ret_val)
2041 break;
2042 }
2043
2044 /*
2045 * If the word is 0x13, then make sure the signature bits
2046 * (15:14) are 11b until the commit has completed.
2047 * This will allow us to write 10b which indicates the
2048 * signature is valid. We want to do this after the write
2049 * has completed so that we don't mark the segment valid
2050 * while the write is still in progress
2051 */
2052 if (i == E1000_ICH_NVM_SIG_WORD)
2053 data |= E1000_ICH_NVM_SIG_MASK;
2054
2055 /* Convert offset to bytes. */
2056 act_offset = (i + new_bank_offset) << 1;
2057
2058 udelay(100);
2059 /* Write the bytes to the new bank. */
2060 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2061 act_offset,
2062 (u8)data);
2063 if (ret_val)
2064 break;
2065
2066 udelay(100);
2067 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2068 act_offset + 1,
2069 (u8)(data >> 8));
2070 if (ret_val)
2071 break;
2072 }
2073
2074 /*
2075 * Don't bother writing the segment valid bits if sector
2076 * programming failed.
2077 */
2078 if (ret_val) {
2079 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2080 e_dbg("Flash commit failed.\n");
2081 nvm->ops.release(hw);
2082 goto out;
2083 }
2084
2085 /*
2086 * Finally validate the new segment by setting bit 15:14
2087 * to 10b in word 0x13 , this can be done without an
2088 * erase as well since these bits are 11 to start with
2089 * and we need to change bit 14 to 0b
2090 */
2091 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2092 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2093 if (ret_val) {
2094 nvm->ops.release(hw);
2095 goto out;
2096 }
2097 data &= 0xBFFF;
2098 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2099 act_offset * 2 + 1,
2100 (u8)(data >> 8));
2101 if (ret_val) {
2102 nvm->ops.release(hw);
2103 goto out;
2104 }
2105
2106 /*
2107 * And invalidate the previously valid segment by setting
2108 * its signature word (0x13) high_byte to 0b. This can be
2109 * done without an erase because flash erase sets all bits
2110 * to 1's. We can write 1's to 0's without an erase
2111 */
2112 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2113 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2114 if (ret_val) {
2115 nvm->ops.release(hw);
2116 goto out;
2117 }
2118
2119 /* Great! Everything worked, we can now clear the cached entries. */
2120 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2121 dev_spec->shadow_ram[i].modified = false;
2122 dev_spec->shadow_ram[i].value = 0xFFFF;
2123 }
2124
2125 nvm->ops.release(hw);
2126
2127 /*
2128 * Reload the EEPROM, or else modifications will not appear
2129 * until after the next adapter reset.
2130 */
2131 e1000e_reload_nvm(hw);
2132 msleep(10);
2133
2134 out:
2135 if (ret_val)
2136 e_dbg("NVM update error: %d\n", ret_val);
2137
2138 return ret_val;
2139 }
2140
2141 /**
2142 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2143 * @hw: pointer to the HW structure
2144 *
2145 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2146 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2147 * calculated, in which case we need to calculate the checksum and set bit 6.
2148 **/
2149 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2150 {
2151 s32 ret_val;
2152 u16 data;
2153
2154 /*
2155 * Read 0x19 and check bit 6. If this bit is 0, the checksum
2156 * needs to be fixed. This bit is an indication that the NVM
2157 * was prepared by OEM software and did not calculate the
2158 * checksum...a likely scenario.
2159 */
2160 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2161 if (ret_val)
2162 return ret_val;
2163
2164 if ((data & 0x40) == 0) {
2165 data |= 0x40;
2166 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2167 if (ret_val)
2168 return ret_val;
2169 ret_val = e1000e_update_nvm_checksum(hw);
2170 if (ret_val)
2171 return ret_val;
2172 }
2173
2174 return e1000e_validate_nvm_checksum_generic(hw);
2175 }
2176
2177 /**
2178 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2179 * @hw: pointer to the HW structure
2180 *
2181 * To prevent malicious write/erase of the NVM, set it to be read-only
2182 * so that the hardware ignores all write/erase cycles of the NVM via
2183 * the flash control registers. The shadow-ram copy of the NVM will
2184 * still be updated, however any updates to this copy will not stick
2185 * across driver reloads.
2186 **/
2187 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2188 {
2189 struct e1000_nvm_info *nvm = &hw->nvm;
2190 union ich8_flash_protected_range pr0;
2191 union ich8_hws_flash_status hsfsts;
2192 u32 gfpreg;
2193
2194 nvm->ops.acquire(hw);
2195
2196 gfpreg = er32flash(ICH_FLASH_GFPREG);
2197
2198 /* Write-protect GbE Sector of NVM */
2199 pr0.regval = er32flash(ICH_FLASH_PR0);
2200 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2201 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2202 pr0.range.wpe = true;
2203 ew32flash(ICH_FLASH_PR0, pr0.regval);
2204
2205 /*
2206 * Lock down a subset of GbE Flash Control Registers, e.g.
2207 * PR0 to prevent the write-protection from being lifted.
2208 * Once FLOCKDN is set, the registers protected by it cannot
2209 * be written until FLOCKDN is cleared by a hardware reset.
2210 */
2211 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2212 hsfsts.hsf_status.flockdn = true;
2213 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2214
2215 nvm->ops.release(hw);
2216 }
2217
2218 /**
2219 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2220 * @hw: pointer to the HW structure
2221 * @offset: The offset (in bytes) of the byte/word to read.
2222 * @size: Size of data to read, 1=byte 2=word
2223 * @data: The byte(s) to write to the NVM.
2224 *
2225 * Writes one/two bytes to the NVM using the flash access registers.
2226 **/
2227 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2228 u8 size, u16 data)
2229 {
2230 union ich8_hws_flash_status hsfsts;
2231 union ich8_hws_flash_ctrl hsflctl;
2232 u32 flash_linear_addr;
2233 u32 flash_data = 0;
2234 s32 ret_val;
2235 u8 count = 0;
2236
2237 if (size < 1 || size > 2 || data > size * 0xff ||
2238 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2239 return -E1000_ERR_NVM;
2240
2241 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2242 hw->nvm.flash_base_addr;
2243
2244 do {
2245 udelay(1);
2246 /* Steps */
2247 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2248 if (ret_val)
2249 break;
2250
2251 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2252 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2253 hsflctl.hsf_ctrl.fldbcount = size -1;
2254 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2255 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2256
2257 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2258
2259 if (size == 1)
2260 flash_data = (u32)data & 0x00FF;
2261 else
2262 flash_data = (u32)data;
2263
2264 ew32flash(ICH_FLASH_FDATA0, flash_data);
2265
2266 /*
2267 * check if FCERR is set to 1 , if set to 1, clear it
2268 * and try the whole sequence a few more times else done
2269 */
2270 ret_val = e1000_flash_cycle_ich8lan(hw,
2271 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2272 if (!ret_val)
2273 break;
2274
2275 /*
2276 * If we're here, then things are most likely
2277 * completely hosed, but if the error condition
2278 * is detected, it won't hurt to give it another
2279 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2280 */
2281 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2282 if (hsfsts.hsf_status.flcerr == 1)
2283 /* Repeat for some time before giving up. */
2284 continue;
2285 if (hsfsts.hsf_status.flcdone == 0) {
2286 e_dbg("Timeout error - flash cycle "
2287 "did not complete.");
2288 break;
2289 }
2290 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2291
2292 return ret_val;
2293 }
2294
2295 /**
2296 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2297 * @hw: pointer to the HW structure
2298 * @offset: The index of the byte to read.
2299 * @data: The byte to write to the NVM.
2300 *
2301 * Writes a single byte to the NVM using the flash access registers.
2302 **/
2303 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2304 u8 data)
2305 {
2306 u16 word = (u16)data;
2307
2308 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2309 }
2310
2311 /**
2312 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2313 * @hw: pointer to the HW structure
2314 * @offset: The offset of the byte to write.
2315 * @byte: The byte to write to the NVM.
2316 *
2317 * Writes a single byte to the NVM using the flash access registers.
2318 * Goes through a retry algorithm before giving up.
2319 **/
2320 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2321 u32 offset, u8 byte)
2322 {
2323 s32 ret_val;
2324 u16 program_retries;
2325
2326 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2327 if (!ret_val)
2328 return ret_val;
2329
2330 for (program_retries = 0; program_retries < 100; program_retries++) {
2331 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2332 udelay(100);
2333 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2334 if (!ret_val)
2335 break;
2336 }
2337 if (program_retries == 100)
2338 return -E1000_ERR_NVM;
2339
2340 return 0;
2341 }
2342
2343 /**
2344 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2345 * @hw: pointer to the HW structure
2346 * @bank: 0 for first bank, 1 for second bank, etc.
2347 *
2348 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2349 * bank N is 4096 * N + flash_reg_addr.
2350 **/
2351 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2352 {
2353 struct e1000_nvm_info *nvm = &hw->nvm;
2354 union ich8_hws_flash_status hsfsts;
2355 union ich8_hws_flash_ctrl hsflctl;
2356 u32 flash_linear_addr;
2357 /* bank size is in 16bit words - adjust to bytes */
2358 u32 flash_bank_size = nvm->flash_bank_size * 2;
2359 s32 ret_val;
2360 s32 count = 0;
2361 s32 j, iteration, sector_size;
2362
2363 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2364
2365 /*
2366 * Determine HW Sector size: Read BERASE bits of hw flash status
2367 * register
2368 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2369 * consecutive sectors. The start index for the nth Hw sector
2370 * can be calculated as = bank * 4096 + n * 256
2371 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2372 * The start index for the nth Hw sector can be calculated
2373 * as = bank * 4096
2374 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2375 * (ich9 only, otherwise error condition)
2376 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2377 */
2378 switch (hsfsts.hsf_status.berasesz) {
2379 case 0:
2380 /* Hw sector size 256 */
2381 sector_size = ICH_FLASH_SEG_SIZE_256;
2382 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2383 break;
2384 case 1:
2385 sector_size = ICH_FLASH_SEG_SIZE_4K;
2386 iteration = 1;
2387 break;
2388 case 2:
2389 sector_size = ICH_FLASH_SEG_SIZE_8K;
2390 iteration = 1;
2391 break;
2392 case 3:
2393 sector_size = ICH_FLASH_SEG_SIZE_64K;
2394 iteration = 1;
2395 break;
2396 default:
2397 return -E1000_ERR_NVM;
2398 }
2399
2400 /* Start with the base address, then add the sector offset. */
2401 flash_linear_addr = hw->nvm.flash_base_addr;
2402 flash_linear_addr += (bank) ? flash_bank_size : 0;
2403
2404 for (j = 0; j < iteration ; j++) {
2405 do {
2406 /* Steps */
2407 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2408 if (ret_val)
2409 return ret_val;
2410
2411 /*
2412 * Write a value 11 (block Erase) in Flash
2413 * Cycle field in hw flash control
2414 */
2415 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2416 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2417 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2418
2419 /*
2420 * Write the last 24 bits of an index within the
2421 * block into Flash Linear address field in Flash
2422 * Address.
2423 */
2424 flash_linear_addr += (j * sector_size);
2425 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2426
2427 ret_val = e1000_flash_cycle_ich8lan(hw,
2428 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2429 if (ret_val == 0)
2430 break;
2431
2432 /*
2433 * Check if FCERR is set to 1. If 1,
2434 * clear it and try the whole sequence
2435 * a few more times else Done
2436 */
2437 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2438 if (hsfsts.hsf_status.flcerr == 1)
2439 /* repeat for some time before giving up */
2440 continue;
2441 else if (hsfsts.hsf_status.flcdone == 0)
2442 return ret_val;
2443 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2444 }
2445
2446 return 0;
2447 }
2448
2449 /**
2450 * e1000_valid_led_default_ich8lan - Set the default LED settings
2451 * @hw: pointer to the HW structure
2452 * @data: Pointer to the LED settings
2453 *
2454 * Reads the LED default settings from the NVM to data. If the NVM LED
2455 * settings is all 0's or F's, set the LED default to a valid LED default
2456 * setting.
2457 **/
2458 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2459 {
2460 s32 ret_val;
2461
2462 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2463 if (ret_val) {
2464 e_dbg("NVM Read Error\n");
2465 return ret_val;
2466 }
2467
2468 if (*data == ID_LED_RESERVED_0000 ||
2469 *data == ID_LED_RESERVED_FFFF)
2470 *data = ID_LED_DEFAULT_ICH8LAN;
2471
2472 return 0;
2473 }
2474
2475 /**
2476 * e1000_id_led_init_pchlan - store LED configurations
2477 * @hw: pointer to the HW structure
2478 *
2479 * PCH does not control LEDs via the LEDCTL register, rather it uses
2480 * the PHY LED configuration register.
2481 *
2482 * PCH also does not have an "always on" or "always off" mode which
2483 * complicates the ID feature. Instead of using the "on" mode to indicate
2484 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2485 * use "link_up" mode. The LEDs will still ID on request if there is no
2486 * link based on logic in e1000_led_[on|off]_pchlan().
2487 **/
2488 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2489 {
2490 struct e1000_mac_info *mac = &hw->mac;
2491 s32 ret_val;
2492 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2493 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2494 u16 data, i, temp, shift;
2495
2496 /* Get default ID LED modes */
2497 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2498 if (ret_val)
2499 goto out;
2500
2501 mac->ledctl_default = er32(LEDCTL);
2502 mac->ledctl_mode1 = mac->ledctl_default;
2503 mac->ledctl_mode2 = mac->ledctl_default;
2504
2505 for (i = 0; i < 4; i++) {
2506 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2507 shift = (i * 5);
2508 switch (temp) {
2509 case ID_LED_ON1_DEF2:
2510 case ID_LED_ON1_ON2:
2511 case ID_LED_ON1_OFF2:
2512 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2513 mac->ledctl_mode1 |= (ledctl_on << shift);
2514 break;
2515 case ID_LED_OFF1_DEF2:
2516 case ID_LED_OFF1_ON2:
2517 case ID_LED_OFF1_OFF2:
2518 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2519 mac->ledctl_mode1 |= (ledctl_off << shift);
2520 break;
2521 default:
2522 /* Do nothing */
2523 break;
2524 }
2525 switch (temp) {
2526 case ID_LED_DEF1_ON2:
2527 case ID_LED_ON1_ON2:
2528 case ID_LED_OFF1_ON2:
2529 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2530 mac->ledctl_mode2 |= (ledctl_on << shift);
2531 break;
2532 case ID_LED_DEF1_OFF2:
2533 case ID_LED_ON1_OFF2:
2534 case ID_LED_OFF1_OFF2:
2535 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2536 mac->ledctl_mode2 |= (ledctl_off << shift);
2537 break;
2538 default:
2539 /* Do nothing */
2540 break;
2541 }
2542 }
2543
2544 out:
2545 return ret_val;
2546 }
2547
2548 /**
2549 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2550 * @hw: pointer to the HW structure
2551 *
2552 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2553 * register, so the the bus width is hard coded.
2554 **/
2555 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2556 {
2557 struct e1000_bus_info *bus = &hw->bus;
2558 s32 ret_val;
2559
2560 ret_val = e1000e_get_bus_info_pcie(hw);
2561
2562 /*
2563 * ICH devices are "PCI Express"-ish. They have
2564 * a configuration space, but do not contain
2565 * PCI Express Capability registers, so bus width
2566 * must be hardcoded.
2567 */
2568 if (bus->width == e1000_bus_width_unknown)
2569 bus->width = e1000_bus_width_pcie_x1;
2570
2571 return ret_val;
2572 }
2573
2574 /**
2575 * e1000_reset_hw_ich8lan - Reset the hardware
2576 * @hw: pointer to the HW structure
2577 *
2578 * Does a full reset of the hardware which includes a reset of the PHY and
2579 * MAC.
2580 **/
2581 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2582 {
2583 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2584 u16 reg;
2585 u32 ctrl, icr, kab;
2586 s32 ret_val;
2587
2588 /*
2589 * Prevent the PCI-E bus from sticking if there is no TLP connection
2590 * on the last TLP read/write transaction when MAC is reset.
2591 */
2592 ret_val = e1000e_disable_pcie_master(hw);
2593 if (ret_val) {
2594 e_dbg("PCI-E Master disable polling has failed.\n");
2595 }
2596
2597 e_dbg("Masking off all interrupts\n");
2598 ew32(IMC, 0xffffffff);
2599
2600 /*
2601 * Disable the Transmit and Receive units. Then delay to allow
2602 * any pending transactions to complete before we hit the MAC
2603 * with the global reset.
2604 */
2605 ew32(RCTL, 0);
2606 ew32(TCTL, E1000_TCTL_PSP);
2607 e1e_flush();
2608
2609 msleep(10);
2610
2611 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2612 if (hw->mac.type == e1000_ich8lan) {
2613 /* Set Tx and Rx buffer allocation to 8k apiece. */
2614 ew32(PBA, E1000_PBA_8K);
2615 /* Set Packet Buffer Size to 16k. */
2616 ew32(PBS, E1000_PBS_16K);
2617 }
2618
2619 if (hw->mac.type == e1000_pchlan) {
2620 /* Save the NVM K1 bit setting*/
2621 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2622 if (ret_val)
2623 return ret_val;
2624
2625 if (reg & E1000_NVM_K1_ENABLE)
2626 dev_spec->nvm_k1_enabled = true;
2627 else
2628 dev_spec->nvm_k1_enabled = false;
2629 }
2630
2631 ctrl = er32(CTRL);
2632
2633 if (!e1000_check_reset_block(hw)) {
2634 /* Clear PHY Reset Asserted bit */
2635 if (hw->mac.type >= e1000_pchlan) {
2636 u32 status = er32(STATUS);
2637 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2638 }
2639
2640 /*
2641 * PHY HW reset requires MAC CORE reset at the same
2642 * time to make sure the interface between MAC and the
2643 * external PHY is reset.
2644 */
2645 ctrl |= E1000_CTRL_PHY_RST;
2646 }
2647 ret_val = e1000_acquire_swflag_ich8lan(hw);
2648 /* Whether or not the swflag was acquired, we need to reset the part */
2649 e_dbg("Issuing a global reset to ich8lan\n");
2650 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2651 msleep(20);
2652
2653 if (!ret_val)
2654 e1000_release_swflag_ich8lan(hw);
2655
2656 if (ctrl & E1000_CTRL_PHY_RST)
2657 ret_val = hw->phy.ops.get_cfg_done(hw);
2658
2659 if (hw->mac.type >= e1000_ich10lan) {
2660 e1000_lan_init_done_ich8lan(hw);
2661 } else {
2662 ret_val = e1000e_get_auto_rd_done(hw);
2663 if (ret_val) {
2664 /*
2665 * When auto config read does not complete, do not
2666 * return with an error. This can happen in situations
2667 * where there is no eeprom and prevents getting link.
2668 */
2669 e_dbg("Auto Read Done did not complete\n");
2670 }
2671 }
2672 /* Dummy read to clear the phy wakeup bit after lcd reset */
2673 if (hw->mac.type == e1000_pchlan)
2674 e1e_rphy(hw, BM_WUC, &reg);
2675
2676 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2677 if (ret_val)
2678 goto out;
2679
2680 if (hw->mac.type == e1000_pchlan) {
2681 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2682 if (ret_val)
2683 goto out;
2684 }
2685 /*
2686 * For PCH, this write will make sure that any noise
2687 * will be detected as a CRC error and be dropped rather than show up
2688 * as a bad packet to the DMA engine.
2689 */
2690 if (hw->mac.type == e1000_pchlan)
2691 ew32(CRC_OFFSET, 0x65656565);
2692
2693 ew32(IMC, 0xffffffff);
2694 icr = er32(ICR);
2695
2696 kab = er32(KABGTXD);
2697 kab |= E1000_KABGTXD_BGSQLBIAS;
2698 ew32(KABGTXD, kab);
2699
2700 if (hw->mac.type == e1000_pchlan)
2701 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2702
2703 out:
2704 return ret_val;
2705 }
2706
2707 /**
2708 * e1000_init_hw_ich8lan - Initialize the hardware
2709 * @hw: pointer to the HW structure
2710 *
2711 * Prepares the hardware for transmit and receive by doing the following:
2712 * - initialize hardware bits
2713 * - initialize LED identification
2714 * - setup receive address registers
2715 * - setup flow control
2716 * - setup transmit descriptors
2717 * - clear statistics
2718 **/
2719 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2720 {
2721 struct e1000_mac_info *mac = &hw->mac;
2722 u32 ctrl_ext, txdctl, snoop;
2723 s32 ret_val;
2724 u16 i;
2725
2726 e1000_initialize_hw_bits_ich8lan(hw);
2727
2728 /* Initialize identification LED */
2729 ret_val = mac->ops.id_led_init(hw);
2730 if (ret_val)
2731 e_dbg("Error initializing identification LED\n");
2732 /* This is not fatal and we should not stop init due to this */
2733
2734 /* Setup the receive address. */
2735 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2736
2737 /* Zero out the Multicast HASH table */
2738 e_dbg("Zeroing the MTA\n");
2739 for (i = 0; i < mac->mta_reg_count; i++)
2740 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2741
2742 /*
2743 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2744 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2745 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2746 */
2747 if (hw->phy.type == e1000_phy_82578) {
2748 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2749 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2750 if (ret_val)
2751 return ret_val;
2752 }
2753
2754 /* Setup link and flow control */
2755 ret_val = e1000_setup_link_ich8lan(hw);
2756
2757 /* Set the transmit descriptor write-back policy for both queues */
2758 txdctl = er32(TXDCTL(0));
2759 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2760 E1000_TXDCTL_FULL_TX_DESC_WB;
2761 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2762 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2763 ew32(TXDCTL(0), txdctl);
2764 txdctl = er32(TXDCTL(1));
2765 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2766 E1000_TXDCTL_FULL_TX_DESC_WB;
2767 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2768 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2769 ew32(TXDCTL(1), txdctl);
2770
2771 /*
2772 * ICH8 has opposite polarity of no_snoop bits.
2773 * By default, we should use snoop behavior.
2774 */
2775 if (mac->type == e1000_ich8lan)
2776 snoop = PCIE_ICH8_SNOOP_ALL;
2777 else
2778 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2779 e1000e_set_pcie_no_snoop(hw, snoop);
2780
2781 ctrl_ext = er32(CTRL_EXT);
2782 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2783 ew32(CTRL_EXT, ctrl_ext);
2784
2785 /*
2786 * Clear all of the statistics registers (clear on read). It is
2787 * important that we do this after we have tried to establish link
2788 * because the symbol error count will increment wildly if there
2789 * is no link.
2790 */
2791 e1000_clear_hw_cntrs_ich8lan(hw);
2792
2793 return 0;
2794 }
2795 /**
2796 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2797 * @hw: pointer to the HW structure
2798 *
2799 * Sets/Clears required hardware bits necessary for correctly setting up the
2800 * hardware for transmit and receive.
2801 **/
2802 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2803 {
2804 u32 reg;
2805
2806 /* Extended Device Control */
2807 reg = er32(CTRL_EXT);
2808 reg |= (1 << 22);
2809 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2810 if (hw->mac.type >= e1000_pchlan)
2811 reg |= E1000_CTRL_EXT_PHYPDEN;
2812 ew32(CTRL_EXT, reg);
2813
2814 /* Transmit Descriptor Control 0 */
2815 reg = er32(TXDCTL(0));
2816 reg |= (1 << 22);
2817 ew32(TXDCTL(0), reg);
2818
2819 /* Transmit Descriptor Control 1 */
2820 reg = er32(TXDCTL(1));
2821 reg |= (1 << 22);
2822 ew32(TXDCTL(1), reg);
2823
2824 /* Transmit Arbitration Control 0 */
2825 reg = er32(TARC(0));
2826 if (hw->mac.type == e1000_ich8lan)
2827 reg |= (1 << 28) | (1 << 29);
2828 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2829 ew32(TARC(0), reg);
2830
2831 /* Transmit Arbitration Control 1 */
2832 reg = er32(TARC(1));
2833 if (er32(TCTL) & E1000_TCTL_MULR)
2834 reg &= ~(1 << 28);
2835 else
2836 reg |= (1 << 28);
2837 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2838 ew32(TARC(1), reg);
2839
2840 /* Device Status */
2841 if (hw->mac.type == e1000_ich8lan) {
2842 reg = er32(STATUS);
2843 reg &= ~(1 << 31);
2844 ew32(STATUS, reg);
2845 }
2846 }
2847
2848 /**
2849 * e1000_setup_link_ich8lan - Setup flow control and link settings
2850 * @hw: pointer to the HW structure
2851 *
2852 * Determines which flow control settings to use, then configures flow
2853 * control. Calls the appropriate media-specific link configuration
2854 * function. Assuming the adapter has a valid link partner, a valid link
2855 * should be established. Assumes the hardware has previously been reset
2856 * and the transmitter and receiver are not enabled.
2857 **/
2858 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2859 {
2860 s32 ret_val;
2861
2862 if (e1000_check_reset_block(hw))
2863 return 0;
2864
2865 /*
2866 * ICH parts do not have a word in the NVM to determine
2867 * the default flow control setting, so we explicitly
2868 * set it to full.
2869 */
2870 if (hw->fc.requested_mode == e1000_fc_default) {
2871 /* Workaround h/w hang when Tx flow control enabled */
2872 if (hw->mac.type == e1000_pchlan)
2873 hw->fc.requested_mode = e1000_fc_rx_pause;
2874 else
2875 hw->fc.requested_mode = e1000_fc_full;
2876 }
2877
2878 /*
2879 * Save off the requested flow control mode for use later. Depending
2880 * on the link partner's capabilities, we may or may not use this mode.
2881 */
2882 hw->fc.current_mode = hw->fc.requested_mode;
2883
2884 e_dbg("After fix-ups FlowControl is now = %x\n",
2885 hw->fc.current_mode);
2886
2887 /* Continue to configure the copper link. */
2888 ret_val = e1000_setup_copper_link_ich8lan(hw);
2889 if (ret_val)
2890 return ret_val;
2891
2892 ew32(FCTTV, hw->fc.pause_time);
2893 if ((hw->phy.type == e1000_phy_82578) ||
2894 (hw->phy.type == e1000_phy_82577)) {
2895 ret_val = hw->phy.ops.write_reg(hw,
2896 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2897 hw->fc.pause_time);
2898 if (ret_val)
2899 return ret_val;
2900 }
2901
2902 return e1000e_set_fc_watermarks(hw);
2903 }
2904
2905 /**
2906 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2907 * @hw: pointer to the HW structure
2908 *
2909 * Configures the kumeran interface to the PHY to wait the appropriate time
2910 * when polling the PHY, then call the generic setup_copper_link to finish
2911 * configuring the copper link.
2912 **/
2913 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2914 {
2915 u32 ctrl;
2916 s32 ret_val;
2917 u16 reg_data;
2918
2919 ctrl = er32(CTRL);
2920 ctrl |= E1000_CTRL_SLU;
2921 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2922 ew32(CTRL, ctrl);
2923
2924 /*
2925 * Set the mac to wait the maximum time between each iteration
2926 * and increase the max iterations when polling the phy;
2927 * this fixes erroneous timeouts at 10Mbps.
2928 */
2929 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2930 if (ret_val)
2931 return ret_val;
2932 ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2933 if (ret_val)
2934 return ret_val;
2935 reg_data |= 0x3F;
2936 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2937 if (ret_val)
2938 return ret_val;
2939
2940 switch (hw->phy.type) {
2941 case e1000_phy_igp_3:
2942 ret_val = e1000e_copper_link_setup_igp(hw);
2943 if (ret_val)
2944 return ret_val;
2945 break;
2946 case e1000_phy_bm:
2947 case e1000_phy_82578:
2948 ret_val = e1000e_copper_link_setup_m88(hw);
2949 if (ret_val)
2950 return ret_val;
2951 break;
2952 case e1000_phy_82577:
2953 ret_val = e1000_copper_link_setup_82577(hw);
2954 if (ret_val)
2955 return ret_val;
2956 break;
2957 case e1000_phy_ife:
2958 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2959 &reg_data);
2960 if (ret_val)
2961 return ret_val;
2962
2963 reg_data &= ~IFE_PMC_AUTO_MDIX;
2964
2965 switch (hw->phy.mdix) {
2966 case 1:
2967 reg_data &= ~IFE_PMC_FORCE_MDIX;
2968 break;
2969 case 2:
2970 reg_data |= IFE_PMC_FORCE_MDIX;
2971 break;
2972 case 0:
2973 default:
2974 reg_data |= IFE_PMC_AUTO_MDIX;
2975 break;
2976 }
2977 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2978 reg_data);
2979 if (ret_val)
2980 return ret_val;
2981 break;
2982 default:
2983 break;
2984 }
2985 return e1000e_setup_copper_link(hw);
2986 }
2987
2988 /**
2989 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2990 * @hw: pointer to the HW structure
2991 * @speed: pointer to store current link speed
2992 * @duplex: pointer to store the current link duplex
2993 *
2994 * Calls the generic get_speed_and_duplex to retrieve the current link
2995 * information and then calls the Kumeran lock loss workaround for links at
2996 * gigabit speeds.
2997 **/
2998 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2999 u16 *duplex)
3000 {
3001 s32 ret_val;
3002
3003 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3004 if (ret_val)
3005 return ret_val;
3006
3007 if ((hw->mac.type == e1000_ich8lan) &&
3008 (hw->phy.type == e1000_phy_igp_3) &&
3009 (*speed == SPEED_1000)) {
3010 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3011 }
3012
3013 return ret_val;
3014 }
3015
3016 /**
3017 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3018 * @hw: pointer to the HW structure
3019 *
3020 * Work-around for 82566 Kumeran PCS lock loss:
3021 * On link status change (i.e. PCI reset, speed change) and link is up and
3022 * speed is gigabit-
3023 * 0) if workaround is optionally disabled do nothing
3024 * 1) wait 1ms for Kumeran link to come up
3025 * 2) check Kumeran Diagnostic register PCS lock loss bit
3026 * 3) if not set the link is locked (all is good), otherwise...
3027 * 4) reset the PHY
3028 * 5) repeat up to 10 times
3029 * Note: this is only called for IGP3 copper when speed is 1gb.
3030 **/
3031 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3032 {
3033 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3034 u32 phy_ctrl;
3035 s32 ret_val;
3036 u16 i, data;
3037 bool link;
3038
3039 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3040 return 0;
3041
3042 /*
3043 * Make sure link is up before proceeding. If not just return.
3044 * Attempting this while link is negotiating fouled up link
3045 * stability
3046 */
3047 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3048 if (!link)
3049 return 0;
3050
3051 for (i = 0; i < 10; i++) {
3052 /* read once to clear */
3053 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3054 if (ret_val)
3055 return ret_val;
3056 /* and again to get new status */
3057 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3058 if (ret_val)
3059 return ret_val;
3060
3061 /* check for PCS lock */
3062 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3063 return 0;
3064
3065 /* Issue PHY reset */
3066 e1000_phy_hw_reset(hw);
3067 mdelay(5);
3068 }
3069 /* Disable GigE link negotiation */
3070 phy_ctrl = er32(PHY_CTRL);
3071 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3072 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3073 ew32(PHY_CTRL, phy_ctrl);
3074
3075 /*
3076 * Call gig speed drop workaround on Gig disable before accessing
3077 * any PHY registers
3078 */
3079 e1000e_gig_downshift_workaround_ich8lan(hw);
3080
3081 /* unable to acquire PCS lock */
3082 return -E1000_ERR_PHY;
3083 }
3084
3085 /**
3086 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3087 * @hw: pointer to the HW structure
3088 * @state: boolean value used to set the current Kumeran workaround state
3089 *
3090 * If ICH8, set the current Kumeran workaround state (enabled - true
3091 * /disabled - false).
3092 **/
3093 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3094 bool state)
3095 {
3096 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3097
3098 if (hw->mac.type != e1000_ich8lan) {
3099 e_dbg("Workaround applies to ICH8 only.\n");
3100 return;
3101 }
3102
3103 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3104 }
3105
3106 /**
3107 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3108 * @hw: pointer to the HW structure
3109 *
3110 * Workaround for 82566 power-down on D3 entry:
3111 * 1) disable gigabit link
3112 * 2) write VR power-down enable
3113 * 3) read it back
3114 * Continue if successful, else issue LCD reset and repeat
3115 **/
3116 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3117 {
3118 u32 reg;
3119 u16 data;
3120 u8 retry = 0;
3121
3122 if (hw->phy.type != e1000_phy_igp_3)
3123 return;
3124
3125 /* Try the workaround twice (if needed) */
3126 do {
3127 /* Disable link */
3128 reg = er32(PHY_CTRL);
3129 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3130 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3131 ew32(PHY_CTRL, reg);
3132
3133 /*
3134 * Call gig speed drop workaround on Gig disable before
3135 * accessing any PHY registers
3136 */
3137 if (hw->mac.type == e1000_ich8lan)
3138 e1000e_gig_downshift_workaround_ich8lan(hw);
3139
3140 /* Write VR power-down enable */
3141 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3142 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3143 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3144
3145 /* Read it back and test */
3146 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3147 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3148 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3149 break;
3150
3151 /* Issue PHY reset and repeat at most one more time */
3152 reg = er32(CTRL);
3153 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3154 retry++;
3155 } while (retry);
3156 }
3157
3158 /**
3159 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3160 * @hw: pointer to the HW structure
3161 *
3162 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3163 * LPLU, Gig disable, MDIC PHY reset):
3164 * 1) Set Kumeran Near-end loopback
3165 * 2) Clear Kumeran Near-end loopback
3166 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3167 **/
3168 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3169 {
3170 s32 ret_val;
3171 u16 reg_data;
3172
3173 if ((hw->mac.type != e1000_ich8lan) ||
3174 (hw->phy.type != e1000_phy_igp_3))
3175 return;
3176
3177 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3178 &reg_data);
3179 if (ret_val)
3180 return;
3181 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3182 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3183 reg_data);
3184 if (ret_val)
3185 return;
3186 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3187 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3188 reg_data);
3189 }
3190
3191 /**
3192 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3193 * @hw: pointer to the HW structure
3194 *
3195 * During S0 to Sx transition, it is possible the link remains at gig
3196 * instead of negotiating to a lower speed. Before going to Sx, set
3197 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3198 * to a lower speed.
3199 *
3200 * Should only be called for applicable parts.
3201 **/
3202 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3203 {
3204 u32 phy_ctrl;
3205
3206 switch (hw->mac.type) {
3207 case e1000_ich9lan:
3208 case e1000_ich10lan:
3209 case e1000_pchlan:
3210 phy_ctrl = er32(PHY_CTRL);
3211 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3212 E1000_PHY_CTRL_GBE_DISABLE;
3213 ew32(PHY_CTRL, phy_ctrl);
3214
3215 if (hw->mac.type == e1000_pchlan)
3216 e1000_phy_hw_reset_ich8lan(hw);
3217 default:
3218 break;
3219 }
3220
3221 return;
3222 }
3223
3224 /**
3225 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3226 * @hw: pointer to the HW structure
3227 *
3228 * Return the LED back to the default configuration.
3229 **/
3230 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3231 {
3232 if (hw->phy.type == e1000_phy_ife)
3233 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3234
3235 ew32(LEDCTL, hw->mac.ledctl_default);
3236 return 0;
3237 }
3238
3239 /**
3240 * e1000_led_on_ich8lan - Turn LEDs on
3241 * @hw: pointer to the HW structure
3242 *
3243 * Turn on the LEDs.
3244 **/
3245 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3246 {
3247 if (hw->phy.type == e1000_phy_ife)
3248 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3249 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3250
3251 ew32(LEDCTL, hw->mac.ledctl_mode2);
3252 return 0;
3253 }
3254
3255 /**
3256 * e1000_led_off_ich8lan - Turn LEDs off
3257 * @hw: pointer to the HW structure
3258 *
3259 * Turn off the LEDs.
3260 **/
3261 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3262 {
3263 if (hw->phy.type == e1000_phy_ife)
3264 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3265 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3266
3267 ew32(LEDCTL, hw->mac.ledctl_mode1);
3268 return 0;
3269 }
3270
3271 /**
3272 * e1000_setup_led_pchlan - Configures SW controllable LED
3273 * @hw: pointer to the HW structure
3274 *
3275 * This prepares the SW controllable LED for use.
3276 **/
3277 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3278 {
3279 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3280 (u16)hw->mac.ledctl_mode1);
3281 }
3282
3283 /**
3284 * e1000_cleanup_led_pchlan - Restore the default LED operation
3285 * @hw: pointer to the HW structure
3286 *
3287 * Return the LED back to the default configuration.
3288 **/
3289 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3290 {
3291 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3292 (u16)hw->mac.ledctl_default);
3293 }
3294
3295 /**
3296 * e1000_led_on_pchlan - Turn LEDs on
3297 * @hw: pointer to the HW structure
3298 *
3299 * Turn on the LEDs.
3300 **/
3301 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3302 {
3303 u16 data = (u16)hw->mac.ledctl_mode2;
3304 u32 i, led;
3305
3306 /*
3307 * If no link, then turn LED on by setting the invert bit
3308 * for each LED that's mode is "link_up" in ledctl_mode2.
3309 */
3310 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3311 for (i = 0; i < 3; i++) {
3312 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3313 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3314 E1000_LEDCTL_MODE_LINK_UP)
3315 continue;
3316 if (led & E1000_PHY_LED0_IVRT)
3317 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3318 else
3319 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3320 }
3321 }
3322
3323 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3324 }
3325
3326 /**
3327 * e1000_led_off_pchlan - Turn LEDs off
3328 * @hw: pointer to the HW structure
3329 *
3330 * Turn off the LEDs.
3331 **/
3332 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3333 {
3334 u16 data = (u16)hw->mac.ledctl_mode1;
3335 u32 i, led;
3336
3337 /*
3338 * If no link, then turn LED off by clearing the invert bit
3339 * for each LED that's mode is "link_up" in ledctl_mode1.
3340 */
3341 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3342 for (i = 0; i < 3; i++) {
3343 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3344 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3345 E1000_LEDCTL_MODE_LINK_UP)
3346 continue;
3347 if (led & E1000_PHY_LED0_IVRT)
3348 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3349 else
3350 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3351 }
3352 }
3353
3354 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3355 }
3356
3357 /**
3358 * e1000_get_cfg_done_ich8lan - Read config done bit
3359 * @hw: pointer to the HW structure
3360 *
3361 * Read the management control register for the config done bit for
3362 * completion status. NOTE: silicon which is EEPROM-less will fail trying
3363 * to read the config done bit, so an error is *ONLY* logged and returns
3364 * 0. If we were to return with error, EEPROM-less silicon
3365 * would not be able to be reset or change link.
3366 **/
3367 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3368 {
3369 u32 bank = 0;
3370
3371 if (hw->mac.type >= e1000_pchlan) {
3372 u32 status = er32(STATUS);
3373
3374 if (status & E1000_STATUS_PHYRA)
3375 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3376 else
3377 e_dbg("PHY Reset Asserted not set - needs delay\n");
3378 }
3379
3380 e1000e_get_cfg_done(hw);
3381
3382 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3383 if ((hw->mac.type != e1000_ich10lan) &&
3384 (hw->mac.type != e1000_pchlan)) {
3385 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3386 (hw->phy.type == e1000_phy_igp_3)) {
3387 e1000e_phy_init_script_igp3(hw);
3388 }
3389 } else {
3390 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3391 /* Maybe we should do a basic PHY config */
3392 e_dbg("EEPROM not present\n");
3393 return -E1000_ERR_CONFIG;
3394 }
3395 }
3396
3397 return 0;
3398 }
3399
3400 /**
3401 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3402 * @hw: pointer to the HW structure
3403 *
3404 * In the case of a PHY power down to save power, or to turn off link during a
3405 * driver unload, or wake on lan is not enabled, remove the link.
3406 **/
3407 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3408 {
3409 /* If the management interface is not enabled, then power down */
3410 if (!(hw->mac.ops.check_mng_mode(hw) ||
3411 hw->phy.ops.check_reset_block(hw)))
3412 e1000_power_down_phy_copper(hw);
3413
3414 return;
3415 }
3416
3417 /**
3418 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3419 * @hw: pointer to the HW structure
3420 *
3421 * Clears hardware counters specific to the silicon family and calls
3422 * clear_hw_cntrs_generic to clear all general purpose counters.
3423 **/
3424 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3425 {
3426 u16 phy_data;
3427
3428 e1000e_clear_hw_cntrs_base(hw);
3429
3430 er32(ALGNERRC);
3431 er32(RXERRC);
3432 er32(TNCRS);
3433 er32(CEXTERR);
3434 er32(TSCTC);
3435 er32(TSCTFC);
3436
3437 er32(MGTPRC);
3438 er32(MGTPDC);
3439 er32(MGTPTC);
3440
3441 er32(IAC);
3442 er32(ICRXOC);
3443
3444 /* Clear PHY statistics registers */
3445 if ((hw->phy.type == e1000_phy_82578) ||
3446 (hw->phy.type == e1000_phy_82577)) {
3447 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3448 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3449 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3450 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3451 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3452 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3453 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3454 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3455 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3456 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3457 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3458 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3459 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3460 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3461 }
3462 }
3463
3464 static struct e1000_mac_operations ich8_mac_ops = {
3465 .id_led_init = e1000e_id_led_init,
3466 .check_mng_mode = e1000_check_mng_mode_ich8lan,
3467 .check_for_link = e1000_check_for_copper_link_ich8lan,
3468 /* cleanup_led dependent on mac type */
3469 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3470 .get_bus_info = e1000_get_bus_info_ich8lan,
3471 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3472 /* led_on dependent on mac type */
3473 /* led_off dependent on mac type */
3474 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3475 .reset_hw = e1000_reset_hw_ich8lan,
3476 .init_hw = e1000_init_hw_ich8lan,
3477 .setup_link = e1000_setup_link_ich8lan,
3478 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3479 /* id_led_init dependent on mac type */
3480 };
3481
3482 static struct e1000_phy_operations ich8_phy_ops = {
3483 .acquire = e1000_acquire_swflag_ich8lan,
3484 .check_reset_block = e1000_check_reset_block_ich8lan,
3485 .commit = NULL,
3486 .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan,
3487 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3488 .get_cable_length = e1000e_get_cable_length_igp_2,
3489 .get_info = e1000_get_phy_info_ich8lan,
3490 .read_reg = e1000e_read_phy_reg_igp,
3491 .release = e1000_release_swflag_ich8lan,
3492 .reset = e1000_phy_hw_reset_ich8lan,
3493 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3494 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3495 .write_reg = e1000e_write_phy_reg_igp,
3496 };
3497
3498 static struct e1000_nvm_operations ich8_nvm_ops = {
3499 .acquire = e1000_acquire_nvm_ich8lan,
3500 .read = e1000_read_nvm_ich8lan,
3501 .release = e1000_release_nvm_ich8lan,
3502 .update = e1000_update_nvm_checksum_ich8lan,
3503 .valid_led_default = e1000_valid_led_default_ich8lan,
3504 .validate = e1000_validate_nvm_checksum_ich8lan,
3505 .write = e1000_write_nvm_ich8lan,
3506 };
3507
3508 struct e1000_info e1000_ich8_info = {
3509 .mac = e1000_ich8lan,
3510 .flags = FLAG_HAS_WOL
3511 | FLAG_IS_ICH
3512 | FLAG_RX_CSUM_ENABLED
3513 | FLAG_HAS_CTRLEXT_ON_LOAD
3514 | FLAG_HAS_AMT
3515 | FLAG_HAS_FLASH
3516 | FLAG_APME_IN_WUC,
3517 .pba = 8,
3518 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
3519 .get_variants = e1000_get_variants_ich8lan,
3520 .mac_ops = &ich8_mac_ops,
3521 .phy_ops = &ich8_phy_ops,
3522 .nvm_ops = &ich8_nvm_ops,
3523 };
3524
3525 struct e1000_info e1000_ich9_info = {
3526 .mac = e1000_ich9lan,
3527 .flags = FLAG_HAS_JUMBO_FRAMES
3528 | FLAG_IS_ICH
3529 | FLAG_HAS_WOL
3530 | FLAG_RX_CSUM_ENABLED
3531 | FLAG_HAS_CTRLEXT_ON_LOAD
3532 | FLAG_HAS_AMT
3533 | FLAG_HAS_ERT
3534 | FLAG_HAS_FLASH
3535 | FLAG_APME_IN_WUC,
3536 .pba = 10,
3537 .max_hw_frame_size = DEFAULT_JUMBO,
3538 .get_variants = e1000_get_variants_ich8lan,
3539 .mac_ops = &ich8_mac_ops,
3540 .phy_ops = &ich8_phy_ops,
3541 .nvm_ops = &ich8_nvm_ops,
3542 };
3543
3544 struct e1000_info e1000_ich10_info = {
3545 .mac = e1000_ich10lan,
3546 .flags = FLAG_HAS_JUMBO_FRAMES
3547 | FLAG_IS_ICH
3548 | FLAG_HAS_WOL
3549 | FLAG_RX_CSUM_ENABLED
3550 | FLAG_HAS_CTRLEXT_ON_LOAD
3551 | FLAG_HAS_AMT
3552 | FLAG_HAS_ERT
3553 | FLAG_HAS_FLASH
3554 | FLAG_APME_IN_WUC,
3555 .pba = 10,
3556 .max_hw_frame_size = DEFAULT_JUMBO,
3557 .get_variants = e1000_get_variants_ich8lan,
3558 .mac_ops = &ich8_mac_ops,
3559 .phy_ops = &ich8_phy_ops,
3560 .nvm_ops = &ich8_nvm_ops,
3561 };
3562
3563 struct e1000_info e1000_pch_info = {
3564 .mac = e1000_pchlan,
3565 .flags = FLAG_IS_ICH
3566 | FLAG_HAS_WOL
3567 | FLAG_RX_CSUM_ENABLED
3568 | FLAG_HAS_CTRLEXT_ON_LOAD
3569 | FLAG_HAS_AMT
3570 | FLAG_HAS_FLASH
3571 | FLAG_HAS_JUMBO_FRAMES
3572 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3573 | FLAG_APME_IN_WUC,
3574 .pba = 26,
3575 .max_hw_frame_size = 4096,
3576 .get_variants = e1000_get_variants_ich8lan,
3577 .mac_ops = &ich8_mac_ops,
3578 .phy_ops = &ich8_phy_ops,
3579 .nvm_ops = &ich8_nvm_ops,
3580 };
linux 2.6 git repository for openrd