?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86, mce: document new 32bit mcelog requirement in Documentation/Changes
[linux-2.6/linux-2.6-openrd.git] / drivers / video / omap / sossi.c
bloba7694622024925befb1f26692523937146dd3588
1 /*
2 * OMAP1 Special OptimiSed Screen Interface support
3 *
4 * Copyright (C) 2004-2005 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21 #include <linux/module.h>
22 #include <linux/mm.h>
23 #include <linux/clk.h>
24 #include <linux/irq.h>
25 #include <linux/io.h>
26
27 #include <mach/dma.h>
28 #include <mach/omapfb.h>
29
30 #include "lcdc.h"
31
32 #define MODULE_NAME "omapfb-sossi"
33
34 #define OMAP_SOSSI_BASE 0xfffbac00
35 #define SOSSI_ID_REG 0x00
36 #define SOSSI_INIT1_REG 0x04
37 #define SOSSI_INIT2_REG 0x08
38 #define SOSSI_INIT3_REG 0x0c
39 #define SOSSI_FIFO_REG 0x10
40 #define SOSSI_REOTABLE_REG 0x14
41 #define SOSSI_TEARING_REG 0x18
42 #define SOSSI_INIT1B_REG 0x1c
43 #define SOSSI_FIFOB_REG 0x20
44
45 #define DMA_GSCR 0xfffedc04
46 #define DMA_LCD_CCR 0xfffee3c2
47 #define DMA_LCD_CTRL 0xfffee3c4
48 #define DMA_LCD_LCH_CTRL 0xfffee3ea
49
50 #define CONF_SOSSI_RESET_R (1 << 23)
51
52 #define RD_ACCESS 0
53 #define WR_ACCESS 1
54
55 #define SOSSI_MAX_XMIT_BYTES (512 * 1024)
56
57 static struct {
58 void __iomem *base;
59 struct clk *fck;
60 unsigned long fck_hz;
61 spinlock_t lock;
62 int bus_pick_count;
63 int bus_pick_width;
64 int tearsync_mode;
65 int tearsync_line;
66 void (*lcdc_callback)(void *data);
67 void *lcdc_callback_data;
68 int vsync_dma_pending;
69 /* timing for read and write access */
70 int clk_div;
71 u8 clk_tw0[2];
72 u8 clk_tw1[2];
73 /*
74 * if last_access is the same as current we don't have to change
75 * the timings
76 */
77 int last_access;
78
79 struct omapfb_device *fbdev;
80 } sossi;
81
82 static inline u32 sossi_read_reg(int reg)
83 {
84 return readl(sossi.base + reg);
85 }
86
87 static inline u16 sossi_read_reg16(int reg)
88 {
89 return readw(sossi.base + reg);
90 }
91
92 static inline u8 sossi_read_reg8(int reg)
93 {
94 return readb(sossi.base + reg);
95 }
96
97 static inline void sossi_write_reg(int reg, u32 value)
98 {
99 writel(value, sossi.base + reg);
100 }
101
102 static inline void sossi_write_reg16(int reg, u16 value)
103 {
104 writew(value, sossi.base + reg);
105 }
106
107 static inline void sossi_write_reg8(int reg, u8 value)
108 {
109 writeb(value, sossi.base + reg);
110 }
111
112 static void sossi_set_bits(int reg, u32 bits)
113 {
114 sossi_write_reg(reg, sossi_read_reg(reg) | bits);
115 }
116
117 static void sossi_clear_bits(int reg, u32 bits)
118 {
119 sossi_write_reg(reg, sossi_read_reg(reg) & ~bits);
120 }
121
122 #define HZ_TO_PS(x) (1000000000 / (x / 1000))
123
124 static u32 ps_to_sossi_ticks(u32 ps, int div)
125 {
126 u32 clk_period = HZ_TO_PS(sossi.fck_hz) * div;
127 return (clk_period + ps - 1) / clk_period;
128 }
129
130 static int calc_rd_timings(struct extif_timings *t)
131 {
132 u32 tw0, tw1;
133 int reon, reoff, recyc, actim;
134 int div = t->clk_div;
135
136 /*
137 * Make sure that after conversion it still holds that:
138 * reoff > reon, recyc >= reoff, actim > reon
139 */
140 reon = ps_to_sossi_ticks(t->re_on_time, div);
141 /* reon will be exactly one sossi tick */
142 if (reon > 1)
143 return -1;
144
145 reoff = ps_to_sossi_ticks(t->re_off_time, div);
146
147 if (reoff <= reon)
148 reoff = reon + 1;
149
150 tw0 = reoff - reon;
151 if (tw0 > 0x10)
152 return -1;
153
154 recyc = ps_to_sossi_ticks(t->re_cycle_time, div);
155 if (recyc <= reoff)
156 recyc = reoff + 1;
157
158 tw1 = recyc - tw0;
159 /* values less then 3 result in the SOSSI block resetting itself */
160 if (tw1 < 3)
161 tw1 = 3;
162 if (tw1 > 0x40)
163 return -1;
164
165 actim = ps_to_sossi_ticks(t->access_time, div);
166 if (actim < reoff)
167 actim++;
168 /*
169 * access time (data hold time) will be exactly one sossi
170 * tick
171 */
172 if (actim - reoff > 1)
173 return -1;
174
175 t->tim[0] = tw0 - 1;
176 t->tim[1] = tw1 - 1;
177
178 return 0;
179 }
180
181 static int calc_wr_timings(struct extif_timings *t)
182 {
183 u32 tw0, tw1;
184 int weon, weoff, wecyc;
185 int div = t->clk_div;
186
187 /*
188 * Make sure that after conversion it still holds that:
189 * weoff > weon, wecyc >= weoff
190 */
191 weon = ps_to_sossi_ticks(t->we_on_time, div);
192 /* weon will be exactly one sossi tick */
193 if (weon > 1)
194 return -1;
195
196 weoff = ps_to_sossi_ticks(t->we_off_time, div);
197 if (weoff <= weon)
198 weoff = weon + 1;
199 tw0 = weoff - weon;
200 if (tw0 > 0x10)
201 return -1;
202
203 wecyc = ps_to_sossi_ticks(t->we_cycle_time, div);
204 if (wecyc <= weoff)
205 wecyc = weoff + 1;
206
207 tw1 = wecyc - tw0;
208 /* values less then 3 result in the SOSSI block resetting itself */
209 if (tw1 < 3)
210 tw1 = 3;
211 if (tw1 > 0x40)
212 return -1;
213
214 t->tim[2] = tw0 - 1;
215 t->tim[3] = tw1 - 1;
216
217 return 0;
218 }
219
220 static void _set_timing(int div, int tw0, int tw1)
221 {
222 u32 l;
223
224 #ifdef VERBOSE
225 dev_dbg(sossi.fbdev->dev, "Using TW0 = %d, TW1 = %d, div = %d\n",
226 tw0 + 1, tw1 + 1, div);
227 #endif
228
229 clk_set_rate(sossi.fck, sossi.fck_hz / div);
230 clk_enable(sossi.fck);
231 l = sossi_read_reg(SOSSI_INIT1_REG);
232 l &= ~((0x0f << 20) | (0x3f << 24));
233 l |= (tw0 << 20) | (tw1 << 24);
234 sossi_write_reg(SOSSI_INIT1_REG, l);
235 clk_disable(sossi.fck);
236 }
237
238 static void _set_bits_per_cycle(int bus_pick_count, int bus_pick_width)
239 {
240 u32 l;
241
242 l = sossi_read_reg(SOSSI_INIT3_REG);
243 l &= ~0x3ff;
244 l |= ((bus_pick_count - 1) << 5) | ((bus_pick_width - 1) & 0x1f);
245 sossi_write_reg(SOSSI_INIT3_REG, l);
246 }
247
248 static void _set_tearsync_mode(int mode, unsigned line)
249 {
250 u32 l;
251
252 l = sossi_read_reg(SOSSI_TEARING_REG);
253 l &= ~(((1 << 11) - 1) << 15);
254 l |= line << 15;
255 l &= ~(0x3 << 26);
256 l |= mode << 26;
257 sossi_write_reg(SOSSI_TEARING_REG, l);
258 if (mode)
259 sossi_set_bits(SOSSI_INIT2_REG, 1 << 6); /* TE logic */
260 else
261 sossi_clear_bits(SOSSI_INIT2_REG, 1 << 6);
262 }
263
264 static inline void set_timing(int access)
265 {
266 if (access != sossi.last_access) {
267 sossi.last_access = access;
268 _set_timing(sossi.clk_div,
269 sossi.clk_tw0[access], sossi.clk_tw1[access]);
270 }
271 }
272
273 static void sossi_start_transfer(void)
274 {
275 /* WE */
276 sossi_clear_bits(SOSSI_INIT2_REG, 1 << 4);
277 /* CS active low */
278 sossi_clear_bits(SOSSI_INIT1_REG, 1 << 30);
279 }
280
281 static void sossi_stop_transfer(void)
282 {
283 /* WE */
284 sossi_set_bits(SOSSI_INIT2_REG, 1 << 4);
285 /* CS active low */
286 sossi_set_bits(SOSSI_INIT1_REG, 1 << 30);
287 }
288
289 static void wait_end_of_write(void)
290 {
291 /* Before reading we must check if some writings are going on */
292 while (!(sossi_read_reg(SOSSI_INIT2_REG) & (1 << 3)));
293 }
294
295 static void send_data(const void *data, unsigned int len)
296 {
297 while (len >= 4) {
298 sossi_write_reg(SOSSI_FIFO_REG, *(const u32 *) data);
299 len -= 4;
300 data += 4;
301 }
302 while (len >= 2) {
303 sossi_write_reg16(SOSSI_FIFO_REG, *(const u16 *) data);
304 len -= 2;
305 data += 2;
306 }
307 while (len) {
308 sossi_write_reg8(SOSSI_FIFO_REG, *(const u8 *) data);
309 len--;
310 data++;
311 }
312 }
313
314 static void set_cycles(unsigned int len)
315 {
316 unsigned long nr_cycles = len / (sossi.bus_pick_width / 8);
317
318 BUG_ON((nr_cycles - 1) & ~0x3ffff);
319
320 sossi_clear_bits(SOSSI_INIT1_REG, 0x3ffff);
321 sossi_set_bits(SOSSI_INIT1_REG, (nr_cycles - 1) & 0x3ffff);
322 }
323
324 static int sossi_convert_timings(struct extif_timings *t)
325 {
326 int r = 0;
327 int div = t->clk_div;
328
329 t->converted = 0;
330
331 if (div <= 0 || div > 8)
332 return -1;
333
334 /* no CS on SOSSI, so ignore cson, csoff, cs_pulsewidth */
335 if ((r = calc_rd_timings(t)) < 0)
336 return r;
337
338 if ((r = calc_wr_timings(t)) < 0)
339 return r;
340
341 t->tim[4] = div;
342
343 t->converted = 1;
344
345 return 0;
346 }
347
348 static void sossi_set_timings(const struct extif_timings *t)
349 {
350 BUG_ON(!t->converted);
351
352 sossi.clk_tw0[RD_ACCESS] = t->tim[0];
353 sossi.clk_tw1[RD_ACCESS] = t->tim[1];
354
355 sossi.clk_tw0[WR_ACCESS] = t->tim[2];
356 sossi.clk_tw1[WR_ACCESS] = t->tim[3];
357
358 sossi.clk_div = t->tim[4];
359 }
360
361 static void sossi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
362 {
363 *clk_period = HZ_TO_PS(sossi.fck_hz);
364 *max_clk_div = 8;
365 }
366
367 static void sossi_set_bits_per_cycle(int bpc)
368 {
369 int bus_pick_count, bus_pick_width;
370
371 /*
372 * We set explicitly the the bus_pick_count as well, although
373 * with remapping/reordering disabled it will be calculated by HW
374 * as (32 / bus_pick_width).
375 */
376 switch (bpc) {
377 case 8:
378 bus_pick_count = 4;
379 bus_pick_width = 8;
380 break;
381 case 16:
382 bus_pick_count = 2;
383 bus_pick_width = 16;
384 break;
385 default:
386 BUG();
387 return;
388 }
389 sossi.bus_pick_width = bus_pick_width;
390 sossi.bus_pick_count = bus_pick_count;
391 }
392
393 static int sossi_setup_tearsync(unsigned pin_cnt,
394 unsigned hs_pulse_time, unsigned vs_pulse_time,
395 int hs_pol_inv, int vs_pol_inv, int div)
396 {
397 int hs, vs;
398 u32 l;
399
400 if (pin_cnt != 1 || div < 1 || div > 8)
401 return -EINVAL;
402
403 hs = ps_to_sossi_ticks(hs_pulse_time, div);
404 vs = ps_to_sossi_ticks(vs_pulse_time, div);
405 if (vs < 8 || vs <= hs || vs >= (1 << 12))
406 return -EDOM;
407 vs /= 8;
408 vs--;
409 if (hs > 8)
410 hs = 8;
411 if (hs)
412 hs--;
413
414 dev_dbg(sossi.fbdev->dev,
415 "setup_tearsync: hs %d vs %d hs_inv %d vs_inv %d\n",
416 hs, vs, hs_pol_inv, vs_pol_inv);
417
418 clk_enable(sossi.fck);
419 l = sossi_read_reg(SOSSI_TEARING_REG);
420 l &= ~((1 << 15) - 1);
421 l |= vs << 3;
422 l |= hs;
423 if (hs_pol_inv)
424 l |= 1 << 29;
425 else
426 l &= ~(1 << 29);
427 if (vs_pol_inv)
428 l |= 1 << 28;
429 else
430 l &= ~(1 << 28);
431 sossi_write_reg(SOSSI_TEARING_REG, l);
432 clk_disable(sossi.fck);
433
434 return 0;
435 }
436
437 static int sossi_enable_tearsync(int enable, unsigned line)
438 {
439 int mode;
440
441 dev_dbg(sossi.fbdev->dev, "tearsync %d line %d\n", enable, line);
442 if (line >= 1 << 11)
443 return -EINVAL;
444 if (enable) {
445 if (line)
446 mode = 2; /* HS or VS */
447 else
448 mode = 3; /* VS only */
449 } else
450 mode = 0;
451 sossi.tearsync_line = line;
452 sossi.tearsync_mode = mode;
453
454 return 0;
455 }
456
457 static void sossi_write_command(const void *data, unsigned int len)
458 {
459 clk_enable(sossi.fck);
460 set_timing(WR_ACCESS);
461 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
462 /* CMD#/DATA */
463 sossi_clear_bits(SOSSI_INIT1_REG, 1 << 18);
464 set_cycles(len);
465 sossi_start_transfer();
466 send_data(data, len);
467 sossi_stop_transfer();
468 wait_end_of_write();
469 clk_disable(sossi.fck);
470 }
471
472 static void sossi_write_data(const void *data, unsigned int len)
473 {
474 clk_enable(sossi.fck);
475 set_timing(WR_ACCESS);
476 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
477 /* CMD#/DATA */
478 sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
479 set_cycles(len);
480 sossi_start_transfer();
481 send_data(data, len);
482 sossi_stop_transfer();
483 wait_end_of_write();
484 clk_disable(sossi.fck);
485 }
486
487 static void sossi_transfer_area(int width, int height,
488 void (callback)(void *data), void *data)
489 {
490 BUG_ON(callback == NULL);
491
492 sossi.lcdc_callback = callback;
493 sossi.lcdc_callback_data = data;
494
495 clk_enable(sossi.fck);
496 set_timing(WR_ACCESS);
497 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
498 _set_tearsync_mode(sossi.tearsync_mode, sossi.tearsync_line);
499 /* CMD#/DATA */
500 sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
501 set_cycles(width * height * sossi.bus_pick_width / 8);
502
503 sossi_start_transfer();
504 if (sossi.tearsync_mode) {
505 /*
506 * Wait for the sync signal and start the transfer only
507 * then. We can't seem to be able to use HW sync DMA for
508 * this since LCD DMA shows huge latencies, as if it
509 * would ignore some of the DMA requests from SoSSI.
510 */
511 unsigned long flags;
512
513 spin_lock_irqsave(&sossi.lock, flags);
514 sossi.vsync_dma_pending++;
515 spin_unlock_irqrestore(&sossi.lock, flags);
516 } else
517 /* Just start the transfer right away. */
518 omap_enable_lcd_dma();
519 }
520
521 static void sossi_dma_callback(void *data)
522 {
523 omap_stop_lcd_dma();
524 sossi_stop_transfer();
525 clk_disable(sossi.fck);
526 sossi.lcdc_callback(sossi.lcdc_callback_data);
527 }
528
529 static void sossi_read_data(void *data, unsigned int len)
530 {
531 clk_enable(sossi.fck);
532 set_timing(RD_ACCESS);
533 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
534 /* CMD#/DATA */
535 sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
536 set_cycles(len);
537 sossi_start_transfer();
538 while (len >= 4) {
539 *(u32 *) data = sossi_read_reg(SOSSI_FIFO_REG);
540 len -= 4;
541 data += 4;
542 }
543 while (len >= 2) {
544 *(u16 *) data = sossi_read_reg16(SOSSI_FIFO_REG);
545 len -= 2;
546 data += 2;
547 }
548 while (len) {
549 *(u8 *) data = sossi_read_reg8(SOSSI_FIFO_REG);
550 len--;
551 data++;
552 }
553 sossi_stop_transfer();
554 clk_disable(sossi.fck);
555 }
556
557 static irqreturn_t sossi_match_irq(int irq, void *data)
558 {
559 unsigned long flags;
560
561 spin_lock_irqsave(&sossi.lock, flags);
562 if (sossi.vsync_dma_pending) {
563 sossi.vsync_dma_pending--;
564 omap_enable_lcd_dma();
565 }
566 spin_unlock_irqrestore(&sossi.lock, flags);
567 return IRQ_HANDLED;
568 }
569
570 static int sossi_init(struct omapfb_device *fbdev)
571 {
572 u32 l, k;
573 struct clk *fck;
574 struct clk *dpll1out_ck;
575 int r;
576
577 sossi.base = ioremap(OMAP_SOSSI_BASE, SZ_1K);
578 if (!sossi.base) {
579 dev_err(fbdev->dev, "can't ioremap SoSSI\n");
580 return -ENOMEM;
581 }
582
583 sossi.fbdev = fbdev;
584 spin_lock_init(&sossi.lock);
585
586 dpll1out_ck = clk_get(fbdev->dev, "ck_dpll1out");
587 if (IS_ERR(dpll1out_ck)) {
588 dev_err(fbdev->dev, "can't get DPLL1OUT clock\n");
589 return PTR_ERR(dpll1out_ck);
590 }
591 /*
592 * We need the parent clock rate, which we might divide further
593 * depending on the timing requirements of the controller. See
594 * _set_timings.
595 */
596 sossi.fck_hz = clk_get_rate(dpll1out_ck);
597 clk_put(dpll1out_ck);
598
599 fck = clk_get(fbdev->dev, "ck_sossi");
600 if (IS_ERR(fck)) {
601 dev_err(fbdev->dev, "can't get SoSSI functional clock\n");
602 return PTR_ERR(fck);
603 }
604 sossi.fck = fck;
605
606 /* Reset and enable the SoSSI module */
607 l = omap_readl(MOD_CONF_CTRL_1);
608 l |= CONF_SOSSI_RESET_R;
609 omap_writel(l, MOD_CONF_CTRL_1);
610 l &= ~CONF_SOSSI_RESET_R;
611 omap_writel(l, MOD_CONF_CTRL_1);
612
613 clk_enable(sossi.fck);
614 l = omap_readl(ARM_IDLECT2);
615 l &= ~(1 << 8); /* DMACK_REQ */
616 omap_writel(l, ARM_IDLECT2);
617
618 l = sossi_read_reg(SOSSI_INIT2_REG);
619 /* Enable and reset the SoSSI block */
620 l |= (1 << 0) | (1 << 1);
621 sossi_write_reg(SOSSI_INIT2_REG, l);
622 /* Take SoSSI out of reset */
623 l &= ~(1 << 1);
624 sossi_write_reg(SOSSI_INIT2_REG, l);
625
626 sossi_write_reg(SOSSI_ID_REG, 0);
627 l = sossi_read_reg(SOSSI_ID_REG);
628 k = sossi_read_reg(SOSSI_ID_REG);
629
630 if (l != 0x55555555 || k != 0xaaaaaaaa) {
631 dev_err(fbdev->dev,
632 "invalid SoSSI sync pattern: %08x, %08x\n", l, k);
633 r = -ENODEV;
634 goto err;
635 }
636
637 if ((r = omap_lcdc_set_dma_callback(sossi_dma_callback, NULL)) < 0) {
638 dev_err(fbdev->dev, "can't get LCDC IRQ\n");
639 r = -ENODEV;
640 goto err;
641 }
642
643 l = sossi_read_reg(SOSSI_ID_REG); /* Component code */
644 l = sossi_read_reg(SOSSI_ID_REG);
645 dev_info(fbdev->dev, "SoSSI version %d.%d initialized\n",
646 l >> 16, l & 0xffff);
647
648 l = sossi_read_reg(SOSSI_INIT1_REG);
649 l |= (1 << 19); /* DMA_MODE */
650 l &= ~(1 << 31); /* REORDERING */
651 sossi_write_reg(SOSSI_INIT1_REG, l);
652
653 if ((r = request_irq(INT_1610_SoSSI_MATCH, sossi_match_irq,
654 IRQ_TYPE_EDGE_FALLING,
655 "sossi_match", sossi.fbdev->dev)) < 0) {
656 dev_err(sossi.fbdev->dev, "can't get SoSSI match IRQ\n");
657 goto err;
658 }
659
660 clk_disable(sossi.fck);
661 return 0;
662
663 err:
664 clk_disable(sossi.fck);
665 clk_put(sossi.fck);
666 return r;
667 }
668
669 static void sossi_cleanup(void)
670 {
671 omap_lcdc_free_dma_callback();
672 clk_put(sossi.fck);
673 iounmap(sossi.base);
674 }
675
676 struct lcd_ctrl_extif omap1_ext_if = {
677 .init = sossi_init,
678 .cleanup = sossi_cleanup,
679 .get_clk_info = sossi_get_clk_info,
680 .convert_timings = sossi_convert_timings,
681 .set_timings = sossi_set_timings,
682 .set_bits_per_cycle = sossi_set_bits_per_cycle,
683 .setup_tearsync = sossi_setup_tearsync,
684 .enable_tearsync = sossi_enable_tearsync,
685 .write_command = sossi_write_command,
686 .read_data = sossi_read_data,
687 .write_data = sossi_write_data,
688 .transfer_area = sossi_transfer_area,
689
690 .max_transmit_size = SOSSI_MAX_XMIT_BYTES,
691 };
692
linux 2.6 git repository for openrd