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x86, mce: document new 32bit mcelog requirement in Documentation/Changes
[linux-2.6/linux-2.6-openrd.git] / drivers / ata / pata_sil680.c
blob4cb649d8d38cbb603e719cac0938f42a068555f4
1 /*
2 * pata_sil680.c - SIL680 PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 *
5 * based upon
6 *
7 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
8 *
9 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
10 * Copyright (C) 2003 Red Hat <alan@redhat.com>
11 *
12 * May be copied or modified under the terms of the GNU General Public License
13 *
14 * Documentation publically available.
15 *
16 * If you have strange problems with nVidia chipset systems please
17 * see the SI support documentation and update your system BIOS
18 * if necessary
19 *
20 * TODO
21 * If we know all our devices are LBA28 (or LBA28 sized) we could use
22 * the command fifo mode.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/blkdev.h>
30 #include <linux/delay.h>
31 #include <scsi/scsi_host.h>
32 #include <linux/libata.h>
33
34 #define DRV_NAME "pata_sil680"
35 #define DRV_VERSION "0.4.9"
36
37 #define SIL680_MMIO_BAR 5
38
39 /**
40 * sil680_selreg - return register base
41 * @hwif: interface
42 * @r: config offset
43 *
44 * Turn a config register offset into the right address in either
45 * PCI space or MMIO space to access the control register in question
46 * Thankfully this is a configuration operation so isnt performance
47 * criticial.
48 */
49
50 static unsigned long sil680_selreg(struct ata_port *ap, int r)
51 {
52 unsigned long base = 0xA0 + r;
53 base += (ap->port_no << 4);
54 return base;
55 }
56
57 /**
58 * sil680_seldev - return register base
59 * @hwif: interface
60 * @r: config offset
61 *
62 * Turn a config register offset into the right address in either
63 * PCI space or MMIO space to access the control register in question
64 * including accounting for the unit shift.
65 */
66
67 static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
68 {
69 unsigned long base = 0xA0 + r;
70 base += (ap->port_no << 4);
71 base |= adev->devno ? 2 : 0;
72 return base;
73 }
74
75
76 /**
77 * sil680_cable_detect - cable detection
78 * @ap: ATA port
79 *
80 * Perform cable detection. The SIL680 stores this in PCI config
81 * space for us.
82 */
83
84 static int sil680_cable_detect(struct ata_port *ap) {
85 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
86 unsigned long addr = sil680_selreg(ap, 0);
87 u8 ata66;
88 pci_read_config_byte(pdev, addr, &ata66);
89 if (ata66 & 1)
90 return ATA_CBL_PATA80;
91 else
92 return ATA_CBL_PATA40;
93 }
94
95 /**
96 * sil680_set_piomode - set initial PIO mode data
97 * @ap: ATA interface
98 * @adev: ATA device
99 *
100 * Program the SIL680 registers for PIO mode. Note that the task speed
101 * registers are shared between the devices so we must pick the lowest
102 * mode for command work.
103 */
104
105 static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
106 {
107 static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 };
108 static u16 speed_t[5] = { 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 };
109
110 unsigned long tfaddr = sil680_selreg(ap, 0x02);
111 unsigned long addr = sil680_seldev(ap, adev, 0x04);
112 unsigned long addr_mask = 0x80 + 4 * ap->port_no;
113 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
114 int pio = adev->pio_mode - XFER_PIO_0;
115 int lowest_pio = pio;
116 int port_shift = 4 * adev->devno;
117 u16 reg;
118 u8 mode;
119
120 struct ata_device *pair = ata_dev_pair(adev);
121
122 if (pair != NULL && adev->pio_mode > pair->pio_mode)
123 lowest_pio = pair->pio_mode - XFER_PIO_0;
124
125 pci_write_config_word(pdev, addr, speed_p[pio]);
126 pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);
127
128 pci_read_config_word(pdev, tfaddr-2, &reg);
129 pci_read_config_byte(pdev, addr_mask, &mode);
130
131 reg &= ~0x0200; /* Clear IORDY */
132 mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */
133
134 if (ata_pio_need_iordy(adev)) {
135 reg |= 0x0200; /* Enable IORDY */
136 mode |= 1 << port_shift;
137 }
138 pci_write_config_word(pdev, tfaddr-2, reg);
139 pci_write_config_byte(pdev, addr_mask, mode);
140 }
141
142 /**
143 * sil680_set_dmamode - set initial DMA mode data
144 * @ap: ATA interface
145 * @adev: ATA device
146 *
147 * Program the MWDMA/UDMA modes for the sil680 k
148 * chipset. The MWDMA mode values are pulled from a lookup table
149 * while the chipset uses mode number for UDMA.
150 */
151
152 static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
153 {
154 static u8 ultra_table[2][7] = {
155 { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */
156 { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */
157 };
158 static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
159
160 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
161 unsigned long ma = sil680_seldev(ap, adev, 0x08);
162 unsigned long ua = sil680_seldev(ap, adev, 0x0C);
163 unsigned long addr_mask = 0x80 + 4 * ap->port_no;
164 int port_shift = adev->devno * 4;
165 u8 scsc, mode;
166 u16 multi, ultra;
167
168 pci_read_config_byte(pdev, 0x8A, &scsc);
169 pci_read_config_byte(pdev, addr_mask, &mode);
170 pci_read_config_word(pdev, ma, &multi);
171 pci_read_config_word(pdev, ua, &ultra);
172
173 /* Mask timing bits */
174 ultra &= ~0x3F;
175 mode &= ~(0x03 << port_shift);
176
177 /* Extract scsc */
178 scsc = (scsc & 0x30) ? 1: 0;
179
180 if (adev->dma_mode >= XFER_UDMA_0) {
181 multi = 0x10C1;
182 ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
183 mode |= (0x03 << port_shift);
184 } else {
185 multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
186 mode |= (0x02 << port_shift);
187 }
188 pci_write_config_byte(pdev, addr_mask, mode);
189 pci_write_config_word(pdev, ma, multi);
190 pci_write_config_word(pdev, ua, ultra);
191 }
192
193 static struct scsi_host_template sil680_sht = {
194 ATA_BMDMA_SHT(DRV_NAME),
195 };
196
197 static struct ata_port_operations sil680_port_ops = {
198 .inherits = &ata_bmdma32_port_ops,
199 .cable_detect = sil680_cable_detect,
200 .set_piomode = sil680_set_piomode,
201 .set_dmamode = sil680_set_dmamode,
202 };
203
204 /**
205 * sil680_init_chip - chip setup
206 * @pdev: PCI device
207 *
208 * Perform all the chip setup which must be done both when the device
209 * is powered up on boot and when we resume in case we resumed from RAM.
210 * Returns the final clock settings.
211 */
212
213 static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio)
214 {
215 u32 class_rev = 0;
216 u8 tmpbyte = 0;
217
218 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
219 class_rev &= 0xff;
220 /* FIXME: double check */
221 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
222
223 pci_write_config_byte(pdev, 0x80, 0x00);
224 pci_write_config_byte(pdev, 0x84, 0x00);
225
226 pci_read_config_byte(pdev, 0x8A, &tmpbyte);
227
228 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
229 tmpbyte & 1, tmpbyte & 0x30);
230
231 *try_mmio = 0;
232 #ifdef CONFIG_PPC
233 if (machine_is(cell))
234 *try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5);
235 #endif
236
237 switch(tmpbyte & 0x30) {
238 case 0x00:
239 /* 133 clock attempt to force it on */
240 pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);
241 break;
242 case 0x30:
243 /* if clocking is disabled */
244 /* 133 clock attempt to force it on */
245 pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
246 break;
247 case 0x10:
248 /* 133 already */
249 break;
250 case 0x20:
251 /* BIOS set PCI x2 clocking */
252 break;
253 }
254
255 pci_read_config_byte(pdev, 0x8A, &tmpbyte);
256 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
257 tmpbyte & 1, tmpbyte & 0x30);
258
259 pci_write_config_byte(pdev, 0xA1, 0x72);
260 pci_write_config_word(pdev, 0xA2, 0x328A);
261 pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
262 pci_write_config_dword(pdev, 0xA8, 0x43924392);
263 pci_write_config_dword(pdev, 0xAC, 0x40094009);
264 pci_write_config_byte(pdev, 0xB1, 0x72);
265 pci_write_config_word(pdev, 0xB2, 0x328A);
266 pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
267 pci_write_config_dword(pdev, 0xB8, 0x43924392);
268 pci_write_config_dword(pdev, 0xBC, 0x40094009);
269
270 switch(tmpbyte & 0x30) {
271 case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break;
272 case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break;
273 case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break;
274 /* This last case is _NOT_ ok */
275 case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n");
276 }
277 return tmpbyte & 0x30;
278 }
279
280 static int __devinit sil680_init_one(struct pci_dev *pdev,
281 const struct pci_device_id *id)
282 {
283 static const struct ata_port_info info = {
284 .flags = ATA_FLAG_SLAVE_POSS,
285 .pio_mask = ATA_PIO4,
286 .mwdma_mask = ATA_MWDMA2,
287 .udma_mask = ATA_UDMA6,
288 .port_ops = &sil680_port_ops
289 };
290 static const struct ata_port_info info_slow = {
291 .flags = ATA_FLAG_SLAVE_POSS,
292 .pio_mask = ATA_PIO4,
293 .mwdma_mask = ATA_MWDMA2,
294 .udma_mask = ATA_UDMA5,
295 .port_ops = &sil680_port_ops
296 };
297 const struct ata_port_info *ppi[] = { &info, NULL };
298 static int printed_version;
299 struct ata_host *host;
300 void __iomem *mmio_base;
301 int rc, try_mmio;
302
303 if (!printed_version++)
304 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
305
306 rc = pcim_enable_device(pdev);
307 if (rc)
308 return rc;
309
310 switch (sil680_init_chip(pdev, &try_mmio)) {
311 case 0:
312 ppi[0] = &info_slow;
313 break;
314 case 0x30:
315 return -ENODEV;
316 }
317
318 if (!try_mmio)
319 goto use_ioports;
320
321 /* Try to acquire MMIO resources and fallback to PIO if
322 * that fails
323 */
324 rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME);
325 if (rc)
326 goto use_ioports;
327
328 /* Allocate host and set it up */
329 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
330 if (!host)
331 return -ENOMEM;
332 host->iomap = pcim_iomap_table(pdev);
333
334 /* Setup DMA masks */
335 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
336 if (rc)
337 return rc;
338 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
339 if (rc)
340 return rc;
341 pci_set_master(pdev);
342
343 /* Get MMIO base and initialize port addresses */
344 mmio_base = host->iomap[SIL680_MMIO_BAR];
345 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;
346 host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;
347 host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;
348 host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;
349 ata_sff_std_ports(&host->ports[0]->ioaddr);
350 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;
351 host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;
352 host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;
353 host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;
354 ata_sff_std_ports(&host->ports[1]->ioaddr);
355
356 /* Register & activate */
357 return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
358 IRQF_SHARED, &sil680_sht);
359
360 use_ioports:
361 return ata_pci_sff_init_one(pdev, ppi, &sil680_sht, NULL);
362 }
363
364 #ifdef CONFIG_PM
365 static int sil680_reinit_one(struct pci_dev *pdev)
366 {
367 struct ata_host *host = dev_get_drvdata(&pdev->dev);
368 int try_mmio, rc;
369
370 rc = ata_pci_device_do_resume(pdev);
371 if (rc)
372 return rc;
373 sil680_init_chip(pdev, &try_mmio);
374 ata_host_resume(host);
375 return 0;
376 }
377 #endif
378
379 static const struct pci_device_id sil680[] = {
380 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },
381
382 { },
383 };
384
385 static struct pci_driver sil680_pci_driver = {
386 .name = DRV_NAME,
387 .id_table = sil680,
388 .probe = sil680_init_one,
389 .remove = ata_pci_remove_one,
390 #ifdef CONFIG_PM
391 .suspend = ata_pci_device_suspend,
392 .resume = sil680_reinit_one,
393 #endif
394 };
395
396 static int __init sil680_init(void)
397 {
398 return pci_register_driver(&sil680_pci_driver);
399 }
400
401 static void __exit sil680_exit(void)
402 {
403 pci_unregister_driver(&sil680_pci_driver);
404 }
405
406 MODULE_AUTHOR("Alan Cox");
407 MODULE_DESCRIPTION("low-level driver for SI680 PATA");
408 MODULE_LICENSE("GPL");
409 MODULE_DEVICE_TABLE(pci, sil680);
410 MODULE_VERSION(DRV_VERSION);
411
412 module_init(sil680_init);
413 module_exit(sil680_exit);
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