2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include <linux/swap.h>
34 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
37 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
,
38 uint32_t read_domains
,
39 uint32_t write_domain
);
40 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
43 static int i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
,
45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
51 static int i915_gem_object_get_page_list(struct drm_gem_object
*obj
);
52 static void i915_gem_object_free_page_list(struct drm_gem_object
*obj
);
53 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
56 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
59 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
60 struct drm_file
*file_priv
)
62 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
63 struct drm_i915_gem_init
*args
= data
;
65 mutex_lock(&dev
->struct_mutex
);
67 if (args
->gtt_start
>= args
->gtt_end
||
68 (args
->gtt_start
& (PAGE_SIZE
- 1)) != 0 ||
69 (args
->gtt_end
& (PAGE_SIZE
- 1)) != 0) {
70 mutex_unlock(&dev
->struct_mutex
);
74 drm_mm_init(&dev_priv
->mm
.gtt_space
, args
->gtt_start
,
75 args
->gtt_end
- args
->gtt_start
);
77 dev
->gtt_total
= (uint32_t) (args
->gtt_end
- args
->gtt_start
);
79 mutex_unlock(&dev
->struct_mutex
);
85 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
86 struct drm_file
*file_priv
)
88 struct drm_i915_gem_get_aperture
*args
= data
;
90 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
93 args
->aper_size
= dev
->gtt_total
;
94 args
->aper_available_size
= (args
->aper_size
-
95 atomic_read(&dev
->pin_memory
));
102 * Creates a new mm object and returns a handle to it.
105 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
106 struct drm_file
*file_priv
)
108 struct drm_i915_gem_create
*args
= data
;
109 struct drm_gem_object
*obj
;
112 args
->size
= roundup(args
->size
, PAGE_SIZE
);
114 /* Allocate the new object */
115 obj
= drm_gem_object_alloc(dev
, args
->size
);
119 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
120 mutex_lock(&dev
->struct_mutex
);
121 drm_gem_object_handle_unreference(obj
);
122 mutex_unlock(&dev
->struct_mutex
);
127 args
->handle
= handle
;
133 * Reads data from the object referenced by handle.
135 * On error, the contents of *data are undefined.
138 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
139 struct drm_file
*file_priv
)
141 struct drm_i915_gem_pread
*args
= data
;
142 struct drm_gem_object
*obj
;
143 struct drm_i915_gem_object
*obj_priv
;
148 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
151 obj_priv
= obj
->driver_private
;
153 /* Bounds check source.
155 * XXX: This could use review for overflow issues...
157 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
158 args
->offset
+ args
->size
> obj
->size
) {
159 drm_gem_object_unreference(obj
);
163 mutex_lock(&dev
->struct_mutex
);
165 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
168 drm_gem_object_unreference(obj
);
169 mutex_unlock(&dev
->struct_mutex
);
173 offset
= args
->offset
;
175 read
= vfs_read(obj
->filp
, (char __user
*)(uintptr_t)args
->data_ptr
,
176 args
->size
, &offset
);
177 if (read
!= args
->size
) {
178 drm_gem_object_unreference(obj
);
179 mutex_unlock(&dev
->struct_mutex
);
186 drm_gem_object_unreference(obj
);
187 mutex_unlock(&dev
->struct_mutex
);
192 /* This is the fast write path which cannot handle
193 * page faults in the source data
197 fast_user_write(struct io_mapping
*mapping
,
198 loff_t page_base
, int page_offset
,
199 char __user
*user_data
,
203 unsigned long unwritten
;
205 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
206 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
208 io_mapping_unmap_atomic(vaddr_atomic
);
214 /* Here's the write path which can sleep for
219 slow_user_write(struct io_mapping
*mapping
,
220 loff_t page_base
, int page_offset
,
221 char __user
*user_data
,
225 unsigned long unwritten
;
227 vaddr
= io_mapping_map_wc(mapping
, page_base
);
230 unwritten
= __copy_from_user(vaddr
+ page_offset
,
232 io_mapping_unmap(vaddr
);
239 i915_gem_gtt_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
240 struct drm_i915_gem_pwrite
*args
,
241 struct drm_file
*file_priv
)
243 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
244 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
246 loff_t offset
, page_base
;
247 char __user
*user_data
;
248 int page_offset
, page_length
;
251 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
253 if (!access_ok(VERIFY_READ
, user_data
, remain
))
257 mutex_lock(&dev
->struct_mutex
);
258 ret
= i915_gem_object_pin(obj
, 0);
260 mutex_unlock(&dev
->struct_mutex
);
263 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
267 obj_priv
= obj
->driver_private
;
268 offset
= obj_priv
->gtt_offset
+ args
->offset
;
272 /* Operation in this page
274 * page_base = page offset within aperture
275 * page_offset = offset within page
276 * page_length = bytes to copy for this page
278 page_base
= (offset
& ~(PAGE_SIZE
-1));
279 page_offset
= offset
& (PAGE_SIZE
-1);
280 page_length
= remain
;
281 if ((page_offset
+ remain
) > PAGE_SIZE
)
282 page_length
= PAGE_SIZE
- page_offset
;
284 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
285 page_offset
, user_data
, page_length
);
287 /* If we get a fault while copying data, then (presumably) our
288 * source page isn't available. In this case, use the
289 * non-atomic function
292 ret
= slow_user_write (dev_priv
->mm
.gtt_mapping
,
293 page_base
, page_offset
,
294 user_data
, page_length
);
299 remain
-= page_length
;
300 user_data
+= page_length
;
301 offset
+= page_length
;
305 i915_gem_object_unpin(obj
);
306 mutex_unlock(&dev
->struct_mutex
);
312 i915_gem_shmem_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
313 struct drm_i915_gem_pwrite
*args
,
314 struct drm_file
*file_priv
)
320 mutex_lock(&dev
->struct_mutex
);
322 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
324 mutex_unlock(&dev
->struct_mutex
);
328 offset
= args
->offset
;
330 written
= vfs_write(obj
->filp
,
331 (char __user
*)(uintptr_t) args
->data_ptr
,
332 args
->size
, &offset
);
333 if (written
!= args
->size
) {
334 mutex_unlock(&dev
->struct_mutex
);
341 mutex_unlock(&dev
->struct_mutex
);
347 * Writes data to the object referenced by handle.
349 * On error, the contents of the buffer that were to be modified are undefined.
352 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
353 struct drm_file
*file_priv
)
355 struct drm_i915_gem_pwrite
*args
= data
;
356 struct drm_gem_object
*obj
;
357 struct drm_i915_gem_object
*obj_priv
;
360 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
363 obj_priv
= obj
->driver_private
;
365 /* Bounds check destination.
367 * XXX: This could use review for overflow issues...
369 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
370 args
->offset
+ args
->size
> obj
->size
) {
371 drm_gem_object_unreference(obj
);
375 /* We can only do the GTT pwrite on untiled buffers, as otherwise
376 * it would end up going through the fenced access, and we'll get
377 * different detiling behavior between reading and writing.
378 * pread/pwrite currently are reading and writing from the CPU
379 * perspective, requiring manual detiling by the client.
381 if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
383 ret
= i915_gem_gtt_pwrite(dev
, obj
, args
, file_priv
);
385 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file_priv
);
389 DRM_INFO("pwrite failed %d\n", ret
);
392 drm_gem_object_unreference(obj
);
398 * Called when user space prepares to use an object with the CPU, either
399 * through the mmap ioctl's mapping or a GTT mapping.
402 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
403 struct drm_file
*file_priv
)
405 struct drm_i915_gem_set_domain
*args
= data
;
406 struct drm_gem_object
*obj
;
407 uint32_t read_domains
= args
->read_domains
;
408 uint32_t write_domain
= args
->write_domain
;
411 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
414 /* Only handle setting domains to types used by the CPU. */
415 if (write_domain
& ~(I915_GEM_DOMAIN_CPU
| I915_GEM_DOMAIN_GTT
))
418 if (read_domains
& ~(I915_GEM_DOMAIN_CPU
| I915_GEM_DOMAIN_GTT
))
421 /* Having something in the write domain implies it's in the read
422 * domain, and only that read domain. Enforce that in the request.
424 if (write_domain
!= 0 && read_domains
!= write_domain
)
427 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
431 mutex_lock(&dev
->struct_mutex
);
433 DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
434 obj
, obj
->size
, read_domains
, write_domain
);
436 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
437 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
439 /* Silently promote "you're not bound, there was nothing to do"
440 * to success, since the client was just asking us to
441 * make sure everything was done.
446 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
449 drm_gem_object_unreference(obj
);
450 mutex_unlock(&dev
->struct_mutex
);
455 * Called when user space has done writes to this buffer
458 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
459 struct drm_file
*file_priv
)
461 struct drm_i915_gem_sw_finish
*args
= data
;
462 struct drm_gem_object
*obj
;
463 struct drm_i915_gem_object
*obj_priv
;
466 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
469 mutex_lock(&dev
->struct_mutex
);
470 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
472 mutex_unlock(&dev
->struct_mutex
);
477 DRM_INFO("%s: sw_finish %d (%p %d)\n",
478 __func__
, args
->handle
, obj
, obj
->size
);
480 obj_priv
= obj
->driver_private
;
482 /* Pinned buffers may be scanout, so flush the cache */
483 if (obj_priv
->pin_count
)
484 i915_gem_object_flush_cpu_write_domain(obj
);
486 drm_gem_object_unreference(obj
);
487 mutex_unlock(&dev
->struct_mutex
);
492 * Maps the contents of an object, returning the address it is mapped
495 * While the mapping holds a reference on the contents of the object, it doesn't
496 * imply a ref on the object itself.
499 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
500 struct drm_file
*file_priv
)
502 struct drm_i915_gem_mmap
*args
= data
;
503 struct drm_gem_object
*obj
;
507 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
510 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
514 offset
= args
->offset
;
516 down_write(¤t
->mm
->mmap_sem
);
517 addr
= do_mmap(obj
->filp
, 0, args
->size
,
518 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
520 up_write(¤t
->mm
->mmap_sem
);
521 mutex_lock(&dev
->struct_mutex
);
522 drm_gem_object_unreference(obj
);
523 mutex_unlock(&dev
->struct_mutex
);
524 if (IS_ERR((void *)addr
))
527 args
->addr_ptr
= (uint64_t) addr
;
533 i915_gem_object_free_page_list(struct drm_gem_object
*obj
)
535 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
536 int page_count
= obj
->size
/ PAGE_SIZE
;
539 if (obj_priv
->page_list
== NULL
)
543 for (i
= 0; i
< page_count
; i
++)
544 if (obj_priv
->page_list
[i
] != NULL
) {
546 set_page_dirty(obj_priv
->page_list
[i
]);
547 mark_page_accessed(obj_priv
->page_list
[i
]);
548 page_cache_release(obj_priv
->page_list
[i
]);
552 drm_free(obj_priv
->page_list
,
553 page_count
* sizeof(struct page
*),
555 obj_priv
->page_list
= NULL
;
559 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
)
561 struct drm_device
*dev
= obj
->dev
;
562 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
563 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
565 /* Add a reference if we're newly entering the active list. */
566 if (!obj_priv
->active
) {
567 drm_gem_object_reference(obj
);
568 obj_priv
->active
= 1;
570 /* Move from whatever list we were on to the tail of execution. */
571 list_move_tail(&obj_priv
->list
,
572 &dev_priv
->mm
.active_list
);
573 obj_priv
->last_rendering_seqno
= seqno
;
577 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
579 struct drm_device
*dev
= obj
->dev
;
580 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
581 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
583 BUG_ON(!obj_priv
->active
);
584 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
585 obj_priv
->last_rendering_seqno
= 0;
589 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
591 struct drm_device
*dev
= obj
->dev
;
592 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
593 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
595 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
596 if (obj_priv
->pin_count
!= 0)
597 list_del_init(&obj_priv
->list
);
599 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
601 obj_priv
->last_rendering_seqno
= 0;
602 if (obj_priv
->active
) {
603 obj_priv
->active
= 0;
604 drm_gem_object_unreference(obj
);
606 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
610 * Creates a new sequence number, emitting a write of it to the status page
611 * plus an interrupt, which will trigger i915_user_interrupt_handler.
613 * Must be called with struct_lock held.
615 * Returned sequence numbers are nonzero on success.
618 i915_add_request(struct drm_device
*dev
, uint32_t flush_domains
)
620 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
621 struct drm_i915_gem_request
*request
;
626 request
= drm_calloc(1, sizeof(*request
), DRM_MEM_DRIVER
);
630 /* Grab the seqno we're going to make this request be, and bump the
631 * next (skipping 0 so it can be the reserved no-seqno value).
633 seqno
= dev_priv
->mm
.next_gem_seqno
;
634 dev_priv
->mm
.next_gem_seqno
++;
635 if (dev_priv
->mm
.next_gem_seqno
== 0)
636 dev_priv
->mm
.next_gem_seqno
++;
639 OUT_RING(MI_STORE_DWORD_INDEX
);
640 OUT_RING(I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
643 OUT_RING(MI_USER_INTERRUPT
);
646 DRM_DEBUG("%d\n", seqno
);
648 request
->seqno
= seqno
;
649 request
->emitted_jiffies
= jiffies
;
650 was_empty
= list_empty(&dev_priv
->mm
.request_list
);
651 list_add_tail(&request
->list
, &dev_priv
->mm
.request_list
);
653 /* Associate any objects on the flushing list matching the write
654 * domain we're flushing with our flush.
656 if (flush_domains
!= 0) {
657 struct drm_i915_gem_object
*obj_priv
, *next
;
659 list_for_each_entry_safe(obj_priv
, next
,
660 &dev_priv
->mm
.flushing_list
, list
) {
661 struct drm_gem_object
*obj
= obj_priv
->obj
;
663 if ((obj
->write_domain
& flush_domains
) ==
665 obj
->write_domain
= 0;
666 i915_gem_object_move_to_active(obj
, seqno
);
672 if (was_empty
&& !dev_priv
->mm
.suspended
)
673 schedule_delayed_work(&dev_priv
->mm
.retire_work
, HZ
);
678 * Command execution barrier
680 * Ensures that all commands in the ring are finished
681 * before signalling the CPU
684 i915_retire_commands(struct drm_device
*dev
)
686 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
687 uint32_t cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
688 uint32_t flush_domains
= 0;
691 /* The sampler always gets flushed on i965 (sigh) */
693 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
696 OUT_RING(0); /* noop */
698 return flush_domains
;
702 * Moves buffers associated only with the given active seqno from the active
703 * to inactive list, potentially freeing them.
706 i915_gem_retire_request(struct drm_device
*dev
,
707 struct drm_i915_gem_request
*request
)
709 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
711 /* Move any buffers on the active list that are no longer referenced
712 * by the ringbuffer to the flushing/inactive lists as appropriate.
714 while (!list_empty(&dev_priv
->mm
.active_list
)) {
715 struct drm_gem_object
*obj
;
716 struct drm_i915_gem_object
*obj_priv
;
718 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
719 struct drm_i915_gem_object
,
723 /* If the seqno being retired doesn't match the oldest in the
724 * list, then the oldest in the list must still be newer than
727 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
730 DRM_INFO("%s: retire %d moves to inactive list %p\n",
731 __func__
, request
->seqno
, obj
);
734 if (obj
->write_domain
!= 0)
735 i915_gem_object_move_to_flushing(obj
);
737 i915_gem_object_move_to_inactive(obj
);
742 * Returns true if seq1 is later than seq2.
745 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
747 return (int32_t)(seq1
- seq2
) >= 0;
751 i915_get_gem_seqno(struct drm_device
*dev
)
753 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
755 return READ_HWSP(dev_priv
, I915_GEM_HWS_INDEX
);
759 * This function clears the request list as sequence numbers are passed.
762 i915_gem_retire_requests(struct drm_device
*dev
)
764 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
767 seqno
= i915_get_gem_seqno(dev
);
769 while (!list_empty(&dev_priv
->mm
.request_list
)) {
770 struct drm_i915_gem_request
*request
;
771 uint32_t retiring_seqno
;
773 request
= list_first_entry(&dev_priv
->mm
.request_list
,
774 struct drm_i915_gem_request
,
776 retiring_seqno
= request
->seqno
;
778 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
779 dev_priv
->mm
.wedged
) {
780 i915_gem_retire_request(dev
, request
);
782 list_del(&request
->list
);
783 drm_free(request
, sizeof(*request
), DRM_MEM_DRIVER
);
790 i915_gem_retire_work_handler(struct work_struct
*work
)
792 drm_i915_private_t
*dev_priv
;
793 struct drm_device
*dev
;
795 dev_priv
= container_of(work
, drm_i915_private_t
,
796 mm
.retire_work
.work
);
799 mutex_lock(&dev
->struct_mutex
);
800 i915_gem_retire_requests(dev
);
801 if (!dev_priv
->mm
.suspended
&&
802 !list_empty(&dev_priv
->mm
.request_list
))
803 schedule_delayed_work(&dev_priv
->mm
.retire_work
, HZ
);
804 mutex_unlock(&dev
->struct_mutex
);
808 * Waits for a sequence number to be signaled, and cleans up the
809 * request and object lists appropriately for that event.
812 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
)
814 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
819 if (!i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
)) {
820 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
821 i915_user_irq_get(dev
);
822 ret
= wait_event_interruptible(dev_priv
->irq_queue
,
823 i915_seqno_passed(i915_get_gem_seqno(dev
),
825 dev_priv
->mm
.wedged
);
826 i915_user_irq_put(dev
);
827 dev_priv
->mm
.waiting_gem_seqno
= 0;
829 if (dev_priv
->mm
.wedged
)
832 if (ret
&& ret
!= -ERESTARTSYS
)
833 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
834 __func__
, ret
, seqno
, i915_get_gem_seqno(dev
));
836 /* Directly dispatch request retiring. While we have the work queue
837 * to handle this, the waiter on a request often wants an associated
838 * buffer to have made it to the inactive list, and we would need
839 * a separate wait queue to handle that.
842 i915_gem_retire_requests(dev
);
848 i915_gem_flush(struct drm_device
*dev
,
849 uint32_t invalidate_domains
,
850 uint32_t flush_domains
)
852 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
857 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__
,
858 invalidate_domains
, flush_domains
);
861 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
862 drm_agp_chipset_flush(dev
);
864 if ((invalidate_domains
| flush_domains
) & ~(I915_GEM_DOMAIN_CPU
|
865 I915_GEM_DOMAIN_GTT
)) {
869 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
870 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
871 * also flushed at 2d versus 3d pipeline switches.
875 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
876 * MI_READ_FLUSH is set, and is always flushed on 965.
878 * I915_GEM_DOMAIN_COMMAND may not exist?
880 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
881 * invalidated when MI_EXE_FLUSH is set.
883 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
884 * invalidated with every MI_FLUSH.
888 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
889 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
890 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
891 * are flushed at any MI_FLUSH.
894 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
895 if ((invalidate_domains
|flush_domains
) &
896 I915_GEM_DOMAIN_RENDER
)
897 cmd
&= ~MI_NO_WRITE_FLUSH
;
898 if (!IS_I965G(dev
)) {
900 * On the 965, the sampler cache always gets flushed
901 * and this bit is reserved.
903 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
904 cmd
|= MI_READ_FLUSH
;
906 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
910 DRM_INFO("%s: queue flush %08x to ring\n", __func__
, cmd
);
914 OUT_RING(0); /* noop */
920 * Ensures that all rendering to the object has completed and the object is
921 * safe to unbind from the GTT or access from the CPU.
924 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
926 struct drm_device
*dev
= obj
->dev
;
927 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
930 /* This function only exists to support waiting for existing rendering,
931 * not for emitting required flushes.
933 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
935 /* If there is rendering queued on the buffer being evicted, wait for
938 if (obj_priv
->active
) {
940 DRM_INFO("%s: object %p wait for seqno %08x\n",
941 __func__
, obj
, obj_priv
->last_rendering_seqno
);
943 ret
= i915_wait_request(dev
, obj_priv
->last_rendering_seqno
);
952 * Unbinds an object from the GTT aperture.
955 i915_gem_object_unbind(struct drm_gem_object
*obj
)
957 struct drm_device
*dev
= obj
->dev
;
958 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
962 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
963 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
965 if (obj_priv
->gtt_space
== NULL
)
968 if (obj_priv
->pin_count
!= 0) {
969 DRM_ERROR("Attempting to unbind pinned buffer\n");
973 /* Move the object to the CPU domain to ensure that
974 * any possible CPU writes while it's not in the GTT
975 * are flushed when we go to remap it. This will
976 * also ensure that all pending GPU writes are finished
979 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
981 if (ret
!= -ERESTARTSYS
)
982 DRM_ERROR("set_domain failed: %d\n", ret
);
986 if (obj_priv
->agp_mem
!= NULL
) {
987 drm_unbind_agp(obj_priv
->agp_mem
);
988 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
989 obj_priv
->agp_mem
= NULL
;
992 BUG_ON(obj_priv
->active
);
994 i915_gem_object_free_page_list(obj
);
996 if (obj_priv
->gtt_space
) {
997 atomic_dec(&dev
->gtt_count
);
998 atomic_sub(obj
->size
, &dev
->gtt_memory
);
1000 drm_mm_put_block(obj_priv
->gtt_space
);
1001 obj_priv
->gtt_space
= NULL
;
1004 /* Remove ourselves from the LRU list if present. */
1005 if (!list_empty(&obj_priv
->list
))
1006 list_del_init(&obj_priv
->list
);
1012 i915_gem_evict_something(struct drm_device
*dev
)
1014 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1015 struct drm_gem_object
*obj
;
1016 struct drm_i915_gem_object
*obj_priv
;
1020 /* If there's an inactive buffer available now, grab it
1023 if (!list_empty(&dev_priv
->mm
.inactive_list
)) {
1024 obj_priv
= list_first_entry(&dev_priv
->mm
.inactive_list
,
1025 struct drm_i915_gem_object
,
1027 obj
= obj_priv
->obj
;
1028 BUG_ON(obj_priv
->pin_count
!= 0);
1030 DRM_INFO("%s: evicting %p\n", __func__
, obj
);
1032 BUG_ON(obj_priv
->active
);
1034 /* Wait on the rendering and unbind the buffer. */
1035 ret
= i915_gem_object_unbind(obj
);
1039 /* If we didn't get anything, but the ring is still processing
1040 * things, wait for one of those things to finish and hopefully
1041 * leave us a buffer to evict.
1043 if (!list_empty(&dev_priv
->mm
.request_list
)) {
1044 struct drm_i915_gem_request
*request
;
1046 request
= list_first_entry(&dev_priv
->mm
.request_list
,
1047 struct drm_i915_gem_request
,
1050 ret
= i915_wait_request(dev
, request
->seqno
);
1054 /* if waiting caused an object to become inactive,
1055 * then loop around and wait for it. Otherwise, we
1056 * assume that waiting freed and unbound something,
1057 * so there should now be some space in the GTT
1059 if (!list_empty(&dev_priv
->mm
.inactive_list
))
1064 /* If we didn't have anything on the request list but there
1065 * are buffers awaiting a flush, emit one and try again.
1066 * When we wait on it, those buffers waiting for that flush
1067 * will get moved to inactive.
1069 if (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1070 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1071 struct drm_i915_gem_object
,
1073 obj
= obj_priv
->obj
;
1078 i915_add_request(dev
, obj
->write_domain
);
1084 DRM_ERROR("inactive empty %d request empty %d "
1085 "flushing empty %d\n",
1086 list_empty(&dev_priv
->mm
.inactive_list
),
1087 list_empty(&dev_priv
->mm
.request_list
),
1088 list_empty(&dev_priv
->mm
.flushing_list
));
1089 /* If we didn't do any of the above, there's nothing to be done
1090 * and we just can't fit it in.
1098 i915_gem_evict_everything(struct drm_device
*dev
)
1103 ret
= i915_gem_evict_something(dev
);
1113 i915_gem_object_get_page_list(struct drm_gem_object
*obj
)
1115 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1117 struct address_space
*mapping
;
1118 struct inode
*inode
;
1122 if (obj_priv
->page_list
)
1125 /* Get the list of pages out of our struct file. They'll be pinned
1126 * at this point until we release them.
1128 page_count
= obj
->size
/ PAGE_SIZE
;
1129 BUG_ON(obj_priv
->page_list
!= NULL
);
1130 obj_priv
->page_list
= drm_calloc(page_count
, sizeof(struct page
*),
1132 if (obj_priv
->page_list
== NULL
) {
1133 DRM_ERROR("Faled to allocate page list\n");
1137 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1138 mapping
= inode
->i_mapping
;
1139 for (i
= 0; i
< page_count
; i
++) {
1140 page
= read_mapping_page(mapping
, i
, NULL
);
1142 ret
= PTR_ERR(page
);
1143 DRM_ERROR("read_mapping_page failed: %d\n", ret
);
1144 i915_gem_object_free_page_list(obj
);
1147 obj_priv
->page_list
[i
] = page
;
1153 * Finds free space in the GTT aperture and binds the object there.
1156 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
1158 struct drm_device
*dev
= obj
->dev
;
1159 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1160 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1161 struct drm_mm_node
*free_space
;
1162 int page_count
, ret
;
1165 alignment
= PAGE_SIZE
;
1166 if (alignment
& (PAGE_SIZE
- 1)) {
1167 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
1172 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
1173 obj
->size
, alignment
, 0);
1174 if (free_space
!= NULL
) {
1175 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
1177 if (obj_priv
->gtt_space
!= NULL
) {
1178 obj_priv
->gtt_space
->private = obj
;
1179 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
1182 if (obj_priv
->gtt_space
== NULL
) {
1183 /* If the gtt is empty and we're still having trouble
1184 * fitting our object in, we're out of memory.
1187 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
1189 if (list_empty(&dev_priv
->mm
.inactive_list
) &&
1190 list_empty(&dev_priv
->mm
.flushing_list
) &&
1191 list_empty(&dev_priv
->mm
.active_list
)) {
1192 DRM_ERROR("GTT full, but LRU list empty\n");
1196 ret
= i915_gem_evict_something(dev
);
1198 if (ret
!= -ERESTARTSYS
)
1199 DRM_ERROR("Failed to evict a buffer %d\n", ret
);
1206 DRM_INFO("Binding object of size %d at 0x%08x\n",
1207 obj
->size
, obj_priv
->gtt_offset
);
1209 ret
= i915_gem_object_get_page_list(obj
);
1211 drm_mm_put_block(obj_priv
->gtt_space
);
1212 obj_priv
->gtt_space
= NULL
;
1216 page_count
= obj
->size
/ PAGE_SIZE
;
1217 /* Create an AGP memory structure pointing at our pages, and bind it
1220 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
1221 obj_priv
->page_list
,
1223 obj_priv
->gtt_offset
,
1224 obj_priv
->agp_type
);
1225 if (obj_priv
->agp_mem
== NULL
) {
1226 i915_gem_object_free_page_list(obj
);
1227 drm_mm_put_block(obj_priv
->gtt_space
);
1228 obj_priv
->gtt_space
= NULL
;
1231 atomic_inc(&dev
->gtt_count
);
1232 atomic_add(obj
->size
, &dev
->gtt_memory
);
1234 /* Assert that the object is not currently in any GPU domain. As it
1235 * wasn't in the GTT, there shouldn't be any way it could have been in
1238 BUG_ON(obj
->read_domains
& ~(I915_GEM_DOMAIN_CPU
|I915_GEM_DOMAIN_GTT
));
1239 BUG_ON(obj
->write_domain
& ~(I915_GEM_DOMAIN_CPU
|I915_GEM_DOMAIN_GTT
));
1245 i915_gem_clflush_object(struct drm_gem_object
*obj
)
1247 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1249 /* If we don't have a page list set up, then we're not pinned
1250 * to GPU, and we can ignore the cache flush because it'll happen
1251 * again at bind time.
1253 if (obj_priv
->page_list
== NULL
)
1256 drm_clflush_pages(obj_priv
->page_list
, obj
->size
/ PAGE_SIZE
);
1259 /** Flushes any GPU write domain for the object if it's dirty. */
1261 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
1263 struct drm_device
*dev
= obj
->dev
;
1266 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
1269 /* Queue the GPU write cache flushing we need. */
1270 i915_gem_flush(dev
, 0, obj
->write_domain
);
1271 seqno
= i915_add_request(dev
, obj
->write_domain
);
1272 obj
->write_domain
= 0;
1273 i915_gem_object_move_to_active(obj
, seqno
);
1276 /** Flushes the GTT write domain for the object if it's dirty. */
1278 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
1280 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
1283 /* No actual flushing is required for the GTT write domain. Writes
1284 * to it immediately go to main memory as far as we know, so there's
1285 * no chipset flush. It also doesn't land in render cache.
1287 obj
->write_domain
= 0;
1290 /** Flushes the CPU write domain for the object if it's dirty. */
1292 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
1294 struct drm_device
*dev
= obj
->dev
;
1296 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
1299 i915_gem_clflush_object(obj
);
1300 drm_agp_chipset_flush(dev
);
1301 obj
->write_domain
= 0;
1305 * Moves a single object to the GTT read, and possibly write domain.
1307 * This function returns when the move is complete, including waiting on
1311 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
1313 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1316 /* Not valid to be called on unbound objects. */
1317 if (obj_priv
->gtt_space
== NULL
)
1320 i915_gem_object_flush_gpu_write_domain(obj
);
1321 /* Wait on any GPU rendering and flushing to occur. */
1322 ret
= i915_gem_object_wait_rendering(obj
);
1326 /* If we're writing through the GTT domain, then CPU and GPU caches
1327 * will need to be invalidated at next use.
1330 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
1332 i915_gem_object_flush_cpu_write_domain(obj
);
1334 /* It should now be out of any other write domains, and we can update
1335 * the domain values for our changes.
1337 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
1338 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
1340 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
1341 obj_priv
->dirty
= 1;
1348 * Moves a single object to the CPU read, and possibly write domain.
1350 * This function returns when the move is complete, including waiting on
1354 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
1356 struct drm_device
*dev
= obj
->dev
;
1359 i915_gem_object_flush_gpu_write_domain(obj
);
1360 /* Wait on any GPU rendering and flushing to occur. */
1361 ret
= i915_gem_object_wait_rendering(obj
);
1365 i915_gem_object_flush_gtt_write_domain(obj
);
1367 /* If we have a partially-valid cache of the object in the CPU,
1368 * finish invalidating it and free the per-page flags.
1370 i915_gem_object_set_to_full_cpu_read_domain(obj
);
1372 /* Flush the CPU cache if it's still invalid. */
1373 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
1374 i915_gem_clflush_object(obj
);
1375 drm_agp_chipset_flush(dev
);
1377 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
1380 /* It should now be out of any other write domains, and we can update
1381 * the domain values for our changes.
1383 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
1385 /* If we're writing through the CPU, then the GPU read domains will
1386 * need to be invalidated at next use.
1389 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
1390 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
1397 * Set the next domain for the specified object. This
1398 * may not actually perform the necessary flushing/invaliding though,
1399 * as that may want to be batched with other set_domain operations
1401 * This is (we hope) the only really tricky part of gem. The goal
1402 * is fairly simple -- track which caches hold bits of the object
1403 * and make sure they remain coherent. A few concrete examples may
1404 * help to explain how it works. For shorthand, we use the notation
1405 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1406 * a pair of read and write domain masks.
1408 * Case 1: the batch buffer
1414 * 5. Unmapped from GTT
1417 * Let's take these a step at a time
1420 * Pages allocated from the kernel may still have
1421 * cache contents, so we set them to (CPU, CPU) always.
1422 * 2. Written by CPU (using pwrite)
1423 * The pwrite function calls set_domain (CPU, CPU) and
1424 * this function does nothing (as nothing changes)
1426 * This function asserts that the object is not
1427 * currently in any GPU-based read or write domains
1429 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
1430 * As write_domain is zero, this function adds in the
1431 * current read domains (CPU+COMMAND, 0).
1432 * flush_domains is set to CPU.
1433 * invalidate_domains is set to COMMAND
1434 * clflush is run to get data out of the CPU caches
1435 * then i915_dev_set_domain calls i915_gem_flush to
1436 * emit an MI_FLUSH and drm_agp_chipset_flush
1437 * 5. Unmapped from GTT
1438 * i915_gem_object_unbind calls set_domain (CPU, CPU)
1439 * flush_domains and invalidate_domains end up both zero
1440 * so no flushing/invalidating happens
1444 * Case 2: The shared render buffer
1448 * 3. Read/written by GPU
1449 * 4. set_domain to (CPU,CPU)
1450 * 5. Read/written by CPU
1451 * 6. Read/written by GPU
1454 * Same as last example, (CPU, CPU)
1456 * Nothing changes (assertions find that it is not in the GPU)
1457 * 3. Read/written by GPU
1458 * execbuffer calls set_domain (RENDER, RENDER)
1459 * flush_domains gets CPU
1460 * invalidate_domains gets GPU
1462 * MI_FLUSH and drm_agp_chipset_flush
1463 * 4. set_domain (CPU, CPU)
1464 * flush_domains gets GPU
1465 * invalidate_domains gets CPU
1466 * wait_rendering (obj) to make sure all drawing is complete.
1467 * This will include an MI_FLUSH to get the data from GPU
1469 * clflush (obj) to invalidate the CPU cache
1470 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1471 * 5. Read/written by CPU
1472 * cache lines are loaded and dirtied
1473 * 6. Read written by GPU
1474 * Same as last GPU access
1476 * Case 3: The constant buffer
1481 * 4. Updated (written) by CPU again
1490 * flush_domains = CPU
1491 * invalidate_domains = RENDER
1494 * drm_agp_chipset_flush
1495 * 4. Updated (written) by CPU again
1497 * flush_domains = 0 (no previous write domain)
1498 * invalidate_domains = 0 (no new read domains)
1501 * flush_domains = CPU
1502 * invalidate_domains = RENDER
1505 * drm_agp_chipset_flush
1508 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
,
1509 uint32_t read_domains
,
1510 uint32_t write_domain
)
1512 struct drm_device
*dev
= obj
->dev
;
1513 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1514 uint32_t invalidate_domains
= 0;
1515 uint32_t flush_domains
= 0;
1517 BUG_ON(read_domains
& I915_GEM_DOMAIN_CPU
);
1518 BUG_ON(write_domain
== I915_GEM_DOMAIN_CPU
);
1521 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
1523 obj
->read_domains
, read_domains
,
1524 obj
->write_domain
, write_domain
);
1527 * If the object isn't moving to a new write domain,
1528 * let the object stay in multiple read domains
1530 if (write_domain
== 0)
1531 read_domains
|= obj
->read_domains
;
1533 obj_priv
->dirty
= 1;
1536 * Flush the current write domain if
1537 * the new read domains don't match. Invalidate
1538 * any read domains which differ from the old
1541 if (obj
->write_domain
&& obj
->write_domain
!= read_domains
) {
1542 flush_domains
|= obj
->write_domain
;
1543 invalidate_domains
|= read_domains
& ~obj
->write_domain
;
1546 * Invalidate any read caches which may have
1547 * stale data. That is, any new read domains.
1549 invalidate_domains
|= read_domains
& ~obj
->read_domains
;
1550 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
1552 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
1553 __func__
, flush_domains
, invalidate_domains
);
1555 i915_gem_clflush_object(obj
);
1558 if ((write_domain
| flush_domains
) != 0)
1559 obj
->write_domain
= write_domain
;
1560 obj
->read_domains
= read_domains
;
1562 dev
->invalidate_domains
|= invalidate_domains
;
1563 dev
->flush_domains
|= flush_domains
;
1565 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
1567 obj
->read_domains
, obj
->write_domain
,
1568 dev
->invalidate_domains
, dev
->flush_domains
);
1573 * Moves the object from a partially CPU read to a full one.
1575 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
1576 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
1579 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
1581 struct drm_device
*dev
= obj
->dev
;
1582 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1584 if (!obj_priv
->page_cpu_valid
)
1587 /* If we're partially in the CPU read domain, finish moving it in.
1589 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
1592 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
1593 if (obj_priv
->page_cpu_valid
[i
])
1595 drm_clflush_pages(obj_priv
->page_list
+ i
, 1);
1597 drm_agp_chipset_flush(dev
);
1600 /* Free the page_cpu_valid mappings which are now stale, whether
1601 * or not we've got I915_GEM_DOMAIN_CPU.
1603 drm_free(obj_priv
->page_cpu_valid
, obj
->size
/ PAGE_SIZE
,
1605 obj_priv
->page_cpu_valid
= NULL
;
1609 * Set the CPU read domain on a range of the object.
1611 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
1612 * not entirely valid. The page_cpu_valid member of the object flags which
1613 * pages have been flushed, and will be respected by
1614 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
1615 * of the whole object.
1617 * This function returns when the move is complete, including waiting on
1621 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
1622 uint64_t offset
, uint64_t size
)
1624 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1627 if (offset
== 0 && size
== obj
->size
)
1628 return i915_gem_object_set_to_cpu_domain(obj
, 0);
1630 i915_gem_object_flush_gpu_write_domain(obj
);
1631 /* Wait on any GPU rendering and flushing to occur. */
1632 ret
= i915_gem_object_wait_rendering(obj
);
1635 i915_gem_object_flush_gtt_write_domain(obj
);
1637 /* If we're already fully in the CPU read domain, we're done. */
1638 if (obj_priv
->page_cpu_valid
== NULL
&&
1639 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
1642 /* Otherwise, create/clear the per-page CPU read domain flag if we're
1643 * newly adding I915_GEM_DOMAIN_CPU
1645 if (obj_priv
->page_cpu_valid
== NULL
) {
1646 obj_priv
->page_cpu_valid
= drm_calloc(1, obj
->size
/ PAGE_SIZE
,
1648 if (obj_priv
->page_cpu_valid
== NULL
)
1650 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
1651 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
1653 /* Flush the cache on any pages that are still invalid from the CPU's
1656 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
1658 if (obj_priv
->page_cpu_valid
[i
])
1661 drm_clflush_pages(obj_priv
->page_list
+ i
, 1);
1663 obj_priv
->page_cpu_valid
[i
] = 1;
1666 /* It should now be out of any other write domains, and we can update
1667 * the domain values for our changes.
1669 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
1671 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
1677 * Pin an object to the GTT and evaluate the relocations landing in it.
1680 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
1681 struct drm_file
*file_priv
,
1682 struct drm_i915_gem_exec_object
*entry
)
1684 struct drm_device
*dev
= obj
->dev
;
1685 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1686 struct drm_i915_gem_relocation_entry reloc
;
1687 struct drm_i915_gem_relocation_entry __user
*relocs
;
1688 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1690 void __iomem
*reloc_page
;
1692 /* Choose the GTT offset for our buffer and put it there. */
1693 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
1697 entry
->offset
= obj_priv
->gtt_offset
;
1699 relocs
= (struct drm_i915_gem_relocation_entry __user
*)
1700 (uintptr_t) entry
->relocs_ptr
;
1701 /* Apply the relocations, using the GTT aperture to avoid cache
1702 * flushing requirements.
1704 for (i
= 0; i
< entry
->relocation_count
; i
++) {
1705 struct drm_gem_object
*target_obj
;
1706 struct drm_i915_gem_object
*target_obj_priv
;
1707 uint32_t reloc_val
, reloc_offset
;
1708 uint32_t __iomem
*reloc_entry
;
1710 ret
= copy_from_user(&reloc
, relocs
+ i
, sizeof(reloc
));
1712 i915_gem_object_unpin(obj
);
1716 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
1717 reloc
.target_handle
);
1718 if (target_obj
== NULL
) {
1719 i915_gem_object_unpin(obj
);
1722 target_obj_priv
= target_obj
->driver_private
;
1724 /* The target buffer should have appeared before us in the
1725 * exec_object list, so it should have a GTT space bound by now.
1727 if (target_obj_priv
->gtt_space
== NULL
) {
1728 DRM_ERROR("No GTT space found for object %d\n",
1729 reloc
.target_handle
);
1730 drm_gem_object_unreference(target_obj
);
1731 i915_gem_object_unpin(obj
);
1735 if (reloc
.offset
> obj
->size
- 4) {
1736 DRM_ERROR("Relocation beyond object bounds: "
1737 "obj %p target %d offset %d size %d.\n",
1738 obj
, reloc
.target_handle
,
1739 (int) reloc
.offset
, (int) obj
->size
);
1740 drm_gem_object_unreference(target_obj
);
1741 i915_gem_object_unpin(obj
);
1744 if (reloc
.offset
& 3) {
1745 DRM_ERROR("Relocation not 4-byte aligned: "
1746 "obj %p target %d offset %d.\n",
1747 obj
, reloc
.target_handle
,
1748 (int) reloc
.offset
);
1749 drm_gem_object_unreference(target_obj
);
1750 i915_gem_object_unpin(obj
);
1754 if (reloc
.write_domain
& I915_GEM_DOMAIN_CPU
||
1755 reloc
.read_domains
& I915_GEM_DOMAIN_CPU
) {
1756 DRM_ERROR("reloc with read/write CPU domains: "
1757 "obj %p target %d offset %d "
1758 "read %08x write %08x",
1759 obj
, reloc
.target_handle
,
1762 reloc
.write_domain
);
1766 if (reloc
.write_domain
&& target_obj
->pending_write_domain
&&
1767 reloc
.write_domain
!= target_obj
->pending_write_domain
) {
1768 DRM_ERROR("Write domain conflict: "
1769 "obj %p target %d offset %d "
1770 "new %08x old %08x\n",
1771 obj
, reloc
.target_handle
,
1774 target_obj
->pending_write_domain
);
1775 drm_gem_object_unreference(target_obj
);
1776 i915_gem_object_unpin(obj
);
1781 DRM_INFO("%s: obj %p offset %08x target %d "
1782 "read %08x write %08x gtt %08x "
1783 "presumed %08x delta %08x\n",
1787 (int) reloc
.target_handle
,
1788 (int) reloc
.read_domains
,
1789 (int) reloc
.write_domain
,
1790 (int) target_obj_priv
->gtt_offset
,
1791 (int) reloc
.presumed_offset
,
1795 target_obj
->pending_read_domains
|= reloc
.read_domains
;
1796 target_obj
->pending_write_domain
|= reloc
.write_domain
;
1798 /* If the relocation already has the right value in it, no
1799 * more work needs to be done.
1801 if (target_obj_priv
->gtt_offset
== reloc
.presumed_offset
) {
1802 drm_gem_object_unreference(target_obj
);
1806 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
1808 drm_gem_object_unreference(target_obj
);
1809 i915_gem_object_unpin(obj
);
1813 /* Map the page containing the relocation we're going to
1816 reloc_offset
= obj_priv
->gtt_offset
+ reloc
.offset
;
1817 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
1820 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
1821 (reloc_offset
& (PAGE_SIZE
- 1)));
1822 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
.delta
;
1825 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
1826 obj
, (unsigned int) reloc
.offset
,
1827 readl(reloc_entry
), reloc_val
);
1829 writel(reloc_val
, reloc_entry
);
1830 io_mapping_unmap_atomic(reloc_page
);
1832 /* Write the updated presumed offset for this entry back out
1835 reloc
.presumed_offset
= target_obj_priv
->gtt_offset
;
1836 ret
= copy_to_user(relocs
+ i
, &reloc
, sizeof(reloc
));
1838 drm_gem_object_unreference(target_obj
);
1839 i915_gem_object_unpin(obj
);
1843 drm_gem_object_unreference(target_obj
);
1848 i915_gem_dump_object(obj
, 128, __func__
, ~0);
1853 /** Dispatch a batchbuffer to the ring
1856 i915_dispatch_gem_execbuffer(struct drm_device
*dev
,
1857 struct drm_i915_gem_execbuffer
*exec
,
1858 uint64_t exec_offset
)
1860 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1861 struct drm_clip_rect __user
*boxes
= (struct drm_clip_rect __user
*)
1862 (uintptr_t) exec
->cliprects_ptr
;
1863 int nbox
= exec
->num_cliprects
;
1865 uint32_t exec_start
, exec_len
;
1868 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
1869 exec_len
= (uint32_t) exec
->batch_len
;
1871 if ((exec_start
| exec_len
) & 0x7) {
1872 DRM_ERROR("alignment\n");
1879 count
= nbox
? nbox
: 1;
1881 for (i
= 0; i
< count
; i
++) {
1883 int ret
= i915_emit_box(dev
, boxes
, i
,
1884 exec
->DR1
, exec
->DR4
);
1889 if (IS_I830(dev
) || IS_845G(dev
)) {
1891 OUT_RING(MI_BATCH_BUFFER
);
1892 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
1893 OUT_RING(exec_start
+ exec_len
- 4);
1898 if (IS_I965G(dev
)) {
1899 OUT_RING(MI_BATCH_BUFFER_START
|
1901 MI_BATCH_NON_SECURE_I965
);
1902 OUT_RING(exec_start
);
1904 OUT_RING(MI_BATCH_BUFFER_START
|
1906 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
1912 /* XXX breadcrumb */
1916 /* Throttle our rendering by waiting until the ring has completed our requests
1917 * emitted over 20 msec ago.
1919 * This should get us reasonable parallelism between CPU and GPU but also
1920 * relatively low latency when blocking on a particular request to finish.
1923 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
1925 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
1929 mutex_lock(&dev
->struct_mutex
);
1930 seqno
= i915_file_priv
->mm
.last_gem_throttle_seqno
;
1931 i915_file_priv
->mm
.last_gem_throttle_seqno
=
1932 i915_file_priv
->mm
.last_gem_seqno
;
1934 ret
= i915_wait_request(dev
, seqno
);
1935 mutex_unlock(&dev
->struct_mutex
);
1940 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1941 struct drm_file
*file_priv
)
1943 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1944 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
1945 struct drm_i915_gem_execbuffer
*args
= data
;
1946 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
1947 struct drm_gem_object
**object_list
= NULL
;
1948 struct drm_gem_object
*batch_obj
;
1949 int ret
, i
, pinned
= 0;
1950 uint64_t exec_offset
;
1951 uint32_t seqno
, flush_domains
;
1955 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1956 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
1959 if (args
->buffer_count
< 1) {
1960 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
1963 /* Copy in the exec list from userland */
1964 exec_list
= drm_calloc(sizeof(*exec_list
), args
->buffer_count
,
1966 object_list
= drm_calloc(sizeof(*object_list
), args
->buffer_count
,
1968 if (exec_list
== NULL
|| object_list
== NULL
) {
1969 DRM_ERROR("Failed to allocate exec or object list "
1971 args
->buffer_count
);
1975 ret
= copy_from_user(exec_list
,
1976 (struct drm_i915_relocation_entry __user
*)
1977 (uintptr_t) args
->buffers_ptr
,
1978 sizeof(*exec_list
) * args
->buffer_count
);
1980 DRM_ERROR("copy %d exec entries failed %d\n",
1981 args
->buffer_count
, ret
);
1985 mutex_lock(&dev
->struct_mutex
);
1987 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1989 if (dev_priv
->mm
.wedged
) {
1990 DRM_ERROR("Execbuf while wedged\n");
1991 mutex_unlock(&dev
->struct_mutex
);
1995 if (dev_priv
->mm
.suspended
) {
1996 DRM_ERROR("Execbuf while VT-switched.\n");
1997 mutex_unlock(&dev
->struct_mutex
);
2001 /* Look up object handles */
2002 for (i
= 0; i
< args
->buffer_count
; i
++) {
2003 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
2004 exec_list
[i
].handle
);
2005 if (object_list
[i
] == NULL
) {
2006 DRM_ERROR("Invalid object handle %d at index %d\n",
2007 exec_list
[i
].handle
, i
);
2013 /* Pin and relocate */
2014 for (pin_tries
= 0; ; pin_tries
++) {
2016 for (i
= 0; i
< args
->buffer_count
; i
++) {
2017 object_list
[i
]->pending_read_domains
= 0;
2018 object_list
[i
]->pending_write_domain
= 0;
2019 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
2030 /* error other than GTT full, or we've already tried again */
2031 if (ret
!= -ENOMEM
|| pin_tries
>= 1) {
2032 DRM_ERROR("Failed to pin buffers %d\n", ret
);
2036 /* unpin all of our buffers */
2037 for (i
= 0; i
< pinned
; i
++)
2038 i915_gem_object_unpin(object_list
[i
]);
2040 /* evict everyone we can from the aperture */
2041 ret
= i915_gem_evict_everything(dev
);
2046 /* Set the pending read domains for the batch buffer to COMMAND */
2047 batch_obj
= object_list
[args
->buffer_count
-1];
2048 batch_obj
->pending_read_domains
= I915_GEM_DOMAIN_COMMAND
;
2049 batch_obj
->pending_write_domain
= 0;
2051 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2053 /* Zero the global flush/invalidate flags. These
2054 * will be modified as new domains are computed
2057 dev
->invalidate_domains
= 0;
2058 dev
->flush_domains
= 0;
2060 for (i
= 0; i
< args
->buffer_count
; i
++) {
2061 struct drm_gem_object
*obj
= object_list
[i
];
2063 /* Compute new gpu domains and update invalidate/flush */
2064 i915_gem_object_set_to_gpu_domain(obj
,
2065 obj
->pending_read_domains
,
2066 obj
->pending_write_domain
);
2069 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2071 if (dev
->invalidate_domains
| dev
->flush_domains
) {
2073 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
2075 dev
->invalidate_domains
,
2076 dev
->flush_domains
);
2079 dev
->invalidate_domains
,
2080 dev
->flush_domains
);
2081 if (dev
->flush_domains
)
2082 (void)i915_add_request(dev
, dev
->flush_domains
);
2085 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2088 for (i
= 0; i
< args
->buffer_count
; i
++) {
2089 i915_gem_object_check_coherency(object_list
[i
],
2090 exec_list
[i
].handle
);
2094 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
2097 i915_gem_dump_object(object_list
[args
->buffer_count
- 1],
2103 /* Exec the batchbuffer */
2104 ret
= i915_dispatch_gem_execbuffer(dev
, args
, exec_offset
);
2106 DRM_ERROR("dispatch failed %d\n", ret
);
2111 * Ensure that the commands in the batch buffer are
2112 * finished before the interrupt fires
2114 flush_domains
= i915_retire_commands(dev
);
2116 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2119 * Get a seqno representing the execution of the current buffer,
2120 * which we can wait on. We would like to mitigate these interrupts,
2121 * likely by only creating seqnos occasionally (so that we have
2122 * *some* interrupts representing completion of buffers that we can
2123 * wait on when trying to clear up gtt space).
2125 seqno
= i915_add_request(dev
, flush_domains
);
2127 i915_file_priv
->mm
.last_gem_seqno
= seqno
;
2128 for (i
= 0; i
< args
->buffer_count
; i
++) {
2129 struct drm_gem_object
*obj
= object_list
[i
];
2131 i915_gem_object_move_to_active(obj
, seqno
);
2133 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
2137 i915_dump_lru(dev
, __func__
);
2140 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2142 /* Copy the new buffer offsets back to the user's exec list. */
2143 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
2144 (uintptr_t) args
->buffers_ptr
,
2146 sizeof(*exec_list
) * args
->buffer_count
);
2148 DRM_ERROR("failed to copy %d exec entries "
2149 "back to user (%d)\n",
2150 args
->buffer_count
, ret
);
2152 if (object_list
!= NULL
) {
2153 for (i
= 0; i
< pinned
; i
++)
2154 i915_gem_object_unpin(object_list
[i
]);
2156 for (i
= 0; i
< args
->buffer_count
; i
++)
2157 drm_gem_object_unreference(object_list
[i
]);
2159 mutex_unlock(&dev
->struct_mutex
);
2162 drm_free(object_list
, sizeof(*object_list
) * args
->buffer_count
,
2164 drm_free(exec_list
, sizeof(*exec_list
) * args
->buffer_count
,
2171 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
2173 struct drm_device
*dev
= obj
->dev
;
2174 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2177 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2178 if (obj_priv
->gtt_space
== NULL
) {
2179 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
2181 DRM_ERROR("Failure to bind: %d", ret
);
2185 obj_priv
->pin_count
++;
2187 /* If the object is not active and not pending a flush,
2188 * remove it from the inactive list
2190 if (obj_priv
->pin_count
== 1) {
2191 atomic_inc(&dev
->pin_count
);
2192 atomic_add(obj
->size
, &dev
->pin_memory
);
2193 if (!obj_priv
->active
&&
2194 (obj
->write_domain
& ~(I915_GEM_DOMAIN_CPU
|
2195 I915_GEM_DOMAIN_GTT
)) == 0 &&
2196 !list_empty(&obj_priv
->list
))
2197 list_del_init(&obj_priv
->list
);
2199 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2205 i915_gem_object_unpin(struct drm_gem_object
*obj
)
2207 struct drm_device
*dev
= obj
->dev
;
2208 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2209 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2211 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2212 obj_priv
->pin_count
--;
2213 BUG_ON(obj_priv
->pin_count
< 0);
2214 BUG_ON(obj_priv
->gtt_space
== NULL
);
2216 /* If the object is no longer pinned, and is
2217 * neither active nor being flushed, then stick it on
2220 if (obj_priv
->pin_count
== 0) {
2221 if (!obj_priv
->active
&&
2222 (obj
->write_domain
& ~(I915_GEM_DOMAIN_CPU
|
2223 I915_GEM_DOMAIN_GTT
)) == 0)
2224 list_move_tail(&obj_priv
->list
,
2225 &dev_priv
->mm
.inactive_list
);
2226 atomic_dec(&dev
->pin_count
);
2227 atomic_sub(obj
->size
, &dev
->pin_memory
);
2229 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2233 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2234 struct drm_file
*file_priv
)
2236 struct drm_i915_gem_pin
*args
= data
;
2237 struct drm_gem_object
*obj
;
2238 struct drm_i915_gem_object
*obj_priv
;
2241 mutex_lock(&dev
->struct_mutex
);
2243 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
2245 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2247 mutex_unlock(&dev
->struct_mutex
);
2250 obj_priv
= obj
->driver_private
;
2252 ret
= i915_gem_object_pin(obj
, args
->alignment
);
2254 drm_gem_object_unreference(obj
);
2255 mutex_unlock(&dev
->struct_mutex
);
2259 /* XXX - flush the CPU caches for pinned objects
2260 * as the X server doesn't manage domains yet
2262 i915_gem_object_flush_cpu_write_domain(obj
);
2263 args
->offset
= obj_priv
->gtt_offset
;
2264 drm_gem_object_unreference(obj
);
2265 mutex_unlock(&dev
->struct_mutex
);
2271 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2272 struct drm_file
*file_priv
)
2274 struct drm_i915_gem_pin
*args
= data
;
2275 struct drm_gem_object
*obj
;
2277 mutex_lock(&dev
->struct_mutex
);
2279 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
2281 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2283 mutex_unlock(&dev
->struct_mutex
);
2287 i915_gem_object_unpin(obj
);
2289 drm_gem_object_unreference(obj
);
2290 mutex_unlock(&dev
->struct_mutex
);
2295 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2296 struct drm_file
*file_priv
)
2298 struct drm_i915_gem_busy
*args
= data
;
2299 struct drm_gem_object
*obj
;
2300 struct drm_i915_gem_object
*obj_priv
;
2302 mutex_lock(&dev
->struct_mutex
);
2303 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
2305 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2307 mutex_unlock(&dev
->struct_mutex
);
2311 obj_priv
= obj
->driver_private
;
2312 args
->busy
= obj_priv
->active
;
2314 drm_gem_object_unreference(obj
);
2315 mutex_unlock(&dev
->struct_mutex
);
2320 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2321 struct drm_file
*file_priv
)
2323 return i915_gem_ring_throttle(dev
, file_priv
);
2326 int i915_gem_init_object(struct drm_gem_object
*obj
)
2328 struct drm_i915_gem_object
*obj_priv
;
2330 obj_priv
= drm_calloc(1, sizeof(*obj_priv
), DRM_MEM_DRIVER
);
2331 if (obj_priv
== NULL
)
2335 * We've just allocated pages from the kernel,
2336 * so they've just been written by the CPU with
2337 * zeros. They'll need to be clflushed before we
2338 * use them with the GPU.
2340 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2341 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
2343 obj_priv
->agp_type
= AGP_USER_MEMORY
;
2345 obj
->driver_private
= obj_priv
;
2346 obj_priv
->obj
= obj
;
2347 INIT_LIST_HEAD(&obj_priv
->list
);
2351 void i915_gem_free_object(struct drm_gem_object
*obj
)
2353 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2355 while (obj_priv
->pin_count
> 0)
2356 i915_gem_object_unpin(obj
);
2358 i915_gem_object_unbind(obj
);
2360 drm_free(obj_priv
->page_cpu_valid
, 1, DRM_MEM_DRIVER
);
2361 drm_free(obj
->driver_private
, 1, DRM_MEM_DRIVER
);
2364 /** Unbinds all objects that are on the given buffer list. */
2366 i915_gem_evict_from_list(struct drm_device
*dev
, struct list_head
*head
)
2368 struct drm_gem_object
*obj
;
2369 struct drm_i915_gem_object
*obj_priv
;
2372 while (!list_empty(head
)) {
2373 obj_priv
= list_first_entry(head
,
2374 struct drm_i915_gem_object
,
2376 obj
= obj_priv
->obj
;
2378 if (obj_priv
->pin_count
!= 0) {
2379 DRM_ERROR("Pinned object in unbind list\n");
2380 mutex_unlock(&dev
->struct_mutex
);
2384 ret
= i915_gem_object_unbind(obj
);
2386 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2388 mutex_unlock(&dev
->struct_mutex
);
2398 i915_gem_idle(struct drm_device
*dev
)
2400 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2401 uint32_t seqno
, cur_seqno
, last_seqno
;
2404 mutex_lock(&dev
->struct_mutex
);
2406 if (dev_priv
->mm
.suspended
|| dev_priv
->ring
.ring_obj
== NULL
) {
2407 mutex_unlock(&dev
->struct_mutex
);
2411 /* Hack! Don't let anybody do execbuf while we don't control the chip.
2412 * We need to replace this with a semaphore, or something.
2414 dev_priv
->mm
.suspended
= 1;
2416 /* Cancel the retire work handler, wait for it to finish if running
2418 mutex_unlock(&dev
->struct_mutex
);
2419 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
2420 mutex_lock(&dev
->struct_mutex
);
2422 i915_kernel_lost_context(dev
);
2424 /* Flush the GPU along with all non-CPU write domains
2426 i915_gem_flush(dev
, ~(I915_GEM_DOMAIN_CPU
|I915_GEM_DOMAIN_GTT
),
2427 ~(I915_GEM_DOMAIN_CPU
|I915_GEM_DOMAIN_GTT
));
2428 seqno
= i915_add_request(dev
, ~(I915_GEM_DOMAIN_CPU
|
2429 I915_GEM_DOMAIN_GTT
));
2432 mutex_unlock(&dev
->struct_mutex
);
2436 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
2440 cur_seqno
= i915_get_gem_seqno(dev
);
2441 if (i915_seqno_passed(cur_seqno
, seqno
))
2443 if (last_seqno
== cur_seqno
) {
2444 if (stuck
++ > 100) {
2445 DRM_ERROR("hardware wedged\n");
2446 dev_priv
->mm
.wedged
= 1;
2447 DRM_WAKEUP(&dev_priv
->irq_queue
);
2452 last_seqno
= cur_seqno
;
2454 dev_priv
->mm
.waiting_gem_seqno
= 0;
2456 i915_gem_retire_requests(dev
);
2458 if (!dev_priv
->mm
.wedged
) {
2459 /* Active and flushing should now be empty as we've
2460 * waited for a sequence higher than any pending execbuffer
2462 WARN_ON(!list_empty(&dev_priv
->mm
.active_list
));
2463 WARN_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
2464 /* Request should now be empty as we've also waited
2465 * for the last request in the list
2467 WARN_ON(!list_empty(&dev_priv
->mm
.request_list
));
2470 /* Empty the active and flushing lists to inactive. If there's
2471 * anything left at this point, it means that we're wedged and
2472 * nothing good's going to happen by leaving them there. So strip
2473 * the GPU domains and just stuff them onto inactive.
2475 while (!list_empty(&dev_priv
->mm
.active_list
)) {
2476 struct drm_i915_gem_object
*obj_priv
;
2478 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
2479 struct drm_i915_gem_object
,
2481 obj_priv
->obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
2482 i915_gem_object_move_to_inactive(obj_priv
->obj
);
2485 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
2486 struct drm_i915_gem_object
*obj_priv
;
2488 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
2489 struct drm_i915_gem_object
,
2491 obj_priv
->obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
2492 i915_gem_object_move_to_inactive(obj_priv
->obj
);
2496 /* Move all inactive buffers out of the GTT. */
2497 ret
= i915_gem_evict_from_list(dev
, &dev_priv
->mm
.inactive_list
);
2498 WARN_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
2500 mutex_unlock(&dev
->struct_mutex
);
2504 i915_gem_cleanup_ringbuffer(dev
);
2505 mutex_unlock(&dev
->struct_mutex
);
2511 i915_gem_init_hws(struct drm_device
*dev
)
2513 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2514 struct drm_gem_object
*obj
;
2515 struct drm_i915_gem_object
*obj_priv
;
2518 /* If we need a physical address for the status page, it's already
2519 * initialized at driver load time.
2521 if (!I915_NEED_GFX_HWS(dev
))
2524 obj
= drm_gem_object_alloc(dev
, 4096);
2526 DRM_ERROR("Failed to allocate status page\n");
2529 obj_priv
= obj
->driver_private
;
2530 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
2532 ret
= i915_gem_object_pin(obj
, 4096);
2534 drm_gem_object_unreference(obj
);
2538 dev_priv
->status_gfx_addr
= obj_priv
->gtt_offset
;
2540 dev_priv
->hw_status_page
= kmap(obj_priv
->page_list
[0]);
2541 if (dev_priv
->hw_status_page
== NULL
) {
2542 DRM_ERROR("Failed to map status page.\n");
2543 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
2544 drm_gem_object_unreference(obj
);
2547 dev_priv
->hws_obj
= obj
;
2548 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
2549 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
2550 I915_READ(HWS_PGA
); /* posting read */
2551 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv
->status_gfx_addr
);
2557 i915_gem_init_ringbuffer(struct drm_device
*dev
)
2559 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2560 struct drm_gem_object
*obj
;
2561 struct drm_i915_gem_object
*obj_priv
;
2565 ret
= i915_gem_init_hws(dev
);
2569 obj
= drm_gem_object_alloc(dev
, 128 * 1024);
2571 DRM_ERROR("Failed to allocate ringbuffer\n");
2574 obj_priv
= obj
->driver_private
;
2576 ret
= i915_gem_object_pin(obj
, 4096);
2578 drm_gem_object_unreference(obj
);
2582 /* Set up the kernel mapping for the ring. */
2583 dev_priv
->ring
.Size
= obj
->size
;
2584 dev_priv
->ring
.tail_mask
= obj
->size
- 1;
2586 dev_priv
->ring
.map
.offset
= dev
->agp
->base
+ obj_priv
->gtt_offset
;
2587 dev_priv
->ring
.map
.size
= obj
->size
;
2588 dev_priv
->ring
.map
.type
= 0;
2589 dev_priv
->ring
.map
.flags
= 0;
2590 dev_priv
->ring
.map
.mtrr
= 0;
2592 drm_core_ioremap_wc(&dev_priv
->ring
.map
, dev
);
2593 if (dev_priv
->ring
.map
.handle
== NULL
) {
2594 DRM_ERROR("Failed to map ringbuffer.\n");
2595 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
2596 drm_gem_object_unreference(obj
);
2599 dev_priv
->ring
.ring_obj
= obj
;
2600 dev_priv
->ring
.virtual_start
= dev_priv
->ring
.map
.handle
;
2602 /* Stop the ring if it's running. */
2603 I915_WRITE(PRB0_CTL
, 0);
2604 I915_WRITE(PRB0_TAIL
, 0);
2605 I915_WRITE(PRB0_HEAD
, 0);
2607 /* Initialize the ring. */
2608 I915_WRITE(PRB0_START
, obj_priv
->gtt_offset
);
2609 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
2611 /* G45 ring initialization fails to reset head to zero */
2613 DRM_ERROR("Ring head not reset to zero "
2614 "ctl %08x head %08x tail %08x start %08x\n",
2615 I915_READ(PRB0_CTL
),
2616 I915_READ(PRB0_HEAD
),
2617 I915_READ(PRB0_TAIL
),
2618 I915_READ(PRB0_START
));
2619 I915_WRITE(PRB0_HEAD
, 0);
2621 DRM_ERROR("Ring head forced to zero "
2622 "ctl %08x head %08x tail %08x start %08x\n",
2623 I915_READ(PRB0_CTL
),
2624 I915_READ(PRB0_HEAD
),
2625 I915_READ(PRB0_TAIL
),
2626 I915_READ(PRB0_START
));
2629 I915_WRITE(PRB0_CTL
,
2630 ((obj
->size
- 4096) & RING_NR_PAGES
) |
2634 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
2636 /* If the head is still not zero, the ring is dead */
2638 DRM_ERROR("Ring initialization failed "
2639 "ctl %08x head %08x tail %08x start %08x\n",
2640 I915_READ(PRB0_CTL
),
2641 I915_READ(PRB0_HEAD
),
2642 I915_READ(PRB0_TAIL
),
2643 I915_READ(PRB0_START
));
2647 /* Update our cache of the ring state */
2648 i915_kernel_lost_context(dev
);
2654 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
2656 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2658 if (dev_priv
->ring
.ring_obj
== NULL
)
2661 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
2663 i915_gem_object_unpin(dev_priv
->ring
.ring_obj
);
2664 drm_gem_object_unreference(dev_priv
->ring
.ring_obj
);
2665 dev_priv
->ring
.ring_obj
= NULL
;
2666 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
2668 if (dev_priv
->hws_obj
!= NULL
) {
2669 struct drm_gem_object
*obj
= dev_priv
->hws_obj
;
2670 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2672 kunmap(obj_priv
->page_list
[0]);
2673 i915_gem_object_unpin(obj
);
2674 drm_gem_object_unreference(obj
);
2675 dev_priv
->hws_obj
= NULL
;
2676 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
2677 dev_priv
->hw_status_page
= NULL
;
2679 /* Write high address into HWS_PGA when disabling. */
2680 I915_WRITE(HWS_PGA
, 0x1ffff000);
2685 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
2686 struct drm_file
*file_priv
)
2688 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2691 if (dev_priv
->mm
.wedged
) {
2692 DRM_ERROR("Reenabling wedged hardware, good luck\n");
2693 dev_priv
->mm
.wedged
= 0;
2696 ret
= i915_gem_init_ringbuffer(dev
);
2700 dev_priv
->mm
.gtt_mapping
= io_mapping_create_wc(dev
->agp
->base
,
2701 dev
->agp
->agp_info
.aper_size
2704 mutex_lock(&dev
->struct_mutex
);
2705 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
2706 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
2707 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
2708 BUG_ON(!list_empty(&dev_priv
->mm
.request_list
));
2709 dev_priv
->mm
.suspended
= 0;
2710 mutex_unlock(&dev
->struct_mutex
);
2712 drm_irq_install(dev
);
2718 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
2719 struct drm_file
*file_priv
)
2721 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2724 ret
= i915_gem_idle(dev
);
2725 drm_irq_uninstall(dev
);
2727 io_mapping_free(dev_priv
->mm
.gtt_mapping
);
2732 i915_gem_lastclose(struct drm_device
*dev
)
2736 ret
= i915_gem_idle(dev
);
2738 DRM_ERROR("failed to idle hardware: %d\n", ret
);
2742 i915_gem_load(struct drm_device
*dev
)
2744 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2746 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
2747 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
2748 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
2749 INIT_LIST_HEAD(&dev_priv
->mm
.request_list
);
2750 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
2751 i915_gem_retire_work_handler
);
2752 dev_priv
->mm
.next_gem_seqno
= 1;
2754 i915_gem_detect_bit_6_swizzle(dev
);