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bzip2/lzma: quiet Kconfig warning for INITRAMFS_COMPRESSION_NONE
[linux-2.6/linux-2.6-openrd.git] / drivers / ide / scc_pata.c
blob0cc137cfe76d57f60577de9a8043ea29cb475d31
1 /*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ide/pci/siimage.c:
7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2003 Red Hat
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/init.h>
31
32 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
33
34 #define SCC_PATA_NAME "scc IDE"
35
36 #define TDVHSEL_MASTER 0x00000001
37 #define TDVHSEL_SLAVE 0x00000004
38
39 #define MODE_JCUSFEN 0x00000080
40
41 #define CCKCTRL_ATARESET 0x00040000
42 #define CCKCTRL_BUFCNT 0x00020000
43 #define CCKCTRL_CRST 0x00010000
44 #define CCKCTRL_OCLKEN 0x00000100
45 #define CCKCTRL_ATACLKOEN 0x00000002
46 #define CCKCTRL_LCLKEN 0x00000001
47
48 #define QCHCD_IOS_SS 0x00000001
49
50 #define QCHSD_STPDIAG 0x00020000
51
52 #define INTMASK_MSK 0xD1000012
53 #define INTSTS_SERROR 0x80000000
54 #define INTSTS_PRERR 0x40000000
55 #define INTSTS_RERR 0x10000000
56 #define INTSTS_ICERR 0x01000000
57 #define INTSTS_BMSINT 0x00000010
58 #define INTSTS_BMHE 0x00000008
59 #define INTSTS_IOIRQS 0x00000004
60 #define INTSTS_INTRQ 0x00000002
61 #define INTSTS_ACTEINT 0x00000001
62
63 #define ECMODE_VALUE 0x01
64
65 static struct scc_ports {
66 unsigned long ctl, dma;
67 struct ide_host *host; /* for removing port from system */
68 } scc_ports[MAX_HWIFS];
69
70 /* PIO transfer mode table */
71 /* JCHST */
72 static unsigned long JCHSTtbl[2][7] = {
73 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
74 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
75 };
76
77 /* JCHHT */
78 static unsigned long JCHHTtbl[2][7] = {
79 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
80 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
81 };
82
83 /* JCHCT */
84 static unsigned long JCHCTtbl[2][7] = {
85 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
86 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
87 };
88
89
90 /* DMA transfer mode table */
91 /* JCHDCTM/JCHDCTS */
92 static unsigned long JCHDCTxtbl[2][7] = {
93 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
94 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
95 };
96
97 /* JCSTWTM/JCSTWTS */
98 static unsigned long JCSTWTxtbl[2][7] = {
99 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
100 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
101 };
102
103 /* JCTSS */
104 static unsigned long JCTSStbl[2][7] = {
105 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
107 };
108
109 /* JCENVT */
110 static unsigned long JCENVTtbl[2][7] = {
111 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
112 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
113 };
114
115 /* JCACTSELS/JCACTSELM */
116 static unsigned long JCACTSELtbl[2][7] = {
117 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
118 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
119 };
120
121
122 static u8 scc_ide_inb(unsigned long port)
123 {
124 u32 data = in_be32((void*)port);
125 return (u8)data;
126 }
127
128 static void scc_exec_command(ide_hwif_t *hwif, u8 cmd)
129 {
130 out_be32((void *)hwif->io_ports.command_addr, cmd);
131 eieio();
132 in_be32((void *)(hwif->dma_base + 0x01c));
133 eieio();
134 }
135
136 static u8 scc_read_status(ide_hwif_t *hwif)
137 {
138 return (u8)in_be32((void *)hwif->io_ports.status_addr);
139 }
140
141 static u8 scc_read_altstatus(ide_hwif_t *hwif)
142 {
143 return (u8)in_be32((void *)hwif->io_ports.ctl_addr);
144 }
145
146 static u8 scc_dma_sff_read_status(ide_hwif_t *hwif)
147 {
148 return (u8)in_be32((void *)(hwif->dma_base + 4));
149 }
150
151 static void scc_set_irq(ide_hwif_t *hwif, int on)
152 {
153 u8 ctl = ATA_DEVCTL_OBS;
154
155 if (on == 4) { /* hack for SRST */
156 ctl |= 4;
157 on &= ~4;
158 }
159
160 ctl |= on ? 0 : 2;
161
162 out_be32((void *)hwif->io_ports.ctl_addr, ctl);
163 eieio();
164 in_be32((void *)(hwif->dma_base + 0x01c));
165 eieio();
166 }
167
168 static void scc_ide_insw(unsigned long port, void *addr, u32 count)
169 {
170 u16 *ptr = (u16 *)addr;
171 while (count--) {
172 *ptr++ = le16_to_cpu(in_be32((void*)port));
173 }
174 }
175
176 static void scc_ide_insl(unsigned long port, void *addr, u32 count)
177 {
178 u16 *ptr = (u16 *)addr;
179 while (count--) {
180 *ptr++ = le16_to_cpu(in_be32((void*)port));
181 *ptr++ = le16_to_cpu(in_be32((void*)port));
182 }
183 }
184
185 static void scc_ide_outb(u8 addr, unsigned long port)
186 {
187 out_be32((void*)port, addr);
188 }
189
190 static void
191 scc_ide_outsw(unsigned long port, void *addr, u32 count)
192 {
193 u16 *ptr = (u16 *)addr;
194 while (count--) {
195 out_be32((void*)port, cpu_to_le16(*ptr++));
196 }
197 }
198
199 static void
200 scc_ide_outsl(unsigned long port, void *addr, u32 count)
201 {
202 u16 *ptr = (u16 *)addr;
203 while (count--) {
204 out_be32((void*)port, cpu_to_le16(*ptr++));
205 out_be32((void*)port, cpu_to_le16(*ptr++));
206 }
207 }
208
209 /**
210 * scc_set_pio_mode - set host controller for PIO mode
211 * @drive: drive
212 * @pio: PIO mode number
213 *
214 * Load the timing settings for this device mode into the
215 * controller.
216 */
217
218 static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
219 {
220 ide_hwif_t *hwif = drive->hwif;
221 struct scc_ports *ports = ide_get_hwifdata(hwif);
222 unsigned long ctl_base = ports->ctl;
223 unsigned long cckctrl_port = ctl_base + 0xff0;
224 unsigned long piosht_port = ctl_base + 0x000;
225 unsigned long pioct_port = ctl_base + 0x004;
226 unsigned long reg;
227 int offset;
228
229 reg = in_be32((void __iomem *)cckctrl_port);
230 if (reg & CCKCTRL_ATACLKOEN) {
231 offset = 1; /* 133MHz */
232 } else {
233 offset = 0; /* 100MHz */
234 }
235 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
236 out_be32((void __iomem *)piosht_port, reg);
237 reg = JCHCTtbl[offset][pio];
238 out_be32((void __iomem *)pioct_port, reg);
239 }
240
241 /**
242 * scc_set_dma_mode - set host controller for DMA mode
243 * @drive: drive
244 * @speed: DMA mode
245 *
246 * Load the timing settings for this device mode into the
247 * controller.
248 */
249
250 static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
251 {
252 ide_hwif_t *hwif = drive->hwif;
253 struct scc_ports *ports = ide_get_hwifdata(hwif);
254 unsigned long ctl_base = ports->ctl;
255 unsigned long cckctrl_port = ctl_base + 0xff0;
256 unsigned long mdmact_port = ctl_base + 0x008;
257 unsigned long mcrcst_port = ctl_base + 0x00c;
258 unsigned long sdmact_port = ctl_base + 0x010;
259 unsigned long scrcst_port = ctl_base + 0x014;
260 unsigned long udenvt_port = ctl_base + 0x018;
261 unsigned long tdvhsel_port = ctl_base + 0x020;
262 int is_slave = drive->dn & 1;
263 int offset, idx;
264 unsigned long reg;
265 unsigned long jcactsel;
266
267 reg = in_be32((void __iomem *)cckctrl_port);
268 if (reg & CCKCTRL_ATACLKOEN) {
269 offset = 1; /* 133MHz */
270 } else {
271 offset = 0; /* 100MHz */
272 }
273
274 idx = speed - XFER_UDMA_0;
275
276 jcactsel = JCACTSELtbl[offset][idx];
277 if (is_slave) {
278 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
279 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
280 jcactsel = jcactsel << 2;
281 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
282 } else {
283 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
284 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
285 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
286 }
287 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
288 out_be32((void __iomem *)udenvt_port, reg);
289 }
290
291 static void scc_dma_host_set(ide_drive_t *drive, int on)
292 {
293 ide_hwif_t *hwif = drive->hwif;
294 u8 unit = drive->dn & 1;
295 u8 dma_stat = scc_dma_sff_read_status(hwif);
296
297 if (on)
298 dma_stat |= (1 << (5 + unit));
299 else
300 dma_stat &= ~(1 << (5 + unit));
301
302 scc_ide_outb(dma_stat, hwif->dma_base + 4);
303 }
304
305 /**
306 * scc_dma_setup - begin a DMA phase
307 * @drive: target device
308 * @cmd: command
309 *
310 * Build an IDE DMA PRD (IDE speak for scatter gather table)
311 * and then set up the DMA transfer registers.
312 *
313 * Returns 0 on success. If a PIO fallback is required then 1
314 * is returned.
315 */
316
317 static int scc_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
318 {
319 ide_hwif_t *hwif = drive->hwif;
320 u32 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;
321 u8 dma_stat;
322
323 /* fall back to pio! */
324 if (ide_build_dmatable(drive, cmd) == 0) {
325 ide_map_sg(drive, cmd);
326 return 1;
327 }
328
329 /* PRD table */
330 out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma);
331
332 /* specify r/w */
333 out_be32((void __iomem *)hwif->dma_base, rw);
334
335 /* read DMA status for INTR & ERROR flags */
336 dma_stat = scc_dma_sff_read_status(hwif);
337
338 /* clear INTR & ERROR flags */
339 out_be32((void __iomem *)(hwif->dma_base + 4), dma_stat | 6);
340 drive->waiting_for_dma = 1;
341 return 0;
342 }
343
344 static void scc_dma_start(ide_drive_t *drive)
345 {
346 ide_hwif_t *hwif = drive->hwif;
347 u8 dma_cmd = scc_ide_inb(hwif->dma_base);
348
349 /* start DMA */
350 scc_ide_outb(dma_cmd | 1, hwif->dma_base);
351 wmb();
352 }
353
354 static int __scc_dma_end(ide_drive_t *drive)
355 {
356 ide_hwif_t *hwif = drive->hwif;
357 u8 dma_stat, dma_cmd;
358
359 drive->waiting_for_dma = 0;
360 /* get DMA command mode */
361 dma_cmd = scc_ide_inb(hwif->dma_base);
362 /* stop DMA */
363 scc_ide_outb(dma_cmd & ~1, hwif->dma_base);
364 /* get DMA status */
365 dma_stat = scc_dma_sff_read_status(hwif);
366 /* clear the INTR & ERROR bits */
367 scc_ide_outb(dma_stat | 6, hwif->dma_base + 4);
368 /* purge DMA mappings */
369 ide_destroy_dmatable(drive);
370 /* verify good DMA status */
371 wmb();
372 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
373 }
374
375 /**
376 * scc_dma_end - Stop DMA
377 * @drive: IDE drive
378 *
379 * Check and clear INT Status register.
380 * Then call __scc_dma_end().
381 */
382
383 static int scc_dma_end(ide_drive_t *drive)
384 {
385 ide_hwif_t *hwif = drive->hwif;
386 void __iomem *dma_base = (void __iomem *)hwif->dma_base;
387 unsigned long intsts_port = hwif->dma_base + 0x014;
388 u32 reg;
389 int dma_stat, data_loss = 0;
390 static int retry = 0;
391
392 /* errata A308 workaround: Step5 (check data loss) */
393 /* We don't check non ide_disk because it is limited to UDMA4 */
394 if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr)
395 & ATA_ERR) &&
396 drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
397 reg = in_be32((void __iomem *)intsts_port);
398 if (!(reg & INTSTS_ACTEINT)) {
399 printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
400 drive->name);
401 data_loss = 1;
402 if (retry++) {
403 struct request *rq = hwif->rq;
404 ide_drive_t *drive;
405 int i;
406
407 /* ERROR_RESET and drive->crc_count are needed
408 * to reduce DMA transfer mode in retry process.
409 */
410 if (rq)
411 rq->errors |= ERROR_RESET;
412
413 ide_port_for_each_dev(i, drive, hwif)
414 drive->crc_count++;
415 }
416 }
417 }
418
419 while (1) {
420 reg = in_be32((void __iomem *)intsts_port);
421
422 if (reg & INTSTS_SERROR) {
423 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
424 out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
425
426 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
427 continue;
428 }
429
430 if (reg & INTSTS_PRERR) {
431 u32 maea0, maec0;
432 unsigned long ctl_base = hwif->config_data;
433
434 maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
435 maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
436
437 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
438
439 out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
440
441 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
442 continue;
443 }
444
445 if (reg & INTSTS_RERR) {
446 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
447 out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
448
449 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
450 continue;
451 }
452
453 if (reg & INTSTS_ICERR) {
454 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
455
456 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
457 out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
458 continue;
459 }
460
461 if (reg & INTSTS_BMSINT) {
462 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
463 out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
464
465 ide_do_reset(drive);
466 continue;
467 }
468
469 if (reg & INTSTS_BMHE) {
470 out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
471 continue;
472 }
473
474 if (reg & INTSTS_ACTEINT) {
475 out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
476 continue;
477 }
478
479 if (reg & INTSTS_IOIRQS) {
480 out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
481 continue;
482 }
483 break;
484 }
485
486 dma_stat = __scc_dma_end(drive);
487 if (data_loss)
488 dma_stat |= 2; /* emulate DMA error (to retry command) */
489 return dma_stat;
490 }
491
492 /* returns 1 if dma irq issued, 0 otherwise */
493 static int scc_dma_test_irq(ide_drive_t *drive)
494 {
495 ide_hwif_t *hwif = drive->hwif;
496 u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
497
498 /* SCC errata A252,A308 workaround: Step4 */
499 if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr)
500 & ATA_ERR) &&
501 (int_stat & INTSTS_INTRQ))
502 return 1;
503
504 /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
505 if (int_stat & INTSTS_IOIRQS)
506 return 1;
507
508 return 0;
509 }
510
511 static u8 scc_udma_filter(ide_drive_t *drive)
512 {
513 ide_hwif_t *hwif = drive->hwif;
514 u8 mask = hwif->ultra_mask;
515
516 /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
517 if ((drive->media != ide_disk) && (mask & 0xE0)) {
518 printk(KERN_INFO "%s: limit %s to UDMA4\n",
519 SCC_PATA_NAME, drive->name);
520 mask = ATA_UDMA4;
521 }
522
523 return mask;
524 }
525
526 /**
527 * setup_mmio_scc - map CTRL/BMID region
528 * @dev: PCI device we are configuring
529 * @name: device name
530 *
531 */
532
533 static int setup_mmio_scc (struct pci_dev *dev, const char *name)
534 {
535 void __iomem *ctl_addr;
536 void __iomem *dma_addr;
537 int i, ret;
538
539 for (i = 0; i < MAX_HWIFS; i++) {
540 if (scc_ports[i].ctl == 0)
541 break;
542 }
543 if (i >= MAX_HWIFS)
544 return -ENOMEM;
545
546 ret = pci_request_selected_regions(dev, (1 << 2) - 1, name);
547 if (ret < 0) {
548 printk(KERN_ERR "%s: can't reserve resources\n", name);
549 return ret;
550 }
551
552 ctl_addr = pci_ioremap_bar(dev, 0);
553 if (!ctl_addr)
554 goto fail_0;
555
556 dma_addr = pci_ioremap_bar(dev, 1);
557 if (!dma_addr)
558 goto fail_1;
559
560 pci_set_master(dev);
561 scc_ports[i].ctl = (unsigned long)ctl_addr;
562 scc_ports[i].dma = (unsigned long)dma_addr;
563 pci_set_drvdata(dev, (void *) &scc_ports[i]);
564
565 return 1;
566
567 fail_1:
568 iounmap(ctl_addr);
569 fail_0:
570 return -ENOMEM;
571 }
572
573 static int scc_ide_setup_pci_device(struct pci_dev *dev,
574 const struct ide_port_info *d)
575 {
576 struct scc_ports *ports = pci_get_drvdata(dev);
577 struct ide_host *host;
578 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
579 int i, rc;
580
581 memset(&hw, 0, sizeof(hw));
582 for (i = 0; i <= 8; i++)
583 hw.io_ports_array[i] = ports->dma + 0x20 + i * 4;
584 hw.irq = dev->irq;
585 hw.dev = &dev->dev;
586 hw.chipset = ide_pci;
587
588 rc = ide_host_add(d, hws, &host);
589 if (rc)
590 return rc;
591
592 ports->host = host;
593
594 return 0;
595 }
596
597 /**
598 * init_setup_scc - set up an SCC PATA Controller
599 * @dev: PCI device
600 * @d: IDE port info
601 *
602 * Perform the initial set up for this device.
603 */
604
605 static int __devinit init_setup_scc(struct pci_dev *dev,
606 const struct ide_port_info *d)
607 {
608 unsigned long ctl_base;
609 unsigned long dma_base;
610 unsigned long cckctrl_port;
611 unsigned long intmask_port;
612 unsigned long mode_port;
613 unsigned long ecmode_port;
614 u32 reg = 0;
615 struct scc_ports *ports;
616 int rc;
617
618 rc = pci_enable_device(dev);
619 if (rc)
620 goto end;
621
622 rc = setup_mmio_scc(dev, d->name);
623 if (rc < 0)
624 goto end;
625
626 ports = pci_get_drvdata(dev);
627 ctl_base = ports->ctl;
628 dma_base = ports->dma;
629 cckctrl_port = ctl_base + 0xff0;
630 intmask_port = dma_base + 0x010;
631 mode_port = ctl_base + 0x024;
632 ecmode_port = ctl_base + 0xf00;
633
634 /* controller initialization */
635 reg = 0;
636 out_be32((void*)cckctrl_port, reg);
637 reg |= CCKCTRL_ATACLKOEN;
638 out_be32((void*)cckctrl_port, reg);
639 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
640 out_be32((void*)cckctrl_port, reg);
641 reg |= CCKCTRL_CRST;
642 out_be32((void*)cckctrl_port, reg);
643
644 for (;;) {
645 reg = in_be32((void*)cckctrl_port);
646 if (reg & CCKCTRL_CRST)
647 break;
648 udelay(5000);
649 }
650
651 reg |= CCKCTRL_ATARESET;
652 out_be32((void*)cckctrl_port, reg);
653
654 out_be32((void*)ecmode_port, ECMODE_VALUE);
655 out_be32((void*)mode_port, MODE_JCUSFEN);
656 out_be32((void*)intmask_port, INTMASK_MSK);
657
658 rc = scc_ide_setup_pci_device(dev, d);
659
660 end:
661 return rc;
662 }
663
664 static void scc_tf_load(ide_drive_t *drive, struct ide_cmd *cmd)
665 {
666 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
667 struct ide_taskfile *tf = &cmd->tf;
668 u8 HIHI = (cmd->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
669
670 if (cmd->ftf_flags & IDE_FTFLAG_FLAGGED)
671 HIHI = 0xFF;
672
673 if (cmd->ftf_flags & IDE_FTFLAG_OUT_DATA)
674 out_be32((void *)io_ports->data_addr,
675 (tf->hob_data << 8) | tf->data);
676
677 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
678 scc_ide_outb(tf->hob_feature, io_ports->feature_addr);
679 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
680 scc_ide_outb(tf->hob_nsect, io_ports->nsect_addr);
681 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
682 scc_ide_outb(tf->hob_lbal, io_ports->lbal_addr);
683 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
684 scc_ide_outb(tf->hob_lbam, io_ports->lbam_addr);
685 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
686 scc_ide_outb(tf->hob_lbah, io_ports->lbah_addr);
687
688 if (cmd->tf_flags & IDE_TFLAG_OUT_FEATURE)
689 scc_ide_outb(tf->feature, io_ports->feature_addr);
690 if (cmd->tf_flags & IDE_TFLAG_OUT_NSECT)
691 scc_ide_outb(tf->nsect, io_ports->nsect_addr);
692 if (cmd->tf_flags & IDE_TFLAG_OUT_LBAL)
693 scc_ide_outb(tf->lbal, io_ports->lbal_addr);
694 if (cmd->tf_flags & IDE_TFLAG_OUT_LBAM)
695 scc_ide_outb(tf->lbam, io_ports->lbam_addr);
696 if (cmd->tf_flags & IDE_TFLAG_OUT_LBAH)
697 scc_ide_outb(tf->lbah, io_ports->lbah_addr);
698
699 if (cmd->tf_flags & IDE_TFLAG_OUT_DEVICE)
700 scc_ide_outb((tf->device & HIHI) | drive->select,
701 io_ports->device_addr);
702 }
703
704 static void scc_tf_read(ide_drive_t *drive, struct ide_cmd *cmd)
705 {
706 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
707 struct ide_taskfile *tf = &cmd->tf;
708
709 if (cmd->ftf_flags & IDE_FTFLAG_IN_DATA) {
710 u16 data = (u16)in_be32((void *)io_ports->data_addr);
711
712 tf->data = data & 0xff;
713 tf->hob_data = (data >> 8) & 0xff;
714 }
715
716 /* be sure we're looking at the low order bits */
717 scc_ide_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
718
719 if (cmd->tf_flags & IDE_TFLAG_IN_FEATURE)
720 tf->feature = scc_ide_inb(io_ports->feature_addr);
721 if (cmd->tf_flags & IDE_TFLAG_IN_NSECT)
722 tf->nsect = scc_ide_inb(io_ports->nsect_addr);
723 if (cmd->tf_flags & IDE_TFLAG_IN_LBAL)
724 tf->lbal = scc_ide_inb(io_ports->lbal_addr);
725 if (cmd->tf_flags & IDE_TFLAG_IN_LBAM)
726 tf->lbam = scc_ide_inb(io_ports->lbam_addr);
727 if (cmd->tf_flags & IDE_TFLAG_IN_LBAH)
728 tf->lbah = scc_ide_inb(io_ports->lbah_addr);
729 if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE)
730 tf->device = scc_ide_inb(io_ports->device_addr);
731
732 if (cmd->tf_flags & IDE_TFLAG_LBA48) {
733 scc_ide_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);
734
735 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
736 tf->hob_feature = scc_ide_inb(io_ports->feature_addr);
737 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
738 tf->hob_nsect = scc_ide_inb(io_ports->nsect_addr);
739 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
740 tf->hob_lbal = scc_ide_inb(io_ports->lbal_addr);
741 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
742 tf->hob_lbam = scc_ide_inb(io_ports->lbam_addr);
743 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
744 tf->hob_lbah = scc_ide_inb(io_ports->lbah_addr);
745 }
746 }
747
748 static void scc_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
749 void *buf, unsigned int len)
750 {
751 unsigned long data_addr = drive->hwif->io_ports.data_addr;
752
753 len++;
754
755 if (drive->io_32bit) {
756 scc_ide_insl(data_addr, buf, len / 4);
757
758 if ((len & 3) >= 2)
759 scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1);
760 } else
761 scc_ide_insw(data_addr, buf, len / 2);
762 }
763
764 static void scc_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
765 void *buf, unsigned int len)
766 {
767 unsigned long data_addr = drive->hwif->io_ports.data_addr;
768
769 len++;
770
771 if (drive->io_32bit) {
772 scc_ide_outsl(data_addr, buf, len / 4);
773
774 if ((len & 3) >= 2)
775 scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1);
776 } else
777 scc_ide_outsw(data_addr, buf, len / 2);
778 }
779
780 /**
781 * init_mmio_iops_scc - set up the iops for MMIO
782 * @hwif: interface to set up
783 *
784 */
785
786 static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
787 {
788 struct pci_dev *dev = to_pci_dev(hwif->dev);
789 struct scc_ports *ports = pci_get_drvdata(dev);
790 unsigned long dma_base = ports->dma;
791
792 ide_set_hwifdata(hwif, ports);
793
794 hwif->dma_base = dma_base;
795 hwif->config_data = ports->ctl;
796 }
797
798 /**
799 * init_iops_scc - set up iops
800 * @hwif: interface to set up
801 *
802 * Do the basic setup for the SCC hardware interface
803 * and then do the MMIO setup.
804 */
805
806 static void __devinit init_iops_scc(ide_hwif_t *hwif)
807 {
808 struct pci_dev *dev = to_pci_dev(hwif->dev);
809
810 hwif->hwif_data = NULL;
811 if (pci_get_drvdata(dev) == NULL)
812 return;
813 init_mmio_iops_scc(hwif);
814 }
815
816 static int __devinit scc_init_dma(ide_hwif_t *hwif,
817 const struct ide_port_info *d)
818 {
819 return ide_allocate_dma_engine(hwif);
820 }
821
822 static u8 scc_cable_detect(ide_hwif_t *hwif)
823 {
824 return ATA_CBL_PATA80;
825 }
826
827 /**
828 * init_hwif_scc - set up hwif
829 * @hwif: interface to set up
830 *
831 * We do the basic set up of the interface structure. The SCC
832 * requires several custom handlers so we override the default
833 * ide DMA handlers appropriately.
834 */
835
836 static void __devinit init_hwif_scc(ide_hwif_t *hwif)
837 {
838 /* PTERADD */
839 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
840
841 if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)
842 hwif->ultra_mask = ATA_UDMA6; /* 133MHz */
843 else
844 hwif->ultra_mask = ATA_UDMA5; /* 100MHz */
845 }
846
847 static const struct ide_tp_ops scc_tp_ops = {
848 .exec_command = scc_exec_command,
849 .read_status = scc_read_status,
850 .read_altstatus = scc_read_altstatus,
851
852 .set_irq = scc_set_irq,
853
854 .tf_load = scc_tf_load,
855 .tf_read = scc_tf_read,
856
857 .input_data = scc_input_data,
858 .output_data = scc_output_data,
859 };
860
861 static const struct ide_port_ops scc_port_ops = {
862 .set_pio_mode = scc_set_pio_mode,
863 .set_dma_mode = scc_set_dma_mode,
864 .udma_filter = scc_udma_filter,
865 .cable_detect = scc_cable_detect,
866 };
867
868 static const struct ide_dma_ops scc_dma_ops = {
869 .dma_host_set = scc_dma_host_set,
870 .dma_setup = scc_dma_setup,
871 .dma_start = scc_dma_start,
872 .dma_end = scc_dma_end,
873 .dma_test_irq = scc_dma_test_irq,
874 .dma_lost_irq = ide_dma_lost_irq,
875 .dma_timeout = ide_dma_timeout,
876 .dma_timer_expiry = ide_dma_sff_timer_expiry,
877 .dma_sff_read_status = scc_dma_sff_read_status,
878 };
879
880 static const struct ide_port_info scc_chipset __devinitdata = {
881 .name = "sccIDE",
882 .init_iops = init_iops_scc,
883 .init_dma = scc_init_dma,
884 .init_hwif = init_hwif_scc,
885 .tp_ops = &scc_tp_ops,
886 .port_ops = &scc_port_ops,
887 .dma_ops = &scc_dma_ops,
888 .host_flags = IDE_HFLAG_SINGLE,
889 .irq_flags = IRQF_SHARED,
890 .pio_mask = ATA_PIO4,
891 };
892
893 /**
894 * scc_init_one - pci layer discovery entry
895 * @dev: PCI device
896 * @id: ident table entry
897 *
898 * Called by the PCI code when it finds an SCC PATA controller.
899 * We then use the IDE PCI generic helper to do most of the work.
900 */
901
902 static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
903 {
904 return init_setup_scc(dev, &scc_chipset);
905 }
906
907 /**
908 * scc_remove - pci layer remove entry
909 * @dev: PCI device
910 *
911 * Called by the PCI code when it removes an SCC PATA controller.
912 */
913
914 static void __devexit scc_remove(struct pci_dev *dev)
915 {
916 struct scc_ports *ports = pci_get_drvdata(dev);
917 struct ide_host *host = ports->host;
918
919 ide_host_remove(host);
920
921 iounmap((void*)ports->dma);
922 iounmap((void*)ports->ctl);
923 pci_release_selected_regions(dev, (1 << 2) - 1);
924 memset(ports, 0, sizeof(*ports));
925 }
926
927 static const struct pci_device_id scc_pci_tbl[] = {
928 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 },
929 { 0, },
930 };
931 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
932
933 static struct pci_driver scc_pci_driver = {
934 .name = "SCC IDE",
935 .id_table = scc_pci_tbl,
936 .probe = scc_init_one,
937 .remove = __devexit_p(scc_remove),
938 };
939
940 static int scc_ide_init(void)
941 {
942 return ide_pci_register_driver(&scc_pci_driver);
943 }
944
945 module_init(scc_ide_init);
946 /* -- No exit code?
947 static void scc_ide_exit(void)
948 {
949 ide_pci_unregister_driver(&scc_pci_driver);
950 }
951 module_exit(scc_ide_exit);
952 */
953
954
955 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
956 MODULE_LICENSE("GPL");
linux 2.6 git repository for openrd