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drm/i915: Pad ringbuffer with NOOPs before wrapping
[linux-2.6/linux-2.6-openrd.git] / drivers / gpu / drm / i915 / i915_drv.h
blob2d5bce643e6a1acc77cda7fcf971d186c6683563
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include "i915_reg.h"
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
36
37 /* General customization:
38 */
39
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
45
46 enum pipe {
47 PIPE_A = 0,
48 PIPE_B,
49 };
50
51 #define I915_NUM_PIPE 2
52
53 /* Interface history:
54 *
55 * 1.1: Original.
56 * 1.2: Add Power Management
57 * 1.3: Add vblank support
58 * 1.4: Fix cmdbuffer path, add heap destroy
59 * 1.5: Add vblank pipe configuration
60 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
61 * - Support vertical blank on secondary display pipe
62 */
63 #define DRIVER_MAJOR 1
64 #define DRIVER_MINOR 6
65 #define DRIVER_PATCHLEVEL 0
66
67 #define WATCH_COHERENCY 0
68 #define WATCH_BUF 0
69 #define WATCH_EXEC 0
70 #define WATCH_LRU 0
71 #define WATCH_RELOC 0
72 #define WATCH_INACTIVE 0
73 #define WATCH_PWRITE 0
74
75 #define I915_GEM_PHYS_CURSOR_0 1
76 #define I915_GEM_PHYS_CURSOR_1 2
77 #define I915_GEM_PHYS_OVERLAY_REGS 3
78 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
79
80 struct drm_i915_gem_phys_object {
81 int id;
82 struct page **page_list;
83 drm_dma_handle_t *handle;
84 struct drm_gem_object *cur_obj;
85 };
86
87 typedef struct _drm_i915_ring_buffer {
88 unsigned long Size;
89 u8 *virtual_start;
90 int head;
91 int tail;
92 int space;
93 drm_local_map_t map;
94 struct drm_gem_object *ring_obj;
95 } drm_i915_ring_buffer_t;
96
97 struct mem_block {
98 struct mem_block *next;
99 struct mem_block *prev;
100 int start;
101 int size;
102 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
103 };
104
105 struct opregion_header;
106 struct opregion_acpi;
107 struct opregion_swsci;
108 struct opregion_asle;
109
110 struct intel_opregion {
111 struct opregion_header *header;
112 struct opregion_acpi *acpi;
113 struct opregion_swsci *swsci;
114 struct opregion_asle *asle;
115 int enabled;
116 };
117
118 struct drm_i915_master_private {
119 drm_local_map_t *sarea;
120 struct _drm_i915_sarea *sarea_priv;
121 };
122 #define I915_FENCE_REG_NONE -1
123
124 struct drm_i915_fence_reg {
125 struct drm_gem_object *obj;
126 };
127
128 struct sdvo_device_mapping {
129 u8 dvo_port;
130 u8 slave_addr;
131 u8 dvo_wiring;
132 u8 initialized;
133 };
134
135 struct drm_i915_error_state {
136 u32 eir;
137 u32 pgtbl_er;
138 u32 pipeastat;
139 u32 pipebstat;
140 u32 ipeir;
141 u32 ipehr;
142 u32 instdone;
143 u32 acthd;
144 u32 instpm;
145 u32 instps;
146 u32 instdone1;
147 u32 seqno;
148 struct timeval time;
149 };
150
151 typedef struct drm_i915_private {
152 struct drm_device *dev;
153
154 int has_gem;
155
156 void __iomem *regs;
157
158 drm_i915_ring_buffer_t ring;
159
160 drm_dma_handle_t *status_page_dmah;
161 void *hw_status_page;
162 dma_addr_t dma_status_page;
163 uint32_t counter;
164 unsigned int status_gfx_addr;
165 drm_local_map_t hws_map;
166 struct drm_gem_object *hws_obj;
167
168 struct resource mch_res;
169
170 unsigned int cpp;
171 int back_offset;
172 int front_offset;
173 int current_page;
174 int page_flipping;
175
176 wait_queue_head_t irq_queue;
177 atomic_t irq_received;
178 /** Protects user_irq_refcount and irq_mask_reg */
179 spinlock_t user_irq_lock;
180 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
181 int user_irq_refcount;
182 /** Cached value of IMR to avoid reads in updating the bitfield */
183 u32 irq_mask_reg;
184 u32 pipestat[2];
185 /** splitted irq regs for graphics and display engine on IGDNG,
186 irq_mask_reg is still used for display irq. */
187 u32 gt_irq_mask_reg;
188 u32 gt_irq_enable_reg;
189 u32 de_irq_enable_reg;
190
191 u32 hotplug_supported_mask;
192 struct work_struct hotplug_work;
193
194 int tex_lru_log_granularity;
195 int allow_batchbuffer;
196 struct mem_block *agp_heap;
197 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
198 int vblank_pipe;
199
200 bool cursor_needs_physical;
201
202 struct drm_mm vram;
203
204 int irq_enabled;
205
206 struct intel_opregion opregion;
207
208 /* LVDS info */
209 int backlight_duty_cycle; /* restore backlight to this value */
210 bool panel_wants_dither;
211 struct drm_display_mode *panel_fixed_mode;
212 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
213 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
214
215 /* Feature bits from the VBIOS */
216 unsigned int int_tv_support:1;
217 unsigned int lvds_dither:1;
218 unsigned int lvds_vbt:1;
219 unsigned int int_crt_support:1;
220 unsigned int lvds_use_ssc:1;
221 unsigned int edp_support:1;
222 int lvds_ssc_freq;
223
224 int crt_ddc_bus; /* -1 = unknown, else GPIO to use for CRT DDC */
225 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
226 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
227 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
228
229 unsigned int fsb_freq, mem_freq;
230
231 spinlock_t error_lock;
232 struct drm_i915_error_state *first_error;
233 struct work_struct error_work;
234 struct workqueue_struct *wq;
235
236 /* Register state */
237 u8 saveLBB;
238 u32 saveDSPACNTR;
239 u32 saveDSPBCNTR;
240 u32 saveDSPARB;
241 u32 saveRENDERSTANDBY;
242 u32 saveHWS;
243 u32 savePIPEACONF;
244 u32 savePIPEBCONF;
245 u32 savePIPEASRC;
246 u32 savePIPEBSRC;
247 u32 saveFPA0;
248 u32 saveFPA1;
249 u32 saveDPLL_A;
250 u32 saveDPLL_A_MD;
251 u32 saveHTOTAL_A;
252 u32 saveHBLANK_A;
253 u32 saveHSYNC_A;
254 u32 saveVTOTAL_A;
255 u32 saveVBLANK_A;
256 u32 saveVSYNC_A;
257 u32 saveBCLRPAT_A;
258 u32 savePIPEASTAT;
259 u32 saveDSPASTRIDE;
260 u32 saveDSPASIZE;
261 u32 saveDSPAPOS;
262 u32 saveDSPAADDR;
263 u32 saveDSPASURF;
264 u32 saveDSPATILEOFF;
265 u32 savePFIT_PGM_RATIOS;
266 u32 saveBLC_PWM_CTL;
267 u32 saveBLC_PWM_CTL2;
268 u32 saveFPB0;
269 u32 saveFPB1;
270 u32 saveDPLL_B;
271 u32 saveDPLL_B_MD;
272 u32 saveHTOTAL_B;
273 u32 saveHBLANK_B;
274 u32 saveHSYNC_B;
275 u32 saveVTOTAL_B;
276 u32 saveVBLANK_B;
277 u32 saveVSYNC_B;
278 u32 saveBCLRPAT_B;
279 u32 savePIPEBSTAT;
280 u32 saveDSPBSTRIDE;
281 u32 saveDSPBSIZE;
282 u32 saveDSPBPOS;
283 u32 saveDSPBADDR;
284 u32 saveDSPBSURF;
285 u32 saveDSPBTILEOFF;
286 u32 saveVGA0;
287 u32 saveVGA1;
288 u32 saveVGA_PD;
289 u32 saveVGACNTRL;
290 u32 saveADPA;
291 u32 saveLVDS;
292 u32 savePP_ON_DELAYS;
293 u32 savePP_OFF_DELAYS;
294 u32 saveDVOA;
295 u32 saveDVOB;
296 u32 saveDVOC;
297 u32 savePP_ON;
298 u32 savePP_OFF;
299 u32 savePP_CONTROL;
300 u32 savePP_DIVISOR;
301 u32 savePFIT_CONTROL;
302 u32 save_palette_a[256];
303 u32 save_palette_b[256];
304 u32 saveFBC_CFB_BASE;
305 u32 saveFBC_LL_BASE;
306 u32 saveFBC_CONTROL;
307 u32 saveFBC_CONTROL2;
308 u32 saveIER;
309 u32 saveIIR;
310 u32 saveIMR;
311 u32 saveCACHE_MODE_0;
312 u32 saveD_STATE;
313 u32 saveDSPCLK_GATE_D;
314 u32 saveMI_ARB_STATE;
315 u32 saveSWF0[16];
316 u32 saveSWF1[16];
317 u32 saveSWF2[3];
318 u8 saveMSR;
319 u8 saveSR[8];
320 u8 saveGR[25];
321 u8 saveAR_INDEX;
322 u8 saveAR[21];
323 u8 saveDACMASK;
324 u8 saveCR[37];
325 uint64_t saveFENCE[16];
326 u32 saveCURACNTR;
327 u32 saveCURAPOS;
328 u32 saveCURABASE;
329 u32 saveCURBCNTR;
330 u32 saveCURBPOS;
331 u32 saveCURBBASE;
332 u32 saveCURSIZE;
333 u32 saveDP_B;
334 u32 saveDP_C;
335 u32 saveDP_D;
336 u32 savePIPEA_GMCH_DATA_M;
337 u32 savePIPEB_GMCH_DATA_M;
338 u32 savePIPEA_GMCH_DATA_N;
339 u32 savePIPEB_GMCH_DATA_N;
340 u32 savePIPEA_DP_LINK_M;
341 u32 savePIPEB_DP_LINK_M;
342 u32 savePIPEA_DP_LINK_N;
343 u32 savePIPEB_DP_LINK_N;
344
345 struct {
346 struct drm_mm gtt_space;
347
348 struct io_mapping *gtt_mapping;
349 int gtt_mtrr;
350
351 /**
352 * List of objects currently involved in rendering from the
353 * ringbuffer.
354 *
355 * Includes buffers having the contents of their GPU caches
356 * flushed, not necessarily primitives. last_rendering_seqno
357 * represents when the rendering involved will be completed.
358 *
359 * A reference is held on the buffer while on this list.
360 */
361 spinlock_t active_list_lock;
362 struct list_head active_list;
363
364 /**
365 * List of objects which are not in the ringbuffer but which
366 * still have a write_domain which needs to be flushed before
367 * unbinding.
368 *
369 * last_rendering_seqno is 0 while an object is in this list.
370 *
371 * A reference is held on the buffer while on this list.
372 */
373 struct list_head flushing_list;
374
375 /**
376 * LRU list of objects which are not in the ringbuffer and
377 * are ready to unbind, but are still in the GTT.
378 *
379 * last_rendering_seqno is 0 while an object is in this list.
380 *
381 * A reference is not held on the buffer while on this list,
382 * as merely being GTT-bound shouldn't prevent its being
383 * freed, and we'll pull it off the list in the free path.
384 */
385 struct list_head inactive_list;
386
387 /** LRU list of objects with fence regs on them. */
388 struct list_head fence_list;
389
390 /**
391 * List of breadcrumbs associated with GPU requests currently
392 * outstanding.
393 */
394 struct list_head request_list;
395
396 /**
397 * We leave the user IRQ off as much as possible,
398 * but this means that requests will finish and never
399 * be retired once the system goes idle. Set a timer to
400 * fire periodically while the ring is running. When it
401 * fires, go retire requests.
402 */
403 struct delayed_work retire_work;
404
405 uint32_t next_gem_seqno;
406
407 /**
408 * Waiting sequence number, if any
409 */
410 uint32_t waiting_gem_seqno;
411
412 /**
413 * Last seq seen at irq time
414 */
415 uint32_t irq_gem_seqno;
416
417 /**
418 * Flag if the X Server, and thus DRM, is not currently in
419 * control of the device.
420 *
421 * This is set between LeaveVT and EnterVT. It needs to be
422 * replaced with a semaphore. It also needs to be
423 * transitioned away from for kernel modesetting.
424 */
425 int suspended;
426
427 /**
428 * Flag if the hardware appears to be wedged.
429 *
430 * This is set when attempts to idle the device timeout.
431 * It prevents command submission from occuring and makes
432 * every pending request fail
433 */
434 int wedged;
435
436 /** Bit 6 swizzling required for X tiling */
437 uint32_t bit_6_swizzle_x;
438 /** Bit 6 swizzling required for Y tiling */
439 uint32_t bit_6_swizzle_y;
440
441 /* storage for physical objects */
442 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
443 } mm;
444 struct sdvo_device_mapping sdvo_mappings[2];
445
446 /* Reclocking support */
447 bool render_reclock_avail;
448 bool lvds_downclock_avail;
449 struct work_struct idle_work;
450 struct timer_list idle_timer;
451 bool busy;
452 u16 orig_clock;
453 } drm_i915_private_t;
454
455 /** driver private structure attached to each drm_gem_object */
456 struct drm_i915_gem_object {
457 struct drm_gem_object *obj;
458
459 /** Current space allocated to this object in the GTT, if any. */
460 struct drm_mm_node *gtt_space;
461
462 /** This object's place on the active/flushing/inactive lists */
463 struct list_head list;
464
465 /** This object's place on the fenced object LRU */
466 struct list_head fence_list;
467
468 /**
469 * This is set if the object is on the active or flushing lists
470 * (has pending rendering), and is not set if it's on inactive (ready
471 * to be unbound).
472 */
473 int active;
474
475 /**
476 * This is set if the object has been written to since last bound
477 * to the GTT
478 */
479 int dirty;
480
481 /** AGP memory structure for our GTT binding. */
482 DRM_AGP_MEM *agp_mem;
483
484 struct page **pages;
485 int pages_refcount;
486
487 /**
488 * Current offset of the object in GTT space.
489 *
490 * This is the same as gtt_space->start
491 */
492 uint32_t gtt_offset;
493 /**
494 * Required alignment for the object
495 */
496 uint32_t gtt_alignment;
497 /**
498 * Fake offset for use by mmap(2)
499 */
500 uint64_t mmap_offset;
501
502 /**
503 * Fence register bits (if any) for this object. Will be set
504 * as needed when mapped into the GTT.
505 * Protected by dev->struct_mutex.
506 */
507 int fence_reg;
508
509 /** How many users have pinned this object in GTT space */
510 int pin_count;
511
512 /** Breadcrumb of last rendering to the buffer. */
513 uint32_t last_rendering_seqno;
514
515 /** Current tiling mode for the object. */
516 uint32_t tiling_mode;
517 uint32_t stride;
518
519 /** Record of address bit 17 of each page at last unbind. */
520 long *bit_17;
521
522 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
523 uint32_t agp_type;
524
525 /**
526 * If present, while GEM_DOMAIN_CPU is in the read domain this array
527 * flags which individual pages are valid.
528 */
529 uint8_t *page_cpu_valid;
530
531 /** User space pin count and filp owning the pin */
532 uint32_t user_pin_count;
533 struct drm_file *pin_filp;
534
535 /** for phy allocated objects */
536 struct drm_i915_gem_phys_object *phys_obj;
537
538 /**
539 * Used for checking the object doesn't appear more than once
540 * in an execbuffer object list.
541 */
542 int in_execbuffer;
543 };
544
545 /**
546 * Request queue structure.
547 *
548 * The request queue allows us to note sequence numbers that have been emitted
549 * and may be associated with active buffers to be retired.
550 *
551 * By keeping this list, we can avoid having to do questionable
552 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
553 * an emission time with seqnos for tracking how far ahead of the GPU we are.
554 */
555 struct drm_i915_gem_request {
556 /** GEM sequence number associated with this request. */
557 uint32_t seqno;
558
559 /** Time at which this request was emitted, in jiffies. */
560 unsigned long emitted_jiffies;
561
562 /** global list entry for this request */
563 struct list_head list;
564
565 /** file_priv list entry for this request */
566 struct list_head client_list;
567 };
568
569 struct drm_i915_file_private {
570 struct {
571 struct list_head request_list;
572 } mm;
573 };
574
575 enum intel_chip_family {
576 CHIP_I8XX = 0x01,
577 CHIP_I9XX = 0x02,
578 CHIP_I915 = 0x04,
579 CHIP_I965 = 0x08,
580 };
581
582 extern struct drm_ioctl_desc i915_ioctls[];
583 extern int i915_max_ioctl;
584 extern unsigned int i915_fbpercrtc;
585 extern unsigned int i915_powersave;
586
587 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
588 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
589
590 /* i915_dma.c */
591 extern void i915_kernel_lost_context(struct drm_device * dev);
592 extern int i915_driver_load(struct drm_device *, unsigned long flags);
593 extern int i915_driver_unload(struct drm_device *);
594 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
595 extern void i915_driver_lastclose(struct drm_device * dev);
596 extern void i915_driver_preclose(struct drm_device *dev,
597 struct drm_file *file_priv);
598 extern void i915_driver_postclose(struct drm_device *dev,
599 struct drm_file *file_priv);
600 extern int i915_driver_device_is_agp(struct drm_device * dev);
601 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
602 unsigned long arg);
603 extern int i915_emit_box(struct drm_device *dev,
604 struct drm_clip_rect *boxes,
605 int i, int DR1, int DR4);
606
607 /* i915_irq.c */
608 extern int i915_irq_emit(struct drm_device *dev, void *data,
609 struct drm_file *file_priv);
610 extern int i915_irq_wait(struct drm_device *dev, void *data,
611 struct drm_file *file_priv);
612 void i915_user_irq_get(struct drm_device *dev);
613 void i915_user_irq_put(struct drm_device *dev);
614 extern void i915_enable_interrupt (struct drm_device *dev);
615
616 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
617 extern void i915_driver_irq_preinstall(struct drm_device * dev);
618 extern int i915_driver_irq_postinstall(struct drm_device *dev);
619 extern void i915_driver_irq_uninstall(struct drm_device * dev);
620 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
621 struct drm_file *file_priv);
622 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
623 struct drm_file *file_priv);
624 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
625 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
626 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
627 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
628 extern int i915_vblank_swap(struct drm_device *dev, void *data,
629 struct drm_file *file_priv);
630 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
631
632 void
633 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
634
635 void
636 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
637
638
639 /* i915_mem.c */
640 extern int i915_mem_alloc(struct drm_device *dev, void *data,
641 struct drm_file *file_priv);
642 extern int i915_mem_free(struct drm_device *dev, void *data,
643 struct drm_file *file_priv);
644 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
645 struct drm_file *file_priv);
646 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
647 struct drm_file *file_priv);
648 extern void i915_mem_takedown(struct mem_block **heap);
649 extern void i915_mem_release(struct drm_device * dev,
650 struct drm_file *file_priv, struct mem_block *heap);
651 /* i915_gem.c */
652 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
653 struct drm_file *file_priv);
654 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
655 struct drm_file *file_priv);
656 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
657 struct drm_file *file_priv);
658 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
659 struct drm_file *file_priv);
660 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
661 struct drm_file *file_priv);
662 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
663 struct drm_file *file_priv);
664 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
665 struct drm_file *file_priv);
666 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
667 struct drm_file *file_priv);
668 int i915_gem_execbuffer(struct drm_device *dev, void *data,
669 struct drm_file *file_priv);
670 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
671 struct drm_file *file_priv);
672 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
673 struct drm_file *file_priv);
674 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
675 struct drm_file *file_priv);
676 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
677 struct drm_file *file_priv);
678 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
679 struct drm_file *file_priv);
680 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
681 struct drm_file *file_priv);
682 int i915_gem_set_tiling(struct drm_device *dev, void *data,
683 struct drm_file *file_priv);
684 int i915_gem_get_tiling(struct drm_device *dev, void *data,
685 struct drm_file *file_priv);
686 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
687 struct drm_file *file_priv);
688 void i915_gem_load(struct drm_device *dev);
689 int i915_gem_init_object(struct drm_gem_object *obj);
690 void i915_gem_free_object(struct drm_gem_object *obj);
691 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
692 void i915_gem_object_unpin(struct drm_gem_object *obj);
693 int i915_gem_object_unbind(struct drm_gem_object *obj);
694 void i915_gem_release_mmap(struct drm_gem_object *obj);
695 void i915_gem_lastclose(struct drm_device *dev);
696 uint32_t i915_get_gem_seqno(struct drm_device *dev);
697 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
698 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
699 void i915_gem_retire_requests(struct drm_device *dev);
700 void i915_gem_retire_work_handler(struct work_struct *work);
701 void i915_gem_clflush_object(struct drm_gem_object *obj);
702 int i915_gem_object_set_domain(struct drm_gem_object *obj,
703 uint32_t read_domains,
704 uint32_t write_domain);
705 int i915_gem_init_ringbuffer(struct drm_device *dev);
706 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
707 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
708 unsigned long end);
709 int i915_gem_idle(struct drm_device *dev);
710 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
711 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
712 int write);
713 int i915_gem_attach_phys_object(struct drm_device *dev,
714 struct drm_gem_object *obj, int id);
715 void i915_gem_detach_phys_object(struct drm_device *dev,
716 struct drm_gem_object *obj);
717 void i915_gem_free_all_phys_object(struct drm_device *dev);
718 int i915_gem_object_get_pages(struct drm_gem_object *obj);
719 void i915_gem_object_put_pages(struct drm_gem_object *obj);
720 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
721
722 /* i915_gem_tiling.c */
723 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
724 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
725 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
726
727 /* i915_gem_debug.c */
728 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
729 const char *where, uint32_t mark);
730 #if WATCH_INACTIVE
731 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
732 #else
733 #define i915_verify_inactive(dev, file, line)
734 #endif
735 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
736 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
737 const char *where, uint32_t mark);
738 void i915_dump_lru(struct drm_device *dev, const char *where);
739
740 /* i915_debugfs.c */
741 int i915_debugfs_init(struct drm_minor *minor);
742 void i915_debugfs_cleanup(struct drm_minor *minor);
743
744 /* i915_suspend.c */
745 extern int i915_save_state(struct drm_device *dev);
746 extern int i915_restore_state(struct drm_device *dev);
747
748 /* i915_suspend.c */
749 extern int i915_save_state(struct drm_device *dev);
750 extern int i915_restore_state(struct drm_device *dev);
751
752 #ifdef CONFIG_ACPI
753 /* i915_opregion.c */
754 extern int intel_opregion_init(struct drm_device *dev, int resume);
755 extern void intel_opregion_free(struct drm_device *dev, int suspend);
756 extern void opregion_asle_intr(struct drm_device *dev);
757 extern void opregion_enable_asle(struct drm_device *dev);
758 #else
759 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
760 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
761 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
762 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
763 #endif
764
765 /* modesetting */
766 extern void intel_modeset_init(struct drm_device *dev);
767 extern void intel_modeset_cleanup(struct drm_device *dev);
768
769 /**
770 * Lock test for when it's just for synchronization of ring access.
771 *
772 * In that case, we don't need to do it when GEM is initialized as nobody else
773 * has access to the ring.
774 */
775 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
776 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
777 LOCK_TEST_WITH_RETURN(dev, file_priv); \
778 } while (0)
779
780 #define I915_READ(reg) readl(dev_priv->regs + (reg))
781 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
782 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
783 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
784 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
785 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
786 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
787 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
788 #define POSTING_READ(reg) (void)I915_READ(reg)
789
790 #define I915_VERBOSE 0
791
792 #define RING_LOCALS volatile unsigned int *ring_virt__;
793
794 #define BEGIN_LP_RING(n) do { \
795 int bytes__ = 4*(n); \
796 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
797 /* a wrap must occur between instructions so pad beforehand */ \
798 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
799 i915_wrap_ring(dev); \
800 if (unlikely (dev_priv->ring.space < bytes__)) \
801 i915_wait_ring(dev, bytes__, __func__); \
802 ring_virt__ = (unsigned int *) \
803 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
804 dev_priv->ring.tail += bytes__; \
805 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
806 dev_priv->ring.space -= bytes__; \
807 } while (0)
808
809 #define OUT_RING(n) do { \
810 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
811 *ring_virt__++ = (n); \
812 } while (0)
813
814 #define ADVANCE_LP_RING() do { \
815 if (I915_VERBOSE) \
816 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
817 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
818 } while(0)
819
820 /**
821 * Reads a dword out of the status page, which is written to from the command
822 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
823 * MI_STORE_DATA_IMM.
824 *
825 * The following dwords have a reserved meaning:
826 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
827 * 0x04: ring 0 head pointer
828 * 0x05: ring 1 head pointer (915-class)
829 * 0x06: ring 2 head pointer (915-class)
830 * 0x10-0x1b: Context status DWords (GM45)
831 * 0x1f: Last written status offset. (GM45)
832 *
833 * The area from dword 0x20 to 0x3ff is available for driver usage.
834 */
835 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
836 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
837 #define I915_GEM_HWS_INDEX 0x20
838 #define I915_BREADCRUMB_INDEX 0x21
839
840 extern int i915_wrap_ring(struct drm_device * dev);
841 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
842
843 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
844 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
845 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
846 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
847 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
848
849 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
850 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
851 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
852 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
853 (dev)->pci_device == 0x27AE)
854 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
855 (dev)->pci_device == 0x2982 || \
856 (dev)->pci_device == 0x2992 || \
857 (dev)->pci_device == 0x29A2 || \
858 (dev)->pci_device == 0x2A02 || \
859 (dev)->pci_device == 0x2A12 || \
860 (dev)->pci_device == 0x2A42 || \
861 (dev)->pci_device == 0x2E02 || \
862 (dev)->pci_device == 0x2E12 || \
863 (dev)->pci_device == 0x2E22 || \
864 (dev)->pci_device == 0x2E32 || \
865 (dev)->pci_device == 0x0042 || \
866 (dev)->pci_device == 0x0046)
867
868 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
869 (dev)->pci_device == 0x2A12)
870
871 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
872
873 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
874 (dev)->pci_device == 0x2E12 || \
875 (dev)->pci_device == 0x2E22 || \
876 (dev)->pci_device == 0x2E32 || \
877 IS_GM45(dev))
878
879 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
880 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
881 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
882
883 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
884 (dev)->pci_device == 0x29B2 || \
885 (dev)->pci_device == 0x29D2 || \
886 (IS_IGD(dev)))
887
888 #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
889 #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
890 #define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
891
892 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
893 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
894 IS_IGDNG(dev))
895
896 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
897 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
898 IS_IGD(dev) || IS_IGDNG_M(dev))
899
900 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
901 IS_IGDNG(dev))
902 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
903 * rows, which changed the alignment requirements and fence programming.
904 */
905 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
906 IS_I915GM(dev)))
907 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
908 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
909 #define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
910 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
911 /* dsparb controlled by hw only */
912 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
913
914 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
915 #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
916
917 #define PRIMARY_RINGBUFFER_SIZE (128*1024)
918
919 #endif
linux 2.6 git repository for openrd