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[PATCH] gianfar: Add support enhanced TSEC features on the MPC 8548
[linux-2.6/linux-2.6-openrd.git] / drivers / net / skge.h
blob36c62b68fab4f8a5185ccb8eb4ef2a5fa0d91122
1 /*
2 * Definitions for the new Marvell Yukon / SysKonenct driver.
3 */
4 #ifndef _SKGE_H
5 #define _SKGE_H
6
7 /* PCI config registers */
8 #define PCI_DEV_REG1 0x40
9 #define PCI_DEV_REG2 0x44
10 #ifndef PCI_VPD
11 #define PCI_VPD 0x50
12 #endif
13
14 /* PCI_OUR_REG_2 32 bit Our Register 2 */
15 enum {
16 PCI_VPD_WR_THR = 0xff<<24, /* Bit 31..24: VPD Write Threshold */
17 PCI_DEV_SEL = 0x7f<<17, /* Bit 23..17: EEPROM Device Select */
18 PCI_VPD_ROM_SZ = 7 <<14, /* Bit 16..14: VPD ROM Size */
19 /* Bit 13..12: reserved */
20 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
21 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
22 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
23 };
24
25 /* PCI_VPD_ADR_REG 16 bit VPD Address Register */
26 enum {
27 PCI_VPD_FLAG = 1<<15, /* starts VPD rd/wr cycle */
28 PCI_VPD_ADR_MSK =0x7fffL, /* Bit 14.. 0: VPD Address Mask */
29 VPD_RES_ID = 0x82,
30 VPD_RES_READ = 0x90,
31 VPD_RES_WRITE = 0x81,
32 VPD_RES_END = 0x78,
33 };
34
35
36 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
37 PCI_STATUS_SIG_SYSTEM_ERROR | \
38 PCI_STATUS_REC_MASTER_ABORT | \
39 PCI_STATUS_REC_TARGET_ABORT | \
40 PCI_STATUS_PARITY)
41
42
43 enum csr_regs {
44 B0_RAP = 0x0000,
45 B0_CTST = 0x0004,
46 B0_LED = 0x0006,
47 B0_POWER_CTRL = 0x0007,
48 B0_ISRC = 0x0008,
49 B0_IMSK = 0x000c,
50 B0_HWE_ISRC = 0x0010,
51 B0_HWE_IMSK = 0x0014,
52 B0_SP_ISRC = 0x0018,
53 B0_XM1_IMSK = 0x0020,
54 B0_XM1_ISRC = 0x0028,
55 B0_XM1_PHY_ADDR = 0x0030,
56 B0_XM1_PHY_DATA = 0x0034,
57 B0_XM2_IMSK = 0x0040,
58 B0_XM2_ISRC = 0x0048,
59 B0_XM2_PHY_ADDR = 0x0050,
60 B0_XM2_PHY_DATA = 0x0054,
61 B0_R1_CSR = 0x0060,
62 B0_R2_CSR = 0x0064,
63 B0_XS1_CSR = 0x0068,
64 B0_XA1_CSR = 0x006c,
65 B0_XS2_CSR = 0x0070,
66 B0_XA2_CSR = 0x0074,
67
68 B2_MAC_1 = 0x0100,
69 B2_MAC_2 = 0x0108,
70 B2_MAC_3 = 0x0110,
71 B2_CONN_TYP = 0x0118,
72 B2_PMD_TYP = 0x0119,
73 B2_MAC_CFG = 0x011a,
74 B2_CHIP_ID = 0x011b,
75 B2_E_0 = 0x011c,
76 B2_E_1 = 0x011d,
77 B2_E_2 = 0x011e,
78 B2_E_3 = 0x011f,
79 B2_FAR = 0x0120,
80 B2_FDP = 0x0124,
81 B2_LD_CTRL = 0x0128,
82 B2_LD_TEST = 0x0129,
83 B2_TI_INI = 0x0130,
84 B2_TI_VAL = 0x0134,
85 B2_TI_CTRL = 0x0138,
86 B2_TI_TEST = 0x0139,
87 B2_IRQM_INI = 0x0140,
88 B2_IRQM_VAL = 0x0144,
89 B2_IRQM_CTRL = 0x0148,
90 B2_IRQM_TEST = 0x0149,
91 B2_IRQM_MSK = 0x014c,
92 B2_IRQM_HWE_MSK = 0x0150,
93 B2_TST_CTRL1 = 0x0158,
94 B2_TST_CTRL2 = 0x0159,
95 B2_GP_IO = 0x015c,
96 B2_I2C_CTRL = 0x0160,
97 B2_I2C_DATA = 0x0164,
98 B2_I2C_IRQ = 0x0168,
99 B2_I2C_SW = 0x016c,
100 B2_BSC_INI = 0x0170,
101 B2_BSC_VAL = 0x0174,
102 B2_BSC_CTRL = 0x0178,
103 B2_BSC_STAT = 0x0179,
104 B2_BSC_TST = 0x017a,
105
106 B3_RAM_ADDR = 0x0180,
107 B3_RAM_DATA_LO = 0x0184,
108 B3_RAM_DATA_HI = 0x0188,
109 B3_RI_WTO_R1 = 0x0190,
110 B3_RI_WTO_XA1 = 0x0191,
111 B3_RI_WTO_XS1 = 0x0192,
112 B3_RI_RTO_R1 = 0x0193,
113 B3_RI_RTO_XA1 = 0x0194,
114 B3_RI_RTO_XS1 = 0x0195,
115 B3_RI_WTO_R2 = 0x0196,
116 B3_RI_WTO_XA2 = 0x0197,
117 B3_RI_WTO_XS2 = 0x0198,
118 B3_RI_RTO_R2 = 0x0199,
119 B3_RI_RTO_XA2 = 0x019a,
120 B3_RI_RTO_XS2 = 0x019b,
121 B3_RI_TO_VAL = 0x019c,
122 B3_RI_CTRL = 0x01a0,
123 B3_RI_TEST = 0x01a2,
124 B3_MA_TOINI_RX1 = 0x01b0,
125 B3_MA_TOINI_RX2 = 0x01b1,
126 B3_MA_TOINI_TX1 = 0x01b2,
127 B3_MA_TOINI_TX2 = 0x01b3,
128 B3_MA_TOVAL_RX1 = 0x01b4,
129 B3_MA_TOVAL_RX2 = 0x01b5,
130 B3_MA_TOVAL_TX1 = 0x01b6,
131 B3_MA_TOVAL_TX2 = 0x01b7,
132 B3_MA_TO_CTRL = 0x01b8,
133 B3_MA_TO_TEST = 0x01ba,
134 B3_MA_RCINI_RX1 = 0x01c0,
135 B3_MA_RCINI_RX2 = 0x01c1,
136 B3_MA_RCINI_TX1 = 0x01c2,
137 B3_MA_RCINI_TX2 = 0x01c3,
138 B3_MA_RCVAL_RX1 = 0x01c4,
139 B3_MA_RCVAL_RX2 = 0x01c5,
140 B3_MA_RCVAL_TX1 = 0x01c6,
141 B3_MA_RCVAL_TX2 = 0x01c7,
142 B3_MA_RC_CTRL = 0x01c8,
143 B3_MA_RC_TEST = 0x01ca,
144 B3_PA_TOINI_RX1 = 0x01d0,
145 B3_PA_TOINI_RX2 = 0x01d4,
146 B3_PA_TOINI_TX1 = 0x01d8,
147 B3_PA_TOINI_TX2 = 0x01dc,
148 B3_PA_TOVAL_RX1 = 0x01e0,
149 B3_PA_TOVAL_RX2 = 0x01e4,
150 B3_PA_TOVAL_TX1 = 0x01e8,
151 B3_PA_TOVAL_TX2 = 0x01ec,
152 B3_PA_CTRL = 0x01f0,
153 B3_PA_TEST = 0x01f2,
154 };
155
156 /* B0_CTST 16 bit Control/Status register */
157 enum {
158 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
159 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
160 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
161 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
162 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
163 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
164 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
165 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
166 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
167 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
168 CS_MRST_CLR = 1<<3, /* Clear Master reset */
169 CS_MRST_SET = 1<<2, /* Set Master reset */
170 CS_RST_CLR = 1<<1, /* Clear Software reset */
171 CS_RST_SET = 1, /* Set Software reset */
172
173 /* B0_LED 8 Bit LED register */
174 /* Bit 7.. 2: reserved */
175 LED_STAT_ON = 1<<1, /* Status LED on */
176 LED_STAT_OFF = 1, /* Status LED off */
177
178 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
179 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
180 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
181 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
182 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
183 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
184 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
185 PC_VCC_ON = 1<<1, /* Switch VCC On */
186 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
187 };
188
189 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
190 enum {
191 IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */
192 IS_HW_ERR = 1<<31, /* Interrupt HW Error */
193 /* Bit 30: reserved */
194 IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */
195 IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */
196 IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */
197 IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */
198 IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
199 IS_IRQ_SW = 1<<24, /* SW forced IRQ */
200 IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
201 /* IRQ from PHY (YUKON only) */
202 IS_TIMINT = 1<<22, /* IRQ from Timer */
203 IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
204 IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
205 IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
206 IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
207 /* Receive Queue 1 */
208 IS_R1_B = 1<<17, /* Q_R1 End of Buffer */
209 IS_R1_F = 1<<16, /* Q_R1 End of Frame */
210 IS_R1_C = 1<<15, /* Q_R1 Encoding Error */
211 /* Receive Queue 2 */
212 IS_R2_B = 1<<14, /* Q_R2 End of Buffer */
213 IS_R2_F = 1<<13, /* Q_R2 End of Frame */
214 IS_R2_C = 1<<12, /* Q_R2 Encoding Error */
215 /* Synchronous Transmit Queue 1 */
216 IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */
217 IS_XS1_F = 1<<10, /* Q_XS1 End of Frame */
218 IS_XS1_C = 1<<9, /* Q_XS1 Encoding Error */
219 /* Asynchronous Transmit Queue 1 */
220 IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
221 IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */
222 IS_XA1_C = 1<<6, /* Q_XA1 Encoding Error */
223 /* Synchronous Transmit Queue 2 */
224 IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
225 IS_XS2_F = 1<<4, /* Q_XS2 End of Frame */
226 IS_XS2_C = 1<<3, /* Q_XS2 Encoding Error */
227 /* Asynchronous Transmit Queue 2 */
228 IS_XA2_B = 1<<2, /* Q_XA2 End of Buffer */
229 IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
230 IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
231
232 IS_PORT_1 = IS_XA1_F| IS_R1_F| IS_MAC1,
233 IS_PORT_2 = IS_XA2_F| IS_R2_F| IS_MAC2,
234 };
235
236
237 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
238 enum {
239 IS_ERR_MSK = 0x00003fff,/* All Error bits */
240
241 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
242 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
243 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
244 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
245 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
246 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
247 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
248 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
249 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
250 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
251 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
252 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
253 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
254 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
255 };
256
257 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
258 enum {
259 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
260 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
261 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
262 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
263 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
264 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
265 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
266 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
267 };
268
269 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
270 enum {
271 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
272 /* Bit 3.. 2: reserved */
273 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
274 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
275 };
276
277 /* B2_CHIP_ID 8 bit Chip Identification Number */
278 enum {
279 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
280 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
281 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
282 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
283 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
284 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
285 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
286
287 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
288 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
289 };
290
291 /* B2_LD_TEST 8 bit EPROM loader test register */
292 enum {
293 LD_T_ON = 1<<3, /* Loader Test mode on */
294 LD_T_OFF = 1<<2, /* Loader Test mode off */
295 LD_T_STEP = 1<<1, /* Decrement FPROM addr. Counter */
296 LD_START = 1<<0, /* Start loading FPROM */
297 };
298
299 /* B2_TI_CTRL 8 bit Timer control */
300 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
301 enum {
302 TIM_START = 1<<2, /* Start Timer */
303 TIM_STOP = 1<<1, /* Stop Timer */
304 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
305 };
306
307 /* B2_TI_TEST 8 Bit Timer Test */
308 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
309 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
310 enum {
311 TIM_T_ON = 1<<2, /* Test mode on */
312 TIM_T_OFF = 1<<1, /* Test mode off */
313 TIM_T_STEP = 1<<0, /* Test step */
314 };
315
316 /* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */
317 /* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */
318 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
319 enum {
320 DPT_MSK = 0x00ffffffL, /* Bit 23.. 0: Desc Poll Timer Bits */
321
322 DPT_START = 1<<1, /* Start Descriptor Poll Timer */
323 DPT_STOP = 1<<0, /* Stop Descriptor Poll Timer */
324 };
325
326 /* B2_GP_IO 32 bit General Purpose I/O Register */
327 enum {
328 GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
329 GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
330 GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
331 GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
332 GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
333 GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
334 GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
335 GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
336 GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
337 GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
338
339 GP_IO_9 = 1<<9, /* IO_9 pin */
340 GP_IO_8 = 1<<8, /* IO_8 pin */
341 GP_IO_7 = 1<<7, /* IO_7 pin */
342 GP_IO_6 = 1<<6, /* IO_6 pin */
343 GP_IO_5 = 1<<5, /* IO_5 pin */
344 GP_IO_4 = 1<<4, /* IO_4 pin */
345 GP_IO_3 = 1<<3, /* IO_3 pin */
346 GP_IO_2 = 1<<2, /* IO_2 pin */
347 GP_IO_1 = 1<<1, /* IO_1 pin */
348 GP_IO_0 = 1<<0, /* IO_0 pin */
349 };
350
351 /* Rx/Tx Path related Arbiter Test Registers */
352 /* B3_MA_TO_TEST 16 bit MAC Arbiter Timeout Test Reg */
353 /* B3_MA_RC_TEST 16 bit MAC Arbiter Recovery Test Reg */
354 /* B3_PA_TEST 16 bit Packet Arbiter Test Register */
355 /* Bit 15, 11, 7, and 3 are reserved in B3_PA_TEST */
356 enum {
357 TX2_T_EV = 1<<15,/* TX2 Timeout/Recv Event occured */
358 TX2_T_ON = 1<<14,/* TX2 Timeout/Recv Timer Test On */
359 TX2_T_OFF = 1<<13,/* TX2 Timeout/Recv Timer Tst Off */
360 TX2_T_STEP = 1<<12,/* TX2 Timeout/Recv Timer Step */
361 TX1_T_EV = 1<<11,/* TX1 Timeout/Recv Event occured */
362 TX1_T_ON = 1<<10,/* TX1 Timeout/Recv Timer Test On */
363 TX1_T_OFF = 1<<9, /* TX1 Timeout/Recv Timer Tst Off */
364 TX1_T_STEP = 1<<8, /* TX1 Timeout/Recv Timer Step */
365 RX2_T_EV = 1<<7, /* RX2 Timeout/Recv Event occured */
366 RX2_T_ON = 1<<6, /* RX2 Timeout/Recv Timer Test On */
367 RX2_T_OFF = 1<<5, /* RX2 Timeout/Recv Timer Tst Off */
368 RX2_T_STEP = 1<<4, /* RX2 Timeout/Recv Timer Step */
369 RX1_T_EV = 1<<3, /* RX1 Timeout/Recv Event occured */
370 RX1_T_ON = 1<<2, /* RX1 Timeout/Recv Timer Test On */
371 RX1_T_OFF = 1<<1, /* RX1 Timeout/Recv Timer Tst Off */
372 RX1_T_STEP = 1<<0, /* RX1 Timeout/Recv Timer Step */
373 };
374
375 /* Descriptor Bit Definition */
376 /* TxCtrl Transmit Buffer Control Field */
377 /* RxCtrl Receive Buffer Control Field */
378 enum {
379 BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
380 BMU_STF = 1<<30, /* Start of Frame */
381 BMU_EOF = 1<<29, /* End of Frame */
382 BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */
383 BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */
384 /* TxCtrl specific bits */
385 BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */
386 BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
387 BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
388 /* RxCtrl specific bits */
389 BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */
390 BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */
391 BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */
392 /* Bit 23..16: BMU Check Opcodes */
393 BMU_CHECK = 0x55<<16, /* Default BMU check */
394 BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */
395 BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */
396 BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */
397 };
398
399 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
400 enum {
401 BSC_START = 1<<1, /* Start Blink Source Counter */
402 BSC_STOP = 1<<0, /* Stop Blink Source Counter */
403 };
404
405 /* B2_BSC_STAT 8 bit Blink Source Counter Status */
406 enum {
407 BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */
408 };
409
410 /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
411 enum {
412 BSC_T_ON = 1<<2, /* Test mode on */
413 BSC_T_OFF = 1<<1, /* Test mode off */
414 BSC_T_STEP = 1<<0, /* Test step */
415 };
416
417 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
418 /* Bit 31..19: reserved */
419 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
420 /* RAM Interface Registers */
421
422 /* B3_RI_CTRL 16 bit RAM Iface Control Register */
423 enum {
424 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
425 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
426
427 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
428 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
429 };
430
431 /* B3_RI_TEST 8 bit RAM Iface Test Register */
432 enum {
433 RI_T_EV = 1<<3, /* Timeout Event occured */
434 RI_T_ON = 1<<2, /* Timeout Timer Test On */
435 RI_T_OFF = 1<<1, /* Timeout Timer Test Off */
436 RI_T_STEP = 1<<0, /* Timeout Timer Step */
437 };
438
439 /* MAC Arbiter Registers */
440 /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
441 enum {
442 MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
443 MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */
444 MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
445 MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
446
447 };
448
449 /* Timeout values */
450 #define SK_MAC_TO_53 72 /* MAC arbiter timeout */
451 #define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
452 #define SK_PKT_TO_MAX 0xffff /* Maximum value */
453 #define SK_RI_TO_53 36 /* RAM interface timeout */
454
455
456 /* B3_MA_RC_CTRL 16 bit MAC Arbiter Recovery Ctrl Reg */
457 enum {
458 MA_ENA_REC_TX2 = 1<<7, /* Enable Recovery Timer TX2 */
459 MA_DIS_REC_TX2 = 1<<6, /* Disable Recovery Timer TX2 */
460 MA_ENA_REC_TX1 = 1<<5, /* Enable Recovery Timer TX1 */
461 MA_DIS_REC_TX1 = 1<<4, /* Disable Recovery Timer TX1 */
462 MA_ENA_REC_RX2 = 1<<3, /* Enable Recovery Timer RX2 */
463 MA_DIS_REC_RX2 = 1<<2, /* Disable Recovery Timer RX2 */
464 MA_ENA_REC_RX1 = 1<<1, /* Enable Recovery Timer RX1 */
465 MA_DIS_REC_RX1 = 1<<0, /* Disable Recovery Timer RX1 */
466 };
467
468 /* Packet Arbiter Registers */
469 /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
470 enum {
471 PA_CLR_TO_TX2 = 1<<13, /* Clear IRQ Packet Timeout TX2 */
472 PA_CLR_TO_TX1 = 1<<12, /* Clear IRQ Packet Timeout TX1 */
473 PA_CLR_TO_RX2 = 1<<11, /* Clear IRQ Packet Timeout RX2 */
474 PA_CLR_TO_RX1 = 1<<10, /* Clear IRQ Packet Timeout RX1 */
475 PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
476 PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
477 PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
478 PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */
479 PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
480 PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */
481 PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
482 PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */
483 PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
484 PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
485 };
486
487 #define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
488 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
489
490
491 /* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
492 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
493 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
494 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
495 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
496
497 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
498
499 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
500 enum {
501 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
502 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
503 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
504 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
505 TXA_START_RC = 1<<3, /* Start sync Rate Control */
506 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
507 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
508 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
509 };
510
511 /*
512 * Bank 4 - 5
513 */
514 /* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
515 enum {
516 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
517 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
518 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
519 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
520 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
521 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
522 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
523 };
524
525
526 enum {
527 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
528 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
529 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
530 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
531 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
532 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
533 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
534 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
535 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
536 };
537
538 /* Queue Register Offsets, use Q_ADDR() to access */
539 enum {
540 B8_Q_REGS = 0x0400, /* base of Queue registers */
541 Q_D = 0x00, /* 8*32 bit Current Descriptor */
542 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
543 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
544 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
545 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
546 Q_BC = 0x30, /* 32 bit Current Byte Counter */
547 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
548 Q_F = 0x38, /* 32 bit Flag Register */
549 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
550 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
551 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
552 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
553 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
554 Q_T2 = 0x40, /* 32 bit Test Register 2 */
555 Q_T3 = 0x44, /* 32 bit Test Register 3 */
556
557 /* Yukon-2 */
558 Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
559 Q_WM = 0x40, /* 16 bit FIFO Watermark */
560 Q_AL = 0x42, /* 8 bit FIFO Alignment */
561 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
562 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
563 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
564 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
565 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
566 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
567 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
568 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
569 };
570 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
571
572 /* RAM Buffer Register Offsets */
573 enum {
574
575 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
576 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
577 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
578 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
579 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
580 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
581 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
582 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
583 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
584 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
585 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
586 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
587 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
588 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
589 };
590
591 /* Receive and Transmit Queues */
592 enum {
593 Q_R1 = 0x0000, /* Receive Queue 1 */
594 Q_R2 = 0x0080, /* Receive Queue 2 */
595 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
596 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
597 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
598 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
599 };
600
601 /* Different MAC Types */
602 enum {
603 SK_MAC_XMAC = 0, /* Xaqti XMAC II */
604 SK_MAC_GMAC = 1, /* Marvell GMAC */
605 };
606
607 /* Different PHY Types */
608 enum {
609 SK_PHY_XMAC = 0,/* integrated in XMAC II */
610 SK_PHY_BCOM = 1,/* Broadcom BCM5400 */
611 SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/
612 SK_PHY_NAT = 3,/* National DP83891 [not supported] */
613 SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
614 SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
615 };
616
617 /* PHY addresses (bits 12..8 of PHY address reg) */
618 enum {
619 PHY_ADDR_XMAC = 0<<8,
620 PHY_ADDR_BCOM = 1<<8,
621 PHY_ADDR_LONE = 3<<8,
622 PHY_ADDR_NAT = 0<<8,
623 /* GPHY address (bits 15..11 of SMI control reg) */
624 PHY_ADDR_MARV = 0,
625 };
626
627 #define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
628
629 /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
630 enum {
631 RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
632 RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
633
634 RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
635 RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
636 RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
637 RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
638 RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
639 RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
640 RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
641 RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
642 RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
643
644 RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
645 RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
646 RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
647 RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
648
649 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
650 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
651 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
652 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
653 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
654 };
655
656 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
657 /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
658 enum {
659 MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */
660 MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */
661 MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
662 MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */
663 MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */
664 MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
665 MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */
666 MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */
667 MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
668 MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */
669 MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
670 MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
671 MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
672 MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
673 #define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT
674 };
675
676 /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
677 enum {
678 MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
679 /* Bit 14: reserved */
680 MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
681 MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
682
683 MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
684 MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
685
686 MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */
687 MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
688 MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
689 MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
690 };
691
692 #define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
693
694 /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
695 /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
696 enum {
697 MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
698 MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
699 MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
700 MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */
701 MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
702 MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */
703 MFF_PC_INC = 1<<0, /* Packet Counter Increment */
704 };
705
706 /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
707 /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
708 enum {
709 MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
710 MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
711 MFF_WP_INC = 1<<4, /* Write Pointer Increm */
712
713 MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
714 MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */
715 MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */
716 };
717
718 /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
719 /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
720 enum {
721 MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
722 MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
723 MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
724 MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
725 };
726
727
728 /* Link LED Counter Registers (GENESIS only) */
729
730 /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
731 /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
732 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
733 enum {
734 LED_START = 1<<2, /* Start Timer */
735 LED_STOP = 1<<1, /* Stop Timer */
736 LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
737 };
738
739 /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
740 /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
741 /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
742 enum {
743 LED_T_ON = 1<<2, /* LED Counter Test mode On */
744 LED_T_OFF = 1<<1, /* LED Counter Test mode Off */
745 LED_T_STEP = 1<<0, /* LED Counter Step */
746 };
747
748 /* LNK_LED_REG 8 bit Link LED Register */
749 enum {
750 LED_BLK_ON = 1<<5, /* Link LED Blinking On */
751 LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */
752 LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */
753 LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */
754 LED_ON = 1<<1, /* switch LED on */
755 LED_OFF = 1<<0, /* switch LED off */
756 };
757
758 /* Receive GMAC FIFO (YUKON and Yukon-2) */
759 enum {
760 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
761 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
762 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
763 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
764 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
765 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
766
767 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
768 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
769
770 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
771
772 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
773
774 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
775 };
776
777
778 /* TXA_TEST 8 bit Tx Arbiter Test Register */
779 enum {
780 TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
781 TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
782 TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
783 TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
784 TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
785 TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
786 };
787
788 /* TXA_STAT 8 bit Tx Arbiter Status Register */
789 enum {
790 TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */
791 };
792
793
794 /* Q_BC 32 bit Current Byte Counter */
795
796 /* BMU Control Status Registers */
797 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
798 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
799 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
800 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
801 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
802 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
803 /* Q_CSR 32 bit BMU Control/Status Register */
804
805 enum {
806 CSR_SV_IDLE = 1<<24, /* BMU SM Idle */
807
808 CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
809 CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
810 CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
811 CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
812 CSR_HPI_RUN = 1<<17, /* Release HPI SM */
813 CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
814 CSR_SV_RUN = 1<<15, /* Release Supervisor SM */
815 CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
816 CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */
817 CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
818 CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
819 CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
820 CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */
821 CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
822 CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
823 CSR_DIS_POL = 1<<6, /* Disable Descr Polling */
824 CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
825 CSR_START = 1<<4, /* Start Rx/Tx Queue */
826 CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */
827 CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */
828 CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */
829 CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */
830 };
831
832 #define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
833 CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
834 CSR_TRANS_RST)
835 #define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
836 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
837 CSR_TRANS_RUN)
838
839 /* Q_F 32 bit Flag Register */
840 enum {
841 F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
842 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
843 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
844 F_WM_REACHED = 1<<25, /* Watermark reached */
845
846 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
847 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
848 };
849
850 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
851 /* RB_START 32 bit RAM Buffer Start Address */
852 /* RB_END 32 bit RAM Buffer End Address */
853 /* RB_WP 32 bit RAM Buffer Write Pointer */
854 /* RB_RP 32 bit RAM Buffer Read Pointer */
855 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
856 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
857 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
858 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
859 /* RB_PC 32 bit RAM Buffer Packet Counter */
860 /* RB_LEV 32 bit RAM Buffer Level Register */
861
862 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
863 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
864 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
865
866 /* RB_CTRL 8 bit RAM Buffer Control Register */
867 enum {
868 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
869 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
870 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
871 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
872 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
873 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
874 };
875
876 /* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
877 enum {
878 TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
879 TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
880 TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
881 TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
882 TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
883 TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
884 TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
885 TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
886
887 TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
888 TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
889 TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
890
891 TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
892 TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
893 TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
894 TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
895 };
896
897 /* Counter and Timer constants, for a host clock of 62.5 MHz */
898 #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
899 #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
900
901 #define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
902
903 #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
904 /* 215 ms at 78.12 MHz */
905
906 #define SK_FACT_62 100 /* is given in percent */
907 #define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
908 #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
909
910
911 /* Transmit GMAC FIFO (YUKON only) */
912 enum {
913 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
914 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
915 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
916
917 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
918 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
919 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
920
921 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
922 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
923 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
924
925 /* Descriptor Poll Timer Registers */
926 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
927 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
928 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
929
930 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
931
932 /* Time Stamp Timer Registers (YUKON only) */
933 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
934 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
935 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
936 };
937
938 /* Status BMU Registers (Yukon-2 only)*/
939 enum {
940 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
941 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
942 /* 0x0e85 - 0x0e86: reserved */
943 STAT_LIST_ADDR_LO = 0x0e88,/* 32 bit Status List Start Addr (low) */
944 STAT_LIST_ADDR_HI = 0x0e8c,/* 32 bit Status List Start Addr (high) */
945 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
946 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
947 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
948 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
949 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
950 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
951
952 /* FIFO Control/Status Registers (Yukon-2 only)*/
953 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
954 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
955 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
956 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
957 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
958 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
959 STAT_FIFO_ISR_WM = 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
960
961 /* Level and ISR Timer Registers (Yukon-2 only)*/
962 STAT_LEV_TIMER_INI = 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
963 STAT_LEV_TIMER_CNT = 0x0eb4,/* 32 bit Level Timer Counter Reg */
964 STAT_LEV_TIMER_CTRL = 0x0eb8,/* 8 bit Level Timer Control Reg */
965 STAT_LEV_TIMER_TEST = 0x0eb9,/* 8 bit Level Timer Test Reg */
966 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
967 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
968 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
969 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
970 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
971 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
972 STAT_ISR_TIMER_CTRL = 0x0ed8,/* 8 bit ISR Timer Control Reg */
973 STAT_ISR_TIMER_TEST = 0x0ed9,/* 8 bit ISR Timer Test Reg */
974
975 ST_LAST_IDX_MASK = 0x007f,/* Last Index Mask */
976 ST_TXRP_IDX_MASK = 0x0fff,/* Tx Report Index Mask */
977 ST_TXTH_IDX_MASK = 0x0fff,/* Tx Threshold Index Mask */
978 ST_WM_IDX_MASK = 0x3f,/* FIFO Watermark Index Mask */
979 };
980
981 enum {
982 LINKLED_OFF = 0x01,
983 LINKLED_ON = 0x02,
984 LINKLED_LINKSYNC_OFF = 0x04,
985 LINKLED_LINKSYNC_ON = 0x08,
986 LINKLED_BLINK_OFF = 0x10,
987 LINKLED_BLINK_ON = 0x20,
988 };
989
990 /* GMAC and GPHY Control Registers (YUKON only) */
991 enum {
992 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
993 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
994 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
995 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
996 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
997
998 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
999
1000 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
1001
1002 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
1003 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
1004 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
1005 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
1006 WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
1007 WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
1008 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
1009
1010 /* WOL Pattern Length Registers (YUKON only) */
1011
1012 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
1013 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
1014
1015 /* WOL Pattern Counter Registers (YUKON only) */
1016
1017 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
1018 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
1019 };
1020
1021 enum {
1022 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
1023 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
1024 };
1025
1026 enum {
1027 BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */
1028 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
1029 BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */
1030 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
1031 };
1032
1033 /*
1034 * Receive Frame Status Encoding
1035 */
1036 enum {
1037 XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */
1038 XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/
1039 XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/
1040 XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */
1041 XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */
1042 XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */
1043
1044 XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
1045 XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
1046 XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
1047 XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
1048 XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
1049 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
1050 XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
1051 XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
1052 XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
1053 XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
1054 XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
1055 XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
1056
1057 /*
1058 * XMR_FS_ERR will be set if
1059 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
1060 * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
1061 * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
1062 * XMR_FS_ERR unless the corresponding bit in the Receive Command
1063 * Register is set.
1064 */
1065 };
1066
1067 /*
1068 ,* XMAC-PHY Registers, indirect addressed over the XMAC
1069 */
1070 enum {
1071 PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1072 PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
1073 PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1074 PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1075 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1076 PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
1077 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1078 PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1079 PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1080
1081 PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
1082 PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
1083 };
1084 /*
1085 * Broadcom-PHY Registers, indirect addressed over XMAC
1086 */
1087 enum {
1088 PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1089 PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1090 PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1091 PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1092 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1093 PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1094 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1095 PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1096 PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1097 /* Broadcom-specific registers */
1098 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1099 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1100 PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1101 PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
1102 PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
1103 PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
1104 PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
1105 PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
1106
1107 PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
1108 PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
1109 PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
1110 PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
1111 };
1112
1113 /*
1114 * Marvel-PHY Registers, indirect addressed over GMAC
1115 */
1116 enum {
1117 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1118 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1119 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1120 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1121 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1122 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1123 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1124 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1125 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1126 /* Marvel-specific registers */
1127 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1128 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1129 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1130 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
1131 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
1132 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
1133 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
1134 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
1135 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
1136 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1137 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1138 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1139 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1140 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1141 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1142 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1143 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1144 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1145
1146 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1147 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1148 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1149 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1150 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1151 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1152 };
1153
1154 /* Level One-PHY Registers, indirect addressed over XMAC */
1155 enum {
1156 PHY_LONE_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1157 PHY_LONE_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1158 PHY_LONE_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1159 PHY_LONE_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1160 PHY_LONE_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1161 PHY_LONE_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1162 PHY_LONE_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1163 PHY_LONE_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1164 PHY_LONE_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1165 /* Level One-specific registers */
1166 PHY_LONE_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1167 PHY_LONE_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1168 PHY_LONE_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1169 PHY_LONE_PORT_CFG = 0x10,/* 16 bit r/w Port Configuration Reg*/
1170 PHY_LONE_Q_STAT = 0x11,/* 16 bit r/o Quick Status Reg */
1171 PHY_LONE_INT_ENAB = 0x12,/* 16 bit r/w Interrupt Enable Reg */
1172 PHY_LONE_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
1173 PHY_LONE_LED_CFG = 0x14,/* 16 bit r/w LED Configuration Reg */
1174 PHY_LONE_PORT_CTRL = 0x15,/* 16 bit r/w Port Control Reg */
1175 PHY_LONE_CIM = 0x16,/* 16 bit r/o CIM Reg */
1176 };
1177
1178 /* National-PHY Registers, indirect addressed over XMAC */
1179 enum {
1180 PHY_NAT_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1181 PHY_NAT_STAT = 0x01,/* 16 bit r/w PHY Status Register */
1182 PHY_NAT_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1183 PHY_NAT_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1184 PHY_NAT_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1185 PHY_NAT_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Ability Reg */
1186 PHY_NAT_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1187 PHY_NAT_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1188 PHY_NAT_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner Reg */
1189 /* National-specific registers */
1190 PHY_NAT_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1191 PHY_NAT_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1192 PHY_NAT_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Register */
1193 PHY_NAT_EXT_CTRL1 = 0x10,/* 16 bit r/o Extended Control Reg1 */
1194 PHY_NAT_Q_STAT1 = 0x11,/* 16 bit r/o Quick Status Reg1 */
1195 PHY_NAT_10B_OP = 0x12,/* 16 bit r/o 10Base-T Operations Reg */
1196 PHY_NAT_EXT_CTRL2 = 0x13,/* 16 bit r/o Extended Control Reg1 */
1197 PHY_NAT_Q_STAT2 = 0x14,/* 16 bit r/o Quick Status Reg2 */
1198
1199 PHY_NAT_PHY_ADDR = 0x19,/* 16 bit r/o PHY Address Register */
1200 };
1201
1202 enum {
1203 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1204 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1205 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1206 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1207 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1208 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1209 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1210 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1211 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
1212 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1213 };
1214
1215 enum {
1216 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1217 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
1218 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
1219 };
1220
1221 enum {
1222 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
1223
1224 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
1225 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1226 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
1227 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1228 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
1229 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
1230 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
1231 };
1232
1233 enum {
1234 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1235 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
1236 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
1237 };
1238
1239 /* different Broadcom PHY Ids */
1240 enum {
1241 PHY_BCOM_ID1_A1 = 0x6041,
1242 PHY_BCOM_ID1_B2 = 0x6043,
1243 PHY_BCOM_ID1_C0 = 0x6044,
1244 PHY_BCOM_ID1_C5 = 0x6047,
1245 };
1246
1247 /* different Marvell PHY Ids */
1248 enum {
1249 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1250 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
1251 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1252 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1253 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1254 };
1255
1256 enum {
1257 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1258 PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1259 PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
1260
1261 PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */
1262 PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */
1263 PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
1264 };
1265
1266 enum {
1267 PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1268
1269 PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
1270 PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
1271 PHY_B_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1272 };
1273
1274 enum {
1275 PHY_L_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1276 /* Bit 12: reserved */
1277 PHY_L_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
1278 PHY_L_AN_PC = 1<<10, /* Bit 10: Pause Capable */
1279
1280 PHY_L_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1281 };
1282
1283 /* PHY_NAT_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement */
1284 /* PHY_NAT_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
1285 /* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */
1286 enum {
1287 PHY_N_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1288
1289 PHY_N_AN_100F = 1<<11, /* Bit 11: 100Base-T2 FD Support */
1290 PHY_N_AN_100H = 1<<10, /* Bit 10: 100Base-T2 HD Support */
1291
1292 PHY_N_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1293 };
1294
1295 /* field type definition for PHY_x_AN_SEL */
1296 enum {
1297 PHY_SEL_TYPE = 1, /* 00001 = Ethernet */
1298 };
1299
1300 enum {
1301 PHY_ANE_LP_NP = 1<<3, /* Bit 3: Link Partner can Next Page */
1302 PHY_ANE_LOC_NP = 1<<2, /* Bit 2: Local PHY can Next Page */
1303 PHY_ANE_RX_PG = 1<<1, /* Bit 1: Page Received */
1304 };
1305
1306 enum {
1307 PHY_ANE_PAR_DF = 1<<4, /* Bit 4: Parallel Detection Fault */
1308
1309 PHY_ANE_LP_CAP = 1<<0, /* Bit 0: Link Partner Auto-Neg. Cap. */
1310 };
1311
1312 enum {
1313 PHY_NP_MORE = 1<<15, /* Bit 15: More, Next Pages to follow */
1314 PHY_NP_ACK1 = 1<<14, /* Bit 14: (ro) Ack1, for receiving a message */
1315 PHY_NP_MSG_VAL = 1<<13, /* Bit 13: Message Page valid */
1316 PHY_NP_ACK2 = 1<<12, /* Bit 12: Ack2, comply with msg content */
1317 PHY_NP_TOG = 1<<11, /* Bit 11: Toggle Bit, ensure sync */
1318 PHY_NP_MSG = 0x07ff, /* Bit 10..0: Message from/to Link Partner */
1319 };
1320
1321 enum {
1322 PHY_X_EX_FD = 1<<15, /* Bit 15: Device Supports Full Duplex */
1323 PHY_X_EX_HD = 1<<14, /* Bit 14: Device Supports Half Duplex */
1324 };
1325
1326 enum {
1327 PHY_X_RS_PAUSE = 3<<7,/* Bit 8..7: selected Pause Mode */
1328 PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */
1329 PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */
1330 PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: duplex or pause cap mismatch */
1331 PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: pause capability mismatch */
1332 };
1333
1334 /** Remote Fault Bits (PHY_X_AN_RFB) encoding */
1335 enum {
1336 X_RFB_OK = 0<<12,/* Bit 13..12 No errors, Link OK */
1337 X_RFB_LF = 1<<12, /* Bit 13..12 Link Failure */
1338 X_RFB_OFF = 2<<12,/* Bit 13..12 Offline */
1339 X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
1340 };
1341
1342 /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
1343 enum {
1344 PHY_X_P_NO_PAUSE = 0<<7,/* Bit 8..7: no Pause Mode */
1345 PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
1346 PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
1347 PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
1348 };
1349
1350
1351 /* Broadcom-Specific */
1352 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1353 enum {
1354 PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1355 PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1356 PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1357 PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
1358 PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
1359 PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
1360 };
1361
1362 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1363 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1364 enum {
1365 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1366 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1367 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1368 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1369 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1370 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1371 /* Bit 9..8: reserved */
1372 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1373 };
1374
1375 /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
1376 enum {
1377 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1378 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1379 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1380 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1381 };
1382
1383 /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
1384 enum {
1385 PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
1386 PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */
1387 PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
1388 PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */
1389 PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */
1390 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
1391 PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */
1392 PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */
1393 PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */
1394 PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */
1395 PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
1396 PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */
1397 PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */
1398 PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
1399 PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */
1400 PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */
1401 };
1402
1403 /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
1404 enum {
1405 PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */
1406 PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */
1407 PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */
1408 PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */
1409 PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */
1410 PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */
1411 PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */
1412 PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */
1413 PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */
1414 PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */
1415 PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */
1416 PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */
1417 PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */
1418 PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
1419 };
1420
1421 /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
1422 enum {
1423 PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */
1424
1425 /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
1426 PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
1427 PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */
1428
1429 /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
1430 PHY_B_AC_L_SQE = 1<<15, /* Bit 15: Low Squelch */
1431 PHY_B_AC_LONG_PACK = 1<<14, /* Bit 14: Rx Long Packets */
1432 PHY_B_AC_ER_CTRL = 3<<12,/* Bit 13..12: Edgerate Control */
1433 /* Bit 11: reserved */
1434 PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */
1435 /* Bit 9.. 8: reserved */
1436 PHY_B_AC_DIS_PRF = 1<<7, /* Bit 7: dis part resp filter */
1437 /* Bit 6: reserved */
1438 PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */
1439 /* Bit 4: reserved */
1440 PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */
1441 };
1442
1443 /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
1444 enum {
1445 PHY_B_AS_AN_C = 1<<15, /* Bit 15: AutoNeg complete */
1446 PHY_B_AS_AN_CA = 1<<14, /* Bit 14: AN Complete Ack */
1447 PHY_B_AS_ANACK_D = 1<<13, /* Bit 13: AN Ack Detect */
1448 PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: AN Ability Detect */
1449 PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */
1450 PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 10..8: AN HDC */
1451 PHY_B_AS_PDF = 1<<7, /* Bit 7: Parallel Detect. Fault */
1452 PHY_B_AS_RF = 1<<6, /* Bit 6: Remote Fault */
1453 PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */
1454 PHY_B_AS_LP_ANAB = 1<<4, /* Bit 4: LP AN Ability */
1455 PHY_B_AS_LP_NPAB = 1<<3, /* Bit 3: LP Next Page Ability */
1456 PHY_B_AS_LS = 1<<2, /* Bit 2: Link Status */
1457 PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
1458 PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
1459 };
1460 #define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT)
1461
1462 /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1463 /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1464 enum {
1465 PHY_B_IS_PSE = 1<<14, /* Bit 14: Pair Swap Error */
1466 PHY_B_IS_MDXI_SC = 1<<13, /* Bit 13: MDIX Status Change */
1467 PHY_B_IS_HCT = 1<<12, /* Bit 12: counter above 32k */
1468 PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */
1469 PHY_B_IS_AN_PR = 1<<10, /* Bit 10: Page Received */
1470 PHY_B_IS_NO_HDCL = 1<<9, /* Bit 9: No HCD Link */
1471 PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: No HCD */
1472 PHY_B_IS_NEG_USHDC = 1<<7, /* Bit 7: Negotiated Unsup. HCD */
1473 PHY_B_IS_SCR_S_ER = 1<<6, /* Bit 6: Scrambler Sync Error */
1474 PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */
1475 PHY_B_IS_LRS_CHANGE = 1<<4, /* Bit 4: Local Rx Stat Change */
1476 PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */
1477 PHY_B_IS_LSP_CHANGE = 1<<2, /* Bit 2: Link Speed Change */
1478 PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */
1479 PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */
1480 };
1481 #define PHY_B_DEF_MSK (~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1482
1483 /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
1484 enum {
1485 PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */
1486 PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
1487 PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
1488 PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
1489 };
1490 /*
1491 * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
1492 */
1493 enum {
1494 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1495 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1496 };
1497
1498 /*
1499 * Level One-Specific
1500 */
1501 /***** PHY_LONE_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1502 enum {
1503 PHY_L_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1504 PHY_L_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1505 PHY_L_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1506 PHY_L_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
1507 PHY_L_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
1508 PHY_L_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
1509 };
1510
1511 /***** PHY_LONE_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1512 enum {
1513 PHY_L_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1514 PHY_L_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1515 PHY_L_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1516 PHY_L_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1517 PHY_L_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1518 PHY_L_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1519
1520 PHY_L_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1521
1522 /***** PHY_LONE_EXT_STAT 16 bit r/o Extended Status Register *****/
1523 PHY_L_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1524 PHY_L_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1525 PHY_L_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1526 PHY_L_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1527 };
1528
1529 /***** PHY_LONE_PORT_CFG 16 bit r/w Port Configuration Reg *****/
1530 enum {
1531 PHY_L_PC_REP_MODE = 1<<15, /* Bit 15: Repeater Mode */
1532
1533 PHY_L_PC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
1534 PHY_L_PC_BY_SCR = 1<<12, /* Bit 12: Bypass Scrambler */
1535 PHY_L_PC_BY_45 = 1<<11, /* Bit 11: Bypass 4B5B-Decoder */
1536 PHY_L_PC_JAB_DIS = 1<<10, /* Bit 10: Jabber Disabled */
1537 PHY_L_PC_SQE = 1<<9, /* Bit 9: Enable Heartbeat */
1538 PHY_L_PC_TP_LOOP = 1<<8, /* Bit 8: TP Loopback */
1539 PHY_L_PC_SSS = 1<<7, /* Bit 7: Smart Speed Selection */
1540 PHY_L_PC_FIFO_SIZE = 1<<6, /* Bit 6: FIFO Size */
1541 PHY_L_PC_PRE_EN = 1<<5, /* Bit 5: Preamble Enable */
1542 PHY_L_PC_CIM = 1<<4, /* Bit 4: Carrier Integrity Mon */
1543 PHY_L_PC_10_SER = 1<<3, /* Bit 3: Use Serial Output */
1544 PHY_L_PC_ANISOL = 1<<2, /* Bit 2: Unisolate Port */
1545 PHY_L_PC_TEN_BIT = 1<<1, /* Bit 1: 10bit iface mode on */
1546 PHY_L_PC_ALTCLOCK = 1<<0, /* Bit 0: (ro) ALTCLOCK Mode on */
1547 };
1548
1549 /***** PHY_LONE_Q_STAT 16 bit r/o Quick Status Reg *****/
1550 enum {
1551 PHY_L_QS_D_RATE = 3<<14,/* Bit 15..14: Data Rate */
1552 PHY_L_QS_TX_STAT = 1<<13, /* Bit 13: Transmitting */
1553 PHY_L_QS_RX_STAT = 1<<12, /* Bit 12: Receiving */
1554 PHY_L_QS_COL_STAT = 1<<11, /* Bit 11: Collision */
1555 PHY_L_QS_L_STAT = 1<<10, /* Bit 10: Link is up */
1556 PHY_L_QS_DUP_MOD = 1<<9, /* Bit 9: Full/Half Duplex */
1557 PHY_L_QS_AN = 1<<8, /* Bit 8: AutoNeg is On */
1558 PHY_L_QS_AN_C = 1<<7, /* Bit 7: AN is Complete */
1559 PHY_L_QS_LLE = 7<<4,/* Bit 6..4: Line Length Estim. */
1560 PHY_L_QS_PAUSE = 1<<3, /* Bit 3: LP advertised Pause */
1561 PHY_L_QS_AS_PAUSE = 1<<2, /* Bit 2: LP adv. asym. Pause */
1562 PHY_L_QS_ISOLATE = 1<<1, /* Bit 1: CIM Isolated */
1563 PHY_L_QS_EVENT = 1<<0, /* Bit 0: Event has occurred */
1564 };
1565
1566 /***** PHY_LONE_INT_ENAB 16 bit r/w Interrupt Enable Reg *****/
1567 /***** PHY_LONE_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1568 enum {
1569 PHY_L_IS_AN_F = 1<<13, /* Bit 13: Auto-Negotiation fault */
1570 PHY_L_IS_CROSS = 1<<11, /* Bit 11: Crossover used */
1571 PHY_L_IS_POL = 1<<10, /* Bit 10: Polarity correct. used */
1572 PHY_L_IS_SS = 1<<9, /* Bit 9: Smart Speed Downgrade */
1573 PHY_L_IS_CFULL = 1<<8, /* Bit 8: Counter Full */
1574 PHY_L_IS_AN_C = 1<<7, /* Bit 7: AutoNeg Complete */
1575 PHY_L_IS_SPEED = 1<<6, /* Bit 6: Speed Changed */
1576 PHY_L_IS_DUP = 1<<5, /* Bit 5: Duplex Changed */
1577 PHY_L_IS_LS = 1<<4, /* Bit 4: Link Status Changed */
1578 PHY_L_IS_ISOL = 1<<3, /* Bit 3: Isolate Occured */
1579 PHY_L_IS_MDINT = 1<<2, /* Bit 2: (ro) STAT: MII Int Pending */
1580 PHY_L_IS_INTEN = 1<<1, /* Bit 1: ENAB: Enable IRQs */
1581 PHY_L_IS_FORCE = 1<<0, /* Bit 0: ENAB: Force Interrupt */
1582 };
1583
1584 /* int. mask */
1585 #define PHY_L_DEF_MSK (PHY_L_IS_LS | PHY_L_IS_ISOL | PHY_L_IS_INTEN)
1586
1587 /***** PHY_LONE_LED_CFG 16 bit r/w LED Configuration Reg *****/
1588 enum {
1589 PHY_L_LC_LEDC = 3<<14,/* Bit 15..14: Col/Blink/On/Off */
1590 PHY_L_LC_LEDR = 3<<12,/* Bit 13..12: Rx/Blink/On/Off */
1591 PHY_L_LC_LEDT = 3<<10,/* Bit 11..10: Tx/Blink/On/Off */
1592 PHY_L_LC_LEDG = 3<<8,/* Bit 9..8: Giga/Blink/On/Off */
1593 PHY_L_LC_LEDS = 3<<6,/* Bit 7..6: 10-100/Blink/On/Off */
1594 PHY_L_LC_LEDL = 3<<4,/* Bit 5..4: Link/Blink/On/Off */
1595 PHY_L_LC_LEDF = 3<<2,/* Bit 3..2: Duplex/Blink/On/Off */
1596 PHY_L_LC_PSTRECH= 1<<1, /* Bit 1: Strech LED Pulses */
1597 PHY_L_LC_FREQ = 1<<0, /* Bit 0: 30/100 ms */
1598 };
1599
1600 /***** PHY_LONE_PORT_CTRL 16 bit r/w Port Control Reg *****/
1601 enum {
1602 PHY_L_PC_TX_TCLK = 1<<15, /* Bit 15: Enable TX_TCLK */
1603 PHY_L_PC_ALT_NP = 1<<13, /* Bit 14: Alternate Next Page */
1604 PHY_L_PC_GMII_ALT= 1<<12, /* Bit 13: Alternate GMII driver */
1605 PHY_L_PC_TEN_CRS = 1<<10, /* Bit 10: Extend CRS*/
1606 };
1607
1608 /***** PHY_LONE_CIM 16 bit r/o CIM Reg *****/
1609 enum {
1610 PHY_L_CIM_ISOL = 0xff<<8,/* Bit 15..8: Isolate Count */
1611 PHY_L_CIM_FALSE_CAR = 0xff, /* Bit 7..0: False Carrier Count */
1612 };
1613
1614 /*
1615 * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding
1616 */
1617 enum {
1618 PHY_L_P_NO_PAUSE= 0<<10,/* Bit 11..10: no Pause Mode */
1619 PHY_L_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
1620 PHY_L_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
1621 PHY_L_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
1622 };
1623
1624 /*
1625 * National-Specific
1626 */
1627 /***** PHY_NAT_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1628 enum {
1629 PHY_N_1000C_TEST= 7<<13,/* Bit 15..13: Test Modes */
1630 PHY_N_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1631 PHY_N_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1632 PHY_N_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
1633 PHY_N_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
1634 PHY_N_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
1635 PHY_N_1000C_APC = 1<<7, /* Bit 7: Asymmetric Pause Cap. */};
1636
1637
1638 /***** PHY_NAT_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1639 enum {
1640 PHY_N_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1641 PHY_N_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1642 PHY_N_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1643 PHY_N_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status*/
1644 PHY_N_1000S_LP_FD= 1<<11, /* Bit 11: Link Partner can FD */
1645 PHY_N_1000S_LP_HD= 1<<10, /* Bit 10: Link Partner can HD */
1646 PHY_N_1000C_LP_APC= 1<<9, /* Bit 9: LP Asym. Pause Cap. */
1647 PHY_N_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1648 };
1649
1650 /***** PHY_NAT_EXT_STAT 16 bit r/o Extended Status Register *****/
1651 enum {
1652 PHY_N_ES_X_FD_CAP= 1<<15, /* Bit 15: 1000Base-X FD capable */
1653 PHY_N_ES_X_HD_CAP= 1<<14, /* Bit 14: 1000Base-X HD capable */
1654 PHY_N_ES_T_FD_CAP= 1<<13, /* Bit 13: 1000Base-T FD capable */
1655 PHY_N_ES_T_HD_CAP= 1<<12, /* Bit 12: 1000Base-T HD capable */
1656 };
1657
1658 /** Marvell-Specific */
1659 enum {
1660 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
1661 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
1662 PHY_M_AN_RF = 1<<13, /* Remote Fault */
1663
1664 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1665 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
1666 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1667 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1668 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1669 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1670 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1671 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1672 };
1673
1674 /* special defines for FIBER (88E1011S only) */
1675 enum {
1676 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1677 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1678 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1679 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1680 };
1681
1682 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1683 enum {
1684 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1685 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1686 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1687 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1688 };
1689
1690 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1691 enum {
1692 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1693 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1694 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1695 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1696 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1697 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1698 };
1699
1700 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1701 enum {
1702 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1703 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1704 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1705 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1706 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1707 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1708 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1709 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1710 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1711 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1712 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1713 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1714 };
1715
1716 enum {
1717 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1718 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1719 };
1720
1721 #define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
1722
1723 enum {
1724 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1725 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1726 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1727 };
1728
1729 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1730 enum {
1731 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1732 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1733 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1734 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1735 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1736
1737 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1738 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1739
1740 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1741 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1742 };
1743
1744 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1745 enum {
1746 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1747 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1748 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1749 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1750 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1751 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1752 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1753 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1754 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1755 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1756 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1757 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1758 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1759 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1760 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1761 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1762 };
1763
1764 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1765
1766 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1767 enum {
1768 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1769 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1770 };
1771
1772 enum {
1773 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1774 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1775 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1776 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1777 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1778 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1779 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1780 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1781 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1782 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1783 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1784 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1785
1786 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1787 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1788 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1789 };
1790
1791 #define PHY_M_DEF_MSK ( PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE | \
1792 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
1793
1794 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1795 enum {
1796 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1797 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1798
1799 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1800 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1801 /* (88E1011 only) */
1802 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1803 /* (88E1011 only) */
1804 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1805 /* (88E1111 only) */
1806 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1807 /* !!! Errata in spec. (1 = disable) */
1808 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1809 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1810 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1811 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1812 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1813 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1814
1815 #define PHY_M_EC_M_DSC(x) ((x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
1816 #define PHY_M_EC_S_DSC(x) ((x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
1817 #define PHY_M_EC_MAC_S(x) ((x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
1818
1819 #define PHY_M_EC_M_DSC_2(x) ((x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
1820 /* 100=5x; 101=6x; 110=7x; 111=8x */
1821 enum {
1822 MAC_TX_CLK_0_MHZ = 2,
1823 MAC_TX_CLK_2_5_MHZ = 6,
1824 MAC_TX_CLK_25_MHZ = 7,
1825 };
1826
1827 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1828 enum {
1829 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1830 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1831 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1832 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1833 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1834 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1835 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1836 /* (88E1111 only) */
1837 };
1838
1839 enum {
1840 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1841 /* (88E1011 only) */
1842 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1843 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1844 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1845 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1846 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1847 };
1848
1849 #define PHY_M_LED_PULS_DUR(x) ( ((x)<<12) & PHY_M_LEDC_PULS_MSK)
1850
1851 enum {
1852 PULS_NO_STR = 0,/* no pulse stretching */
1853 PULS_21MS = 1,/* 21 ms to 42 ms */
1854 PULS_42MS = 2,/* 42 ms to 84 ms */
1855 PULS_84MS = 3,/* 84 ms to 170 ms */
1856 PULS_170MS = 4,/* 170 ms to 340 ms */
1857 PULS_340MS = 5,/* 340 ms to 670 ms */
1858 PULS_670MS = 6,/* 670 ms to 1.3 s */
1859 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1860 };
1861
1862 #define PHY_M_LED_BLINK_RT(x) ( ((x)<<8) & PHY_M_LEDC_BL_R_MSK)
1863
1864 enum {
1865 BLINK_42MS = 0,/* 42 ms */
1866 BLINK_84MS = 1,/* 84 ms */
1867 BLINK_170MS = 2,/* 170 ms */
1868 BLINK_340MS = 3,/* 340 ms */
1869 BLINK_670MS = 4,/* 670 ms */
1870 };
1871
1872 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1873 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1874 /* Bit 13..12: reserved */
1875 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1876 #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1877 #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1878 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1879 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1880 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1881
1882 enum {
1883 MO_LED_NORM = 0,
1884 MO_LED_BLINK = 1,
1885 MO_LED_OFF = 2,
1886 MO_LED_ON = 3,
1887 };
1888
1889 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1890 enum {
1891 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1892 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1893 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1894 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1895 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1896 };
1897
1898 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1899 enum {
1900 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1901 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1902 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1903 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1904 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1905 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1906 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1907 /* (88E1111 only) */
1908 /* Bit 9.. 4: reserved (88E1011 only) */
1909 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1910 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1911 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1912 };
1913
1914 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
1915 enum {
1916 PHY_M_CABD_ENA_TEST = 1<<15, /* Enable Test (Page 0) */
1917 PHY_M_CABD_DIS_WAIT = 1<<15, /* Disable Waiting Period (Page 1) */
1918 /* (88E1111 only) */
1919 PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */
1920 PHY_M_CABD_AMPL_MSK = 0x1f<<8,/* Bit 12.. 8: Amplitude Mask */
1921 /* (88E1111 only) */
1922 PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */
1923 };
1924
1925 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
1926 enum {
1927 CABD_STAT_NORMAL= 0,
1928 CABD_STAT_SHORT = 1,
1929 CABD_STAT_OPEN = 2,
1930 CABD_STAT_FAIL = 3,
1931 };
1932
1933 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1934 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1935 /* Bit 15..12: reserved (used internally) */
1936 enum {
1937 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1938 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1939 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1940 };
1941
1942 #define PHY_M_FELP_LED2_CTRL(x) ( ((x)<<8) & PHY_M_FELP_LED2_MSK)
1943 #define PHY_M_FELP_LED1_CTRL(x) ( ((x)<<4) & PHY_M_FELP_LED1_MSK)
1944 #define PHY_M_FELP_LED0_CTRL(x) ( ((x)<<0) & PHY_M_FELP_LED0_MSK)
1945
1946 enum {
1947 LED_PAR_CTRL_COLX = 0x00,
1948 LED_PAR_CTRL_ERROR = 0x01,
1949 LED_PAR_CTRL_DUPLEX = 0x02,
1950 LED_PAR_CTRL_DP_COL = 0x03,
1951 LED_PAR_CTRL_SPEED = 0x04,
1952 LED_PAR_CTRL_LINK = 0x05,
1953 LED_PAR_CTRL_TX = 0x06,
1954 LED_PAR_CTRL_RX = 0x07,
1955 LED_PAR_CTRL_ACT = 0x08,
1956 LED_PAR_CTRL_LNK_RX = 0x09,
1957 LED_PAR_CTRL_LNK_AC = 0x0a,
1958 LED_PAR_CTRL_ACT_BL = 0x0b,
1959 LED_PAR_CTRL_TX_BL = 0x0c,
1960 LED_PAR_CTRL_RX_BL = 0x0d,
1961 LED_PAR_CTRL_COL_BL = 0x0e,
1962 LED_PAR_CTRL_INACT = 0x0f
1963 };
1964
1965 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1966 enum {
1967 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1968 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1969 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1970 };
1971
1972 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1973 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1974 enum {
1975 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1976 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1977 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1978 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1979 };
1980 #define PHY_M_MAC_MODE_SEL(x) ( ((x)<<7) & PHY_M_MAC_MD_MSK)
1981
1982 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1983 enum {
1984 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1985 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1986 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1987 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1988 };
1989
1990 #define PHY_M_LEDC_LOS_CTRL(x) ( ((x)<<12) & PHY_M_LEDC_LOS_MSK)
1991 #define PHY_M_LEDC_INIT_CTRL(x) ( ((x)<<8) & PHY_M_LEDC_INIT_MSK)
1992 #define PHY_M_LEDC_STA1_CTRL(x) ( ((x)<<4) & PHY_M_LEDC_STA1_MSK)
1993 #define PHY_M_LEDC_STA0_CTRL(x) ( ((x)<<0) & PHY_M_LEDC_STA0_MSK)
1994
1995 /* GMAC registers */
1996 /* Port Registers */
1997 enum {
1998 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1999 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
2000 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
2001 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
2002 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
2003 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
2004 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
2005 /* Source Address Registers */
2006 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
2007 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
2008 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
2009 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
2010 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
2011 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
2012
2013 /* Multicast Address Hash Registers */
2014 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
2015 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
2016 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
2017 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
2018
2019 /* Interrupt Source Registers */
2020 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
2021 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
2022 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
2023
2024 /* Interrupt Mask Registers */
2025 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
2026 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
2027 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
2028
2029 /* Serial Management Interface (SMI) Registers */
2030 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
2031 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
2032 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
2033 };
2034
2035 /* MIB Counters */
2036 #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
2037 #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
2038
2039 /*
2040 * MIB Counters base address definitions (low word) -
2041 * use offset 4 for access to high word (32 bit r/o)
2042 */
2043 enum {
2044 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
2045 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
2046 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
2047 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
2048 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
2049 /* GM_MIB_CNT_BASE + 40: reserved */
2050 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
2051 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
2052 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
2053 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
2054 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
2055 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
2056 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
2057 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
2058 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
2059 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
2060 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
2061 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
2062 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
2063 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
2064 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
2065 /* GM_MIB_CNT_BASE + 168: reserved */
2066 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
2067 /* GM_MIB_CNT_BASE + 184: reserved */
2068 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
2069 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
2070 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
2071 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
2072 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
2073 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
2074 GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
2075 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
2076 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
2077 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
2078 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
2079 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
2080 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
2081
2082 GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
2083 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
2084 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
2085 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
2086 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
2087 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
2088 };
2089
2090 /* GMAC Bit Definitions */
2091 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
2092 enum {
2093 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
2094 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
2095 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
2096 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
2097 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
2098 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
2099 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
2100 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
2101
2102 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
2103 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
2104 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
2105 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
2106 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
2107 };
2108
2109 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
2110 enum {
2111 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
2112 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
2113 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
2114 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
2115 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
2116 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
2117 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
2118 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
2119 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
2120 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
2121 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
2122 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
2123 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
2124 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
2125 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
2126 };
2127
2128 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
2129 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
2130
2131 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
2132 enum {
2133 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
2134 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
2135 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
2136 GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */
2137 };
2138
2139 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
2140 #define TX_COL_DEF 0x04
2141
2142 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
2143 enum {
2144 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
2145 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
2146 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
2147 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
2148 };
2149
2150 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
2151 enum {
2152 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
2153 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
2154 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
2155
2156 TX_JAM_LEN_DEF = 0x03,
2157 TX_JAM_IPG_DEF = 0x0b,
2158 TX_IPG_JAM_DEF = 0x1c,
2159 };
2160
2161 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
2162 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
2163 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
2164
2165
2166 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
2167 enum {
2168 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
2169 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
2170 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
2171 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
2172 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
2173 };
2174
2175 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
2176 #define DATA_BLIND_DEF 0x04
2177
2178 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
2179 #define IPG_DATA_DEF 0x1e
2180
2181 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
2182 enum {
2183 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
2184 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
2185 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
2186 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
2187 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
2188 };
2189
2190 #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
2191 #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
2192
2193 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
2194 enum {
2195 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
2196 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
2197 };
2198
2199 /* Receive Frame Status Encoding */
2200 enum {
2201 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
2202 GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */
2203 GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */
2204 GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
2205 GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */
2206 GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */
2207 GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */
2208 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
2209 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
2210 GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
2211 GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */
2212 GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */
2213
2214 GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */
2215 GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */
2216
2217 /*
2218 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
2219 */
2220 GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
2221 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
2222 GMR_FS_JABBER,
2223 /* Rx GMAC FIFO Flush Mask (default) */
2224 RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
2225 GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE |
2226 GMR_FS_JABBER,
2227 };
2228
2229 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
2230 enum {
2231 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
2232 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
2233 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
2234
2235 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
2236 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
2237 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
2238 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
2239 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
2240 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
2241 GMF_CLI_RX_FC = 1<<4, /* Clear IRQ Rx Frame Complete */
2242 GMF_OPER_ON = 1<<3, /* Operational Mode On */
2243 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
2244 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
2245 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
2246
2247 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
2248 };
2249
2250
2251 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
2252 enum {
2253 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
2254 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
2255 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
2256
2257 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
2258 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
2259 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
2260 };
2261
2262 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
2263 enum {
2264 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
2265 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
2266 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
2267 };
2268
2269 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
2270 enum {
2271 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
2272 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
2273 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
2274 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
2275 GMC_PAUSE_ON = 1<<3, /* Pause On */
2276 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
2277 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
2278 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
2279 };
2280
2281 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
2282 enum {
2283 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
2284 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
2285 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
2286 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
2287 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
2288 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
2289 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
2290 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
2291 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
2292 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
2293 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
2294 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
2295 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
2296 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
2297 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
2298 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
2299 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
2300 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
2301 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
2302 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
2303 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
2304 /* Bits 7..2: reserved */
2305 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
2306 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
2307 };
2308
2309 #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
2310 #define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
2311 #define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)
2312
2313 /* forced speed and duplex mode (don't mix with other ANEG bits) */
2314 #define GPC_FRC10MBIT_HALF 0
2315 #define GPC_FRC10MBIT_FULL GPC_ANEG_0
2316 #define GPC_FRC100MBIT_HALF GPC_ANEG_1
2317 #define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1)
2318
2319 /* auto-negotiation with limited advertised speeds */
2320 /* mix only with master/slave settings (for copper) */
2321 #define GPC_ADV_1000_HALF GPC_ANEG_2
2322 #define GPC_ADV_1000_FULL GPC_ANEG_3
2323 #define GPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3)
2324
2325 /* master/slave settings */
2326 /* only for copper with 1000 Mbps */
2327 #define GPC_FORCE_MASTER 0
2328 #define GPC_FORCE_SLAVE GPC_ANEG_0
2329 #define GPC_PREF_MASTER GPC_ANEG_1
2330 #define GPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0)
2331
2332 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
2333 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
2334 enum {
2335 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
2336 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
2337 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
2338 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
2339 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
2340 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
2341
2342 #define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | GM_IS_TX_FF_UR)
2343
2344 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
2345 /* Bits 15.. 2: reserved */
2346 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
2347 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
2348
2349
2350 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
2351 WOL_CTL_LINK_CHG_OCC = 1<<15,
2352 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
2353 WOL_CTL_PATTERN_OCC = 1<<13,
2354 WOL_CTL_CLEAR_RESULT = 1<<12,
2355 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
2356 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
2357 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
2358 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
2359 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
2360 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
2361 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
2362 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
2363 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
2364 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
2365 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
2366 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
2367 };
2368
2369 #define WOL_CTL_DEFAULT \
2370 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
2371 WOL_CTL_DIS_PME_ON_PATTERN | \
2372 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
2373 WOL_CTL_DIS_LINK_CHG_UNIT | \
2374 WOL_CTL_DIS_PATTERN_UNIT | \
2375 WOL_CTL_DIS_MAGIC_PKT_UNIT)
2376
2377 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
2378 #define WOL_CTL_PATT_ENA(x) (1 << (x))
2379
2380
2381 /* XMAC II registers */
2382 enum {
2383 XM_MMU_CMD = 0x0000, /* 16 bit r/w MMU Command Register */
2384 XM_POFF = 0x0008, /* 32 bit r/w Packet Offset Register */
2385 XM_BURST = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
2386 XM_1L_VLAN_TAG = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
2387 XM_2L_VLAN_TAG = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
2388 XM_TX_CMD = 0x0020, /* 16 bit r/w Transmit Command Register */
2389 XM_TX_RT_LIM = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
2390 XM_TX_STIME = 0x0028, /* 16 bit r/w Transmit Slottime Register */
2391 XM_TX_IPG = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
2392 XM_RX_CMD = 0x0030, /* 16 bit r/w Receive Command Register */
2393 XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */
2394 XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */
2395 XM_GP_PORT = 0x0040, /* 32 bit r/w General Purpose Port Register */
2396 XM_IMSK = 0x0044, /* 16 bit r/w Interrupt Mask Register */
2397 XM_ISRC = 0x0048, /* 16 bit r/o Interrupt Status Register */
2398 XM_HW_CFG = 0x004c, /* 16 bit r/w Hardware Config Register */
2399 XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
2400 XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
2401 XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */
2402 XM_HT_THR = 0x0066, /* 16 bit r/w Host Request Threshold */
2403 XM_PAUSE_DA = 0x0068, /* NA reg r/w Pause Destination Address */
2404 XM_CTL_PARA = 0x0070, /* 32 bit r/w Control Parameter Register */
2405 XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
2406 XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
2407 XM_TX_STAT = 0x0078, /* 32 bit r/o Tx Status LIFO Register */
2408
2409 XM_EXM_START = 0x0080, /* r/w Start Address of the EXM Regs */
2410 #define XM_EXM(reg) (XM_EXM_START + ((reg) << 3))
2411 };
2412
2413 enum {
2414 XM_SRC_CHK = 0x0100, /* NA reg r/w Source Check Address Register */
2415 XM_SA = 0x0108, /* NA reg r/w Station Address Register */
2416 XM_HSM = 0x0110, /* 64 bit r/w Hash Match Address Registers */
2417 XM_RX_LO_WM = 0x0118, /* 16 bit r/w Receive Low Water Mark */
2418 XM_RX_HI_WM = 0x011a, /* 16 bit r/w Receive High Water Mark */
2419 XM_RX_THR = 0x011c, /* 32 bit r/w Receive Request Threshold */
2420 XM_DEV_ID = 0x0120, /* 32 bit r/o Device ID Register */
2421 XM_MODE = 0x0124, /* 32 bit r/w Mode Register */
2422 XM_LSA = 0x0128, /* NA reg r/o Last Source Register */
2423 XM_TS_READ = 0x0130, /* 32 bit r/o Time Stamp Read Register */
2424 XM_TS_LOAD = 0x0134, /* 32 bit r/o Time Stamp Load Value */
2425 XM_STAT_CMD = 0x0200, /* 16 bit r/w Statistics Command Register */
2426 XM_RX_CNT_EV = 0x0204, /* 32 bit r/o Rx Counter Event Register */
2427 XM_TX_CNT_EV = 0x0208, /* 32 bit r/o Tx Counter Event Register */
2428 XM_RX_EV_MSK = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
2429 XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
2430 XM_TXF_OK = 0x0280, /* 32 bit r/o Frames Transmitted OK Conuter */
2431 XM_TXO_OK_HI = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/
2432 XM_TXO_OK_LO = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */
2433 XM_TXF_BC_OK = 0x028c, /* 32 bit r/o Broadcast Frames Xmitted OK */
2434 XM_TXF_MC_OK = 0x0290, /* 32 bit r/o Multicast Frames Xmitted OK */
2435 XM_TXF_UC_OK = 0x0294, /* 32 bit r/o Unicast Frames Xmitted OK */
2436 XM_TXF_LONG = 0x0298, /* 32 bit r/o Tx Long Frame Counter */
2437 XM_TXE_BURST = 0x029c, /* 32 bit r/o Tx Burst Event Counter */
2438 XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
2439 XM_TXF_MCTRL = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
2440 XM_TXF_SNG_COL = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */
2441 XM_TXF_MUL_COL = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */
2442 XM_TXF_ABO_COL = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */
2443 XM_TXF_LAT_COL = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */
2444 XM_TXF_DEF = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */
2445 XM_TXF_EX_DEF = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */
2446 XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
2447 XM_TXE_CS_ERR = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
2448 XM_TXP_UTIL = 0x02c8, /* 32 bit r/o Tx Utilization in % */
2449 XM_TXF_64B = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */
2450 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2451 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2452 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2453 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2454 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2455 XM_RXF_OK = 0x0300, /* 32 bit r/o Frames Received OK */
2456 XM_RXO_OK_HI = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */
2457 XM_RXO_OK_LO = 0x0308, /* 32 bit r/o Octets Received OK Low Counter*/
2458 XM_RXF_BC_OK = 0x030c, /* 32 bit r/o Broadcast Frames Received OK */
2459 XM_RXF_MC_OK = 0x0310, /* 32 bit r/o Multicast Frames Received OK */
2460 XM_RXF_UC_OK = 0x0314, /* 32 bit r/o Unicast Frames Received OK */
2461 XM_RXF_MPAUSE = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
2462 XM_RXF_MCTRL = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */
2463 XM_RXF_INV_MP = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */
2464 XM_RXF_INV_MOC = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
2465 XM_RXE_BURST = 0x0328, /* 32 bit r/o Rx Burst Event Counter */
2466 XM_RXE_FMISS = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */
2467 XM_RXF_FRA_ERR = 0x0330, /* 32 bit r/o Rx Framing Error Counter */
2468 XM_RXE_FIFO_OV = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */
2469 XM_RXF_JAB_PKT = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */
2470 XM_RXE_CAR_ERR = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */
2471 XM_RXF_LEN_ERR = 0x0340, /* 32 bit r/o Rx in Range Length Error */
2472 XM_RXE_SYM_ERR = 0x0344, /* 32 bit r/o Rx Symbol Error Counter */
2473 XM_RXE_SHT_ERR = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */
2474 XM_RXE_RUNT = 0x034c, /* 32 bit r/o Rx Runt Event Counter */
2475 XM_RXF_LNG_ERR = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */
2476 XM_RXF_FCS_ERR = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
2477 XM_RXF_CEX_ERR = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
2478 XM_RXP_UTIL = 0x0360, /* 32 bit r/o Rx Utilization in % */
2479 XM_RXF_64B = 0x0368, /* 32 bit r/o 64 Byte Rx Frame Counter */
2480 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2481 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2482 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2483 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2484 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2485 };
2486
2487 /* XM_MMU_CMD 16 bit r/w MMU Command Register */
2488 enum {
2489 XM_MMU_PHY_RDY = 1<<12,/* Bit 12: PHY Read Ready */
2490 XM_MMU_PHY_BUSY = 1<<11,/* Bit 11: PHY Busy */
2491 XM_MMU_IGN_PF = 1<<10,/* Bit 10: Ignore Pause Frame */
2492 XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
2493 XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */
2494 XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */
2495 XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */
2496 XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */
2497 XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */
2498 XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
2499 XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */
2500 XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */
2501 };
2502
2503
2504 /* XM_TX_CMD 16 bit r/w Transmit Command Register */
2505 enum {
2506 XM_TX_BK2BK = 1<<6, /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/
2507 XM_TX_ENC_BYP = 1<<5, /* Bit 5: Set Encoder in Bypass Mode */
2508 XM_TX_SAM_LINE = 1<<4, /* Bit 4: (sc) Start utilization calculation */
2509 XM_TX_NO_GIG_MD = 1<<3, /* Bit 3: Disable Carrier Extension */
2510 XM_TX_NO_PRE = 1<<2, /* Bit 2: Disable Preamble Generation */
2511 XM_TX_NO_CRC = 1<<1, /* Bit 1: Disable CRC Generation */
2512 XM_TX_AUTO_PAD = 1<<0, /* Bit 0: Enable Automatic Padding */
2513 };
2514
2515 /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
2516 #define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */
2517
2518
2519 /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
2520 #define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */
2521
2522
2523 /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
2524 #define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */
2525
2526
2527 /* XM_RX_CMD 16 bit r/w Receive Command Register */
2528 enum {
2529 XM_RX_LENERR_OK = 1<<8, /* Bit 8 don't set Rx Err bit for */
2530 /* inrange error packets */
2531 XM_RX_BIG_PK_OK = 1<<7, /* Bit 7 don't set Rx Err bit for */
2532 /* jumbo packets */
2533 XM_RX_IPG_CAP = 1<<6, /* Bit 6 repl. type field with IPG */
2534 XM_RX_TP_MD = 1<<5, /* Bit 5: Enable transparent Mode */
2535 XM_RX_STRIP_FCS = 1<<4, /* Bit 4: Enable FCS Stripping */
2536 XM_RX_SELF_RX = 1<<3, /* Bit 3: Enable Rx of own packets */
2537 XM_RX_SAM_LINE = 1<<2, /* Bit 2: (sc) Start utilization calculation */
2538 XM_RX_STRIP_PAD = 1<<1, /* Bit 1: Strip pad bytes of Rx frames */
2539 XM_RX_DIS_CEXT = 1<<0, /* Bit 0: Disable carrier ext. check */
2540 };
2541
2542
2543 /* XM_PHY_ADDR 16 bit r/w PHY Address Register */
2544 #define XM_PHY_ADDR_SZ 0x1f /* Bit 4..0: PHY Address bits */
2545
2546
2547 /* XM_GP_PORT 32 bit r/w General Purpose Port Register */
2548 enum {
2549 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
2550 XM_GP_FRC_INT = 1<<5, /* Bit 5: (sc) Force Interrupt */
2551 XM_GP_RES_MAC = 1<<3, /* Bit 3: (sc) Reset MAC and FIFOs */
2552 XM_GP_RES_STAT = 1<<2, /* Bit 2: (sc) Reset the statistics module */
2553 XM_GP_INP_ASS = 1<<0, /* Bit 0: (ro) GP Input Pin asserted */
2554 };
2555
2556
2557 /* XM_IMSK 16 bit r/w Interrupt Mask Register */
2558 /* XM_ISRC 16 bit r/o Interrupt Status Register */
2559 enum {
2560 XM_IS_LNK_AE = 1<<14, /* Bit 14: Link Asynchronous Event */
2561 XM_IS_TX_ABORT = 1<<13, /* Bit 13: Transmit Abort, late Col. etc */
2562 XM_IS_FRC_INT = 1<<12, /* Bit 12: Force INT bit set in GP */
2563 XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */
2564 XM_IS_LIPA_RC = 1<<10, /* Bit 10: Link Partner requests config */
2565 XM_IS_RX_PAGE = 1<<9, /* Bit 9: Page Received */
2566 XM_IS_TX_PAGE = 1<<8, /* Bit 8: Next Page Loaded for Transmit */
2567 XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
2568 XM_IS_TSC_OV = 1<<6, /* Bit 6: Time Stamp Counter Overflow */
2569 XM_IS_RXC_OV = 1<<5, /* Bit 5: Rx Counter Event Overflow */
2570 XM_IS_TXC_OV = 1<<4, /* Bit 4: Tx Counter Event Overflow */
2571 XM_IS_RXF_OV = 1<<3, /* Bit 3: Receive FIFO Overflow */
2572 XM_IS_TXF_UR = 1<<2, /* Bit 2: Transmit FIFO Underrun */
2573 XM_IS_TX_COMP = 1<<1, /* Bit 1: Frame Tx Complete */
2574 XM_IS_RX_COMP = 1<<0, /* Bit 0: Frame Rx Complete */
2575 };
2576
2577 #define XM_DEF_MSK (~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | \
2578 XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV | \
2579 XM_IS_RXF_OV | XM_IS_TXF_UR))
2580
2581
2582 /* XM_HW_CFG 16 bit r/w Hardware Config Register */
2583 enum {
2584 XM_HW_GEN_EOP = 1<<3, /* Bit 3: generate End of Packet pulse */
2585 XM_HW_COM4SIG = 1<<2, /* Bit 2: use Comma Detect for Sig. Det.*/
2586 XM_HW_GMII_MD = 1<<0, /* Bit 0: GMII Interface selected */
2587 };
2588
2589
2590 /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
2591 /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
2592 #define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
2593
2594 /* XM_TX_THR 16 bit r/w Tx Request Threshold */
2595 /* XM_HT_THR 16 bit r/w Host Request Threshold */
2596 /* XM_RX_THR 16 bit r/w Rx Request Threshold */
2597 #define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */
2598
2599
2600 /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */
2601 enum {
2602 XM_ST_VALID = (1UL<<31), /* Bit 31: Status Valid */
2603 XM_ST_BYTE_CNT = (0x3fffL<<17), /* Bit 30..17: Tx frame Length */
2604 XM_ST_RETRY_CNT = (0x1fL<<12), /* Bit 16..12: Retry Count */
2605 XM_ST_EX_COL = 1<<11, /* Bit 11: Excessive Collisions */
2606 XM_ST_EX_DEF = 1<<10, /* Bit 10: Excessive Deferral */
2607 XM_ST_BURST = 1<<9, /* Bit 9: p. xmitted in burst md*/
2608 XM_ST_DEFER = 1<<8, /* Bit 8: packet was defered */
2609 XM_ST_BC = 1<<7, /* Bit 7: Broadcast packet */
2610 XM_ST_MC = 1<<6, /* Bit 6: Multicast packet */
2611 XM_ST_UC = 1<<5, /* Bit 5: Unicast packet */
2612 XM_ST_TX_UR = 1<<4, /* Bit 4: FIFO Underrun occured */
2613 XM_ST_CS_ERR = 1<<3, /* Bit 3: Carrier Sense Error */
2614 XM_ST_LAT_COL = 1<<2, /* Bit 2: Late Collision Error */
2615 XM_ST_MUL_COL = 1<<1, /* Bit 1: Multiple Collisions */
2616 XM_ST_SGN_COL = 1<<0, /* Bit 0: Single Collision */
2617 };
2618
2619 /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
2620 /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
2621 #define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
2622
2623
2624 /* XM_DEV_ID 32 bit r/o Device ID Register */
2625 #define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */
2626 #define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */
2627
2628
2629 /* XM_MODE 32 bit r/w Mode Register */
2630 enum {
2631 XM_MD_ENA_REJ = 1<<26, /* Bit 26: Enable Frame Reject */
2632 XM_MD_SPOE_E = 1<<25, /* Bit 25: Send Pause on Edge */
2633 /* extern generated */
2634 XM_MD_TX_REP = 1<<24, /* Bit 24: Transmit Repeater Mode */
2635 XM_MD_SPOFF_I = 1<<23, /* Bit 23: Send Pause on FIFO full */
2636 /* intern generated */
2637 XM_MD_LE_STW = 1<<22, /* Bit 22: Rx Stat Word in Little Endian */
2638 XM_MD_TX_CONT = 1<<21, /* Bit 21: Send Continuous */
2639 XM_MD_TX_PAUSE = 1<<20, /* Bit 20: (sc) Send Pause Frame */
2640 XM_MD_ATS = 1<<19, /* Bit 19: Append Time Stamp */
2641 XM_MD_SPOL_I = 1<<18, /* Bit 18: Send Pause on Low */
2642 /* intern generated */
2643 XM_MD_SPOH_I = 1<<17, /* Bit 17: Send Pause on High */
2644 /* intern generated */
2645 XM_MD_CAP = 1<<16, /* Bit 16: Check Address Pair */
2646 XM_MD_ENA_HASH = 1<<15, /* Bit 15: Enable Hashing */
2647 XM_MD_CSA = 1<<14, /* Bit 14: Check Station Address */
2648 XM_MD_CAA = 1<<13, /* Bit 13: Check Address Array */
2649 XM_MD_RX_MCTRL = 1<<12, /* Bit 12: Rx MAC Control Frame */
2650 XM_MD_RX_RUNT = 1<<11, /* Bit 11: Rx Runt Frames */
2651 XM_MD_RX_IRLE = 1<<10, /* Bit 10: Rx in Range Len Err Frame */
2652 XM_MD_RX_LONG = 1<<9, /* Bit 9: Rx Long Frame */
2653 XM_MD_RX_CRCE = 1<<8, /* Bit 8: Rx CRC Error Frame */
2654 XM_MD_RX_ERR = 1<<7, /* Bit 7: Rx Error Frame */
2655 XM_MD_DIS_UC = 1<<6, /* Bit 6: Disable Rx Unicast */
2656 XM_MD_DIS_MC = 1<<5, /* Bit 5: Disable Rx Multicast */
2657 XM_MD_DIS_BC = 1<<4, /* Bit 4: Disable Rx Broadcast */
2658 XM_MD_ENA_PROM = 1<<3, /* Bit 3: Enable Promiscuous */
2659 XM_MD_ENA_BE = 1<<2, /* Bit 2: Enable Big Endian */
2660 XM_MD_FTF = 1<<1, /* Bit 1: (sc) Flush Tx FIFO */
2661 XM_MD_FRF = 1<<0, /* Bit 0: (sc) Flush Rx FIFO */
2662 };
2663
2664 #define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
2665 #define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
2666 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA | XM_MD_CAA)
2667
2668 /* XM_STAT_CMD 16 bit r/w Statistics Command Register */
2669 enum {
2670 XM_SC_SNP_RXC = 1<<5, /* Bit 5: (sc) Snap Rx Counters */
2671 XM_SC_SNP_TXC = 1<<4, /* Bit 4: (sc) Snap Tx Counters */
2672 XM_SC_CP_RXC = 1<<3, /* Bit 3: Copy Rx Counters Continuously */
2673 XM_SC_CP_TXC = 1<<2, /* Bit 2: Copy Tx Counters Continuously */
2674 XM_SC_CLR_RXC = 1<<1, /* Bit 1: (sc) Clear Rx Counters */
2675 XM_SC_CLR_TXC = 1<<0, /* Bit 0: (sc) Clear Tx Counters */
2676 };
2677
2678
2679 /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
2680 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
2681 enum {
2682 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
2683 XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
2684 XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
2685 XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
2686 XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
2687 XMR_64B_OV = 1<<26, /* Bit 26: 64 Byte Rx Cnt Ov */
2688 XMR_UTIL_OV = 1<<25, /* Bit 25: Rx Util Cnt Overflow */
2689 XMR_UTIL_UR = 1<<24, /* Bit 24: Rx Util Cnt Underrun */
2690 XMR_CEX_ERR_OV = 1<<23, /* Bit 23: CEXT Err Cnt Ov */
2691 XMR_FCS_ERR_OV = 1<<21, /* Bit 21: Rx FCS Error Cnt Ov */
2692 XMR_LNG_ERR_OV = 1<<20, /* Bit 20: Rx too Long Err Cnt Ov*/
2693 XMR_RUNT_OV = 1<<19, /* Bit 19: Runt Event Cnt Ov */
2694 XMR_SHT_ERR_OV = 1<<18, /* Bit 18: Rx Short Ev Err Cnt Ov*/
2695 XMR_SYM_ERR_OV = 1<<17, /* Bit 17: Rx Sym Err Cnt Ov */
2696 XMR_CAR_ERR_OV = 1<<15, /* Bit 15: Rx Carr Ev Err Cnt Ov */
2697 XMR_JAB_PKT_OV = 1<<14, /* Bit 14: Rx Jabb Packet Cnt Ov */
2698 XMR_FIFO_OV = 1<<13, /* Bit 13: Rx FIFO Ov Ev Cnt Ov */
2699 XMR_FRA_ERR_OV = 1<<12, /* Bit 12: Rx Framing Err Cnt Ov */
2700 XMR_FMISS_OV = 1<<11, /* Bit 11: Rx Missed Ev Cnt Ov */
2701 XMR_BURST = 1<<10, /* Bit 10: Rx Burst Event Cnt Ov */
2702 XMR_INV_MOC = 1<<9, /* Bit 9: Rx with inv. MAC OC Ov*/
2703 XMR_INV_MP = 1<<8, /* Bit 8: Rx inv Pause Frame Ov */
2704 XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
2705 XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
2706 XMR_UC_OK_OV = 1<<5, /* Bit 5: Rx Unicast Frame CntOv*/
2707 XMR_MC_OK_OV = 1<<4, /* Bit 4: Rx Multicast Cnt Ov */
2708 XMR_BC_OK_OV = 1<<3, /* Bit 3: Rx Broadcast Cnt Ov */
2709 XMR_OK_LO_OV = 1<<2, /* Bit 2: Octets Rx OK Low CntOv*/
2710 XMR_OK_HI_OV = 1<<1, /* Bit 1: Octets Rx OK Hi Cnt Ov*/
2711 XMR_OK_OV = 1<<0, /* Bit 0: Frames Received Ok Ov */
2712 };
2713
2714 #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
2715
2716 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
2717 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
2718 enum {
2719 XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
2720 XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
2721 XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
2722 XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
2723 XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
2724 XMT_64B_OV = 1<<20, /* Bit 20: 64 Byte Tx Cnt Ov */
2725 XMT_UTIL_OV = 1<<19, /* Bit 19: Tx Util Cnt Overflow */
2726 XMT_UTIL_UR = 1<<18, /* Bit 18: Tx Util Cnt Underrun */
2727 XMT_CS_ERR_OV = 1<<17, /* Bit 17: Tx Carr Sen Err Cnt Ov*/
2728 XMT_FIFO_UR_OV = 1<<16, /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
2729 XMT_EX_DEF_OV = 1<<15, /* Bit 15: Tx Ex Deferall Cnt Ov */
2730 XMT_DEF = 1<<14, /* Bit 14: Tx Deferred Cnt Ov */
2731 XMT_LAT_COL_OV = 1<<13, /* Bit 13: Tx Late Col Cnt Ov */
2732 XMT_ABO_COL_OV = 1<<12, /* Bit 12: Tx abo dueto Ex Col Ov*/
2733 XMT_MUL_COL_OV = 1<<11, /* Bit 11: Tx Mult Col Cnt Ov */
2734 XMT_SNG_COL = 1<<10, /* Bit 10: Tx Single Col Cnt Ov */
2735 XMT_MCTRL_OV = 1<<9, /* Bit 9: Tx MAC Ctrl Counter Ov*/
2736 XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
2737 XMT_BURST = 1<<7, /* Bit 7: Tx Burst Event Cnt Ov */
2738 XMT_LONG = 1<<6, /* Bit 6: Tx Long Frame Cnt Ov */
2739 XMT_UC_OK_OV = 1<<5, /* Bit 5: Tx Unicast Cnt Ov */
2740 XMT_MC_OK_OV = 1<<4, /* Bit 4: Tx Multicast Cnt Ov */
2741 XMT_BC_OK_OV = 1<<3, /* Bit 3: Tx Broadcast Cnt Ov */
2742 XMT_OK_LO_OV = 1<<2, /* Bit 2: Octets Tx OK Low CntOv*/
2743 XMT_OK_HI_OV = 1<<1, /* Bit 1: Octets Tx OK Hi Cnt Ov*/
2744 XMT_OK_OV = 1<<0, /* Bit 0: Frames Tx Ok Ov */
2745 };
2746
2747 #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
2748
2749 struct skge_rx_desc {
2750 u32 control;
2751 u32 next_offset;
2752 u32 dma_lo;
2753 u32 dma_hi;
2754 u32 status;
2755 u32 timestamp;
2756 u16 csum2;
2757 u16 csum1;
2758 u16 csum2_start;
2759 u16 csum1_start;
2760 };
2761
2762 struct skge_tx_desc {
2763 u32 control;
2764 u32 next_offset;
2765 u32 dma_lo;
2766 u32 dma_hi;
2767 u32 status;
2768 u32 csum_offs;
2769 u16 csum_write;
2770 u16 csum_start;
2771 u32 rsvd;
2772 };
2773
2774 struct skge_element {
2775 struct skge_element *next;
2776 void *desc;
2777 struct sk_buff *skb;
2778 DECLARE_PCI_UNMAP_ADDR(mapaddr);
2779 DECLARE_PCI_UNMAP_LEN(maplen);
2780 };
2781
2782 struct skge_ring {
2783 struct skge_element *to_clean;
2784 struct skge_element *to_use;
2785 struct skge_element *start;
2786 unsigned long count;
2787 };
2788
2789
2790 struct skge_hw {
2791 void __iomem *regs;
2792 struct pci_dev *pdev;
2793 u32 intr_mask;
2794 struct net_device *dev[2];
2795
2796 u8 mac_cfg;
2797 u8 chip_id;
2798 u8 phy_type;
2799 u8 pmd_type;
2800 u16 phy_addr;
2801
2802 u32 ram_size;
2803 u32 ram_offset;
2804
2805 struct tasklet_struct ext_tasklet;
2806 spinlock_t phy_lock;
2807 };
2808
2809 static inline int isdualport(const struct skge_hw *hw)
2810 {
2811 return !(hw->mac_cfg & CFG_SNG_MAC);
2812 }
2813
2814 static inline u8 chip_rev(const struct skge_hw *hw)
2815 {
2816 return (hw->mac_cfg & CFG_CHIP_R_MSK) >> 4;
2817 }
2818
2819 static inline int iscopper(const struct skge_hw *hw)
2820 {
2821 return (hw->pmd_type == 'T');
2822 }
2823
2824 enum {
2825 FLOW_MODE_NONE = 0, /* No Flow-Control */
2826 FLOW_MODE_LOC_SEND = 1, /* Local station sends PAUSE */
2827 FLOW_MODE_REM_SEND = 2, /* Symmetric or just remote */
2828 FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */
2829 };
2830
2831 struct skge_port {
2832 u32 msg_enable;
2833 struct skge_hw *hw;
2834 struct net_device *netdev;
2835 int port;
2836
2837 spinlock_t tx_lock;
2838 u32 tx_avail;
2839 struct skge_ring tx_ring;
2840 struct skge_ring rx_ring;
2841
2842 struct net_device_stats net_stats;
2843
2844 u8 rx_csum;
2845 u8 blink_on;
2846 u8 flow_control;
2847 u8 wol;
2848 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
2849 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
2850 u16 speed; /* SPEED_1000, SPEED_100, ... */
2851 u32 advertising;
2852
2853 void *mem; /* PCI memory for rings */
2854 dma_addr_t dma;
2855 unsigned long mem_size;
2856
2857 struct timer_list link_check;
2858 struct timer_list led_blink;
2859 };
2860
2861
2862 /* Register accessor for memory mapped device */
2863 static inline u32 skge_read32(const struct skge_hw *hw, int reg)
2864 {
2865 return readl(hw->regs + reg);
2866
2867 }
2868
2869 static inline u16 skge_read16(const struct skge_hw *hw, int reg)
2870 {
2871 return readw(hw->regs + reg);
2872 }
2873
2874 static inline u8 skge_read8(const struct skge_hw *hw, int reg)
2875 {
2876 return readb(hw->regs + reg);
2877 }
2878
2879 static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val)
2880 {
2881 writel(val, hw->regs + reg);
2882 }
2883
2884 static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val)
2885 {
2886 writew(val, hw->regs + reg);
2887 }
2888
2889 static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
2890 {
2891 writeb(val, hw->regs + reg);
2892 }
2893
2894 /* MAC Related Registers inside the device. */
2895 #define SKGEMAC_REG(port,reg) (((port)<<7)+(reg))
2896
2897 /* PCI config space can be accessed via memory mapped space */
2898 #define SKGEPCI_REG(reg) ((reg)+ 0x380)
2899
2900 #define SKGEXM_REG(port, reg) \
2901 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2902
2903 static inline u32 skge_xm_read32(const struct skge_hw *hw, int port, int reg)
2904 {
2905 return skge_read32(hw, SKGEXM_REG(port,reg));
2906 }
2907
2908 static inline u16 skge_xm_read16(const struct skge_hw *hw, int port, int reg)
2909 {
2910 return skge_read16(hw, SKGEXM_REG(port,reg));
2911 }
2912
2913 static inline u8 skge_xm_read8(const struct skge_hw *hw, int port, int reg)
2914 {
2915 return skge_read8(hw, SKGEXM_REG(port,reg));
2916 }
2917
2918 static inline void skge_xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
2919 {
2920 skge_write32(hw, SKGEXM_REG(port,r), v);
2921 }
2922
2923 static inline void skge_xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
2924 {
2925 skge_write16(hw, SKGEXM_REG(port,r), v);
2926 }
2927
2928 static inline void skge_xm_write8(const struct skge_hw *hw, int port, int r, u8 v)
2929 {
2930 skge_write8(hw, SKGEXM_REG(port,r), v);
2931 }
2932
2933 static inline void skge_xm_outhash(const struct skge_hw *hw, int port, int reg,
2934 const u8 *hash)
2935 {
2936 skge_xm_write16(hw, port, reg,
2937 (u16)hash[0] | ((u16)hash[1] << 8));
2938 skge_xm_write16(hw, port, reg+2,
2939 (u16)hash[2] | ((u16)hash[3] << 8));
2940 skge_xm_write16(hw, port, reg+4,
2941 (u16)hash[4] | ((u16)hash[5] << 8));
2942 skge_xm_write16(hw, port, reg+6,
2943 (u16)hash[6] | ((u16)hash[7] << 8));
2944 }
2945
2946 static inline void skge_xm_outaddr(const struct skge_hw *hw, int port, int reg,
2947 const u8 *addr)
2948 {
2949 skge_xm_write16(hw, port, reg,
2950 (u16)addr[0] | ((u16)addr[1] << 8));
2951 skge_xm_write16(hw, port, reg,
2952 (u16)addr[2] | ((u16)addr[3] << 8));
2953 skge_xm_write16(hw, port, reg,
2954 (u16)addr[4] | ((u16)addr[5] << 8));
2955 }
2956
2957
2958 #define SKGEGMA_REG(port,reg) \
2959 ((reg) + BASE_GMAC_1 + \
2960 (port) * (BASE_GMAC_2-BASE_GMAC_1))
2961
2962 static inline u16 skge_gma_read16(const struct skge_hw *hw, int port, int reg)
2963 {
2964 return skge_read16(hw, SKGEGMA_REG(port,reg));
2965 }
2966
2967 static inline u32 skge_gma_read32(const struct skge_hw *hw, int port, int reg)
2968 {
2969 return (u32) skge_read16(hw, SKGEGMA_REG(port,reg))
2970 | ((u32)skge_read16(hw, SKGEGMA_REG(port,reg+4)) << 16);
2971 }
2972
2973 static inline u8 skge_gma_read8(const struct skge_hw *hw, int port, int reg)
2974 {
2975 return skge_read8(hw, SKGEGMA_REG(port,reg));
2976 }
2977
2978 static inline void skge_gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
2979 {
2980 skge_write16(hw, SKGEGMA_REG(port,r), v);
2981 }
2982
2983 static inline void skge_gma_write32(const struct skge_hw *hw, int port, int r, u32 v)
2984 {
2985 skge_write16(hw, SKGEGMA_REG(port, r), (u16) v);
2986 skge_write32(hw, SKGEGMA_REG(port, r+4), (u16)(v >> 16));
2987 }
2988
2989 static inline void skge_gma_write8(const struct skge_hw *hw, int port, int r, u8 v)
2990 {
2991 skge_write8(hw, SKGEGMA_REG(port,r), v);
2992 }
2993
2994 static inline void skge_gm_set_addr(struct skge_hw *hw, int port, int reg,
2995 const u8 *addr)
2996 {
2997 skge_gma_write16(hw, port, reg,
2998 (u16) addr[0] | ((u16) addr[1] << 8));
2999 skge_gma_write16(hw, port, reg+4,
3000 (u16) addr[2] | ((u16) addr[3] << 8));
3001 skge_gma_write16(hw, port, reg+8,
3002 (u16) addr[4] | ((u16) addr[5] << 8));
3003 }
3004
3005 #endif
linux 2.6 git repository for openrd