arch/x86/kernel/quirks.c

   1 /*
   2  * This file contains work-arounds for x86 and x86_64 platform bugs.
   3  */
   4 #include <linux/pci.h>
   5 #include <linux/irq.h>
   6
   7 #include <asm/hpet.h>
   8
   9 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
  10
  11 static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
  12 {
  13         u8 config, rev;
  14         u16 word;
  15
  16         /* BIOS may enable hardware IRQ balancing for
  17          * E7520/E7320/E7525(revision ID 0x9 and below)
  18          * based platforms.
  19          * Disable SW irqbalance/affinity on those platforms.
  20          */
  21         pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
  22         if (rev > 0x9)
  23                 return;
  24
  25         /* enable access to config space*/
  26         pci_read_config_byte(dev, 0xf4, &config);
  27         pci_write_config_byte(dev, 0xf4, config|0x2);
  28
  29         /*
  30          * read xTPR register.  We may not have a pci_dev for device 8
  31          * because it might be hidden until the above write.
  32          */
  33         pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
  34
  35         if (!(word & (1 << 13))) {
  36                 dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
  37                         "disabling irq balancing and affinity\n");
  38                 noirqdebug_setup("");
  39 #ifdef CONFIG_PROC_FS
  40                 no_irq_affinity = 1;
  41 #endif
  42         }
  43
  44         /* put back the original value for config space*/
  45         if (!(config & 0x2))
  46                 pci_write_config_byte(dev, 0xf4, config);
  47 }
  48 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
  49                         quirk_intel_irqbalance);
  50 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
  51                         quirk_intel_irqbalance);
  52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
  53                         quirk_intel_irqbalance);
  54 #endif
  55
  56 #if defined(CONFIG_HPET_TIMER)
  57 unsigned long force_hpet_address;
  58
  59 static enum {
  60         NONE_FORCE_HPET_RESUME,
  61         OLD_ICH_FORCE_HPET_RESUME,
  62         ICH_FORCE_HPET_RESUME,
  63         VT8237_FORCE_HPET_RESUME,
  64         NVIDIA_FORCE_HPET_RESUME,
  65         ATI_FORCE_HPET_RESUME,
  66 } force_hpet_resume_type;
  67
  68 static void __iomem *rcba_base;
  69
  70 static void ich_force_hpet_resume(void)
  71 {
  72         u32 val;
  73
  74         if (!force_hpet_address)
  75                 return;
  76
  77         BUG_ON(rcba_base == NULL);
  78
  79         /* read the Function Disable register, dword mode only */
  80         val = readl(rcba_base + 0x3404);
  81         if (!(val & 0x80)) {
  82                 /* HPET disabled in HPTC. Trying to enable */
  83                 writel(val | 0x80, rcba_base + 0x3404);
  84         }
  85
  86         val = readl(rcba_base + 0x3404);
  87         if (!(val & 0x80))
  88                 BUG();
  89         else
  90                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
  91
  92         return;
  93 }
  94
  95 static void ich_force_enable_hpet(struct pci_dev *dev)
  96 {
  97         u32 val;
  98         u32 uninitialized_var(rcba);
  99         int err = 0;
 100
 101         if (hpet_address || force_hpet_address)
 102                 return;
 103
 104         pci_read_config_dword(dev, 0xF0, &rcba);
 105         rcba &= 0xFFFFC000;
 106         if (rcba == 0) {
 107                 dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
 108                         "cannot force enable HPET\n");
 109                 return;
 110         }
 111
 112         /* use bits 31:14, 16 kB aligned */
 113         rcba_base = ioremap_nocache(rcba, 0x4000);
 114         if (rcba_base == NULL) {
 115                 dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
 116                         "cannot force enable HPET\n");
 117                 return;
 118         }
 119
 120         /* read the Function Disable register, dword mode only */
 121         val = readl(rcba_base + 0x3404);
 122
 123         if (val & 0x80) {
 124                 /* HPET is enabled in HPTC. Just not reported by BIOS */
 125                 val = val & 0x3;
 126                 force_hpet_address = 0xFED00000 | (val << 12);
 127                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 128                         "0x%lx\n", force_hpet_address);
 129                 iounmap(rcba_base);
 130                 return;
 131         }
 132
 133         /* HPET disabled in HPTC. Trying to enable */
 134         writel(val | 0x80, rcba_base + 0x3404);
 135
 136         val = readl(rcba_base + 0x3404);
 137         if (!(val & 0x80)) {
 138                 err = 1;
 139         } else {
 140                 val = val & 0x3;
 141                 force_hpet_address = 0xFED00000 | (val << 12);
 142         }
 143
 144         if (err) {
 145                 force_hpet_address = 0;
 146                 iounmap(rcba_base);
 147                 dev_printk(KERN_DEBUG, &dev->dev,
 148                         "Failed to force enable HPET\n");
 149         } else {
 150                 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
 151                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 152                         "0x%lx\n", force_hpet_address);
 153         }
 154 }
 155
 156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
 157                          ich_force_enable_hpet);
 158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
 159                          ich_force_enable_hpet);
 160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
 161                          ich_force_enable_hpet);
 162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
 163                          ich_force_enable_hpet);
 164 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
 165                          ich_force_enable_hpet);
 166 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
 167                          ich_force_enable_hpet);
 168 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
 169                          ich_force_enable_hpet);
 170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4,
 171                          ich_force_enable_hpet);
 172 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
 173                          ich_force_enable_hpet);
 174
 175
 176 static struct pci_dev *cached_dev;
 177
 178 static void hpet_print_force_info(void)
 179 {
 180         printk(KERN_INFO "HPET not enabled in BIOS. "
 181                "You might try hpet=force boot option\n");
 182 }
 183
 184 static void old_ich_force_hpet_resume(void)
 185 {
 186         u32 val;
 187         u32 uninitialized_var(gen_cntl);
 188
 189         if (!force_hpet_address || !cached_dev)
 190                 return;
 191
 192         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
 193         gen_cntl &= (~(0x7 << 15));
 194         gen_cntl |= (0x4 << 15);
 195
 196         pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
 197         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
 198         val = gen_cntl >> 15;
 199         val &= 0x7;
 200         if (val == 0x4)
 201                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
 202         else
 203                 BUG();
 204 }
 205
 206 static void old_ich_force_enable_hpet(struct pci_dev *dev)
 207 {
 208         u32 val;
 209         u32 uninitialized_var(gen_cntl);
 210
 211         if (hpet_address || force_hpet_address)
 212                 return;
 213
 214         pci_read_config_dword(dev, 0xD0, &gen_cntl);
 215         /*
 216          * Bit 17 is HPET enable bit.
 217          * Bit 16:15 control the HPET base address.
 218          */
 219         val = gen_cntl >> 15;
 220         val &= 0x7;
 221         if (val & 0x4) {
 222                 val &= 0x3;
 223                 force_hpet_address = 0xFED00000 | (val << 12);
 224                 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
 225                         force_hpet_address);
 226                 return;
 227         }
 228
 229         /*
 230          * HPET is disabled. Trying enabling at FED00000 and check
 231          * whether it sticks
 232          */
 233         gen_cntl &= (~(0x7 << 15));
 234         gen_cntl |= (0x4 << 15);
 235         pci_write_config_dword(dev, 0xD0, gen_cntl);
 236
 237         pci_read_config_dword(dev, 0xD0, &gen_cntl);
 238
 239         val = gen_cntl >> 15;
 240         val &= 0x7;
 241         if (val & 0x4) {
 242                 /* HPET is enabled in HPTC. Just not reported by BIOS */
 243                 val &= 0x3;
 244                 force_hpet_address = 0xFED00000 | (val << 12);
 245                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 246                         "0x%lx\n", force_hpet_address);
 247                 cached_dev = dev;
 248                 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
 249                 return;
 250         }
 251
 252         dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
 253 }
 254
 255 /*
 256  * Undocumented chipset features. Make sure that the user enforced
 257  * this.
 258  */
 259 static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
 260 {
 261         if (hpet_force_user)
 262                 old_ich_force_enable_hpet(dev);
 263         else
 264                 hpet_print_force_info();
 265 }
 266
 267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
 268                          old_ich_force_enable_hpet_user);
 269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
 270                          old_ich_force_enable_hpet_user);
 271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
 272                          old_ich_force_enable_hpet_user);
 273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
 274                          old_ich_force_enable_hpet_user);
 275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
 276                          old_ich_force_enable_hpet_user);
 277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
 278                          old_ich_force_enable_hpet);
 279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
 280                          old_ich_force_enable_hpet);
 281
 282
 283 static void vt8237_force_hpet_resume(void)
 284 {
 285         u32 val;
 286
 287         if (!force_hpet_address || !cached_dev)
 288                 return;
 289
 290         val = 0xfed00000 | 0x80;
 291         pci_write_config_dword(cached_dev, 0x68, val);
 292
 293         pci_read_config_dword(cached_dev, 0x68, &val);
 294         if (val & 0x80)
 295                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
 296         else
 297                 BUG();
 298 }
 299
 300 static void vt8237_force_enable_hpet(struct pci_dev *dev)
 301 {
 302         u32 uninitialized_var(val);
 303
 304         if (hpet_address || force_hpet_address)
 305                 return;
 306
 307         if (!hpet_force_user) {
 308                 hpet_print_force_info();
 309                 return;
 310         }
 311
 312         pci_read_config_dword(dev, 0x68, &val);
 313         /*
 314          * Bit 7 is HPET enable bit.
 315          * Bit 31:10 is HPET base address (contrary to what datasheet claims)
 316          */
 317         if (val & 0x80) {
 318                 force_hpet_address = (val & ~0x3ff);
 319                 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
 320                         force_hpet_address);
 321                 return;
 322         }
 323
 324         /*
 325          * HPET is disabled. Trying enabling at FED00000 and check
 326          * whether it sticks
 327          */
 328         val = 0xfed00000 | 0x80;
 329         pci_write_config_dword(dev, 0x68, val);
 330
 331         pci_read_config_dword(dev, 0x68, &val);
 332         if (val & 0x80) {
 333                 force_hpet_address = (val & ~0x3ff);
 334                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 335                         "0x%lx\n", force_hpet_address);
 336                 cached_dev = dev;
 337                 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
 338                 return;
 339         }
 340
 341         dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
 342 }
 343
 344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
 345                          vt8237_force_enable_hpet);
 346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
 347                          vt8237_force_enable_hpet);
 348
 349 static void ati_force_hpet_resume(void)
 350 {
 351         pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
 352         printk(KERN_DEBUG "Force enabled HPET at resume\n");
 353 }
 354
 355 static u32 ati_ixp4x0_rev(struct pci_dev *dev)
 356 {
 357         u32 d;
 358         u8  b;
 359
 360         pci_read_config_byte(dev, 0xac, &b);
 361         b &= ~(1<<5);
 362         pci_write_config_byte(dev, 0xac, b);
 363         pci_read_config_dword(dev, 0x70, &d);
 364         d |= 1<<8;
 365         pci_write_config_dword(dev, 0x70, d);
 366         pci_read_config_dword(dev, 0x8, &d);
 367         d &= 0xff;
 368         dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d);
 369         return d;
 370 }
 371
 372 static void ati_force_enable_hpet(struct pci_dev *dev)
 373 {
 374         u32 d, val;
 375         u8  b;
 376
 377         if (hpet_address || force_hpet_address)
 378                 return;
 379
 380         if (!hpet_force_user) {
 381                 hpet_print_force_info();
 382                 return;
 383         }
 384
 385         d = ati_ixp4x0_rev(dev);
 386         if (d  < 0x82)
 387                 return;
 388
 389         /* base address */
 390         pci_write_config_dword(dev, 0x14, 0xfed00000);
 391         pci_read_config_dword(dev, 0x14, &val);
 392
 393         /* enable interrupt */
 394         outb(0x72, 0xcd6); b = inb(0xcd7);
 395         b |= 0x1;
 396         outb(0x72, 0xcd6); outb(b, 0xcd7);
 397         outb(0x72, 0xcd6); b = inb(0xcd7);
 398         if (!(b & 0x1))
 399                 return;
 400         pci_read_config_dword(dev, 0x64, &d);
 401         d |= (1<<10);
 402         pci_write_config_dword(dev, 0x64, d);
 403         pci_read_config_dword(dev, 0x64, &d);
 404         if (!(d & (1<<10)))
 405                 return;
 406
 407         force_hpet_address = val;
 408         force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
 409         dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
 410                    force_hpet_address);
 411         cached_dev = dev;
 412 }
 413 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
 414                          ati_force_enable_hpet);
 415
 416 /*
 417  * Undocumented chipset feature taken from LinuxBIOS.
 418  */
 419 static void nvidia_force_hpet_resume(void)
 420 {
 421         pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
 422         printk(KERN_DEBUG "Force enabled HPET at resume\n");
 423 }
 424
 425 static void nvidia_force_enable_hpet(struct pci_dev *dev)
 426 {
 427         u32 uninitialized_var(val);
 428
 429         if (hpet_address || force_hpet_address)
 430                 return;
 431
 432         if (!hpet_force_user) {
 433                 hpet_print_force_info();
 434                 return;
 435         }
 436
 437         pci_write_config_dword(dev, 0x44, 0xfed00001);
 438         pci_read_config_dword(dev, 0x44, &val);
 439         force_hpet_address = val & 0xfffffffe;
 440         force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
 441         dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
 442                 force_hpet_address);
 443         cached_dev = dev;
 444         return;
 445 }
 446
 447 /* ISA Bridges */
 448 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
 449                         nvidia_force_enable_hpet);
 450 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
 451                         nvidia_force_enable_hpet);
 452
 453 /* LPC bridges */
 454 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
 455                         nvidia_force_enable_hpet);
 456 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
 457                         nvidia_force_enable_hpet);
 458 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
 459                         nvidia_force_enable_hpet);
 460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
 461                         nvidia_force_enable_hpet);
 462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
 463                         nvidia_force_enable_hpet);
 464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
 465                         nvidia_force_enable_hpet);
 466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
 467                         nvidia_force_enable_hpet);
 468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
 469                         nvidia_force_enable_hpet);
 470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
 471                         nvidia_force_enable_hpet);
 472
 473 void force_hpet_resume(void)
 474 {
 475         switch (force_hpet_resume_type) {
 476         case ICH_FORCE_HPET_RESUME:
 477                 ich_force_hpet_resume();
 478                 return;
 479         case OLD_ICH_FORCE_HPET_RESUME:
 480                 old_ich_force_hpet_resume();
 481                 return;
 482         case VT8237_FORCE_HPET_RESUME:
 483                 vt8237_force_hpet_resume();
 484                 return;
 485         case NVIDIA_FORCE_HPET_RESUME:
 486                 nvidia_force_hpet_resume();
 487                 return;
 488         case ATI_FORCE_HPET_RESUME:
 489                 ati_force_hpet_resume();
 490                 return;
 491         default:
 492                 break;
 493         }
 494 }
 495
 496 #endif