2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/uv/uv_hub.h>
63 #include <asm/uv/uv_irq.h>
67 #define __apicdebuginit(type) static type __init
70 * Is the SiS APIC rmw bug present ?
71 * -1 = don't know, 0 = no, 1 = yes
73 int sis_apic_bug
= -1;
75 static DEFINE_SPINLOCK(ioapic_lock
);
76 static DEFINE_SPINLOCK(vector_lock
);
79 * # of IRQ routing registers
81 int nr_ioapic_registers
[MAX_IO_APICS
];
83 /* I/O APIC entries */
84 struct mpc_ioapic mp_ioapics
[MAX_IO_APICS
];
87 /* MP IRQ source entries */
88 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
90 /* # of MP IRQ source entries */
93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
97 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
99 int skip_ioapic_setup
;
101 void arch_disable_smp_support(void)
105 noioapicreroute
= -1;
107 skip_ioapic_setup
= 1;
110 static int __init
parse_noapic(char *str
)
112 /* disable IO-APIC */
113 arch_disable_smp_support();
116 early_param("noapic", parse_noapic
);
121 * This is performance-critical, we want to do it O(1)
123 * the indexing order of this array favors 1:1 mappings
124 * between pins and IRQs.
127 struct irq_pin_list
{
129 struct irq_pin_list
*next
;
132 static struct irq_pin_list
*get_one_free_irq_2_pin(int cpu
)
134 struct irq_pin_list
*pin
;
137 node
= cpu_to_node(cpu
);
139 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
145 struct irq_pin_list
*irq_2_pin
;
146 cpumask_var_t domain
;
147 cpumask_var_t old_domain
;
148 unsigned move_cleanup_count
;
150 u8 move_in_progress
: 1;
151 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
152 u8 move_desc_pending
: 1;
156 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
157 #ifdef CONFIG_SPARSE_IRQ
158 static struct irq_cfg irq_cfgx
[] = {
160 static struct irq_cfg irq_cfgx
[NR_IRQS
] = {
162 [0] = { .vector
= IRQ0_VECTOR
, },
163 [1] = { .vector
= IRQ1_VECTOR
, },
164 [2] = { .vector
= IRQ2_VECTOR
, },
165 [3] = { .vector
= IRQ3_VECTOR
, },
166 [4] = { .vector
= IRQ4_VECTOR
, },
167 [5] = { .vector
= IRQ5_VECTOR
, },
168 [6] = { .vector
= IRQ6_VECTOR
, },
169 [7] = { .vector
= IRQ7_VECTOR
, },
170 [8] = { .vector
= IRQ8_VECTOR
, },
171 [9] = { .vector
= IRQ9_VECTOR
, },
172 [10] = { .vector
= IRQ10_VECTOR
, },
173 [11] = { .vector
= IRQ11_VECTOR
, },
174 [12] = { .vector
= IRQ12_VECTOR
, },
175 [13] = { .vector
= IRQ13_VECTOR
, },
176 [14] = { .vector
= IRQ14_VECTOR
, },
177 [15] = { .vector
= IRQ15_VECTOR
, },
180 int __init
arch_early_irq_init(void)
183 struct irq_desc
*desc
;
188 count
= ARRAY_SIZE(irq_cfgx
);
190 for (i
= 0; i
< count
; i
++) {
191 desc
= irq_to_desc(i
);
192 desc
->chip_data
= &cfg
[i
];
193 alloc_bootmem_cpumask_var(&cfg
[i
].domain
);
194 alloc_bootmem_cpumask_var(&cfg
[i
].old_domain
);
195 if (i
< NR_IRQS_LEGACY
)
196 cpumask_setall(cfg
[i
].domain
);
202 #ifdef CONFIG_SPARSE_IRQ
203 static struct irq_cfg
*irq_cfg(unsigned int irq
)
205 struct irq_cfg
*cfg
= NULL
;
206 struct irq_desc
*desc
;
208 desc
= irq_to_desc(irq
);
210 cfg
= desc
->chip_data
;
215 static struct irq_cfg
*get_one_free_irq_cfg(int cpu
)
220 node
= cpu_to_node(cpu
);
222 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
224 if (!alloc_cpumask_var_node(&cfg
->domain
, GFP_ATOMIC
, node
)) {
227 } else if (!alloc_cpumask_var_node(&cfg
->old_domain
,
229 free_cpumask_var(cfg
->domain
);
233 cpumask_clear(cfg
->domain
);
234 cpumask_clear(cfg
->old_domain
);
241 int arch_init_chip_data(struct irq_desc
*desc
, int cpu
)
245 cfg
= desc
->chip_data
;
247 desc
->chip_data
= get_one_free_irq_cfg(cpu
);
248 if (!desc
->chip_data
) {
249 printk(KERN_ERR
"can not alloc irq_cfg\n");
257 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
260 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int cpu
)
262 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
264 cfg
->irq_2_pin
= NULL
;
265 old_entry
= old_cfg
->irq_2_pin
;
269 entry
= get_one_free_irq_2_pin(cpu
);
273 entry
->apic
= old_entry
->apic
;
274 entry
->pin
= old_entry
->pin
;
277 old_entry
= old_entry
->next
;
279 entry
= get_one_free_irq_2_pin(cpu
);
287 /* still use the old one */
290 entry
->apic
= old_entry
->apic
;
291 entry
->pin
= old_entry
->pin
;
294 old_entry
= old_entry
->next
;
298 cfg
->irq_2_pin
= head
;
301 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
303 struct irq_pin_list
*entry
, *next
;
305 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
308 entry
= old_cfg
->irq_2_pin
;
315 old_cfg
->irq_2_pin
= NULL
;
318 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
319 struct irq_desc
*desc
, int cpu
)
322 struct irq_cfg
*old_cfg
;
324 cfg
= get_one_free_irq_cfg(cpu
);
329 desc
->chip_data
= cfg
;
331 old_cfg
= old_desc
->chip_data
;
333 memcpy(cfg
, old_cfg
, sizeof(struct irq_cfg
));
335 init_copy_irq_2_pin(old_cfg
, cfg
, cpu
);
338 static void free_irq_cfg(struct irq_cfg
*old_cfg
)
343 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
345 struct irq_cfg
*old_cfg
, *cfg
;
347 old_cfg
= old_desc
->chip_data
;
348 cfg
= desc
->chip_data
;
354 free_irq_2_pin(old_cfg
, cfg
);
355 free_irq_cfg(old_cfg
);
356 old_desc
->chip_data
= NULL
;
361 set_extra_move_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
363 struct irq_cfg
*cfg
= desc
->chip_data
;
365 if (!cfg
->move_in_progress
) {
366 /* it means that domain is not changed */
367 if (!cpumask_intersects(desc
->affinity
, mask
))
368 cfg
->move_desc_pending
= 1;
374 static struct irq_cfg
*irq_cfg(unsigned int irq
)
376 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
381 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
383 set_extra_move_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
390 unsigned int unused
[3];
392 unsigned int unused2
[11];
396 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
398 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
399 + (mp_ioapics
[idx
].apicaddr
& ~PAGE_MASK
);
402 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
404 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
405 writel(vector
, &io_apic
->eoi
);
408 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
410 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
411 writel(reg
, &io_apic
->index
);
412 return readl(&io_apic
->data
);
415 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
417 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
418 writel(reg
, &io_apic
->index
);
419 writel(value
, &io_apic
->data
);
423 * Re-write a value: to be used for read-modify-write
424 * cycles where the read already set up the index register.
426 * Older SiS APIC requires we rewrite the index register
428 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
430 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
433 writel(reg
, &io_apic
->index
);
434 writel(value
, &io_apic
->data
);
437 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
439 struct irq_pin_list
*entry
;
442 spin_lock_irqsave(&ioapic_lock
, flags
);
443 entry
= cfg
->irq_2_pin
;
451 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
452 /* Is the remote IRR bit set? */
453 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
454 spin_unlock_irqrestore(&ioapic_lock
, flags
);
461 spin_unlock_irqrestore(&ioapic_lock
, flags
);
467 struct { u32 w1
, w2
; };
468 struct IO_APIC_route_entry entry
;
471 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
473 union entry_union eu
;
475 spin_lock_irqsave(&ioapic_lock
, flags
);
476 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
477 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
478 spin_unlock_irqrestore(&ioapic_lock
, flags
);
483 * When we write a new IO APIC routing entry, we need to write the high
484 * word first! If the mask bit in the low word is clear, we will enable
485 * the interrupt, and we need to make sure the entry is fully populated
486 * before that happens.
489 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
491 union entry_union eu
;
493 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
494 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
497 void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
500 spin_lock_irqsave(&ioapic_lock
, flags
);
501 __ioapic_write_entry(apic
, pin
, e
);
502 spin_unlock_irqrestore(&ioapic_lock
, flags
);
506 * When we mask an IO APIC routing entry, we need to write the low
507 * word first, in order to set the mask bit before we change the
510 static void ioapic_mask_entry(int apic
, int pin
)
513 union entry_union eu
= { .entry
.mask
= 1 };
515 spin_lock_irqsave(&ioapic_lock
, flags
);
516 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
517 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
518 spin_unlock_irqrestore(&ioapic_lock
, flags
);
522 static void send_cleanup_vector(struct irq_cfg
*cfg
)
524 cpumask_var_t cleanup_mask
;
526 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
528 cfg
->move_cleanup_count
= 0;
529 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
530 cfg
->move_cleanup_count
++;
531 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
532 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
534 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
535 cfg
->move_cleanup_count
= cpumask_weight(cleanup_mask
);
536 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
537 free_cpumask_var(cleanup_mask
);
539 cfg
->move_in_progress
= 0;
542 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
545 struct irq_pin_list
*entry
;
546 u8 vector
= cfg
->vector
;
548 entry
= cfg
->irq_2_pin
;
558 * With interrupt-remapping, destination information comes
559 * from interrupt-remapping table entry.
561 if (!irq_remapped(irq
))
562 io_apic_write(apic
, 0x11 + pin
*2, dest
);
563 reg
= io_apic_read(apic
, 0x10 + pin
*2);
564 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
566 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
574 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
);
577 * Either sets desc->affinity to a valid value, and returns
578 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
579 * leaves desc->affinity untouched.
582 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
)
587 if (!cpumask_intersects(mask
, cpu_online_mask
))
591 cfg
= desc
->chip_data
;
592 if (assign_irq_vector(irq
, cfg
, mask
))
595 cpumask_and(desc
->affinity
, cfg
->domain
, mask
);
596 set_extra_move_desc(desc
, mask
);
598 return apic
->cpu_mask_to_apicid_and(desc
->affinity
, cpu_online_mask
);
602 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
610 cfg
= desc
->chip_data
;
612 spin_lock_irqsave(&ioapic_lock
, flags
);
613 dest
= set_desc_affinity(desc
, mask
);
614 if (dest
!= BAD_APICID
) {
615 /* Only the high 8 bits are valid. */
616 dest
= SET_APIC_LOGICAL_ID(dest
);
617 __target_IO_APIC_irq(irq
, dest
, cfg
);
619 spin_unlock_irqrestore(&ioapic_lock
, flags
);
623 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
625 struct irq_desc
*desc
;
627 desc
= irq_to_desc(irq
);
629 set_ioapic_affinity_irq_desc(desc
, mask
);
631 #endif /* CONFIG_SMP */
634 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
635 * shared ISA-space IRQs, so we have to support them. We are super
636 * fast in the common case, and fast for shared ISA-space IRQs.
638 static void add_pin_to_irq_cpu(struct irq_cfg
*cfg
, int cpu
, int apic
, int pin
)
640 struct irq_pin_list
*entry
;
642 entry
= cfg
->irq_2_pin
;
644 entry
= get_one_free_irq_2_pin(cpu
);
646 printk(KERN_ERR
"can not alloc irq_2_pin to add %d - %d\n",
650 cfg
->irq_2_pin
= entry
;
656 while (entry
->next
) {
657 /* not again, please */
658 if (entry
->apic
== apic
&& entry
->pin
== pin
)
664 entry
->next
= get_one_free_irq_2_pin(cpu
);
671 * Reroute an IRQ to a different pin.
673 static void __init
replace_pin_at_irq_cpu(struct irq_cfg
*cfg
, int cpu
,
674 int oldapic
, int oldpin
,
675 int newapic
, int newpin
)
677 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
681 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
682 entry
->apic
= newapic
;
685 /* every one is different, right? */
691 /* why? call replace before add? */
693 add_pin_to_irq_cpu(cfg
, cpu
, newapic
, newpin
);
696 static inline void io_apic_modify_irq(struct irq_cfg
*cfg
,
697 int mask_and
, int mask_or
,
698 void (*final
)(struct irq_pin_list
*entry
))
701 struct irq_pin_list
*entry
;
703 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
706 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
709 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
715 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
717 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
721 static void io_apic_sync(struct irq_pin_list
*entry
)
724 * Synchronize the IO-APIC and the CPU by doing
725 * a dummy read from the IO-APIC
727 struct io_apic __iomem
*io_apic
;
728 io_apic
= io_apic_base(entry
->apic
);
729 readl(&io_apic
->data
);
732 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
734 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
736 #else /* CONFIG_X86_32 */
737 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
739 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, NULL
);
742 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg
*cfg
)
744 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
745 IO_APIC_REDIR_MASKED
, NULL
);
748 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg
*cfg
)
750 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
,
751 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
753 #endif /* CONFIG_X86_32 */
755 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
757 struct irq_cfg
*cfg
= desc
->chip_data
;
762 spin_lock_irqsave(&ioapic_lock
, flags
);
763 __mask_IO_APIC_irq(cfg
);
764 spin_unlock_irqrestore(&ioapic_lock
, flags
);
767 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
769 struct irq_cfg
*cfg
= desc
->chip_data
;
772 spin_lock_irqsave(&ioapic_lock
, flags
);
773 __unmask_IO_APIC_irq(cfg
);
774 spin_unlock_irqrestore(&ioapic_lock
, flags
);
777 static void mask_IO_APIC_irq(unsigned int irq
)
779 struct irq_desc
*desc
= irq_to_desc(irq
);
781 mask_IO_APIC_irq_desc(desc
);
783 static void unmask_IO_APIC_irq(unsigned int irq
)
785 struct irq_desc
*desc
= irq_to_desc(irq
);
787 unmask_IO_APIC_irq_desc(desc
);
790 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
792 struct IO_APIC_route_entry entry
;
794 /* Check delivery_mode to be sure we're not clearing an SMI pin */
795 entry
= ioapic_read_entry(apic
, pin
);
796 if (entry
.delivery_mode
== dest_SMI
)
799 * Disable it in the IO-APIC irq-routing table:
801 ioapic_mask_entry(apic
, pin
);
804 static void clear_IO_APIC (void)
808 for (apic
= 0; apic
< nr_ioapics
; apic
++)
809 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
810 clear_IO_APIC_pin(apic
, pin
);
815 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
816 * specific CPU-side IRQs.
820 static int pirq_entries
[MAX_PIRQS
] = {
821 [0 ... MAX_PIRQS
- 1] = -1
824 static int __init
ioapic_pirq_setup(char *str
)
827 int ints
[MAX_PIRQS
+1];
829 get_options(str
, ARRAY_SIZE(ints
), ints
);
831 apic_printk(APIC_VERBOSE
, KERN_INFO
832 "PIRQ redirection, working around broken MP-BIOS.\n");
834 if (ints
[0] < MAX_PIRQS
)
837 for (i
= 0; i
< max
; i
++) {
838 apic_printk(APIC_VERBOSE
, KERN_DEBUG
839 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
841 * PIRQs are mapped upside down, usually.
843 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
848 __setup("pirq=", ioapic_pirq_setup
);
849 #endif /* CONFIG_X86_32 */
851 #ifdef CONFIG_INTR_REMAP
852 /* I/O APIC RTE contents at the OS boot up */
853 static struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
856 * Saves all the IO-APIC RTE's
858 int save_IO_APIC_setup(void)
860 union IO_APIC_reg_01 reg_01
;
865 * The number of IO-APIC IRQ registers (== #pins):
867 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
868 spin_lock_irqsave(&ioapic_lock
, flags
);
869 reg_01
.raw
= io_apic_read(apic
, 1);
870 spin_unlock_irqrestore(&ioapic_lock
, flags
);
871 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
874 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
875 early_ioapic_entries
[apic
] =
876 kzalloc(sizeof(struct IO_APIC_route_entry
) *
877 nr_ioapic_registers
[apic
], GFP_KERNEL
);
878 if (!early_ioapic_entries
[apic
])
882 for (apic
= 0; apic
< nr_ioapics
; apic
++)
883 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
884 early_ioapic_entries
[apic
][pin
] =
885 ioapic_read_entry(apic
, pin
);
891 kfree(early_ioapic_entries
[apic
--]);
892 memset(early_ioapic_entries
, 0,
893 ARRAY_SIZE(early_ioapic_entries
));
898 void mask_IO_APIC_setup(void)
902 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
903 if (!early_ioapic_entries
[apic
])
905 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
906 struct IO_APIC_route_entry entry
;
908 entry
= early_ioapic_entries
[apic
][pin
];
911 ioapic_write_entry(apic
, pin
, entry
);
917 void restore_IO_APIC_setup(void)
921 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
922 if (!early_ioapic_entries
[apic
])
924 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
925 ioapic_write_entry(apic
, pin
,
926 early_ioapic_entries
[apic
][pin
]);
927 kfree(early_ioapic_entries
[apic
]);
928 early_ioapic_entries
[apic
] = NULL
;
932 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
935 * for now plain restore of previous settings.
936 * TBD: In the case of OS enabling interrupt-remapping,
937 * IO-APIC RTE's need to be setup to point to interrupt-remapping
938 * table entries. for now, do a plain restore, and wait for
939 * the setup_IO_APIC_irqs() to do proper initialization.
941 restore_IO_APIC_setup();
946 * Find the IRQ entry number of a certain pin.
948 static int find_irq_entry(int apic
, int pin
, int type
)
952 for (i
= 0; i
< mp_irq_entries
; i
++)
953 if (mp_irqs
[i
].irqtype
== type
&&
954 (mp_irqs
[i
].dstapic
== mp_ioapics
[apic
].apicid
||
955 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
956 mp_irqs
[i
].dstirq
== pin
)
963 * Find the pin to which IRQ[irq] (ISA) is connected
965 static int __init
find_isa_irq_pin(int irq
, int type
)
969 for (i
= 0; i
< mp_irq_entries
; i
++) {
970 int lbus
= mp_irqs
[i
].srcbus
;
972 if (test_bit(lbus
, mp_bus_not_pci
) &&
973 (mp_irqs
[i
].irqtype
== type
) &&
974 (mp_irqs
[i
].srcbusirq
== irq
))
976 return mp_irqs
[i
].dstirq
;
981 static int __init
find_isa_irq_apic(int irq
, int type
)
985 for (i
= 0; i
< mp_irq_entries
; i
++) {
986 int lbus
= mp_irqs
[i
].srcbus
;
988 if (test_bit(lbus
, mp_bus_not_pci
) &&
989 (mp_irqs
[i
].irqtype
== type
) &&
990 (mp_irqs
[i
].srcbusirq
== irq
))
993 if (i
< mp_irq_entries
) {
995 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
996 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
)
1005 * Find a specific PCI IRQ entry.
1006 * Not an __init, possibly needed by modules
1008 static int pin_2_irq(int idx
, int apic
, int pin
);
1010 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
1012 int apic
, i
, best_guess
= -1;
1014 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1016 if (test_bit(bus
, mp_bus_not_pci
)) {
1017 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1020 for (i
= 0; i
< mp_irq_entries
; i
++) {
1021 int lbus
= mp_irqs
[i
].srcbus
;
1023 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1024 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
||
1025 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1028 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1029 !mp_irqs
[i
].irqtype
&&
1031 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1032 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1034 if (!(apic
|| IO_APIC_IRQ(irq
)))
1037 if (pin
== (mp_irqs
[i
].srcbusirq
& 3))
1040 * Use the first all-but-pin matching entry as a
1041 * best-guess fuzzy result for broken mptables.
1050 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1052 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1054 * EISA Edge/Level control register, ELCR
1056 static int EISA_ELCR(unsigned int irq
)
1058 if (irq
< NR_IRQS_LEGACY
) {
1059 unsigned int port
= 0x4d0 + (irq
>> 3);
1060 return (inb(port
) >> (irq
& 7)) & 1;
1062 apic_printk(APIC_VERBOSE
, KERN_INFO
1063 "Broken MPtable reports ISA irq %d\n", irq
);
1069 /* ISA interrupts are always polarity zero edge triggered,
1070 * when listed as conforming in the MP table. */
1072 #define default_ISA_trigger(idx) (0)
1073 #define default_ISA_polarity(idx) (0)
1075 /* EISA interrupts are always polarity zero and can be edge or level
1076 * trigger depending on the ELCR value. If an interrupt is listed as
1077 * EISA conforming in the MP table, that means its trigger type must
1078 * be read in from the ELCR */
1080 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
1081 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1083 /* PCI interrupts are always polarity one level triggered,
1084 * when listed as conforming in the MP table. */
1086 #define default_PCI_trigger(idx) (1)
1087 #define default_PCI_polarity(idx) (1)
1089 /* MCA interrupts are always polarity zero level triggered,
1090 * when listed as conforming in the MP table. */
1092 #define default_MCA_trigger(idx) (1)
1093 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1095 static int MPBIOS_polarity(int idx
)
1097 int bus
= mp_irqs
[idx
].srcbus
;
1101 * Determine IRQ line polarity (high active or low active):
1103 switch (mp_irqs
[idx
].irqflag
& 3)
1105 case 0: /* conforms, ie. bus-type dependent polarity */
1106 if (test_bit(bus
, mp_bus_not_pci
))
1107 polarity
= default_ISA_polarity(idx
);
1109 polarity
= default_PCI_polarity(idx
);
1111 case 1: /* high active */
1116 case 2: /* reserved */
1118 printk(KERN_WARNING
"broken BIOS!!\n");
1122 case 3: /* low active */
1127 default: /* invalid */
1129 printk(KERN_WARNING
"broken BIOS!!\n");
1137 static int MPBIOS_trigger(int idx
)
1139 int bus
= mp_irqs
[idx
].srcbus
;
1143 * Determine IRQ trigger mode (edge or level sensitive):
1145 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
1147 case 0: /* conforms, ie. bus-type dependent */
1148 if (test_bit(bus
, mp_bus_not_pci
))
1149 trigger
= default_ISA_trigger(idx
);
1151 trigger
= default_PCI_trigger(idx
);
1152 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1153 switch (mp_bus_id_to_type
[bus
]) {
1154 case MP_BUS_ISA
: /* ISA pin */
1156 /* set before the switch */
1159 case MP_BUS_EISA
: /* EISA pin */
1161 trigger
= default_EISA_trigger(idx
);
1164 case MP_BUS_PCI
: /* PCI pin */
1166 /* set before the switch */
1169 case MP_BUS_MCA
: /* MCA pin */
1171 trigger
= default_MCA_trigger(idx
);
1176 printk(KERN_WARNING
"broken BIOS!!\n");
1188 case 2: /* reserved */
1190 printk(KERN_WARNING
"broken BIOS!!\n");
1199 default: /* invalid */
1201 printk(KERN_WARNING
"broken BIOS!!\n");
1209 static inline int irq_polarity(int idx
)
1211 return MPBIOS_polarity(idx
);
1214 static inline int irq_trigger(int idx
)
1216 return MPBIOS_trigger(idx
);
1219 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1220 static int pin_2_irq(int idx
, int apic
, int pin
)
1223 int bus
= mp_irqs
[idx
].srcbus
;
1226 * Debugging check, we are in big trouble if this message pops up!
1228 if (mp_irqs
[idx
].dstirq
!= pin
)
1229 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1231 if (test_bit(bus
, mp_bus_not_pci
)) {
1232 irq
= mp_irqs
[idx
].srcbusirq
;
1235 * PCI IRQs are mapped in order
1239 irq
+= nr_ioapic_registers
[i
++];
1242 * For MPS mode, so far only needed by ES7000 platform
1244 if (ioapic_renumber_irq
)
1245 irq
= ioapic_renumber_irq(apic
, irq
);
1248 #ifdef CONFIG_X86_32
1250 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1252 if ((pin
>= 16) && (pin
<= 23)) {
1253 if (pirq_entries
[pin
-16] != -1) {
1254 if (!pirq_entries
[pin
-16]) {
1255 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1256 "disabling PIRQ%d\n", pin
-16);
1258 irq
= pirq_entries
[pin
-16];
1259 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1260 "using PIRQ%d -> IRQ %d\n",
1270 void lock_vector_lock(void)
1272 /* Used to the online set of cpus does not change
1273 * during assign_irq_vector.
1275 spin_lock(&vector_lock
);
1278 void unlock_vector_lock(void)
1280 spin_unlock(&vector_lock
);
1284 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1287 * NOTE! The local APIC isn't very good at handling
1288 * multiple interrupts at the same interrupt level.
1289 * As the interrupt level is determined by taking the
1290 * vector number and shifting that right by 4, we
1291 * want to spread these out a bit so that they don't
1292 * all fall in the same interrupt level.
1294 * Also, we've got to be careful not to trash gate
1295 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1297 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1298 unsigned int old_vector
;
1300 cpumask_var_t tmp_mask
;
1302 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1305 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1308 old_vector
= cfg
->vector
;
1310 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1311 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1312 if (!cpumask_empty(tmp_mask
)) {
1313 free_cpumask_var(tmp_mask
);
1318 /* Only try and allocate irqs on cpus that are present */
1320 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1324 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1326 vector
= current_vector
;
1327 offset
= current_offset
;
1330 if (vector
>= first_system_vector
) {
1331 /* If out of vectors on large boxen, must share them. */
1332 offset
= (offset
+ 1) % 8;
1333 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1335 if (unlikely(current_vector
== vector
))
1338 if (test_bit(vector
, used_vectors
))
1341 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1342 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1345 current_vector
= vector
;
1346 current_offset
= offset
;
1348 cfg
->move_in_progress
= 1;
1349 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1351 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1352 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1353 cfg
->vector
= vector
;
1354 cpumask_copy(cfg
->domain
, tmp_mask
);
1358 free_cpumask_var(tmp_mask
);
1363 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1366 unsigned long flags
;
1368 spin_lock_irqsave(&vector_lock
, flags
);
1369 err
= __assign_irq_vector(irq
, cfg
, mask
);
1370 spin_unlock_irqrestore(&vector_lock
, flags
);
1374 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1378 BUG_ON(!cfg
->vector
);
1380 vector
= cfg
->vector
;
1381 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1382 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1385 cpumask_clear(cfg
->domain
);
1387 if (likely(!cfg
->move_in_progress
))
1389 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1390 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1392 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1394 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1398 cfg
->move_in_progress
= 0;
1401 void __setup_vector_irq(int cpu
)
1403 /* Initialize vector_irq on a new cpu */
1404 /* This function must be called with vector_lock held */
1406 struct irq_cfg
*cfg
;
1407 struct irq_desc
*desc
;
1409 /* Mark the inuse vectors */
1410 for_each_irq_desc(irq
, desc
) {
1411 cfg
= desc
->chip_data
;
1412 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1414 vector
= cfg
->vector
;
1415 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1417 /* Mark the free vectors */
1418 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1419 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1424 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1425 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1429 static struct irq_chip ioapic_chip
;
1430 static struct irq_chip ir_ioapic_chip
;
1431 static struct irq_chip msi_ir_chip
;
1433 #define IOAPIC_AUTO -1
1434 #define IOAPIC_EDGE 0
1435 #define IOAPIC_LEVEL 1
1437 #ifdef CONFIG_X86_32
1438 static inline int IO_APIC_irq_trigger(int irq
)
1442 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1443 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1444 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1445 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1446 return irq_trigger(idx
);
1450 * nonexistent IRQs are edge default
1455 static inline int IO_APIC_irq_trigger(int irq
)
1461 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1464 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1465 trigger
== IOAPIC_LEVEL
)
1466 desc
->status
|= IRQ_LEVEL
;
1468 desc
->status
&= ~IRQ_LEVEL
;
1470 if (irq_remapped(irq
)) {
1471 desc
->status
|= IRQ_MOVE_PCNTXT
;
1473 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1477 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1478 handle_edge_irq
, "edge");
1482 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1483 trigger
== IOAPIC_LEVEL
)
1484 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1488 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1489 handle_edge_irq
, "edge");
1492 int setup_ioapic_entry(int apic_id
, int irq
,
1493 struct IO_APIC_route_entry
*entry
,
1494 unsigned int destination
, int trigger
,
1495 int polarity
, int vector
, int pin
)
1498 * add it to the IO-APIC irq-routing table:
1500 memset(entry
,0,sizeof(*entry
));
1502 if (intr_remapping_enabled
) {
1503 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1505 struct IR_IO_APIC_route_entry
*ir_entry
=
1506 (struct IR_IO_APIC_route_entry
*) entry
;
1510 panic("No mapping iommu for ioapic %d\n", apic_id
);
1512 index
= alloc_irte(iommu
, irq
, 1);
1514 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1516 memset(&irte
, 0, sizeof(irte
));
1519 irte
.dst_mode
= apic
->irq_dest_mode
;
1521 * Trigger mode in the IRTE will always be edge, and the
1522 * actual level or edge trigger will be setup in the IO-APIC
1523 * RTE. This will help simplify level triggered irq migration.
1524 * For more details, see the comments above explainig IO-APIC
1525 * irq migration in the presence of interrupt-remapping.
1527 irte
.trigger_mode
= 0;
1528 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
1529 irte
.vector
= vector
;
1530 irte
.dest_id
= IRTE_DEST(destination
);
1532 modify_irte(irq
, &irte
);
1534 ir_entry
->index2
= (index
>> 15) & 0x1;
1536 ir_entry
->format
= 1;
1537 ir_entry
->index
= (index
& 0x7fff);
1539 * IO-APIC RTE will be configured with virtual vector.
1540 * irq handler will do the explicit EOI to the io-apic.
1542 ir_entry
->vector
= pin
;
1544 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1545 entry
->dest_mode
= apic
->irq_dest_mode
;
1546 entry
->dest
= destination
;
1547 entry
->vector
= vector
;
1550 entry
->mask
= 0; /* enable IRQ */
1551 entry
->trigger
= trigger
;
1552 entry
->polarity
= polarity
;
1554 /* Mask level triggered irqs.
1555 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1562 static void setup_IO_APIC_irq(int apic_id
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1563 int trigger
, int polarity
)
1565 struct irq_cfg
*cfg
;
1566 struct IO_APIC_route_entry entry
;
1569 if (!IO_APIC_IRQ(irq
))
1572 cfg
= desc
->chip_data
;
1574 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1577 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1579 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1580 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1581 "IRQ %d Mode:%i Active:%i)\n",
1582 apic_id
, mp_ioapics
[apic_id
].apicid
, pin
, cfg
->vector
,
1583 irq
, trigger
, polarity
);
1586 if (setup_ioapic_entry(mp_ioapics
[apic_id
].apicid
, irq
, &entry
,
1587 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1588 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1589 mp_ioapics
[apic_id
].apicid
, pin
);
1590 __clear_irq_vector(irq
, cfg
);
1594 ioapic_register_intr(irq
, desc
, trigger
);
1595 if (irq
< NR_IRQS_LEGACY
)
1596 disable_8259A_irq(irq
);
1598 ioapic_write_entry(apic_id
, pin
, entry
);
1601 static void __init
setup_IO_APIC_irqs(void)
1603 int apic_id
, pin
, idx
, irq
;
1605 struct irq_desc
*desc
;
1606 struct irq_cfg
*cfg
;
1607 int cpu
= boot_cpu_id
;
1609 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1611 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
1612 for (pin
= 0; pin
< nr_ioapic_registers
[apic_id
]; pin
++) {
1614 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1618 apic_printk(APIC_VERBOSE
,
1619 KERN_DEBUG
" %d-%d",
1620 mp_ioapics
[apic_id
].apicid
, pin
);
1622 apic_printk(APIC_VERBOSE
, " %d-%d",
1623 mp_ioapics
[apic_id
].apicid
, pin
);
1627 apic_printk(APIC_VERBOSE
,
1628 " (apicid-pin) not connected\n");
1632 irq
= pin_2_irq(idx
, apic_id
, pin
);
1635 * Skip the timer IRQ if there's a quirk handler
1636 * installed and if it returns 1:
1638 if (apic
->multi_timer_check
&&
1639 apic
->multi_timer_check(apic_id
, irq
))
1642 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
1644 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1647 cfg
= desc
->chip_data
;
1648 add_pin_to_irq_cpu(cfg
, cpu
, apic_id
, pin
);
1650 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1651 irq_trigger(idx
), irq_polarity(idx
));
1656 apic_printk(APIC_VERBOSE
,
1657 " (apicid-pin) not connected\n");
1661 * Set up the timer pin, possibly with the 8259A-master behind.
1663 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1666 struct IO_APIC_route_entry entry
;
1668 if (intr_remapping_enabled
)
1671 memset(&entry
, 0, sizeof(entry
));
1674 * We use logical delivery to get the timer IRQ
1677 entry
.dest_mode
= apic
->irq_dest_mode
;
1678 entry
.mask
= 0; /* don't mask IRQ for edge */
1679 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1680 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1683 entry
.vector
= vector
;
1686 * The timer IRQ doesn't have to know that behind the
1687 * scene we may have a 8259A-master in AEOI mode ...
1689 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1692 * Add it to the IO-APIC irq-routing table:
1694 ioapic_write_entry(apic_id
, pin
, entry
);
1698 __apicdebuginit(void) print_IO_APIC(void)
1701 union IO_APIC_reg_00 reg_00
;
1702 union IO_APIC_reg_01 reg_01
;
1703 union IO_APIC_reg_02 reg_02
;
1704 union IO_APIC_reg_03 reg_03
;
1705 unsigned long flags
;
1706 struct irq_cfg
*cfg
;
1707 struct irq_desc
*desc
;
1710 if (apic_verbosity
== APIC_QUIET
)
1713 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1714 for (i
= 0; i
< nr_ioapics
; i
++)
1715 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1716 mp_ioapics
[i
].apicid
, nr_ioapic_registers
[i
]);
1719 * We are a bit conservative about what we expect. We have to
1720 * know about every hardware change ASAP.
1722 printk(KERN_INFO
"testing the IO APIC.......................\n");
1724 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1726 spin_lock_irqsave(&ioapic_lock
, flags
);
1727 reg_00
.raw
= io_apic_read(apic
, 0);
1728 reg_01
.raw
= io_apic_read(apic
, 1);
1729 if (reg_01
.bits
.version
>= 0x10)
1730 reg_02
.raw
= io_apic_read(apic
, 2);
1731 if (reg_01
.bits
.version
>= 0x20)
1732 reg_03
.raw
= io_apic_read(apic
, 3);
1733 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1736 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].apicid
);
1737 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1738 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1739 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1740 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1742 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1743 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1745 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1746 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1749 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1750 * but the value of reg_02 is read as the previous read register
1751 * value, so ignore it if reg_02 == reg_01.
1753 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1754 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1755 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1759 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1760 * or reg_03, but the value of reg_0[23] is read as the previous read
1761 * register value, so ignore it if reg_03 == reg_0[12].
1763 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1764 reg_03
.raw
!= reg_01
.raw
) {
1765 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1766 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1769 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1771 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1772 " Stat Dmod Deli Vect: \n");
1774 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1775 struct IO_APIC_route_entry entry
;
1777 entry
= ioapic_read_entry(apic
, i
);
1779 printk(KERN_DEBUG
" %02x %03X ",
1784 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1789 entry
.delivery_status
,
1791 entry
.delivery_mode
,
1796 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1797 for_each_irq_desc(irq
, desc
) {
1798 struct irq_pin_list
*entry
;
1800 cfg
= desc
->chip_data
;
1801 entry
= cfg
->irq_2_pin
;
1804 printk(KERN_DEBUG
"IRQ%d ", irq
);
1806 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1809 entry
= entry
->next
;
1814 printk(KERN_INFO
".................................... done.\n");
1819 __apicdebuginit(void) print_APIC_bitfield(int base
)
1824 if (apic_verbosity
== APIC_QUIET
)
1827 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1828 for (i
= 0; i
< 8; i
++) {
1829 v
= apic_read(base
+ i
*0x10);
1830 for (j
= 0; j
< 32; j
++) {
1840 __apicdebuginit(void) print_local_APIC(void *dummy
)
1842 unsigned int v
, ver
, maxlvt
;
1845 if (apic_verbosity
== APIC_QUIET
)
1848 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1849 smp_processor_id(), hard_smp_processor_id());
1850 v
= apic_read(APIC_ID
);
1851 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1852 v
= apic_read(APIC_LVR
);
1853 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1854 ver
= GET_APIC_VERSION(v
);
1855 maxlvt
= lapic_get_maxlvt();
1857 v
= apic_read(APIC_TASKPRI
);
1858 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1860 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1861 if (!APIC_XAPIC(ver
)) {
1862 v
= apic_read(APIC_ARBPRI
);
1863 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1864 v
& APIC_ARBPRI_MASK
);
1866 v
= apic_read(APIC_PROCPRI
);
1867 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1871 * Remote read supported only in the 82489DX and local APIC for
1872 * Pentium processors.
1874 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1875 v
= apic_read(APIC_RRR
);
1876 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1879 v
= apic_read(APIC_LDR
);
1880 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1881 if (!x2apic_enabled()) {
1882 v
= apic_read(APIC_DFR
);
1883 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1885 v
= apic_read(APIC_SPIV
);
1886 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1888 printk(KERN_DEBUG
"... APIC ISR field:\n");
1889 print_APIC_bitfield(APIC_ISR
);
1890 printk(KERN_DEBUG
"... APIC TMR field:\n");
1891 print_APIC_bitfield(APIC_TMR
);
1892 printk(KERN_DEBUG
"... APIC IRR field:\n");
1893 print_APIC_bitfield(APIC_IRR
);
1895 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1896 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1897 apic_write(APIC_ESR
, 0);
1899 v
= apic_read(APIC_ESR
);
1900 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1903 icr
= apic_icr_read();
1904 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1905 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1907 v
= apic_read(APIC_LVTT
);
1908 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1910 if (maxlvt
> 3) { /* PC is LVT#4. */
1911 v
= apic_read(APIC_LVTPC
);
1912 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1914 v
= apic_read(APIC_LVT0
);
1915 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1916 v
= apic_read(APIC_LVT1
);
1917 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1919 if (maxlvt
> 2) { /* ERR is LVT#3. */
1920 v
= apic_read(APIC_LVTERR
);
1921 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1924 v
= apic_read(APIC_TMICT
);
1925 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1926 v
= apic_read(APIC_TMCCT
);
1927 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1928 v
= apic_read(APIC_TDCR
);
1929 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1933 __apicdebuginit(void) print_all_local_APICs(void)
1938 for_each_online_cpu(cpu
)
1939 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1943 __apicdebuginit(void) print_PIC(void)
1946 unsigned long flags
;
1948 if (apic_verbosity
== APIC_QUIET
)
1951 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1953 spin_lock_irqsave(&i8259A_lock
, flags
);
1955 v
= inb(0xa1) << 8 | inb(0x21);
1956 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1958 v
= inb(0xa0) << 8 | inb(0x20);
1959 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1963 v
= inb(0xa0) << 8 | inb(0x20);
1967 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1969 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1971 v
= inb(0x4d1) << 8 | inb(0x4d0);
1972 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1975 __apicdebuginit(int) print_all_ICs(void)
1978 print_all_local_APICs();
1984 fs_initcall(print_all_ICs
);
1987 /* Where if anywhere is the i8259 connect in external int mode */
1988 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1990 void __init
enable_IO_APIC(void)
1992 union IO_APIC_reg_01 reg_01
;
1993 int i8259_apic
, i8259_pin
;
1995 unsigned long flags
;
1998 * The number of IO-APIC IRQ registers (== #pins):
2000 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
2001 spin_lock_irqsave(&ioapic_lock
, flags
);
2002 reg_01
.raw
= io_apic_read(apic
, 1);
2003 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2004 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
2006 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
2008 /* See if any of the pins is in ExtINT mode */
2009 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
2010 struct IO_APIC_route_entry entry
;
2011 entry
= ioapic_read_entry(apic
, pin
);
2013 /* If the interrupt line is enabled and in ExtInt mode
2014 * I have found the pin where the i8259 is connected.
2016 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
2017 ioapic_i8259
.apic
= apic
;
2018 ioapic_i8259
.pin
= pin
;
2024 /* Look to see what if the MP table has reported the ExtINT */
2025 /* If we could not find the appropriate pin by looking at the ioapic
2026 * the i8259 probably is not connected the ioapic but give the
2027 * mptable a chance anyway.
2029 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
2030 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
2031 /* Trust the MP table if nothing is setup in the hardware */
2032 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
2033 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
2034 ioapic_i8259
.pin
= i8259_pin
;
2035 ioapic_i8259
.apic
= i8259_apic
;
2037 /* Complain if the MP table and the hardware disagree */
2038 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
2039 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
2041 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
2045 * Do not trust the IO-APIC being empty at bootup
2051 * Not an __init, needed by the reboot code
2053 void disable_IO_APIC(void)
2056 * Clear the IO-APIC before rebooting:
2061 * If the i8259 is routed through an IOAPIC
2062 * Put that IOAPIC in virtual wire mode
2063 * so legacy interrupts can be delivered.
2065 * With interrupt-remapping, for now we will use virtual wire A mode,
2066 * as virtual wire B is little complex (need to configure both
2067 * IOAPIC RTE aswell as interrupt-remapping table entry).
2068 * As this gets called during crash dump, keep this simple for now.
2070 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
2071 struct IO_APIC_route_entry entry
;
2073 memset(&entry
, 0, sizeof(entry
));
2074 entry
.mask
= 0; /* Enabled */
2075 entry
.trigger
= 0; /* Edge */
2077 entry
.polarity
= 0; /* High */
2078 entry
.delivery_status
= 0;
2079 entry
.dest_mode
= 0; /* Physical */
2080 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
2082 entry
.dest
= read_apic_id();
2085 * Add it to the IO-APIC irq-routing table:
2087 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
2091 * Use virtual wire A mode when interrupt remapping is enabled.
2093 disconnect_bsp_APIC(!intr_remapping_enabled
&& ioapic_i8259
.pin
!= -1);
2096 #ifdef CONFIG_X86_32
2098 * function to set the IO-APIC physical IDs based on the
2099 * values stored in the MPC table.
2101 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2104 static void __init
setup_ioapic_ids_from_mpc(void)
2106 union IO_APIC_reg_00 reg_00
;
2107 physid_mask_t phys_id_present_map
;
2110 unsigned char old_id
;
2111 unsigned long flags
;
2113 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
2117 * Don't check I/O APIC IDs for xAPIC systems. They have
2118 * no meaning without the serial APIC bus.
2120 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2121 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2124 * This is broken; anything with a real cpu count has to
2125 * circumvent this idiocy regardless.
2127 phys_id_present_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
2130 * Set the IOAPIC ID to the value stored in the MPC table.
2132 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
2134 /* Read the register 0 value */
2135 spin_lock_irqsave(&ioapic_lock
, flags
);
2136 reg_00
.raw
= io_apic_read(apic_id
, 0);
2137 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2139 old_id
= mp_ioapics
[apic_id
].apicid
;
2141 if (mp_ioapics
[apic_id
].apicid
>= get_physical_broadcast()) {
2142 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2143 apic_id
, mp_ioapics
[apic_id
].apicid
);
2144 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2146 mp_ioapics
[apic_id
].apicid
= reg_00
.bits
.ID
;
2150 * Sanity check, is the ID really free? Every APIC in a
2151 * system must have a unique ID or we get lots of nice
2152 * 'stuck on smp_invalidate_needed IPI wait' messages.
2154 if (apic
->check_apicid_used(phys_id_present_map
,
2155 mp_ioapics
[apic_id
].apicid
)) {
2156 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2157 apic_id
, mp_ioapics
[apic_id
].apicid
);
2158 for (i
= 0; i
< get_physical_broadcast(); i
++)
2159 if (!physid_isset(i
, phys_id_present_map
))
2161 if (i
>= get_physical_broadcast())
2162 panic("Max APIC ID exceeded!\n");
2163 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2165 physid_set(i
, phys_id_present_map
);
2166 mp_ioapics
[apic_id
].apicid
= i
;
2169 tmp
= apic
->apicid_to_cpu_present(mp_ioapics
[apic_id
].apicid
);
2170 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2171 "phys_id_present_map\n",
2172 mp_ioapics
[apic_id
].apicid
);
2173 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2178 * We need to adjust the IRQ routing table
2179 * if the ID changed.
2181 if (old_id
!= mp_ioapics
[apic_id
].apicid
)
2182 for (i
= 0; i
< mp_irq_entries
; i
++)
2183 if (mp_irqs
[i
].dstapic
== old_id
)
2185 = mp_ioapics
[apic_id
].apicid
;
2188 * Read the right value from the MPC table and
2189 * write it into the ID register.
2191 apic_printk(APIC_VERBOSE
, KERN_INFO
2192 "...changing IO-APIC physical APIC ID to %d ...",
2193 mp_ioapics
[apic_id
].apicid
);
2195 reg_00
.bits
.ID
= mp_ioapics
[apic_id
].apicid
;
2196 spin_lock_irqsave(&ioapic_lock
, flags
);
2197 io_apic_write(apic_id
, 0, reg_00
.raw
);
2198 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2203 spin_lock_irqsave(&ioapic_lock
, flags
);
2204 reg_00
.raw
= io_apic_read(apic_id
, 0);
2205 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2206 if (reg_00
.bits
.ID
!= mp_ioapics
[apic_id
].apicid
)
2207 printk("could not set ID!\n");
2209 apic_printk(APIC_VERBOSE
, " ok.\n");
2214 int no_timer_check __initdata
;
2216 static int __init
notimercheck(char *s
)
2221 __setup("no_timer_check", notimercheck
);
2224 * There is a nasty bug in some older SMP boards, their mptable lies
2225 * about the timer IRQ. We do the following to work around the situation:
2227 * - timer IRQ defaults to IO-APIC IRQ
2228 * - if this function detects that timer IRQs are defunct, then we fall
2229 * back to ISA timer IRQs
2231 static int __init
timer_irq_works(void)
2233 unsigned long t1
= jiffies
;
2234 unsigned long flags
;
2239 local_save_flags(flags
);
2241 /* Let ten ticks pass... */
2242 mdelay((10 * 1000) / HZ
);
2243 local_irq_restore(flags
);
2246 * Expect a few ticks at least, to be sure some possible
2247 * glue logic does not lock up after one or two first
2248 * ticks in a non-ExtINT mode. Also the local APIC
2249 * might have cached one ExtINT interrupt. Finally, at
2250 * least one tick may be lost due to delays.
2254 if (time_after(jiffies
, t1
+ 4))
2260 * In the SMP+IOAPIC case it might happen that there are an unspecified
2261 * number of pending IRQ events unhandled. These cases are very rare,
2262 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2263 * better to do it this way as thus we do not have to be aware of
2264 * 'pending' interrupts in the IRQ path, except at this point.
2267 * Edge triggered needs to resend any interrupt
2268 * that was delayed but this is now handled in the device
2273 * Starting up a edge-triggered IO-APIC interrupt is
2274 * nasty - we need to make sure that we get the edge.
2275 * If it is already asserted for some reason, we need
2276 * return 1 to indicate that is was pending.
2278 * This is not complete - we should be able to fake
2279 * an edge even if it isn't on the 8259A...
2282 static unsigned int startup_ioapic_irq(unsigned int irq
)
2284 int was_pending
= 0;
2285 unsigned long flags
;
2286 struct irq_cfg
*cfg
;
2288 spin_lock_irqsave(&ioapic_lock
, flags
);
2289 if (irq
< NR_IRQS_LEGACY
) {
2290 disable_8259A_irq(irq
);
2291 if (i8259A_irq_pending(irq
))
2295 __unmask_IO_APIC_irq(cfg
);
2296 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2301 #ifdef CONFIG_X86_64
2302 static int ioapic_retrigger_irq(unsigned int irq
)
2305 struct irq_cfg
*cfg
= irq_cfg(irq
);
2306 unsigned long flags
;
2308 spin_lock_irqsave(&vector_lock
, flags
);
2309 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2310 spin_unlock_irqrestore(&vector_lock
, flags
);
2315 static int ioapic_retrigger_irq(unsigned int irq
)
2317 apic
->send_IPI_self(irq_cfg(irq
)->vector
);
2324 * Level and edge triggered IO-APIC interrupts need different handling,
2325 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2326 * handled with the level-triggered descriptor, but that one has slightly
2327 * more overhead. Level-triggered interrupts cannot be handled with the
2328 * edge-triggered handler, without risking IRQ storms and other ugly
2334 #ifdef CONFIG_INTR_REMAP
2337 * Migrate the IO-APIC irq in the presence of intr-remapping.
2339 * For both level and edge triggered, irq migration is a simple atomic
2340 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2342 * For level triggered, we eliminate the io-apic RTE modification (with the
2343 * updated vector information), by using a virtual vector (io-apic pin number).
2344 * Real vector that is used for interrupting cpu will be coming from
2345 * the interrupt-remapping table entry.
2348 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2350 struct irq_cfg
*cfg
;
2355 if (!cpumask_intersects(mask
, cpu_online_mask
))
2359 if (get_irte(irq
, &irte
))
2362 cfg
= desc
->chip_data
;
2363 if (assign_irq_vector(irq
, cfg
, mask
))
2366 set_extra_move_desc(desc
, mask
);
2368 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2370 irte
.vector
= cfg
->vector
;
2371 irte
.dest_id
= IRTE_DEST(dest
);
2374 * Modified the IRTE and flushes the Interrupt entry cache.
2376 modify_irte(irq
, &irte
);
2378 if (cfg
->move_in_progress
)
2379 send_cleanup_vector(cfg
);
2381 cpumask_copy(desc
->affinity
, mask
);
2385 * Migrates the IRQ destination in the process context.
2387 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2388 const struct cpumask
*mask
)
2390 migrate_ioapic_irq_desc(desc
, mask
);
2392 static void set_ir_ioapic_affinity_irq(unsigned int irq
,
2393 const struct cpumask
*mask
)
2395 struct irq_desc
*desc
= irq_to_desc(irq
);
2397 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2400 static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2401 const struct cpumask
*mask
)
2406 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2408 unsigned vector
, me
;
2414 me
= smp_processor_id();
2415 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2417 struct irq_desc
*desc
;
2418 struct irq_cfg
*cfg
;
2419 irq
= __get_cpu_var(vector_irq
)[vector
];
2424 desc
= irq_to_desc(irq
);
2429 spin_lock(&desc
->lock
);
2430 if (!cfg
->move_cleanup_count
)
2433 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2436 __get_cpu_var(vector_irq
)[vector
] = -1;
2437 cfg
->move_cleanup_count
--;
2439 spin_unlock(&desc
->lock
);
2445 static void irq_complete_move(struct irq_desc
**descp
)
2447 struct irq_desc
*desc
= *descp
;
2448 struct irq_cfg
*cfg
= desc
->chip_data
;
2449 unsigned vector
, me
;
2451 if (likely(!cfg
->move_in_progress
)) {
2452 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2453 if (likely(!cfg
->move_desc_pending
))
2456 /* domain has not changed, but affinity did */
2457 me
= smp_processor_id();
2458 if (cpumask_test_cpu(me
, desc
->affinity
)) {
2459 *descp
= desc
= move_irq_desc(desc
, me
);
2460 /* get the new one */
2461 cfg
= desc
->chip_data
;
2462 cfg
->move_desc_pending
= 0;
2468 vector
= ~get_irq_regs()->orig_ax
;
2469 me
= smp_processor_id();
2471 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
)) {
2472 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2473 *descp
= desc
= move_irq_desc(desc
, me
);
2474 /* get the new one */
2475 cfg
= desc
->chip_data
;
2477 send_cleanup_vector(cfg
);
2481 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2484 #ifdef CONFIG_INTR_REMAP
2485 static void __eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2488 struct irq_pin_list
*entry
;
2490 entry
= cfg
->irq_2_pin
;
2498 io_apic_eoi(apic
, pin
);
2499 entry
= entry
->next
;
2504 eoi_ioapic_irq(struct irq_desc
*desc
)
2506 struct irq_cfg
*cfg
;
2507 unsigned long flags
;
2511 cfg
= desc
->chip_data
;
2513 spin_lock_irqsave(&ioapic_lock
, flags
);
2514 __eoi_ioapic_irq(irq
, cfg
);
2515 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2518 static void ack_x2apic_level(unsigned int irq
)
2520 struct irq_desc
*desc
= irq_to_desc(irq
);
2522 eoi_ioapic_irq(desc
);
2525 static void ack_x2apic_edge(unsigned int irq
)
2532 static void ack_apic_edge(unsigned int irq
)
2534 struct irq_desc
*desc
= irq_to_desc(irq
);
2536 irq_complete_move(&desc
);
2537 move_native_irq(irq
);
2541 atomic_t irq_mis_count
;
2543 static void ack_apic_level(unsigned int irq
)
2545 struct irq_desc
*desc
= irq_to_desc(irq
);
2547 #ifdef CONFIG_X86_32
2551 struct irq_cfg
*cfg
;
2552 int do_unmask_irq
= 0;
2554 irq_complete_move(&desc
);
2555 #ifdef CONFIG_GENERIC_PENDING_IRQ
2556 /* If we are moving the irq we need to mask it */
2557 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2559 mask_IO_APIC_irq_desc(desc
);
2563 #ifdef CONFIG_X86_32
2565 * It appears there is an erratum which affects at least version 0x11
2566 * of I/O APIC (that's the 82093AA and cores integrated into various
2567 * chipsets). Under certain conditions a level-triggered interrupt is
2568 * erroneously delivered as edge-triggered one but the respective IRR
2569 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2570 * message but it will never arrive and further interrupts are blocked
2571 * from the source. The exact reason is so far unknown, but the
2572 * phenomenon was observed when two consecutive interrupt requests
2573 * from a given source get delivered to the same CPU and the source is
2574 * temporarily disabled in between.
2576 * A workaround is to simulate an EOI message manually. We achieve it
2577 * by setting the trigger mode to edge and then to level when the edge
2578 * trigger mode gets detected in the TMR of a local APIC for a
2579 * level-triggered interrupt. We mask the source for the time of the
2580 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2581 * The idea is from Manfred Spraul. --macro
2583 cfg
= desc
->chip_data
;
2586 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2590 * We must acknowledge the irq before we move it or the acknowledge will
2591 * not propagate properly.
2595 /* Now we can move and renable the irq */
2596 if (unlikely(do_unmask_irq
)) {
2597 /* Only migrate the irq if the ack has been received.
2599 * On rare occasions the broadcast level triggered ack gets
2600 * delayed going to ioapics, and if we reprogram the
2601 * vector while Remote IRR is still set the irq will never
2604 * To prevent this scenario we read the Remote IRR bit
2605 * of the ioapic. This has two effects.
2606 * - On any sane system the read of the ioapic will
2607 * flush writes (and acks) going to the ioapic from
2609 * - We get to see if the ACK has actually been delivered.
2611 * Based on failed experiments of reprogramming the
2612 * ioapic entry from outside of irq context starting
2613 * with masking the ioapic entry and then polling until
2614 * Remote IRR was clear before reprogramming the
2615 * ioapic I don't trust the Remote IRR bit to be
2616 * completey accurate.
2618 * However there appears to be no other way to plug
2619 * this race, so if the Remote IRR bit is not
2620 * accurate and is causing problems then it is a hardware bug
2621 * and you can go talk to the chipset vendor about it.
2623 cfg
= desc
->chip_data
;
2624 if (!io_apic_level_ack_pending(cfg
))
2625 move_masked_irq(irq
);
2626 unmask_IO_APIC_irq_desc(desc
);
2629 #ifdef CONFIG_X86_32
2630 if (!(v
& (1 << (i
& 0x1f)))) {
2631 atomic_inc(&irq_mis_count
);
2632 spin_lock(&ioapic_lock
);
2633 __mask_and_edge_IO_APIC_irq(cfg
);
2634 __unmask_and_level_IO_APIC_irq(cfg
);
2635 spin_unlock(&ioapic_lock
);
2640 static struct irq_chip ioapic_chip __read_mostly
= {
2642 .startup
= startup_ioapic_irq
,
2643 .mask
= mask_IO_APIC_irq
,
2644 .unmask
= unmask_IO_APIC_irq
,
2645 .ack
= ack_apic_edge
,
2646 .eoi
= ack_apic_level
,
2648 .set_affinity
= set_ioapic_affinity_irq
,
2650 .retrigger
= ioapic_retrigger_irq
,
2653 #ifdef CONFIG_INTR_REMAP
2654 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2655 .name
= "IR-IO-APIC",
2656 .startup
= startup_ioapic_irq
,
2657 .mask
= mask_IO_APIC_irq
,
2658 .unmask
= unmask_IO_APIC_irq
,
2659 .ack
= ack_x2apic_edge
,
2660 .eoi
= ack_x2apic_level
,
2662 .set_affinity
= set_ir_ioapic_affinity_irq
,
2664 .retrigger
= ioapic_retrigger_irq
,
2668 static inline void init_IO_APIC_traps(void)
2671 struct irq_desc
*desc
;
2672 struct irq_cfg
*cfg
;
2675 * NOTE! The local APIC isn't very good at handling
2676 * multiple interrupts at the same interrupt level.
2677 * As the interrupt level is determined by taking the
2678 * vector number and shifting that right by 4, we
2679 * want to spread these out a bit so that they don't
2680 * all fall in the same interrupt level.
2682 * Also, we've got to be careful not to trash gate
2683 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2685 for_each_irq_desc(irq
, desc
) {
2686 cfg
= desc
->chip_data
;
2687 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2689 * Hmm.. We don't have an entry for this,
2690 * so default to an old-fashioned 8259
2691 * interrupt if we can..
2693 if (irq
< NR_IRQS_LEGACY
)
2694 make_8259A_irq(irq
);
2696 /* Strange. Oh, well.. */
2697 desc
->chip
= &no_irq_chip
;
2703 * The local APIC irq-chip implementation:
2706 static void mask_lapic_irq(unsigned int irq
)
2710 v
= apic_read(APIC_LVT0
);
2711 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2714 static void unmask_lapic_irq(unsigned int irq
)
2718 v
= apic_read(APIC_LVT0
);
2719 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2722 static void ack_lapic_irq(unsigned int irq
)
2727 static struct irq_chip lapic_chip __read_mostly
= {
2728 .name
= "local-APIC",
2729 .mask
= mask_lapic_irq
,
2730 .unmask
= unmask_lapic_irq
,
2731 .ack
= ack_lapic_irq
,
2734 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2736 desc
->status
&= ~IRQ_LEVEL
;
2737 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2741 static void __init
setup_nmi(void)
2744 * Dirty trick to enable the NMI watchdog ...
2745 * We put the 8259A master into AEOI mode and
2746 * unmask on all local APICs LVT0 as NMI.
2748 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2749 * is from Maciej W. Rozycki - so we do not have to EOI from
2750 * the NMI handler or the timer interrupt.
2752 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2754 enable_NMI_through_LVT0();
2756 apic_printk(APIC_VERBOSE
, " done.\n");
2760 * This looks a bit hackish but it's about the only one way of sending
2761 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2762 * not support the ExtINT mode, unfortunately. We need to send these
2763 * cycles as some i82489DX-based boards have glue logic that keeps the
2764 * 8259A interrupt line asserted until INTA. --macro
2766 static inline void __init
unlock_ExtINT_logic(void)
2769 struct IO_APIC_route_entry entry0
, entry1
;
2770 unsigned char save_control
, save_freq_select
;
2772 pin
= find_isa_irq_pin(8, mp_INT
);
2777 apic
= find_isa_irq_apic(8, mp_INT
);
2783 entry0
= ioapic_read_entry(apic
, pin
);
2784 clear_IO_APIC_pin(apic
, pin
);
2786 memset(&entry1
, 0, sizeof(entry1
));
2788 entry1
.dest_mode
= 0; /* physical delivery */
2789 entry1
.mask
= 0; /* unmask IRQ now */
2790 entry1
.dest
= hard_smp_processor_id();
2791 entry1
.delivery_mode
= dest_ExtINT
;
2792 entry1
.polarity
= entry0
.polarity
;
2796 ioapic_write_entry(apic
, pin
, entry1
);
2798 save_control
= CMOS_READ(RTC_CONTROL
);
2799 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2800 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2802 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2807 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2811 CMOS_WRITE(save_control
, RTC_CONTROL
);
2812 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2813 clear_IO_APIC_pin(apic
, pin
);
2815 ioapic_write_entry(apic
, pin
, entry0
);
2818 static int disable_timer_pin_1 __initdata
;
2819 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2820 static int __init
disable_timer_pin_setup(char *arg
)
2822 disable_timer_pin_1
= 1;
2825 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2827 int timer_through_8259 __initdata
;
2830 * This code may look a bit paranoid, but it's supposed to cooperate with
2831 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2832 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2833 * fanatically on his truly buggy board.
2835 * FIXME: really need to revamp this for all platforms.
2837 static inline void __init
check_timer(void)
2839 struct irq_desc
*desc
= irq_to_desc(0);
2840 struct irq_cfg
*cfg
= desc
->chip_data
;
2841 int cpu
= boot_cpu_id
;
2842 int apic1
, pin1
, apic2
, pin2
;
2843 unsigned long flags
;
2846 local_irq_save(flags
);
2849 * get/set the timer IRQ vector:
2851 disable_8259A_irq(0);
2852 assign_irq_vector(0, cfg
, apic
->target_cpus());
2855 * As IRQ0 is to be enabled in the 8259A, the virtual
2856 * wire has to be disabled in the local APIC. Also
2857 * timer interrupts need to be acknowledged manually in
2858 * the 8259A for the i82489DX when using the NMI
2859 * watchdog as that APIC treats NMIs as level-triggered.
2860 * The AEOI mode will finish them in the 8259A
2863 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2865 #ifdef CONFIG_X86_32
2869 ver
= apic_read(APIC_LVR
);
2870 ver
= GET_APIC_VERSION(ver
);
2871 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2875 pin1
= find_isa_irq_pin(0, mp_INT
);
2876 apic1
= find_isa_irq_apic(0, mp_INT
);
2877 pin2
= ioapic_i8259
.pin
;
2878 apic2
= ioapic_i8259
.apic
;
2880 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2881 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2882 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2885 * Some BIOS writers are clueless and report the ExtINTA
2886 * I/O APIC input from the cascaded 8259A as the timer
2887 * interrupt input. So just in case, if only one pin
2888 * was found above, try it both directly and through the
2892 if (intr_remapping_enabled
)
2893 panic("BIOS bug: timer not connected to IO-APIC");
2897 } else if (pin2
== -1) {
2904 * Ok, does IRQ0 through the IOAPIC work?
2907 add_pin_to_irq_cpu(cfg
, cpu
, apic1
, pin1
);
2908 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2910 /* for edge trigger, setup_IO_APIC_irq already
2911 * leave it unmasked.
2912 * so only need to unmask if it is level-trigger
2913 * do we really have level trigger timer?
2916 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2917 if (idx
!= -1 && irq_trigger(idx
))
2918 unmask_IO_APIC_irq_desc(desc
);
2920 if (timer_irq_works()) {
2921 if (nmi_watchdog
== NMI_IO_APIC
) {
2923 enable_8259A_irq(0);
2925 if (disable_timer_pin_1
> 0)
2926 clear_IO_APIC_pin(0, pin1
);
2929 if (intr_remapping_enabled
)
2930 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2931 local_irq_disable();
2932 clear_IO_APIC_pin(apic1
, pin1
);
2934 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2935 "8254 timer not connected to IO-APIC\n");
2937 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2938 "(IRQ0) through the 8259A ...\n");
2939 apic_printk(APIC_QUIET
, KERN_INFO
2940 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2942 * legacy devices should be connected to IO APIC #0
2944 replace_pin_at_irq_cpu(cfg
, cpu
, apic1
, pin1
, apic2
, pin2
);
2945 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2946 enable_8259A_irq(0);
2947 if (timer_irq_works()) {
2948 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2949 timer_through_8259
= 1;
2950 if (nmi_watchdog
== NMI_IO_APIC
) {
2951 disable_8259A_irq(0);
2953 enable_8259A_irq(0);
2958 * Cleanup, just in case ...
2960 local_irq_disable();
2961 disable_8259A_irq(0);
2962 clear_IO_APIC_pin(apic2
, pin2
);
2963 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2966 if (nmi_watchdog
== NMI_IO_APIC
) {
2967 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2968 "through the IO-APIC - disabling NMI Watchdog!\n");
2969 nmi_watchdog
= NMI_NONE
;
2971 #ifdef CONFIG_X86_32
2975 apic_printk(APIC_QUIET
, KERN_INFO
2976 "...trying to set up timer as Virtual Wire IRQ...\n");
2978 lapic_register_intr(0, desc
);
2979 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2980 enable_8259A_irq(0);
2982 if (timer_irq_works()) {
2983 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2986 local_irq_disable();
2987 disable_8259A_irq(0);
2988 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2989 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2991 apic_printk(APIC_QUIET
, KERN_INFO
2992 "...trying to set up timer as ExtINT IRQ...\n");
2996 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2998 unlock_ExtINT_logic();
3000 if (timer_irq_works()) {
3001 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3004 local_irq_disable();
3005 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3006 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3007 "report. Then try booting with the 'noapic' option.\n");
3009 local_irq_restore(flags
);
3013 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3014 * to devices. However there may be an I/O APIC pin available for
3015 * this interrupt regardless. The pin may be left unconnected, but
3016 * typically it will be reused as an ExtINT cascade interrupt for
3017 * the master 8259A. In the MPS case such a pin will normally be
3018 * reported as an ExtINT interrupt in the MP table. With ACPI
3019 * there is no provision for ExtINT interrupts, and in the absence
3020 * of an override it would be treated as an ordinary ISA I/O APIC
3021 * interrupt, that is edge-triggered and unmasked by default. We
3022 * used to do this, but it caused problems on some systems because
3023 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3024 * the same ExtINT cascade interrupt to drive the local APIC of the
3025 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3026 * the I/O APIC in all cases now. No actual device should request
3027 * it anyway. --macro
3029 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3031 void __init
setup_IO_APIC(void)
3035 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3038 io_apic_irqs
= ~PIC_IRQS
;
3040 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3042 * Set up IO-APIC IRQ routing.
3044 #ifdef CONFIG_X86_32
3046 setup_ioapic_ids_from_mpc();
3049 setup_IO_APIC_irqs();
3050 init_IO_APIC_traps();
3055 * Called after all the initialization is done. If we didnt find any
3056 * APIC bugs then we can allow the modify fast path
3059 static int __init
io_apic_bug_finalize(void)
3061 if (sis_apic_bug
== -1)
3066 late_initcall(io_apic_bug_finalize
);
3068 struct sysfs_ioapic_data
{
3069 struct sys_device dev
;
3070 struct IO_APIC_route_entry entry
[0];
3072 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3074 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3076 struct IO_APIC_route_entry
*entry
;
3077 struct sysfs_ioapic_data
*data
;
3080 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3081 entry
= data
->entry
;
3082 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3083 *entry
= ioapic_read_entry(dev
->id
, i
);
3088 static int ioapic_resume(struct sys_device
*dev
)
3090 struct IO_APIC_route_entry
*entry
;
3091 struct sysfs_ioapic_data
*data
;
3092 unsigned long flags
;
3093 union IO_APIC_reg_00 reg_00
;
3096 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3097 entry
= data
->entry
;
3099 spin_lock_irqsave(&ioapic_lock
, flags
);
3100 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3101 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].apicid
) {
3102 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].apicid
;
3103 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3105 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3106 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3107 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3112 static struct sysdev_class ioapic_sysdev_class
= {
3114 .suspend
= ioapic_suspend
,
3115 .resume
= ioapic_resume
,
3118 static int __init
ioapic_init_sysfs(void)
3120 struct sys_device
* dev
;
3123 error
= sysdev_class_register(&ioapic_sysdev_class
);
3127 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3128 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3129 * sizeof(struct IO_APIC_route_entry
);
3130 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3131 if (!mp_ioapic_data
[i
]) {
3132 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3135 dev
= &mp_ioapic_data
[i
]->dev
;
3137 dev
->cls
= &ioapic_sysdev_class
;
3138 error
= sysdev_register(dev
);
3140 kfree(mp_ioapic_data
[i
]);
3141 mp_ioapic_data
[i
] = NULL
;
3142 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3150 device_initcall(ioapic_init_sysfs
);
3152 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
3154 * Dynamic irq allocate and deallocation
3156 unsigned int create_irq_nr(unsigned int irq_want
)
3158 /* Allocate an unused irq */
3161 unsigned long flags
;
3162 struct irq_cfg
*cfg_new
= NULL
;
3163 int cpu
= boot_cpu_id
;
3164 struct irq_desc
*desc_new
= NULL
;
3167 if (irq_want
< nr_irqs_gsi
)
3168 irq_want
= nr_irqs_gsi
;
3170 spin_lock_irqsave(&vector_lock
, flags
);
3171 for (new = irq_want
; new < nr_irqs
; new++) {
3172 desc_new
= irq_to_desc_alloc_cpu(new, cpu
);
3174 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3177 cfg_new
= desc_new
->chip_data
;
3179 if (cfg_new
->vector
!= 0)
3181 if (__assign_irq_vector(new, cfg_new
, apic
->target_cpus()) == 0)
3185 spin_unlock_irqrestore(&vector_lock
, flags
);
3188 dynamic_irq_init(irq
);
3189 /* restore it, in case dynamic_irq_init clear it */
3191 desc_new
->chip_data
= cfg_new
;
3196 int create_irq(void)
3198 unsigned int irq_want
;
3201 irq_want
= nr_irqs_gsi
;
3202 irq
= create_irq_nr(irq_want
);
3210 void destroy_irq(unsigned int irq
)
3212 unsigned long flags
;
3213 struct irq_cfg
*cfg
;
3214 struct irq_desc
*desc
;
3216 /* store it, in case dynamic_irq_cleanup clear it */
3217 desc
= irq_to_desc(irq
);
3218 cfg
= desc
->chip_data
;
3219 dynamic_irq_cleanup(irq
);
3220 /* connect back irq_cfg */
3222 desc
->chip_data
= cfg
;
3225 spin_lock_irqsave(&vector_lock
, flags
);
3226 __clear_irq_vector(irq
, cfg
);
3227 spin_unlock_irqrestore(&vector_lock
, flags
);
3231 * MSI message composition
3233 #ifdef CONFIG_PCI_MSI
3234 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3236 struct irq_cfg
*cfg
;
3244 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3248 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3250 if (irq_remapped(irq
)) {
3255 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3256 BUG_ON(ir_index
== -1);
3258 memset (&irte
, 0, sizeof(irte
));
3261 irte
.dst_mode
= apic
->irq_dest_mode
;
3262 irte
.trigger_mode
= 0; /* edge */
3263 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
3264 irte
.vector
= cfg
->vector
;
3265 irte
.dest_id
= IRTE_DEST(dest
);
3267 modify_irte(irq
, &irte
);
3269 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3270 msg
->data
= sub_handle
;
3271 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3273 MSI_ADDR_IR_INDEX1(ir_index
) |
3274 MSI_ADDR_IR_INDEX2(ir_index
);
3276 if (x2apic_enabled())
3277 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3278 MSI_ADDR_EXT_DEST_ID(dest
);
3280 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3284 ((apic
->irq_dest_mode
== 0) ?
3285 MSI_ADDR_DEST_MODE_PHYSICAL
:
3286 MSI_ADDR_DEST_MODE_LOGICAL
) |
3287 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3288 MSI_ADDR_REDIRECTION_CPU
:
3289 MSI_ADDR_REDIRECTION_LOWPRI
) |
3290 MSI_ADDR_DEST_ID(dest
);
3293 MSI_DATA_TRIGGER_EDGE
|
3294 MSI_DATA_LEVEL_ASSERT
|
3295 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3296 MSI_DATA_DELIVERY_FIXED
:
3297 MSI_DATA_DELIVERY_LOWPRI
) |
3298 MSI_DATA_VECTOR(cfg
->vector
);
3304 static void set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3306 struct irq_desc
*desc
= irq_to_desc(irq
);
3307 struct irq_cfg
*cfg
;
3311 dest
= set_desc_affinity(desc
, mask
);
3312 if (dest
== BAD_APICID
)
3315 cfg
= desc
->chip_data
;
3317 read_msi_msg_desc(desc
, &msg
);
3319 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3320 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3321 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3322 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3324 write_msi_msg_desc(desc
, &msg
);
3326 #ifdef CONFIG_INTR_REMAP
3328 * Migrate the MSI irq to another cpumask. This migration is
3329 * done in the process context using interrupt-remapping hardware.
3332 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3334 struct irq_desc
*desc
= irq_to_desc(irq
);
3335 struct irq_cfg
*cfg
= desc
->chip_data
;
3339 if (get_irte(irq
, &irte
))
3342 dest
= set_desc_affinity(desc
, mask
);
3343 if (dest
== BAD_APICID
)
3346 irte
.vector
= cfg
->vector
;
3347 irte
.dest_id
= IRTE_DEST(dest
);
3350 * atomically update the IRTE with the new destination and vector.
3352 modify_irte(irq
, &irte
);
3355 * After this point, all the interrupts will start arriving
3356 * at the new destination. So, time to cleanup the previous
3357 * vector allocation.
3359 if (cfg
->move_in_progress
)
3360 send_cleanup_vector(cfg
);
3364 #endif /* CONFIG_SMP */
3367 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3368 * which implement the MSI or MSI-X Capability Structure.
3370 static struct irq_chip msi_chip
= {
3372 .unmask
= unmask_msi_irq
,
3373 .mask
= mask_msi_irq
,
3374 .ack
= ack_apic_edge
,
3376 .set_affinity
= set_msi_irq_affinity
,
3378 .retrigger
= ioapic_retrigger_irq
,
3381 #ifdef CONFIG_INTR_REMAP
3382 static struct irq_chip msi_ir_chip
= {
3383 .name
= "IR-PCI-MSI",
3384 .unmask
= unmask_msi_irq
,
3385 .mask
= mask_msi_irq
,
3386 .ack
= ack_x2apic_edge
,
3388 .set_affinity
= ir_set_msi_irq_affinity
,
3390 .retrigger
= ioapic_retrigger_irq
,
3395 * Map the PCI dev to the corresponding remapping hardware unit
3396 * and allocate 'nvec' consecutive interrupt-remapping table entries
3399 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3401 struct intel_iommu
*iommu
;
3404 iommu
= map_dev_to_ir(dev
);
3407 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3411 index
= alloc_irte(iommu
, irq
, nvec
);
3414 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3421 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3426 ret
= msi_compose_msg(dev
, irq
, &msg
);
3430 set_irq_msi(irq
, msidesc
);
3431 write_msi_msg(irq
, &msg
);
3433 if (irq_remapped(irq
)) {
3434 struct irq_desc
*desc
= irq_to_desc(irq
);
3436 * irq migration in process context
3438 desc
->status
|= IRQ_MOVE_PCNTXT
;
3439 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3441 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3443 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3448 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3451 int ret
, sub_handle
;
3452 struct msi_desc
*msidesc
;
3453 unsigned int irq_want
;
3454 struct intel_iommu
*iommu
= 0;
3457 irq_want
= nr_irqs_gsi
;
3459 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3460 irq
= create_irq_nr(irq_want
);
3464 if (!intr_remapping_enabled
)
3469 * allocate the consecutive block of IRTE's
3472 index
= msi_alloc_irte(dev
, irq
, nvec
);
3478 iommu
= map_dev_to_ir(dev
);
3484 * setup the mapping between the irq and the IRTE
3485 * base index, the sub_handle pointing to the
3486 * appropriate interrupt remap table entry.
3488 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3491 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3503 void arch_teardown_msi_irq(unsigned int irq
)
3508 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3510 static void dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3512 struct irq_desc
*desc
= irq_to_desc(irq
);
3513 struct irq_cfg
*cfg
;
3517 dest
= set_desc_affinity(desc
, mask
);
3518 if (dest
== BAD_APICID
)
3521 cfg
= desc
->chip_data
;
3523 dmar_msi_read(irq
, &msg
);
3525 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3526 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3527 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3528 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3530 dmar_msi_write(irq
, &msg
);
3533 #endif /* CONFIG_SMP */
3535 struct irq_chip dmar_msi_type
= {
3537 .unmask
= dmar_msi_unmask
,
3538 .mask
= dmar_msi_mask
,
3539 .ack
= ack_apic_edge
,
3541 .set_affinity
= dmar_msi_set_affinity
,
3543 .retrigger
= ioapic_retrigger_irq
,
3546 int arch_setup_dmar_msi(unsigned int irq
)
3551 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3554 dmar_msi_write(irq
, &msg
);
3555 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3561 #ifdef CONFIG_HPET_TIMER
3564 static void hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3566 struct irq_desc
*desc
= irq_to_desc(irq
);
3567 struct irq_cfg
*cfg
;
3571 dest
= set_desc_affinity(desc
, mask
);
3572 if (dest
== BAD_APICID
)
3575 cfg
= desc
->chip_data
;
3577 hpet_msi_read(irq
, &msg
);
3579 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3580 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3581 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3582 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3584 hpet_msi_write(irq
, &msg
);
3587 #endif /* CONFIG_SMP */
3589 struct irq_chip hpet_msi_type
= {
3591 .unmask
= hpet_msi_unmask
,
3592 .mask
= hpet_msi_mask
,
3593 .ack
= ack_apic_edge
,
3595 .set_affinity
= hpet_msi_set_affinity
,
3597 .retrigger
= ioapic_retrigger_irq
,
3600 int arch_setup_hpet_msi(unsigned int irq
)
3605 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3609 hpet_msi_write(irq
, &msg
);
3610 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
, handle_edge_irq
,
3617 #endif /* CONFIG_PCI_MSI */
3619 * Hypertransport interrupt support
3621 #ifdef CONFIG_HT_IRQ
3625 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3627 struct ht_irq_msg msg
;
3628 fetch_ht_irq_msg(irq
, &msg
);
3630 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3631 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3633 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3634 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3636 write_ht_irq_msg(irq
, &msg
);
3639 static void set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3641 struct irq_desc
*desc
= irq_to_desc(irq
);
3642 struct irq_cfg
*cfg
;
3645 dest
= set_desc_affinity(desc
, mask
);
3646 if (dest
== BAD_APICID
)
3649 cfg
= desc
->chip_data
;
3651 target_ht_irq(irq
, dest
, cfg
->vector
);
3656 static struct irq_chip ht_irq_chip
= {
3658 .mask
= mask_ht_irq
,
3659 .unmask
= unmask_ht_irq
,
3660 .ack
= ack_apic_edge
,
3662 .set_affinity
= set_ht_irq_affinity
,
3664 .retrigger
= ioapic_retrigger_irq
,
3667 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3669 struct irq_cfg
*cfg
;
3676 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3678 struct ht_irq_msg msg
;
3681 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3682 apic
->target_cpus());
3684 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3688 HT_IRQ_LOW_DEST_ID(dest
) |
3689 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3690 ((apic
->irq_dest_mode
== 0) ?
3691 HT_IRQ_LOW_DM_PHYSICAL
:
3692 HT_IRQ_LOW_DM_LOGICAL
) |
3693 HT_IRQ_LOW_RQEOI_EDGE
|
3694 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3695 HT_IRQ_LOW_MT_FIXED
:
3696 HT_IRQ_LOW_MT_ARBITRATED
) |
3697 HT_IRQ_LOW_IRQ_MASKED
;
3699 write_ht_irq_msg(irq
, &msg
);
3701 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3702 handle_edge_irq
, "edge");
3704 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3708 #endif /* CONFIG_HT_IRQ */
3710 #ifdef CONFIG_X86_UV
3712 * Re-target the irq to the specified CPU and enable the specified MMR located
3713 * on the specified blade to allow the sending of MSIs to the specified CPU.
3715 int arch_enable_uv_irq(char *irq_name
, unsigned int irq
, int cpu
, int mmr_blade
,
3716 unsigned long mmr_offset
)
3718 const struct cpumask
*eligible_cpu
= cpumask_of(cpu
);
3719 struct irq_cfg
*cfg
;
3721 unsigned long mmr_value
;
3722 struct uv_IO_APIC_route_entry
*entry
;
3723 unsigned long flags
;
3728 err
= assign_irq_vector(irq
, cfg
, eligible_cpu
);
3732 spin_lock_irqsave(&vector_lock
, flags
);
3733 set_irq_chip_and_handler_name(irq
, &uv_irq_chip
, handle_percpu_irq
,
3735 spin_unlock_irqrestore(&vector_lock
, flags
);
3738 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3739 BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3741 entry
->vector
= cfg
->vector
;
3742 entry
->delivery_mode
= apic
->irq_delivery_mode
;
3743 entry
->dest_mode
= apic
->irq_dest_mode
;
3744 entry
->polarity
= 0;
3747 entry
->dest
= apic
->cpu_mask_to_apicid(eligible_cpu
);
3749 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3750 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3756 * Disable the specified MMR located on the specified blade so that MSIs are
3757 * longer allowed to be sent.
3759 void arch_disable_uv_irq(int mmr_blade
, unsigned long mmr_offset
)
3761 unsigned long mmr_value
;
3762 struct uv_IO_APIC_route_entry
*entry
;
3766 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3767 BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3771 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3772 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3774 #endif /* CONFIG_X86_64 */
3776 int __init
io_apic_get_redir_entries (int ioapic
)
3778 union IO_APIC_reg_01 reg_01
;
3779 unsigned long flags
;
3781 spin_lock_irqsave(&ioapic_lock
, flags
);
3782 reg_01
.raw
= io_apic_read(ioapic
, 1);
3783 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3785 return reg_01
.bits
.entries
;
3788 void __init
probe_nr_irqs_gsi(void)
3792 nr
= acpi_probe_gsi();
3793 if (nr
> nr_irqs_gsi
) {
3796 /* for acpi=off or acpi is not compiled in */
3800 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3801 nr
+= io_apic_get_redir_entries(idx
) + 1;
3803 if (nr
> nr_irqs_gsi
)
3807 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3810 #ifdef CONFIG_SPARSE_IRQ
3811 int __init
arch_probe_nr_irqs(void)
3815 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3816 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3818 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3819 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3821 * for MSI and HT dyn irq
3823 nr
+= nr_irqs_gsi
* 16;
3832 /* --------------------------------------------------------------------------
3833 ACPI-based IOAPIC Configuration
3834 -------------------------------------------------------------------------- */
3838 #ifdef CONFIG_X86_32
3839 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3841 union IO_APIC_reg_00 reg_00
;
3842 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3844 unsigned long flags
;
3848 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3849 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3850 * supports up to 16 on one shared APIC bus.
3852 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3853 * advantage of new APIC bus architecture.
3856 if (physids_empty(apic_id_map
))
3857 apic_id_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
3859 spin_lock_irqsave(&ioapic_lock
, flags
);
3860 reg_00
.raw
= io_apic_read(ioapic
, 0);
3861 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3863 if (apic_id
>= get_physical_broadcast()) {
3864 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3865 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3866 apic_id
= reg_00
.bits
.ID
;
3870 * Every APIC in a system must have a unique ID or we get lots of nice
3871 * 'stuck on smp_invalidate_needed IPI wait' messages.
3873 if (apic
->check_apicid_used(apic_id_map
, apic_id
)) {
3875 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3876 if (!apic
->check_apicid_used(apic_id_map
, i
))
3880 if (i
== get_physical_broadcast())
3881 panic("Max apic_id exceeded!\n");
3883 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3884 "trying %d\n", ioapic
, apic_id
, i
);
3889 tmp
= apic
->apicid_to_cpu_present(apic_id
);
3890 physids_or(apic_id_map
, apic_id_map
, tmp
);
3892 if (reg_00
.bits
.ID
!= apic_id
) {
3893 reg_00
.bits
.ID
= apic_id
;
3895 spin_lock_irqsave(&ioapic_lock
, flags
);
3896 io_apic_write(ioapic
, 0, reg_00
.raw
);
3897 reg_00
.raw
= io_apic_read(ioapic
, 0);
3898 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3901 if (reg_00
.bits
.ID
!= apic_id
) {
3902 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3907 apic_printk(APIC_VERBOSE
, KERN_INFO
3908 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3913 int __init
io_apic_get_version(int ioapic
)
3915 union IO_APIC_reg_01 reg_01
;
3916 unsigned long flags
;
3918 spin_lock_irqsave(&ioapic_lock
, flags
);
3919 reg_01
.raw
= io_apic_read(ioapic
, 1);
3920 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3922 return reg_01
.bits
.version
;
3926 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
3928 struct irq_desc
*desc
;
3929 struct irq_cfg
*cfg
;
3930 int cpu
= boot_cpu_id
;
3932 if (!IO_APIC_IRQ(irq
)) {
3933 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3938 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
3940 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3945 * IRQs < 16 are already in the irq_2_pin[] map
3947 if (irq
>= NR_IRQS_LEGACY
) {
3948 cfg
= desc
->chip_data
;
3949 add_pin_to_irq_cpu(cfg
, cpu
, ioapic
, pin
);
3952 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, triggering
, polarity
);
3958 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
3962 if (skip_ioapic_setup
)
3965 for (i
= 0; i
< mp_irq_entries
; i
++)
3966 if (mp_irqs
[i
].irqtype
== mp_INT
&&
3967 mp_irqs
[i
].srcbusirq
== bus_irq
)
3969 if (i
>= mp_irq_entries
)
3972 *trigger
= irq_trigger(i
);
3973 *polarity
= irq_polarity(i
);
3977 #endif /* CONFIG_ACPI */
3980 * This function currently is only a helper for the i386 smp boot process where
3981 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3982 * so mask in all cases should simply be apic->target_cpus()
3985 void __init
setup_ioapic_dest(void)
3987 int pin
, ioapic
, irq
, irq_entry
;
3988 struct irq_desc
*desc
;
3989 struct irq_cfg
*cfg
;
3990 const struct cpumask
*mask
;
3992 if (skip_ioapic_setup
== 1)
3995 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
3996 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
3997 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3998 if (irq_entry
== -1)
4000 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4002 /* setup_IO_APIC_irqs could fail to get vector for some device
4003 * when you have too many devices, because at that time only boot
4006 desc
= irq_to_desc(irq
);
4007 cfg
= desc
->chip_data
;
4009 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
,
4010 irq_trigger(irq_entry
),
4011 irq_polarity(irq_entry
));
4017 * Honour affinities which have been set in early boot
4020 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4021 mask
= desc
->affinity
;
4023 mask
= apic
->target_cpus();
4025 if (intr_remapping_enabled
)
4026 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4028 set_ioapic_affinity_irq_desc(desc
, mask
);
4035 #define IOAPIC_RESOURCE_NAME_SIZE 11
4037 static struct resource
*ioapic_resources
;
4039 static struct resource
* __init
ioapic_setup_resources(void)
4042 struct resource
*res
;
4046 if (nr_ioapics
<= 0)
4049 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4052 mem
= alloc_bootmem(n
);
4056 mem
+= sizeof(struct resource
) * nr_ioapics
;
4058 for (i
= 0; i
< nr_ioapics
; i
++) {
4060 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4061 sprintf(mem
, "IOAPIC %u", i
);
4062 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4066 ioapic_resources
= res
;
4071 void __init
ioapic_init_mappings(void)
4073 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4074 struct resource
*ioapic_res
;
4077 ioapic_res
= ioapic_setup_resources();
4078 for (i
= 0; i
< nr_ioapics
; i
++) {
4079 if (smp_found_config
) {
4080 ioapic_phys
= mp_ioapics
[i
].apicaddr
;
4081 #ifdef CONFIG_X86_32
4084 "WARNING: bogus zero IO-APIC "
4085 "address found in MPTABLE, "
4086 "disabling IO/APIC support!\n");
4087 smp_found_config
= 0;
4088 skip_ioapic_setup
= 1;
4089 goto fake_ioapic_page
;
4093 #ifdef CONFIG_X86_32
4096 ioapic_phys
= (unsigned long)
4097 alloc_bootmem_pages(PAGE_SIZE
);
4098 ioapic_phys
= __pa(ioapic_phys
);
4100 set_fixmap_nocache(idx
, ioapic_phys
);
4101 apic_printk(APIC_VERBOSE
,
4102 "mapped IOAPIC to %08lx (%08lx)\n",
4103 __fix_to_virt(idx
), ioapic_phys
);
4106 if (ioapic_res
!= NULL
) {
4107 ioapic_res
->start
= ioapic_phys
;
4108 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
4114 static int __init
ioapic_insert_resources(void)
4117 struct resource
*r
= ioapic_resources
;
4121 "IO APIC resources could be not be allocated.\n");
4125 for (i
= 0; i
< nr_ioapics
; i
++) {
4126 insert_resource(&iomem_resource
, r
);
4133 /* Insert the IO APIC resources after PCI initialization has occured to handle
4134 * IO APICS that are mapped in on a BAR in PCI space. */
4135 late_initcall(ioapic_insert_resources
);