| blob | d5b65962dd36a0bf9050cd61c51140979f9ca3d2 |
1 /*
2 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
3 *
4 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
5 * Author: Thomas Dahlmann
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
22 /*
23 * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
24 * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
25 * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
26 *
27 * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
28 * be used as host port) and UOC bits PAD_EN and APU are set (should be done
29 * by BIOS init).
30 *
31 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
32 * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
33 * can be used with gadget ether.
34 */
36 /* debug control */
37 /* #define UDC_VERBOSE */
39 /* Driver strings */
43 /* system */
44 #include <linux/module.h>
45 #include <linux/pci.h>
46 #include <linux/kernel.h>
47 #include <linux/delay.h>
48 #include <linux/ioport.h>
49 #include <linux/sched.h>
50 #include <linux/slab.h>
51 #include <linux/errno.h>
52 #include <linux/init.h>
53 #include <linux/timer.h>
54 #include <linux/list.h>
55 #include <linux/interrupt.h>
56 #include <linux/ioctl.h>
57 #include <linux/fs.h>
58 #include <linux/dmapool.h>
59 #include <linux/moduleparam.h>
60 #include <linux/device.h>
61 #include <linux/io.h>
62 #include <linux/irq.h>
64 #include <asm/byteorder.h>
65 #include <asm/system.h>
66 #include <asm/unaligned.h>
68 /* gadget stack */
69 #include <linux/usb/ch9.h>
70 #include <linux/usb/gadget.h>
72 /* udc specific */
91 /* description */
95 /* structure to hold endpoint function pointers */
98 /* received setup data */
101 /* pointer to device object */
104 /* irq spin lock for soft reset */
106 /* stall spin lock */
109 /*
110 * slave mode: pending bytes in rx fifo after nyet,
111 * used if EPIN irq came but no req was available
112 */
115 /* count soft resets after suspend to avoid loop */
119 /* timer */
123 /* set_rde -- Is used to control enabling of RX DMA. Problem is
124 * that UDC has only one bit (RDE) to enable/disable RX DMA for
125 * all OUT endpoints. So we have to handle race conditions like
126 * when OUT data reaches the fifo but no request was queued yet.
127 * This cannot be solved by letting the RX DMA disabled until a
128 * request gets queued because there may be other OUT packets
129 * in the FIFO (important for not blocking control traffic).
130 * The value of set_rde controls the correspondig timer.
131 *
132 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
133 * set_rde 0 == do not touch RDE, do no start the RDE timer
134 * set_rde 1 == timer function will look whether FIFO has data
135 * set_rde 2 == set by timer function to enable RX DMA on next call
136 */
144 /* tasklet for usb disconnect */
149 /* endpoint names used for print */
152 ep0_string,
160 };
162 /* DMA usage flag */
164 /* packet per buffer dma */
166 /* with per descr. update */
168 /* buffer fill mode */
170 /* full speed only mode */
172 /* tx buffer size for high speed */
175 /* module parameters */
186 /*---------------------------------------------------------------------------*/
187 /* Prints UDC device registers and endpoint irq registers */
189 {
210 }
214 }
217 }
219 }
221 /* Masks unused interrupts */
223 {
224 u32 tmp;
226 /* mask all dev interrupts */
237 /* mask all ep interrupts */
241 }
243 /* Enables endpoint 0 interrupts */
245 {
246 u32 tmp;
250 /* read irq mask */
252 /* enable ep0 irq's */
258 }
260 /* Enables device interrupts for SET_INTF and SET_CONFIG */
262 {
263 u32 tmp;
267 /* read irq mask */
270 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
279 }
281 /* Calculates fifo start of endpoint based on preceeding endpoints */
283 {
285 u32 tmp;
294 /* traverse ep's */
297 /* read fifo size */
301 }
302 }
304 }
306 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
310 {
317 }
320 /* Enables endpoint, is called by gadget driver */
321 static int
323 {
326 u32 tmp;
328 u8 udc_csr_epix;
333 || !desc
350 /* set traffic type */
355 /* set max packet size */
362 /* IN ep */
365 /* ep ix in UDC CSR register space */
368 /* set buffer size (tx fifo entries) */
370 /* double buffering: fifo size = 2 x max packet size */
372 tmp,
373 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
375 UDC_EPIN_BUFF_SIZE);
378 /* calc. tx fifo base addr */
381 /* flush fifo */
386 /* OUT ep */
388 /* ep ix in UDC CSR register space */
391 /* set max packet size UDC CSR */
394 UDC_CSR_NE_MAX_PKT);
398 /* alloc and init BNA dummy request */
401 }
405 }
407 /* set ep values */
409 /* max packet */
411 /* ep number */
413 /* ep direction */
415 /* ep type */
417 /* ep config */
419 /* ep interface */
421 /* ep alt */
423 /* write reg */
426 /* enable ep irq */
431 /*
432 * clear NAK by writing CNAK
433 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
434 */
441 }
447 }
449 /* Resets endpoint */
451 {
452 u32 tmp;
460 /* set NAK */
466 /* disable interrupt */
472 /* unset P and IN bit of potential former DMA */
481 /* flush the fifo */
486 }
487 /* reset desc pointer */
489 }
491 /* Disables endpoint, is called by gadget driver */
493 {
513 }
515 /* Allocates request packet, called by gadget driver */
518 {
537 /* ep0 in requests are allocated from data pool here */
543 }
549 /* prevent from using desc. - set HOST BUSY */
551 UDC_DMA_STP_STS_BS_HOST_BUSY,
552 UDC_DMA_STP_STS_BS);
557 }
560 }
562 /* Frees request packet, called by gadget driver */
563 static void
565 {
579 /* free dma chain if created */
582 }
586 }
588 }
590 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
592 {
594 /* set last bit */
596 /* set next pointer to itself */
598 /* set HOST BUSY */
601 UDC_DMA_STP_STS_BS_DMA_DONE,
602 UDC_DMA_STP_STS_BS);
603 #ifdef UDC_VERBOSE
606 #endif
607 }
608 }
610 /* Allocate BNA dummy descriptor */
612 {
616 /* alloc the dummy request */
622 }
624 }
626 /* Write data to TX fifo for IN packets */
627 static void
629 {
649 /* dwords first */
652 }
654 /* remaining bytes must be written by byte access */
658 }
660 /* dummy write confirm */
662 }
664 /* Read dwords from RX fifo for OUT transfers */
666 {
673 }
675 }
677 /* Read bytes from RX fifo for OUT transfers */
679 {
681 u32 tmp;
685 /* dwords first */
688 }
690 /* remaining bytes must be read by byte access */
696 }
697 }
700 }
702 /* Read data from RX fifo for OUT transfers */
703 static int
705 {
711 /* received number bytes */
723 }
725 }
728 /* last packet ? */
733 /* read rx fifo bytes */
738 }
740 /* create/re-init a DMA descriptor or a DMA descriptor chain */
742 {
744 u32 tmp;
750 /* set buffer pointer */
753 /* set last bit */
756 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
764 }
767 /* write tx bytes */
771 UDC_DMA_IN_STS_TXBYTES);
773 }
774 }
776 }
783 /*
784 * if bytes < max packet then tx bytes must
785 * be written in packet per buffer mode
786 */
790 /* write tx bytes */
794 UDC_DMA_IN_STS_TXBYTES);
795 /* reset frame num */
799 UDC_DMA_IN_STS_FRAMENUM);
800 }
801 /* set HOST BUSY */
804 UDC_DMA_STP_STS_BS_HOST_BUSY,
805 UDC_DMA_STP_STS_BS);
808 /* set HOST READY */
811 UDC_DMA_STP_STS_BS_HOST_READY,
812 UDC_DMA_STP_STS_BS);
815 /* clear NAK by writing CNAK */
822 }
824 }
827 }
829 /* Completes request packet ... caller MUST hold lock */
830 static void
834 {
841 /* unmap DMA */
847 PCI_DMA_TODEVICE);
848 else
852 PCI_DMA_FROMDEVICE);
855 }
860 /* set new status if pending */
864 /* remove from ep queue */
874 }
876 /* frees pci pool descriptors of a DMA chain */
878 {
887 /* do not free first desc., will be done by free for request */
897 }
900 }
902 /* Iterates to the end of a DMA chain and returns last descriptor */
904 {
910 }
914 }
916 /* Iterates to the end of a DMA chain and counts bytes received */
918 {
920 u32 count;
923 /* received number bytes */
928 /* received number bytes */
931 UDC_DMA_OUT_STS_RXBYTES);
932 }
933 }
937 }
939 /* Creates or re-inits a DMA chain */
944 )
945 {
948 dma_addr_t dma_addr;
959 /* unset L bit in first desc for OUT */
962 }
964 /* alloc only new desc's if not already available */
967 len++;
968 }
971 /* shorter chain already allocated before */
974 }
977 }
980 /* gen. required number of descriptors and buffers */
982 /* create or determine next desc. */
992 /* first td */
999 }
1004 else
1007 /* short packet ? */
1011 /* short packet */
1013 }
1015 /* link td and assign tx bytes */
1020 /* req->td_data->next = virt_to_phys(td); */
1021 }
1022 /* write tx bytes */
1024 /* first desc */
1028 UDC_DMA_IN_STS_TXBYTES);
1029 /* second desc */
1031 txbytes,
1032 UDC_DMA_IN_STS_TXBYTES);
1033 }
1038 /* last->next = virt_to_phys(td); */
1039 }
1041 /* write tx bytes */
1043 txbytes,
1044 UDC_DMA_IN_STS_TXBYTES);
1045 }
1046 }
1048 }
1049 /* set last bit */
1052 /* last desc. points to itself */
1054 }
1057 }
1059 /* Enabling RX DMA */
1061 {
1062 u32 tmp;
1065 /* stop RDE timer */
1069 }
1070 /* set RDE */
1074 }
1076 /* Queues a request packet, called by gadget driver */
1077 static int
1079 {
1086 u32 tmp;
1088 /* check the inputs */
1105 /* map dma (usually done before) */
1113 PCI_DMA_TODEVICE);
1114 else
1118 PCI_DMA_FROMDEVICE);
1120 }
1131 /* on empty queue just do first transfer */
1133 /* zlp */
1135 /* IN zlp's are handled by hardware */
1138 /*
1139 * if set_config or set_intf is waiting for ack by zlp
1140 * then set CSR_DONE
1141 */
1147 }
1148 /* setup command is ACK'ed now by zlp */
1150 /* clear NAK by writing CNAK in EP0_IN */
1156 UDC_EP0IN_IX);
1158 }
1160 }
1165 /* write desc pointer to enable DMA */
1167 /* set HOST READY */
1170 UDC_DMA_IN_STS_BS_HOST_READY,
1171 UDC_DMA_IN_STS_BS);
1172 }
1174 /* disabled rx dma while descriptor update */
1176 /* stop RDE timer */
1180 }
1181 /* clear RDE */
1187 /*
1188 * if BNA occurred then let BNA dummy desc.
1189 * point to current desc.
1190 */
1196 }
1197 }
1198 /* write desc pointer */
1201 /* clear NAK by writing CNAK */
1208 }
1211 /* enable ep irq */
1215 }
1216 }
1220 /*
1221 * prep_dma not used for OUT ep's, this is not possible
1222 * for PPB modes, because of chain creation reasons
1223 */
1228 }
1229 }
1231 /* add request to ep queue */
1236 /* open rxfifo if out data queued */
1238 /* enable DMA */
1243 }
1244 /* stop OUT naking */
1249 /*
1250 * read pending bytes afer nyet:
1251 * referring to isr
1252 */
1254 /* finish */
1256 }
1259 }
1260 }
1261 }
1263 finished:
1266 }
1268 /* Empty request queue of an endpoint; caller holds spinlock */
1270 {
1277 queue);
1279 }
1280 }
1282 /* Dequeues a request packet, called by gadget driver */
1284 {
1300 /* request in processing or next one */
1306 u32 tmp;
1307 u32 dma_sts;
1308 /* stop potential receive DMA */
1312 /*
1313 * Cancel transfer later in ISR
1314 * if descriptor was touched.
1315 */
1317 UDC_DMA_OUT_STS_BS);
1324 }
1326 }
1327 }
1328 }
1334 }
1336 /* Halt or clear halt of endpoint */
1337 static int
1339 {
1341 u32 tmp;
1357 /* halt or clear halt */
1362 /*
1363 * set STALL
1364 * rxfifo empty not taken into acount
1365 */
1371 /* setup poll timer */
1374 HZ * UDC_POLLSTALL_TIMER_USECONDS
1379 }
1380 }
1381 }
1383 /* ep is halted by set_halt() before */
1386 /* clear stall bit */
1388 /* clear NAK by writing CNAK */
1393 }
1394 }
1397 }
1399 /* gadget interface */
1411 /* fifo ops not implemented */
1412 };
1414 /*-------------------------------------------------------------------------*/
1416 /* Get frame counter (not implemented) */
1418 {
1420 }
1422 /* Remote wakeup gadget interface */
1424 {
1433 }
1435 /* gadget operations */
1439 };
1441 /* Setups endpoint parameters, adds endpoints to linked list */
1443 {
1444 /* make gadget ep lists */
1453 /* fifo config */
1460 }
1462 /* init registers at driver load time */
1464 {
1465 u32 tmp;
1467 /* init controller by soft reset */
1470 /* mask not needed interrupts */
1473 /* put into initial config */
1475 /* link up all endpoints */
1478 /* program speed */
1484 }
1488 }
1490 /* Inits UDC context */
1492 {
1493 u32 tmp;
1499 /* stop RDE timer */
1503 }
1504 /* stop poll stall timer */
1507 }
1508 /* disable DMA */
1514 /* enable dynamic CSR programming */
1517 /* set self powered */
1519 /* set remote wakeupable */
1527 }
1529 /* Sets initial endpoint parameters */
1531 {
1533 u32 tmp;
1534 u32 reg;
1538 /* read enum speed */
1545 }
1547 /* set basic ep parameters */
1553 /* txfifo size is calculated at enable time */
1556 /* fifo size */
1564 }
1566 /*
1567 * ep will be reset only if ep was not enabled before to avoid
1568 * disabling ep interrupts when ENUM interrupt occurs but ep is
1569 * not enabled by gadget driver
1570 */
1573 }
1576 /*
1577 * ep->dma is not really used, just to indicate that
1578 * DMA is active: remove this
1579 * dma regs = dev control regs
1580 */
1583 /* nak OUT endpoints until enable - not for ep0 */
1586 /* set NAK */
1592 }
1593 }
1594 }
1595 /* EP0 max packet */
1599 UDC_FS_EP0OUT_MAX_PKT_SIZE;
1603 }
1605 /*
1606 * with suspend bug workaround, ep0 params for gadget driver
1607 * are set at gadget driver bind() call
1608 */
1613 /* init cfg/alt/int */
1617 }
1619 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1621 {
1627 /* put into initial config */
1630 /* enable device setup interrupts */
1632 }
1634 /*
1635 * Calls gadget with disconnect event and resets the UDC and makes
1636 * initial bringup to be ready for ep0 events
1637 */
1639 {
1645 /* mask interrupts */
1648 /* REVISIT there doesn't seem to be a point to having this
1649 * talk to a tasklet ... do it directly, we already hold
1650 * the spinlock needed to process the disconnect.
1651 */
1654 }
1656 /* Tasklet for disconnect to be outside of interrupt context */
1658 {
1660 u32 tmp;
1670 /* empty queues */
1673 }
1675 }
1677 /* disable ep0 */
1683 /* init controller by soft reset */
1685 soft_reset_occured++;
1686 }
1688 /* re-enable dev interrupts */
1690 /* back to full speed ? */
1695 }
1698 }
1700 /* Reset the UDC core */
1702 {
1706 /*
1707 * reset possible waiting interrupts, because int.
1708 * status is lost after soft reset,
1709 * ep int. status reset
1710 */
1712 /* device int. status reset */
1720 }
1722 /* RDE timer callback to set RDE bit */
1724 {
1725 u32 tmp;
1730 /*
1731 * open the fifo if fifo was filled on last timer call
1732 * conditionally
1733 */
1735 /* set RDE to receive setup data */
1742 /*
1743 * if fifo empty setup polling, do not just
1744 * open the fifo
1745 */
1749 }
1751 /*
1752 * fifo contains data now, setup timer for opening
1753 * the fifo when timer expires to be able to receive
1754 * setup packets, when data packets gets queued by
1755 * gadget layer then timer will forced to expire with
1756 * set_rde=0 (RDE is set in udc_queue())
1757 */
1758 set_rde++;
1759 /* debug: lhadmot_timer_start = 221070 */
1763 }
1764 }
1772 }
1774 /* Handle halt state, used in stall poll timer */
1776 {
1777 u32 tmp;
1778 /* set stall as long not halted */
1781 /* STALL cleared ? */
1783 /*
1784 * FIXME: MSC spec requires that stall remains
1785 * even on receivng of CLEAR_FEATURE HALT. So
1786 * we would set STALL again here to be compliant.
1787 * But with current mass storage drivers this does
1788 * not work (would produce endless host retries).
1789 * So we clear halt on CLEAR_FEATURE.
1790 *
1791 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1792 tmp |= AMD_BIT(UDC_EPCTL_S);
1793 writel(tmp, &ep->regs->ctl);*/
1795 /* clear NAK by writing CNAK */
1800 }
1801 }
1802 }
1804 /* Stall timer callback to poll S bit and set it again after */
1806 {
1811 /*
1812 * only one IN and OUT endpoints are handled
1813 * IN poll stall
1814 */
1819 /* OUT poll stall */
1825 /* setup timer again when still halted */
1828 HZ * UDC_POLLSTALL_TIMER_USECONDS
1831 }
1836 }
1838 /* Inits endpoint 0 so that SETUP packets are processed */
1840 {
1841 u32 tmp;
1845 /* flush fifo */
1850 /* set ep0 directions */
1854 /* set buffer size (tx fifo entries) of EP0_IN */
1858 UDC_EPIN_BUFF_SIZE);
1861 UDC_EPIN_BUFF_SIZE);
1864 /* set max packet size of EP0_IN */
1868 UDC_EP_MAX_PKT_SIZE);
1871 UDC_EP_MAX_PKT_SIZE);
1874 /* set max packet size of EP0_OUT */
1878 UDC_EP_MAX_PKT_SIZE);
1881 UDC_EP_MAX_PKT_SIZE);
1884 /* set max packet size of EP0 in UDC CSR */
1888 UDC_CSR_NE_MAX_PKT);
1891 UDC_CSR_NE_MAX_PKT);
1897 /* write dma desc address */
1902 /* stop RDE timer */
1906 }
1907 /* stop pollstall timer */
1910 }
1911 /* enable DMA */
1920 }
1922 }
1924 /* clear NAK by writing CNAK for EP0IN */
1931 /* clear NAK by writing CNAK for EP0OUT */
1937 }
1939 /* Make endpoint 0 ready for control traffic */
1941 {
1943 /* enable ep0 interrupts */
1945 /* enable device setup interrupts */
1949 }
1951 /* Called by gadget driver to register itself */
1953 {
1956 u32 tmp;
1972 /* Some gadget drivers use both ep0 directions.
1973 * NOTE: to gadget driver, ep0 is just one endpoint...
1974 */
1984 }
1986 /* get ready for ep0 traffic */
1989 /* clear SD */
1997 }
2000 /* shutdown requests and disconnect from gadget */
2001 static void
2005 {
2008 /* empty queues and init hardware */
2012 }
2018 }
2019 /* init */
2021 }
2023 /* Called by gadget driver to unregister itself */
2025 {
2028 u32 tmp;
2044 /* set SD */
2053 }
2057 /* Clear pending NAK bits */
2059 {
2060 u32 tmp;
2061 u32 reg;
2063 /* check epin's */
2068 /* clear NAK by writing CNAK */
2074 }
2075 }
2076 /* ... and ep0out */
2079 /* clear NAK by writing CNAK */
2086 }
2087 }
2089 /* Enabling RX DMA after setup packet */
2091 {
2093 /*
2094 * only enable RXDMA when no data endpoint enabled
2095 * or data is queued
2096 */
2100 /*
2101 * setup timer for enabling RDE (to not enable
2102 * RXFIFO DMA for data endpoints to early)
2103 */
2110 }
2111 }
2112 }
2113 }
2114 }
2117 /* Interrupt handler for data OUT traffic */
2119 {
2121 u32 tmp;
2133 /* BNA event ? */
2137 /* clear BNA */
2141 else
2145 }
2146 }
2147 /* HE event ? */
2151 /* clear HE */
2155 }
2159 /* next request */
2165 }
2167 /* fifo mode */
2170 /* read fifo */
2174 /* finish */
2176 /* next request */
2182 }
2184 /* DMA */
2188 /* check for DMA done */
2191 UDC_DMA_OUT_STS_BS);
2192 /* packet per buffer mode - rx bytes */
2194 /*
2195 * if BNA occurred then recover desc. from
2196 * BNA dummy desc.
2197 */
2204 }
2207 }
2209 /* buffer fill mode - rx bytes */
2211 /* received number bytes */
2213 UDC_DMA_OUT_STS_RXBYTES);
2215 /* packet per buffer mode - rx bytes */
2219 /* received number bytes */
2221 /* every desc. counts bytes */
2224 /* last desc. counts bytes */
2226 UDC_DMA_OUT_STS_RXBYTES);
2229 /*
2230 * on 64k packets the RXBYTES
2231 * field is zero
2232 */
2234 }
2235 }
2237 }
2245 }
2247 }
2250 /* complete request */
2253 /* next request */
2257 queue);
2258 /*
2259 * DMA may be already started by udc_queue()
2260 * called by gadget drivers completion
2261 * routine. This happens when queue
2262 * holds one request only.
2263 */
2265 /* next dma */
2268 /* write desc pointer */
2272 /* enable DMA */
2274 }
2276 /*
2277 * implant BNA dummy descriptor to allow
2278 * RXFIFO opening by RDE
2279 */
2281 /* write desc pointer */
2285 }
2287 /*
2288 * schedule timer for setting RDE if queue
2289 * remains empty to allow ep0 packets pass
2290 * through
2291 */
2295 jiffies
2300 }
2301 }
2304 }
2307 /*
2308 * RX DMA must be reenabled for each desc in PPBDU mode
2309 * and must be enabled for PPBNDU mode in case of BNA
2310 */
2312 }
2317 }
2319 /* check pending CNAKS */
2321 /* CNAk processing when rxfifo empty only */
2324 }
2325 }
2327 /* clear OUT bits in ep status */
2329 finished:
2331 }
2333 /* Interrupt handler for data IN traffic */
2335 {
2337 u32 tmp;
2338 u32 epsts;
2349 /* BNA ? */
2356 /* clear BNA */
2360 }
2361 }
2362 /* HE event ? */
2368 /* clear HE */
2372 }
2374 /* DMA completion */
2381 /*
2382 * length bytes transfered
2383 * check dma done of last desc. in PPBDU mode
2384 */
2388 dma_done =
2390 UDC_DMA_IN_STS_BS);
2391 /* don't care DMA done */
2393 }
2395 /* assume all bytes transferred */
2397 }
2400 /* complete req */
2403 /* further request available ? */
2405 /* disable interrupt */
2409 }
2410 }
2411 }
2414 }
2415 /*
2416 * status reg has IN bit set and TDC not set (if TDC was handled,
2417 * IN must not be handled (UDC defect) ?
2418 */
2423 /* next request */
2426 /* FIFO mode */
2428 /* write fifo */
2436 /* complete req */
2438 }
2439 /* DMA */
2447 /*
2448 * unset L bit of first desc.
2449 * for chain
2450 */
2455 UDC_DMA_IN_STS_L);
2456 }
2458 /* write desc pointer */
2461 /* set HOST READY */
2465 UDC_DMA_IN_STS_BS_HOST_READY,
2466 UDC_DMA_IN_STS_BS);
2468 /* set poll demand bit */
2472 }
2473 }
2475 }
2476 }
2477 /* clear status bits */
2480 finished:
2483 }
2485 /* Interrupt handler for Control OUT traffic */
2489 {
2491 u32 tmp;
2493 u32 count;
2500 /* clear irq */
2504 /* check BNA and clear if set */
2512 }
2514 /* type of data: SETUP or DATA 0 bytes */
2518 /* setup data */
2525 /* set NAK for EP0_IN */
2530 /* get setup data */
2533 /* clear OUT bits in ep status */
2541 /* set HOST READY */
2543 UDC_DMA_STP_STS_BS_HOST_READY;
2545 /* read fifo */
2547 }
2549 /* determine direction of control data */
2552 /* enable RDE */
2557 /*
2558 * implant BNA dummy descriptor to allow RXFIFO opening
2559 * by RDE
2560 */
2562 /* write desc pointer */
2566 }
2570 /*
2571 * setup timer for enabling RDE (to not enable
2572 * RXFIFO DMA for data to early)
2573 */
2580 }
2581 }
2582 }
2584 /*
2585 * mass storage reset must be processed here because
2586 * next packet may be a CLEAR_FEATURE HALT which would not
2587 * clear the stall bit when no STALL handshake was received
2588 * before (autostall can cause this)
2589 */
2593 /*
2594 * clear stall bits
2595 * only one IN and OUT endpoints are handled
2596 */
2601 }
2603 /* call gadget with setup data received */
2610 /* ep0 in returns data (not zlp) on IN phase */
2612 UDC_EP0IN_MAXPACKET) {
2613 /* clear NAK by writing CNAK in EP0_IN */
2619 /* if unsupported request then stall */
2627 /* clear NAK by writing CNAK in EP0_OUT */
2634 }
2637 /* clear OUT bits in ep status */
2640 }
2642 /* data packet 0 bytes */
2644 /* clear OUT bits in ep status */
2647 /* get setup data: only 0 packet */
2649 /* no req if 0 packet, just reactivate */
2653 /* set HOST READY */
2657 UDC_DMA_OUT_STS_BS_HOST_READY,
2658 UDC_DMA_OUT_STS_BS);
2659 /* enable RDE */
2664 /* control write */
2666 /* re-program desc. pointer for possible ZLPs */
2669 /* enable RDE */
2671 }
2674 /* received number bytes */
2677 /* out data for fifo mode not working */
2680 /* 0 packet or real data ? */
2684 /* dummy read confirm */
2687 }
2688 }
2689 }
2691 /* check pending CNAKS */
2693 /* CNAk processing when rxfifo empty only */
2696 }
2697 }
2699 finished:
2701 }
2703 /* Interrupt handler for Control IN traffic */
2705 {
2707 u32 tmp;
2714 /* clear irq */
2718 /* DMA completion */
2723 /* clear TDC bit */
2727 /* status reg has IN bit set ? */
2732 /* clear IN bit */
2735 }
2738 /* halt ep0in */
2744 /* next request */
2749 /* write desc pointer */
2751 /* set HOST READY */
2755 UDC_DMA_STP_STS_BS_HOST_READY,
2756 UDC_DMA_STP_STS_BS);
2758 /* set poll demand bit */
2759 tmp =
2765 /* all bytes will be transferred */
2768 /* complete req */
2772 /* write fifo */
2775 /* lengh bytes transfered */
2783 /* complete req */
2785 }
2786 }
2788 }
2789 }
2793 /* clear IN bit */
2796 }
2797 }
2800 }
2803 /* Interrupt handler for global device events */
2807 {
2809 u32 tmp;
2810 u32 cfg;
2812 u16 i;
2813 u8 udc_csr_epix;
2815 /* SET_CONFIG irq ? */
2819 /* read config value */
2826 /* make usb request for gadget driver */
2831 /* programm the NE registers */
2836 /* ep ix in UDC CSR register space */
2840 /* OUT ep */
2842 /* ep ix in UDC CSR register space */
2844 }
2847 /* ep cfg */
2849 UDC_CSR_NE_CFG);
2850 /* write reg */
2853 /* clear stall bits */
2858 }
2859 /* call gadget zero with setup data received */
2869 /* read interface and alt setting values */
2874 /* make usb request for gadget driver */
2884 /* programm the NE registers */
2889 /* ep ix in UDC CSR register space */
2893 /* OUT ep */
2895 /* ep ix in UDC CSR register space */
2897 }
2899 /* UDC CSR reg */
2900 /* set ep values */
2902 /* ep interface */
2904 UDC_CSR_NE_INTF);
2905 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2906 /* ep alt */
2908 UDC_CSR_NE_ALT);
2909 /* write reg */
2912 /* clear stall bits */
2917 }
2919 /* call gadget zero with setup data received */
2929 /* allow soft reset when suspend occurs */
2935 /* mask not needed interrupts */
2938 /* call gadget to resume and reset configs etc. */
2943 }
2947 /* disable ep0 to empty req queue */
2951 /* soft reset when rxfifo not empty */
2956 soft_reset_after_usbreset_occured++;
2957 }
2959 /*
2960 * DMA reset to kill potential old DMA hw hang,
2961 * POLL bit is already reset by ep_init() through
2962 * disconnect()
2963 */
2969 /* put into initial config */
2972 /* enable device setup interrupts */
2975 /* enable suspend interrupt */
2989 }
2996 /* disable ep0 to empty req queue */
3000 /* link up all endpoints */
3008 }
3010 /* init ep 0 */
3013 /* enable ep0 interrupts */
3015 }
3016 /* session valid change interrupt */
3021 /* check that session is not valid to detect disconnect */
3024 /* disable suspend interrupt */
3029 /* cleanup on disconnect */
3031 }
3033 }
3036 }
3038 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
3040 {
3042 u32 reg;
3043 u16 i;
3044 u32 ep_irq;
3049 /* check for ep irq */
3057 /*
3058 * data endpoint
3059 * iterate ep's
3060 */
3066 /* clear irq status */
3069 /* irq for out ep ? */
3072 else
3074 }
3076 }
3079 /* check for dev irq */
3082 /* clear irq */
3085 }
3090 }
3092 /* Tears down device */
3094 {
3097 }
3099 /* Cleanup on device remove */
3101 {
3102 /* remove timer */
3103 stop_timer++;
3108 /* remove pollstall timer */
3109 stop_pollstall_timer++;
3115 }
3117 /* Reset all pci context */
3119 {
3124 /* gadget driver must not be registered */
3127 /* dma pool cleanup */
3132 /* cleanup DMA desc's for ep0in */
3141 }
3143 /* reset controller */
3159 }
3161 /* create dma pools on init */
3163 {
3168 /* consistent DMA mode setting ? */
3174 }
3176 /* DMA setup */
3183 }
3185 /* EP0 in dma regs = dev control regs */
3188 /* dma desc for setup data */
3195 }
3196 /* setup */
3202 }
3205 /* data: 0 packets !? */
3211 }
3215 finished:
3217 }
3219 /* Called by pci bus driver to init pci context */
3223 )
3224 {
3230 /* one udc only */
3234 }
3236 /* init */
3241 }
3243 /* pci setup */
3249 }
3252 /* PCI resource allocation */
3262 }
3272 }
3280 }
3288 }
3293 /* chip revision for Hs AMD5536 */
3299 /* init dma pools */
3304 }
3312 /* general probing */
3316 finished:
3320 }
3322 /* general probe */
3324 {
3326 u32 reg;
3329 /* mark timer as not initialized */
3333 /* device struct setup */
3343 /* udc csr registers base */
3345 /* dev registers base */
3347 /* ep registers base */
3349 /* fifo's base */
3353 /* init registers, interrupts, ... */
3368 }
3377 /* timer init */
3381 /* timer pollstall init */
3386 /* set SD */
3391 /* print dev register info */
3396 finished:
3398 }
3400 /* Initiates a remote wakeup */
3402 {
3404 u32 tmp;
3418 }
3420 /* PCI device parameters */
3422 {
3426 },
3427 {},
3428 };
3431 /* PCI functions */
3437 };
3439 /* Inits driver */
3441 {
3443 }
3446 /* Cleans driver */
3448 {
3450 }