drivers/serial/sh-sci.h

   1 /* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
   2  *
   3  *  linux/drivers/serial/sh-sci.h
   4  *
   5  *  SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
   6  *  Copyright (C) 1999, 2000  Niibe Yutaka
   7  *  Copyright (C) 2000  Greg Banks
   8  *  Copyright (C) 2002, 2003  Paul Mundt
   9  *  Modified to support multiple serial ports. Stuart Menefy (May 2000).
  10  *  Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
  11  *  Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
  12  */
  13 #include <linux/serial_core.h>
  14 #include <asm/io.h>
  15
  16 #if defined(__H8300H__) || defined(__H8300S__)
  17 #include <asm/gpio.h>
  18 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
  19 #include <asm/regs306x.h>
  20 #endif
  21 #if defined(CONFIG_H8S2678)
  22 #include <asm/regs267x.h>
  23 #endif
  24 #endif
  25
  26 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
  27 # define SCSPTR 0xffffff7c /* 8 bit */
  28 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  29 # define SCI_ONLY
  30 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  31       defined(CONFIG_CPU_SUBTYPE_SH7709) || \
  32       defined(CONFIG_CPU_SUBTYPE_SH7706)
  33 # define SCPCR  0xA4000116 /* 16 bit SCI and SCIF */
  34 # define SCPDR  0xA4000136 /* 8  bit SCI and SCIF */
  35 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  36 # define SCI_AND_SCIF
  37 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
  38 # define SCIF0          0xA4400000
  39 # define SCIF2          0xA4410000
  40 # define SCSMR_Ir       0xA44A0000
  41 # define IRDA_SCIF      SCIF0
  42 # define SCPCR 0xA4000116
  43 # define SCPDR 0xA4000136
  44
  45 /* Set the clock source,
  46  * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
  47  * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
  48  */
  49 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
  50 # define SCIF_ONLY
  51 #elif defined(CONFIG_SH_RTS7751R2D)
  52 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  53 # define SCIF_ORER 0x0001   /* overrun error bit */
  54 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  55 # define SCIF_ONLY
  56 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
  57       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
  58       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
  59       defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
  60       defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
  61       defined(CONFIG_CPU_SUBTYPE_SH7751R)
  62 # define SCSPTR1 0xffe0001c /* 8  bit SCI */
  63 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  64 # define SCIF_ORER 0x0001   /* overrun error bit */
  65 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
  66         0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
  67         0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
  68 # define SCI_AND_SCIF
  69 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
  70 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
  71 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
  72 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
  73 # define SCIF_ORER 0x0001  /* overrun error bit */
  74 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  75 # define SCIF_ONLY
  76 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
  77 # define SCPCR  0xA4050116        /* 16 bit SCIF */
  78 # define SCPDR  0xA4050136        /* 16 bit SCIF */
  79 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
  80 # define SCIF_ONLY
  81 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
  82 # define SCSPTR0 0xA4400000       /* 16 bit SCIF */
  83 # define SCI_NPORTS 2
  84 # define SCIF_ORER 0x0001   /* overrun error bit */
  85 # define PACR 0xa4050100
  86 # define PBCR 0xa4050102
  87 # define SCSCR_INIT(port)          0x3B
  88 # define SCIF_ONLY
  89 #elif defined(CONFIG_CPU_SUBTYPE_SH73180)
  90 # define SCPDR  0xA4050138        /* 16 bit SCIF */
  91 # define SCSPTR2 SCPDR
  92 # define SCIF_ORER 0x0001   /* overrun error bit */
  93 # define SCSCR_INIT(port)  0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */
  94 # define SCIF_ONLY
  95 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
  96 # define SCSPTR0 0xffe00010     /* 16 bit SCIF */
  97 # define SCSPTR1 0xffe10010     /* 16 bit SCIF */
  98 # define SCSPTR2 0xffe20010     /* 16 bit SCIF */
  99 # define SCSPTR3 0xffe30010     /* 16 bit SCIF */
 100 # define SCSCR_INIT(port) 0x32  /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
 101 # define SCIF_ONLY
 102 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
 103 # define SCPDR0                 0xA405013E      /* 16 bit SCIF0 PSDR */
 104 # define SCSPTR0                SCPDR0
 105 # define SCIF_ORER              0x0001  /* overrun error bit */
 106 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 107 # define SCIF_ONLY
 108 # define PORT_PSCR              0xA405011E
 109 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
 110 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
 111 # define SCIF_ORER 0x0001   /* overrun error bit */
 112 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 113 # define SCIF_ONLY
 114 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 115 # define SCSPTR1 0xffe00020 /* 16 bit SCIF */
 116 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
 117 # define SCIF_ORER 0x0001   /* overrun error bit */
 118 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 119 # define SCIF_ONLY
 120 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 121 # include <asm/hardware.h>
 122 # define SCIF_BASE_ADDR    0x01030000
 123 # define SCIF_ADDR_SH5     PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
 124 # define SCIF_PTR2_OFFS    0x0000020
 125 # define SCIF_LSR2_OFFS    0x0000024
 126 # define SCSPTR2           ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
 127 # define SCLSR2            ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
 128 # define SCSCR_INIT(port)  0x38                           /* TIE=0,RIE=0,
 129                                                              TE=1,RE=1,REIE=1 */
 130 # define SCIF_ONLY
 131 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
 132 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 133 # define SCI_ONLY
 134 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 135 #elif defined(CONFIG_H8S2678)
 136 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 137 # define SCI_ONLY
 138 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 139 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 140 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
 141 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
 142 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
 143 # define SCIF_ORER 0x0001  /* overrun error bit */
 144 # define SCSCR_INIT(port)       0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
 145 # define SCIF_ONLY
 146 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 147 # define SCSPTR0        0xffe00024      /* 16 bit SCIF */
 148 # define SCSPTR1        0xffe10024      /* 16 bit SCIF */
 149 # define SCIF_ORER      0x0001          /* Overrun error bit */
 150 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 151 # define SCIF_ONLY
 152 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
 153 # define SCSPTR0        0xffea0024      /* 16 bit SCIF */
 154 # define SCSPTR1        0xffeb0024      /* 16 bit SCIF */
 155 # define SCSPTR2        0xffec0024      /* 16 bit SCIF */
 156 # define SCSPTR3        0xffed0024      /* 16 bit SCIF */
 157 # define SCSPTR4        0xffee0024      /* 16 bit SCIF */
 158 # define SCSPTR5        0xffef0024      /* 16 bit SCIF */
 159 # define SCIF_OPER      0x0001          /* Overrun error bit */
 160 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 161 # define SCIF_ONLY
 162 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
 163 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
 164 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
 165 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
 166 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
 167 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 168 # define SCIF_ONLY
 169 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 170 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
 171 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
 172 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
 173 # define SCIF_ORER 0x0001  /* overrun error bit */
 174 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 175 # define SCIF_ONLY
 176 #else
 177 # error CPU subtype not defined
 178 #endif
 179
 180 /* SCSCR */
 181 #define SCI_CTRL_FLAGS_TIE  0x80 /* all */
 182 #define SCI_CTRL_FLAGS_RIE  0x40 /* all */
 183 #define SCI_CTRL_FLAGS_TE   0x20 /* all */
 184 #define SCI_CTRL_FLAGS_RE   0x10 /* all */
 185 #if defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
 186     defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
 187     defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 188     defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 189     defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
 190     defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
 191     defined(CONFIG_CPU_SUBTYPE_SH7780)  || \
 192     defined(CONFIG_CPU_SUBTYPE_SH7785)
 193 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
 194 #else
 195 #define SCI_CTRL_FLAGS_REIE 0
 196 #endif
 197 /*      SCI_CTRL_FLAGS_MPIE 0x08  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 198 /*      SCI_CTRL_FLAGS_TEIE 0x04  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 199 /*      SCI_CTRL_FLAGS_CKE1 0x02  * all */
 200 /*      SCI_CTRL_FLAGS_CKE0 0x01  * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
 201
 202 /* SCxSR SCI */
 203 #define SCI_TDRE  0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 204 #define SCI_RDRF  0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 205 #define SCI_ORER  0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 206 #define SCI_FER   0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 207 #define SCI_PER   0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 208 #define SCI_TEND  0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 209 /*      SCI_MPB   0x02  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 210 /*      SCI_MPBT  0x01  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 211
 212 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
 213
 214 /* SCxSR SCIF */
 215 #define SCIF_ER    0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 216 #define SCIF_TEND  0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 217 #define SCIF_TDFE  0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 218 #define SCIF_BRK   0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 219 #define SCIF_FER   0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 220 #define SCIF_PER   0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 221 #define SCIF_RDF   0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 222 #define SCIF_DR    0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 223
 224 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
 225 #define SCIF_ORER    0x0200
 226 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
 227 #define SCIF_RFDC_MASK 0x007f
 228 #define SCIF_TXROOM_MAX 64
 229 #else
 230 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 231 #define SCIF_RFDC_MASK 0x001f
 232 #define SCIF_TXROOM_MAX 16
 233 #endif
 234
 235 #if defined(SCI_ONLY)
 236 # define SCxSR_TEND(port)               SCI_TEND
 237 # define SCxSR_ERRORS(port)             SCI_ERRORS
 238 # define SCxSR_RDxF(port)               SCI_RDRF
 239 # define SCxSR_TDxE(port)               SCI_TDRE
 240 # define SCxSR_ORER(port)               SCI_ORER
 241 # define SCxSR_FER(port)                SCI_FER
 242 # define SCxSR_PER(port)                SCI_PER
 243 # define SCxSR_BRK(port)                0x00
 244 # define SCxSR_RDxF_CLEAR(port)         0xbc
 245 # define SCxSR_ERROR_CLEAR(port)        0xc4
 246 # define SCxSR_TDxE_CLEAR(port)         0x78
 247 # define SCxSR_BREAK_CLEAR(port)        0xc4
 248 #elif defined(SCIF_ONLY)
 249 # define SCxSR_TEND(port)               SCIF_TEND
 250 # define SCxSR_ERRORS(port)             SCIF_ERRORS
 251 # define SCxSR_RDxF(port)               SCIF_RDF
 252 # define SCxSR_TDxE(port)               SCIF_TDFE
 253 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
 254 # define SCxSR_ORER(port)               SCIF_ORER
 255 #else
 256 # define SCxSR_ORER(port)               0x0000
 257 #endif
 258 # define SCxSR_FER(port)                SCIF_FER
 259 # define SCxSR_PER(port)                SCIF_PER
 260 # define SCxSR_BRK(port)                SCIF_BRK
 261 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
 262 # define SCxSR_RDxF_CLEAR(port)         (sci_in(port,SCxSR)&0xfffc)
 263 # define SCxSR_ERROR_CLEAR(port)        (sci_in(port,SCxSR)&0xfd73)
 264 # define SCxSR_TDxE_CLEAR(port)         (sci_in(port,SCxSR)&0xffdf)
 265 # define SCxSR_BREAK_CLEAR(port)        (sci_in(port,SCxSR)&0xffe3)
 266 #else
 267 /* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */
 268 # define SCxSR_RDxF_CLEAR(port)         0x00fc
 269 # define SCxSR_ERROR_CLEAR(port)        0x0073
 270 # define SCxSR_TDxE_CLEAR(port)         0x00df
 271 # define SCxSR_BREAK_CLEAR(port)        0x00e3
 272 #endif
 273 #else
 274 # define SCxSR_TEND(port)        (((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
 275 # define SCxSR_ERRORS(port)      (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
 276 # define SCxSR_RDxF(port)        (((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
 277 # define SCxSR_TDxE(port)        (((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
 278 # define SCxSR_ORER(port)        (((port)->type == PORT_SCI) ? SCI_ORER   : 0x0000)
 279 # define SCxSR_FER(port)         (((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
 280 # define SCxSR_PER(port)         (((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
 281 # define SCxSR_BRK(port)         (((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
 282 # define SCxSR_RDxF_CLEAR(port)  (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
 283 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
 284 # define SCxSR_TDxE_CLEAR(port)  (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
 285 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
 286 #endif
 287
 288 /* SCFCR */
 289 #define SCFCR_RFRST 0x0002
 290 #define SCFCR_TFRST 0x0004
 291 #define SCFCR_TCRST 0x4000
 292 #define SCFCR_MCE   0x0008
 293
 294 #define SCI_MAJOR               204
 295 #define SCI_MINOR_START         8
 296
 297 /* Generic serial flags */
 298 #define SCI_RX_THROTTLE         0x0000001
 299
 300 #define SCI_MAGIC 0xbabeface
 301
 302 /*
 303  * Events are used to schedule things to happen at timer-interrupt
 304  * time, instead of at rs interrupt time.
 305  */
 306 #define SCI_EVENT_WRITE_WAKEUP  0
 307
 308 #define SCI_IN(size, offset)                                    \
 309   unsigned int addr = port->mapbase + (offset);                 \
 310   if ((size) == 8) {                                            \
 311     return ctrl_inb(addr);                                      \
 312   } else {                                                      \
 313     return ctrl_inw(addr);                                      \
 314   }
 315 #define SCI_OUT(size, offset, value)                            \
 316   unsigned int addr = port->mapbase + (offset);                 \
 317   if ((size) == 8) {                                            \
 318     ctrl_outb(value, addr);                                     \
 319   } else {                                                      \
 320     ctrl_outw(value, addr);                                     \
 321   }
 322
 323 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
 324   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 325   {                                                                     \
 326     if (port->type == PORT_SCI) {                                       \
 327       SCI_IN(sci_size, sci_offset)                                      \
 328     } else {                                                            \
 329       SCI_IN(scif_size, scif_offset);                                   \
 330     }                                                                   \
 331   }                                                                     \
 332   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 333   {                                                                     \
 334     if (port->type == PORT_SCI) {                                       \
 335       SCI_OUT(sci_size, sci_offset, value)                              \
 336     } else {                                                            \
 337       SCI_OUT(scif_size, scif_offset, value);                           \
 338     }                                                                   \
 339   }
 340
 341 #define CPU_SCIF_FNS(name, scif_offset, scif_size)                              \
 342   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 343   {                                                                     \
 344     SCI_IN(scif_size, scif_offset);                                     \
 345   }                                                                     \
 346   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 347   {                                                                     \
 348     SCI_OUT(scif_size, scif_offset, value);                             \
 349   }
 350
 351 #define CPU_SCI_FNS(name, sci_offset, sci_size)                         \
 352   static inline unsigned int sci_##name##_in(struct uart_port* port)    \
 353   {                                                                     \
 354     SCI_IN(sci_size, sci_offset);                                       \
 355   }                                                                     \
 356   static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
 357   {                                                                     \
 358     SCI_OUT(sci_size, sci_offset, value);                               \
 359   }
 360
 361 #ifdef CONFIG_CPU_SH3
 362 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 363 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 364                                 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 365                                  h8_sci_offset, h8_sci_size) \
 366   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 367 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 368           CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 369 #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
 370     defined(CONFIG_CPU_SUBTYPE_SH7705)
 371 #define SCIF_FNS(name, scif_offset, scif_size) \
 372   CPU_SCIF_FNS(name, scif_offset, scif_size)
 373 #else
 374 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 375                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 376                  h8_sci_offset, h8_sci_size) \
 377   CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
 378 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 379   CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
 380 #endif
 381 #elif defined(__H8300H__) || defined(__H8300S__)
 382 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 383                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 384                  h8_sci_offset, h8_sci_size) \
 385   CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
 386 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
 387 #else
 388 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 389                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 390                  h8_sci_offset, h8_sci_size) \
 391   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 392 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 393   CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 394 #endif
 395
 396 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
 397     defined(CONFIG_CPU_SUBTYPE_SH7705)
 398
 399 SCIF_FNS(SCSMR,  0x00, 16)
 400 SCIF_FNS(SCBRR,  0x04,  8)
 401 SCIF_FNS(SCSCR,  0x08, 16)
 402 SCIF_FNS(SCTDSR, 0x0c,  8)
 403 SCIF_FNS(SCFER,  0x10, 16)
 404 SCIF_FNS(SCxSR,  0x14, 16)
 405 SCIF_FNS(SCFCR,  0x18, 16)
 406 SCIF_FNS(SCFDR,  0x1c, 16)
 407 SCIF_FNS(SCxTDR, 0x20,  8)
 408 SCIF_FNS(SCxRDR, 0x24,  8)
 409 SCIF_FNS(SCLSR,  0x24, 16)
 410 #else
 411 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 412 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
 413 SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16, 0x00,  8)
 414 SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8, 0x01,  8)
 415 SCIx_FNS(SCSCR,  0x04,  8, 0x08,  8, 0x04,  8, 0x08, 16, 0x02,  8)
 416 SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)
 417 SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16, 0x04,  8)
 418 SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
 419 SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
 420 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
 421     defined(CONFIG_CPU_SUBTYPE_SH7780) || \
 422     defined(CONFIG_CPU_SUBTYPE_SH7785)
 423 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 424 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 425 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 426 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 427 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 428 #else
 429 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 430 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 431 SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
 432 #endif
 433 #endif
 434 #define sci_in(port, reg) sci_##reg##_in(port)
 435 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
 436
 437 /* H8/300 series SCI pins assignment */
 438 #if defined(__H8300H__) || defined(__H8300S__)
 439 static const struct __attribute__((packed)) {
 440         int port;             /* GPIO port no */
 441         unsigned short rx,tx; /* GPIO bit no */
 442 } h8300_sci_pins[] = {
 443 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
 444         {    /* SCI0 */
 445                 .port = H8300_GPIO_P9,
 446                 .rx   = H8300_GPIO_B2,
 447                 .tx   = H8300_GPIO_B0,
 448         },
 449         {    /* SCI1 */
 450                 .port = H8300_GPIO_P9,
 451                 .rx   = H8300_GPIO_B3,
 452                 .tx   = H8300_GPIO_B1,
 453         },
 454         {    /* SCI2 */
 455                 .port = H8300_GPIO_PB,
 456                 .rx   = H8300_GPIO_B7,
 457                 .tx   = H8300_GPIO_B6,
 458         }
 459 #elif defined(CONFIG_H8S2678)
 460         {    /* SCI0 */
 461                 .port = H8300_GPIO_P3,
 462                 .rx   = H8300_GPIO_B2,
 463                 .tx   = H8300_GPIO_B0,
 464         },
 465         {    /* SCI1 */
 466                 .port = H8300_GPIO_P3,
 467                 .rx   = H8300_GPIO_B3,
 468                 .tx   = H8300_GPIO_B1,
 469         },
 470         {    /* SCI2 */
 471                 .port = H8300_GPIO_P5,
 472                 .rx   = H8300_GPIO_B1,
 473                 .tx   = H8300_GPIO_B0,
 474         }
 475 #endif
 476 };
 477 #endif
 478
 479 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
 480 static inline int sci_rxd_in(struct uart_port *port)
 481 {
 482         if (port->mapbase == 0xfffffe80)
 483                 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
 484         return 1;
 485 }
 486 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 487       defined(CONFIG_CPU_SUBTYPE_SH7709) || \
 488       defined(CONFIG_CPU_SUBTYPE_SH7706)
 489 static inline int sci_rxd_in(struct uart_port *port)
 490 {
 491         if (port->mapbase == 0xfffffe80)
 492                 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
 493         if (port->mapbase == 0xa4000150)
 494                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 495         if (port->mapbase == 0xa4000140)
 496                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 497         return 1;
 498 }
 499 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 500 static inline int sci_rxd_in(struct uart_port *port)
 501 {
 502         if (port->mapbase == SCIF0)
 503                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 504         if (port->mapbase == SCIF2)
 505                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 506         return 1;
 507 }
 508 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 509 static inline int sci_rxd_in(struct uart_port *port)
 510 {
 511           return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
 512 }
 513 static inline void set_sh771x_scif_pfc(struct uart_port *port)
 514 {
 515         if (port->mapbase == 0xA4400000){
 516                 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
 517                 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
 518                 return;
 519         }
 520         if (port->mapbase == 0xA4410000){
 521                 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
 522                 return;
 523         }
 524 }
 525
 526 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
 527       defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
 528       defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
 529       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 530       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 531       defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
 532       defined(CONFIG_CPU_SUBTYPE_SH4_202)
 533 static inline int sci_rxd_in(struct uart_port *port)
 534 {
 535 #ifndef SCIF_ONLY
 536         if (port->mapbase == 0xffe00000)
 537                 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
 538 #endif
 539 #ifndef SCI_ONLY
 540         if (port->mapbase == 0xffe80000)
 541                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 542 #endif
 543         return 1;
 544 }
 545 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 546 static inline int sci_rxd_in(struct uart_port *port)
 547 {
 548         if (port->mapbase == 0xfe600000)
 549                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 550         if (port->mapbase == 0xfe610000)
 551                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 552         if (port->mapbase == 0xfe620000)
 553                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 554         return 1;
 555 }
 556 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
 557 static inline int sci_rxd_in(struct uart_port *port)
 558 {
 559         if (port->mapbase == 0xa4430000)
 560                 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
 561         return 1;
 562 }
 563 #elif defined(CONFIG_CPU_SUBTYPE_SH73180)
 564 static inline int sci_rxd_in(struct uart_port *port)
 565 {
 566         return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
 567 }
 568 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
 569 static inline int sci_rxd_in(struct uart_port *port)
 570 {
 571         if (port->mapbase == 0xffe00000)
 572                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 573         if (port->mapbase == 0xffe10000)
 574                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 575         if (port->mapbase == 0xffe20000)
 576                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 577         if (port->mapbase == 0xffe30000)
 578                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 579         return 1;
 580 }
 581 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
 582 static inline int sci_rxd_in(struct uart_port *port)
 583 {
 584         if (port->mapbase == 0xffe00000)
 585                 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
 586         return 1;
 587 }
 588 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 589 static inline int sci_rxd_in(struct uart_port *port)
 590 {
 591         if (port->mapbase == 0xffe00000)
 592                 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
 593         else
 594                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 595
 596 }
 597 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 598 static inline int sci_rxd_in(struct uart_port *port)
 599 {
 600          return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
 601 }
 602 #elif defined(__H8300H__) || defined(__H8300S__)
 603 static inline int sci_rxd_in(struct uart_port *port)
 604 {
 605         int ch = (port->mapbase - SMR0) >> 3;
 606         return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
 607 }
 608 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 609 static inline int sci_rxd_in(struct uart_port *port)
 610 {
 611         if (port->mapbase == 0xff923000)
 612                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 613         if (port->mapbase == 0xff924000)
 614                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 615         if (port->mapbase == 0xff925000)
 616                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 617         return 1;
 618 }
 619 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 620 static inline int sci_rxd_in(struct uart_port *port)
 621 {
 622         if (port->mapbase == 0xffe00000)
 623                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 624         if (port->mapbase == 0xffe10000)
 625                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 626         return 1;
 627 }
 628 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
 629 static inline int sci_rxd_in(struct uart_port *port)
 630 {
 631         if (port->mapbase == 0xffea0000)
 632                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 633         if (port->mapbase == 0xffeb0000)
 634                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 635         if (port->mapbase == 0xffec0000)
 636                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 637         if (port->mapbase == 0xffed0000)
 638                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 639         if (port->mapbase == 0xffee0000)
 640                 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
 641         if (port->mapbase == 0xffef0000)
 642                 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
 643         return 1;
 644 }
 645 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
 646 static inline int sci_rxd_in(struct uart_port *port)
 647 {
 648         if (port->mapbase == 0xfffe8000)
 649                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 650         if (port->mapbase == 0xfffe8800)
 651                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 652         if (port->mapbase == 0xfffe9000)
 653                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 654         if (port->mapbase == 0xfffe9800)
 655                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 656         return 1;
 657 }
 658 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 659 static inline int sci_rxd_in(struct uart_port *port)
 660 {
 661         if (port->mapbase == 0xf8400000)
 662                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 663         if (port->mapbase == 0xf8410000)
 664                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 665         if (port->mapbase == 0xf8420000)
 666                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 667         return 1;
 668 }
 669 #endif
 670
 671 /*
 672  * Values for the BitRate Register (SCBRR)
 673  *
 674  * The values are actually divisors for a frequency which can
 675  * be internal to the SH3 (14.7456MHz) or derived from an external
 676  * clock source.  This driver assumes the internal clock is used;
 677  * to support using an external clock source, config options or
 678  * possibly command-line options would need to be added.
 679  *
 680  * Also, to support speeds below 2400 (why?) the lower 2 bits of
 681  * the SCSMR register would also need to be set to non-zero values.
 682  *
 683  * -- Greg Banks 27Feb2000
 684  *
 685  * Answer: The SCBRR register is only eight bits, and the value in
 686  * it gets larger with lower baud rates. At around 2400 (depending on
 687  * the peripherial module clock) you run out of bits. However the
 688  * lower two bits of SCSMR allow the module clock to be divided down,
 689  * scaling the value which is needed in SCBRR.
 690  *
 691  * -- Stuart Menefy - 23 May 2000
 692  *
 693  * I meant, why would anyone bother with bitrates below 2400.
 694  *
 695  * -- Greg Banks - 7Jul2000
 696  *
 697  * You "speedist"!  How will I use my 110bps ASR-33 teletype with paper
 698  * tape reader as a console!
 699  *
 700  * -- Mitch Davis - 15 Jul 2000
 701  */
 702
 703 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
 704     defined(CONFIG_CPU_SUBTYPE_SH7780) || \
 705     defined(CONFIG_CPU_SUBTYPE_SH7785)
 706 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
 707 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 708 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 709 #elif defined(__H8300H__) || defined(__H8300S__)
 710 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
 711 #elif defined(CONFIG_SUPERH64)
 712 #define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
 713 #else /* Generic SH */
 714 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 715 #endif