1 /* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */
3 Written 1998-2000 by Donald Becker.
5 Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please
6 send all bug reports to me, and not to Donald Becker, as this code
7 has been heavily modified from Donald's original version.
9 This software may be used and distributed according to the terms of
10 the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on or derived from this code fall under the GPL and must
12 retain the authorship, copyright and license notice. This file is not
13 a complete program and may only be used when the entire operating
14 system is licensed under the GPL.
16 The information below comes from Donald Becker's original driver:
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
23 Support and updates available at
24 http://www.scyld.com/network/starfire.html
25 [link no longer provides useful info -jgarzik]
29 #define DRV_NAME "starfire"
30 #define DRV_VERSION "2.0"
31 #define DRV_RELDATE "June 27, 2006"
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/crc32.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/if_vlan.h>
44 #include <asm/processor.h> /* Processor type for cache alignment. */
45 #include <asm/uaccess.h>
48 #include "starfire_firmware.h"
50 * The current frame processor firmware fails to checksum a fragment
51 * of length 1. If and when this is fixed, the #define below can be removed.
53 #define HAS_BROKEN_FIRMWARE
56 * If using the broken firmware, data must be padded to the next 32-bit boundary.
58 #ifdef HAS_BROKEN_FIRMWARE
59 #define PADDING_MASK 3
63 * Define this if using the driver with the zero-copy patch
67 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
71 #ifndef CONFIG_ADAPTEC_STARFIRE_NAPI
72 #undef HAVE_NETDEV_POLL
75 /* The user-configurable values.
76 These may be modified when a driver module is loaded.*/
78 /* Used for tuning interrupt latency vs. overhead. */
79 static int intr_latency
;
80 static int small_frames
;
82 static int debug
= 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
83 static int max_interrupt_work
= 20;
85 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
86 The Starfire has a 512 element hash table based on the Ethernet CRC. */
87 static const int multicast_filter_limit
= 512;
88 /* Whether to do TCP/UDP checksums in hardware */
89 static int enable_hw_cksum
= 1;
91 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
93 * Set the copy breakpoint for the copy-only-tiny-frames scheme.
94 * Setting to > 1518 effectively disables this feature.
97 * The ia64 doesn't allow for unaligned loads even of integers being
98 * misaligned on a 2 byte boundary. Thus always force copying of
99 * packets as the starfire doesn't allow for misaligned DMAs ;-(
102 * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64,
103 * at least, having unaligned frames leads to a rather serious performance
106 #if defined(__ia64__) || defined(__alpha__) || defined(__sparc__)
107 static int rx_copybreak
= PKT_BUF_SZ
;
109 static int rx_copybreak
/* = 0 */;
112 /* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */
114 #define DMA_BURST_SIZE 64
116 #define DMA_BURST_SIZE 128
119 /* Used to pass the media type, etc.
120 Both 'options[]' and 'full_duplex[]' exist for driver interoperability.
121 The media type is usually passed in 'options[]'.
122 These variables are deprecated, use ethtool instead. -Ion
124 #define MAX_UNITS 8 /* More are supported, limit only on options */
125 static int options
[MAX_UNITS
] = {0, };
126 static int full_duplex
[MAX_UNITS
] = {0, };
128 /* Operational parameters that are set at compile time. */
130 /* The "native" ring sizes are either 256 or 2048.
131 However in some modes a descriptor may be marked to wrap the ring earlier.
133 #define RX_RING_SIZE 256
134 #define TX_RING_SIZE 32
135 /* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */
136 #define DONE_Q_SIZE 1024
137 /* All queues must be aligned on a 256-byte boundary */
138 #define QUEUE_ALIGN 256
140 #if RX_RING_SIZE > 256
141 #define RX_Q_ENTRIES Rx2048QEntries
143 #define RX_Q_ENTRIES Rx256QEntries
146 /* Operational parameters that usually are not changed. */
147 /* Time in jiffies before concluding the transmitter is hung. */
148 #define TX_TIMEOUT (2 * HZ)
152 * We need a much better method to determine if dma_addr_t is 64-bit.
154 #if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__mips64__) || (defined(__mips__) && defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR))
155 /* 64-bit dma_addr_t */
156 #define ADDR_64BITS /* This chip uses 64 bit addresses. */
157 #define netdrv_addr_t u64
158 #define cpu_to_dma(x) cpu_to_le64(x)
159 #define dma_to_cpu(x) le64_to_cpu(x)
160 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
161 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit
162 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit
163 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
164 #define RX_DESC_ADDR_SIZE RxDescAddr64bit
165 #else /* 32-bit dma_addr_t */
166 #define netdrv_addr_t u32
167 #define cpu_to_dma(x) cpu_to_le32(x)
168 #define dma_to_cpu(x) le32_to_cpu(x)
169 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
170 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit
171 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit
172 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit
173 #define RX_DESC_ADDR_SIZE RxDescAddr32bit
176 #define skb_first_frag_len(skb) skb_headlen(skb)
177 #define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
179 #ifdef HAVE_NETDEV_POLL
180 #define init_poll(dev) \
182 dev->poll = &netdev_poll; \
183 dev->weight = max_interrupt_work; \
185 #define netdev_rx(dev, ioaddr) \
188 if (netif_rx_schedule_prep(dev)) { \
189 __netif_rx_schedule(dev); \
190 intr_enable = readl(ioaddr + IntrEnable); \
191 intr_enable &= ~(IntrRxDone | IntrRxEmpty); \
192 writel(intr_enable, ioaddr + IntrEnable); \
193 readl(ioaddr + IntrEnable); /* flush PCI posting buffers */ \
195 /* Paranoia check */ \
196 intr_enable = readl(ioaddr + IntrEnable); \
197 if (intr_enable & (IntrRxDone | IntrRxEmpty)) { \
198 printk(KERN_INFO "%s: interrupt while in polling mode!\n", dev->name); \
199 intr_enable &= ~(IntrRxDone | IntrRxEmpty); \
200 writel(intr_enable, ioaddr + IntrEnable); \
204 #define netdev_receive_skb(skb) netif_receive_skb(skb)
205 #define vlan_netdev_receive_skb(skb, vlgrp, vlid) vlan_hwaccel_receive_skb(skb, vlgrp, vlid)
206 static int netdev_poll(struct net_device
*dev
, int *budget
);
207 #else /* not HAVE_NETDEV_POLL */
208 #define init_poll(dev)
209 #define netdev_receive_skb(skb) netif_rx(skb)
210 #define vlan_netdev_receive_skb(skb, vlgrp, vlid) vlan_hwaccel_rx(skb, vlgrp, vlid)
211 #define netdev_rx(dev, ioaddr) \
213 int quota = np->dirty_rx + RX_RING_SIZE - np->cur_rx; \
214 __netdev_rx(dev, "a);\
216 #endif /* not HAVE_NETDEV_POLL */
217 /* end of compatibility code */
220 /* These identify the driver base version and may not be removed. */
221 static const char version
[] __devinitdata
=
222 KERN_INFO
"starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
223 KERN_INFO
" (unofficial 2.2/2.4 kernel port, version " DRV_VERSION
", " DRV_RELDATE
")\n";
225 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
226 MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
227 MODULE_LICENSE("GPL");
228 MODULE_VERSION(DRV_VERSION
);
230 module_param(max_interrupt_work
, int, 0);
231 module_param(mtu
, int, 0);
232 module_param(debug
, int, 0);
233 module_param(rx_copybreak
, int, 0);
234 module_param(intr_latency
, int, 0);
235 module_param(small_frames
, int, 0);
236 module_param_array(options
, int, NULL
, 0);
237 module_param_array(full_duplex
, int, NULL
, 0);
238 module_param(enable_hw_cksum
, int, 0);
239 MODULE_PARM_DESC(max_interrupt_work
, "Maximum events handled per interrupt");
240 MODULE_PARM_DESC(mtu
, "MTU (all boards)");
241 MODULE_PARM_DESC(debug
, "Debug level (0-6)");
242 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
243 MODULE_PARM_DESC(intr_latency
, "Maximum interrupt latency, in microseconds");
244 MODULE_PARM_DESC(small_frames
, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)");
245 MODULE_PARM_DESC(options
, "Deprecated: Bits 0-3: media type, bit 17: full duplex");
246 MODULE_PARM_DESC(full_duplex
, "Deprecated: Forced full-duplex setting (0/1)");
247 MODULE_PARM_DESC(enable_hw_cksum
, "Enable/disable hardware cksum support (0/1)");
252 I. Board Compatibility
254 This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter.
256 II. Board-specific settings
258 III. Driver operation
262 The Starfire hardware uses multiple fixed-size descriptor queues/rings. The
263 ring sizes are set fixed by the hardware, but may optionally be wrapped
264 earlier by the END bit in the descriptor.
265 This driver uses that hardware queue size for the Rx ring, where a large
266 number of entries has no ill effect beyond increases the potential backlog.
267 The Tx ring is wrapped with the END bit, since a large hardware Tx queue
268 disables the queue layer priority ordering and we have no mechanism to
269 utilize the hardware two-level priority queue. When modifying the
270 RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning
273 IIIb/c. Transmit/Receive Structure
275 See the Adaptec manual for the many possible structures, and options for
276 each structure. There are far too many to document all of them here.
278 For transmit this driver uses type 0/1 transmit descriptors (depending
279 on the 32/64 bitness of the architecture), and relies on automatic
280 minimum-length padding. It does not use the completion queue
281 consumer index, but instead checks for non-zero status entries.
283 For receive this driver uses type 2/3 receive descriptors. The driver
284 allocates full frame size skbuffs for the Rx ring buffers, so all frames
285 should fit in a single descriptor. The driver does not use the completion
286 queue consumer index, but instead checks for non-zero status entries.
288 When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff
289 is allocated and the frame is copied to the new skbuff. When the incoming
290 frame is larger, the skbuff is passed directly up the protocol stack.
291 Buffers consumed this way are replaced by newly allocated skbuffs in a later
294 A notable aspect of operation is that unaligned buffers are not permitted by
295 the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame
296 isn't longword aligned, which may cause problems on some machine
297 e.g. Alphas and IA64. For these architectures, the driver is forced to copy
298 the frame into a new skbuff unconditionally. Copied frames are put into the
299 skbuff at an offset of "+2", thus 16-byte aligning the IP header.
301 IIId. Synchronization
303 The driver runs as two independent, single-threaded flows of control. One
304 is the send-packet routine, which enforces single-threaded use by the
305 dev->tbusy flag. The other thread is the interrupt handler, which is single
306 threaded by the hardware and interrupt handling software.
308 The send packet thread has partial control over the Tx ring and the netif_queue
309 status. If the number of free Tx slots in the ring falls below a certain number
310 (currently hardcoded to 4), it signals the upper layer to stop the queue.
312 The interrupt handler has exclusive control over the Rx ring and records stats
313 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
314 empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the
315 number of free Tx slow is above the threshold, it signals the upper layer to
322 The Adaptec Starfire manuals, available only from Adaptec.
323 http://www.scyld.com/expert/100mbps.html
324 http://www.scyld.com/expert/NWay.html
328 - StopOnPerr is broken, don't enable
329 - Hardware ethernet padding exposes random data, perform software padding
330 instead (unverified -- works correctly for all the hardware I have)
336 enum chip_capability_flags
{CanHaveMII
=1, };
342 static struct pci_device_id starfire_pci_tbl
[] = {
343 { 0x9004, 0x6915, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CH_6915
},
346 MODULE_DEVICE_TABLE(pci
, starfire_pci_tbl
);
348 /* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */
349 static const struct chip_info
{
352 } netdrv_tbl
[] __devinitdata
= {
353 { "Adaptec Starfire 6915", CanHaveMII
},
357 /* Offsets to the device registers.
358 Unlike software-only systems, device drivers interact with complex hardware.
359 It's not useful to define symbolic names for every register bit in the
360 device. The name can only partially document the semantics and make
361 the driver longer and more difficult to read.
362 In general, only the important configuration values or bits changed
363 multiple times should be defined symbolically.
365 enum register_offsets
{
366 PCIDeviceConfig
=0x50040, GenCtrl
=0x50070, IntrTimerCtrl
=0x50074,
367 IntrClear
=0x50080, IntrStatus
=0x50084, IntrEnable
=0x50088,
368 MIICtrl
=0x52000, TxStationAddr
=0x50120, EEPROMCtrl
=0x51000,
369 GPIOCtrl
=0x5008C, TxDescCtrl
=0x50090,
370 TxRingPtr
=0x50098, HiPriTxRingPtr
=0x50094, /* Low and High priority. */
371 TxRingHiAddr
=0x5009C, /* 64 bit address extension. */
372 TxProducerIdx
=0x500A0, TxConsumerIdx
=0x500A4,
374 CompletionHiAddr
=0x500B4, TxCompletionAddr
=0x500B8,
375 RxCompletionAddr
=0x500BC, RxCompletionQ2Addr
=0x500C0,
376 CompletionQConsumerIdx
=0x500C4, RxDMACtrl
=0x500D0,
377 RxDescQCtrl
=0x500D4, RxDescQHiAddr
=0x500DC, RxDescQAddr
=0x500E0,
378 RxDescQIdx
=0x500E8, RxDMAStatus
=0x500F0, RxFilterMode
=0x500F4,
379 TxMode
=0x55000, VlanType
=0x55064,
380 PerfFilterTable
=0x56000, HashTable
=0x56100,
381 TxGfpMem
=0x58000, RxGfpMem
=0x5a000,
385 * Bits in the interrupt status/mask registers.
386 * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register
387 * enables all the interrupt sources that are or'ed into those status bits.
389 enum intr_status_bits
{
390 IntrLinkChange
=0xf0000000, IntrStatsMax
=0x08000000,
391 IntrAbnormalSummary
=0x02000000, IntrGeneralTimer
=0x01000000,
392 IntrSoftware
=0x800000, IntrRxComplQ1Low
=0x400000,
393 IntrTxComplQLow
=0x200000, IntrPCI
=0x100000,
394 IntrDMAErr
=0x080000, IntrTxDataLow
=0x040000,
395 IntrRxComplQ2Low
=0x020000, IntrRxDescQ1Low
=0x010000,
396 IntrNormalSummary
=0x8000, IntrTxDone
=0x4000,
397 IntrTxDMADone
=0x2000, IntrTxEmpty
=0x1000,
398 IntrEarlyRxQ2
=0x0800, IntrEarlyRxQ1
=0x0400,
399 IntrRxQ2Done
=0x0200, IntrRxQ1Done
=0x0100,
400 IntrRxGFPDead
=0x80, IntrRxDescQ2Low
=0x40,
401 IntrNoTxCsum
=0x20, IntrTxBadID
=0x10,
402 IntrHiPriTxBadID
=0x08, IntrRxGfp
=0x04,
403 IntrTxGfp
=0x02, IntrPCIPad
=0x01,
405 IntrRxDone
=IntrRxQ2Done
| IntrRxQ1Done
,
406 IntrRxEmpty
=IntrRxDescQ1Low
| IntrRxDescQ2Low
,
407 IntrNormalMask
=0xff00, IntrAbnormalMask
=0x3ff00fe,
410 /* Bits in the RxFilterMode register. */
412 AcceptBroadcast
=0x04, AcceptAllMulticast
=0x02, AcceptAll
=0x01,
413 AcceptMulticast
=0x10, PerfectFilter
=0x40, HashFilter
=0x30,
414 PerfectFilterVlan
=0x80, MinVLANPrio
=0xE000, VlanMode
=0x0200,
418 /* Bits in the TxMode register */
420 MiiSoftReset
=0x8000, MIILoopback
=0x4000,
421 TxFlowEnable
=0x0800, RxFlowEnable
=0x0400,
422 PadEnable
=0x04, FullDuplex
=0x02, HugeFrame
=0x01,
425 /* Bits in the TxDescCtrl register. */
427 TxDescSpaceUnlim
=0x00, TxDescSpace32
=0x10, TxDescSpace64
=0x20,
428 TxDescSpace128
=0x30, TxDescSpace256
=0x40,
429 TxDescType0
=0x00, TxDescType1
=0x01, TxDescType2
=0x02,
430 TxDescType3
=0x03, TxDescType4
=0x04,
431 TxNoDMACompletion
=0x08,
432 TxDescQAddr64bit
=0x80, TxDescQAddr32bit
=0,
433 TxHiPriFIFOThreshShift
=24, TxPadLenShift
=16,
434 TxDMABurstSizeShift
=8,
437 /* Bits in the RxDescQCtrl register. */
439 RxBufferLenShift
=16, RxMinDescrThreshShift
=0,
440 RxPrefetchMode
=0x8000, RxVariableQ
=0x2000,
441 Rx2048QEntries
=0x4000, Rx256QEntries
=0,
442 RxDescAddr64bit
=0x1000, RxDescAddr32bit
=0,
443 RxDescQAddr64bit
=0x0100, RxDescQAddr32bit
=0,
444 RxDescSpace4
=0x000, RxDescSpace8
=0x100,
445 RxDescSpace16
=0x200, RxDescSpace32
=0x300,
446 RxDescSpace64
=0x400, RxDescSpace128
=0x500,
450 /* Bits in the RxDMACtrl register. */
451 enum rx_dmactrl_bits
{
452 RxReportBadFrames
=0x80000000, RxDMAShortFrames
=0x40000000,
453 RxDMABadFrames
=0x20000000, RxDMACrcErrorFrames
=0x10000000,
454 RxDMAControlFrame
=0x08000000, RxDMAPauseFrame
=0x04000000,
455 RxChecksumIgnore
=0, RxChecksumRejectTCPUDP
=0x02000000,
456 RxChecksumRejectTCPOnly
=0x01000000,
457 RxCompletionQ2Enable
=0x800000,
458 RxDMAQ2Disable
=0, RxDMAQ2FPOnly
=0x100000,
459 RxDMAQ2SmallPkt
=0x200000, RxDMAQ2HighPrio
=0x300000,
460 RxDMAQ2NonIP
=0x400000,
461 RxUseBackupQueue
=0x080000, RxDMACRC
=0x040000,
462 RxEarlyIntThreshShift
=12, RxHighPrioThreshShift
=8,
466 /* Bits in the RxCompletionAddr register */
468 RxComplQAddr64bit
=0x80, RxComplQAddr32bit
=0,
469 RxComplProducerWrEn
=0x40,
470 RxComplType0
=0x00, RxComplType1
=0x10,
471 RxComplType2
=0x20, RxComplType3
=0x30,
472 RxComplThreshShift
=0,
475 /* Bits in the TxCompletionAddr register */
477 TxComplQAddr64bit
=0x80, TxComplQAddr32bit
=0,
478 TxComplProducerWrEn
=0x40,
479 TxComplIntrStatus
=0x20,
480 CommonQueueMode
=0x10,
481 TxComplThreshShift
=0,
484 /* Bits in the GenCtrl register */
486 RxEnable
=0x05, TxEnable
=0x0a,
487 RxGFPEnable
=0x10, TxGFPEnable
=0x20,
490 /* Bits in the IntrTimerCtrl register */
491 enum intr_ctrl_bits
{
492 Timer10X
=0x800, EnableIntrMasking
=0x60, SmallFrameBypass
=0x100,
493 SmallFrame64
=0, SmallFrame128
=0x200, SmallFrame256
=0x400, SmallFrame512
=0x600,
494 IntrLatencyMask
=0x1f,
497 /* The Rx and Tx buffer descriptors. */
498 struct starfire_rx_desc
{
502 RxDescValid
=1, RxDescEndRing
=2,
505 /* Completion queue entry. */
506 struct short_rx_done_desc
{
507 u32 status
; /* Low 16 bits is length. */
509 struct basic_rx_done_desc
{
510 u32 status
; /* Low 16 bits is length. */
514 struct csum_rx_done_desc
{
515 u32 status
; /* Low 16 bits is length. */
516 u16 csum
; /* Partial checksum */
519 struct full_rx_done_desc
{
520 u32 status
; /* Low 16 bits is length. */
524 u16 csum
; /* partial checksum */
527 /* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
529 typedef struct full_rx_done_desc rx_done_desc
;
530 #define RxComplType RxComplType3
531 #else /* not VLAN_SUPPORT */
532 typedef struct csum_rx_done_desc rx_done_desc
;
533 #define RxComplType RxComplType2
534 #endif /* not VLAN_SUPPORT */
537 RxOK
=0x20000000, RxFIFOErr
=0x10000000, RxBufQ2
=0x08000000,
540 /* Type 1 Tx descriptor. */
541 struct starfire_tx_desc_1
{
542 u32 status
; /* Upper bits are status, lower 16 length. */
546 /* Type 2 Tx descriptor. */
547 struct starfire_tx_desc_2
{
548 u32 status
; /* Upper bits are status, lower 16 length. */
554 typedef struct starfire_tx_desc_2 starfire_tx_desc
;
555 #define TX_DESC_TYPE TxDescType2
556 #else /* not ADDR_64BITS */
557 typedef struct starfire_tx_desc_1 starfire_tx_desc
;
558 #define TX_DESC_TYPE TxDescType1
559 #endif /* not ADDR_64BITS */
560 #define TX_DESC_SPACING TxDescSpaceUnlim
564 TxCRCEn
=0x01000000, TxDescIntr
=0x08000000,
565 TxRingWrap
=0x04000000, TxCalTCP
=0x02000000,
567 struct tx_done_desc
{
568 u32 status
; /* timestamp, index. */
570 u32 intrstatus
; /* interrupt status */
574 struct rx_ring_info
{
578 struct tx_ring_info
{
581 unsigned int used_slots
;
585 struct netdev_private
{
586 /* Descriptor rings first for alignment. */
587 struct starfire_rx_desc
*rx_ring
;
588 starfire_tx_desc
*tx_ring
;
589 dma_addr_t rx_ring_dma
;
590 dma_addr_t tx_ring_dma
;
591 /* The addresses of rx/tx-in-place skbuffs. */
592 struct rx_ring_info rx_info
[RX_RING_SIZE
];
593 struct tx_ring_info tx_info
[TX_RING_SIZE
];
594 /* Pointers to completion queues (full pages). */
595 rx_done_desc
*rx_done_q
;
596 dma_addr_t rx_done_q_dma
;
597 unsigned int rx_done
;
598 struct tx_done_desc
*tx_done_q
;
599 dma_addr_t tx_done_q_dma
;
600 unsigned int tx_done
;
601 struct net_device_stats stats
;
602 struct pci_dev
*pci_dev
;
604 struct vlan_group
*vlgrp
;
607 dma_addr_t queue_mem_dma
;
608 size_t queue_mem_size
;
610 /* Frequently used values: keep some adjacent for cache effect. */
612 unsigned int cur_rx
, dirty_rx
; /* Producer/consumer ring indices */
613 unsigned int cur_tx
, dirty_tx
, reap_tx
;
614 unsigned int rx_buf_sz
; /* Based on MTU+slack. */
615 /* These values keep track of the transceiver/media in use. */
616 int speed100
; /* Set if speed == 100MBit. */
620 /* MII transceiver section. */
621 struct mii_if_info mii_if
; /* MII lib hooks/info */
622 int phy_cnt
; /* MII device addresses. */
623 unsigned char phys
[PHY_CNT
]; /* MII device addresses. */
628 static int mdio_read(struct net_device
*dev
, int phy_id
, int location
);
629 static void mdio_write(struct net_device
*dev
, int phy_id
, int location
, int value
);
630 static int netdev_open(struct net_device
*dev
);
631 static void check_duplex(struct net_device
*dev
);
632 static void tx_timeout(struct net_device
*dev
);
633 static void init_ring(struct net_device
*dev
);
634 static int start_tx(struct sk_buff
*skb
, struct net_device
*dev
);
635 static irqreturn_t
intr_handler(int irq
, void *dev_instance
, struct pt_regs
*regs
);
636 static void netdev_error(struct net_device
*dev
, int intr_status
);
637 static int __netdev_rx(struct net_device
*dev
, int *quota
);
638 static void refill_rx_ring(struct net_device
*dev
);
639 static void netdev_error(struct net_device
*dev
, int intr_status
);
640 static void set_rx_mode(struct net_device
*dev
);
641 static struct net_device_stats
*get_stats(struct net_device
*dev
);
642 static int netdev_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
643 static int netdev_close(struct net_device
*dev
);
644 static void netdev_media_change(struct net_device
*dev
);
645 static struct ethtool_ops ethtool_ops
;
649 static void netdev_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
651 struct netdev_private
*np
= netdev_priv(dev
);
653 spin_lock(&np
->lock
);
655 printk("%s: Setting vlgrp to %p\n", dev
->name
, grp
);
658 spin_unlock(&np
->lock
);
661 static void netdev_vlan_rx_add_vid(struct net_device
*dev
, unsigned short vid
)
663 struct netdev_private
*np
= netdev_priv(dev
);
665 spin_lock(&np
->lock
);
667 printk("%s: Adding vlanid %d to vlan filter\n", dev
->name
, vid
);
669 spin_unlock(&np
->lock
);
672 static void netdev_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
674 struct netdev_private
*np
= netdev_priv(dev
);
676 spin_lock(&np
->lock
);
678 printk("%s: removing vlanid %d from vlan filter\n", dev
->name
, vid
);
680 np
->vlgrp
->vlan_devices
[vid
] = NULL
;
682 spin_unlock(&np
->lock
);
684 #endif /* VLAN_SUPPORT */
687 static int __devinit
starfire_init_one(struct pci_dev
*pdev
,
688 const struct pci_device_id
*ent
)
690 struct netdev_private
*np
;
691 int i
, irq
, option
, chip_idx
= ent
->driver_data
;
692 struct net_device
*dev
;
693 static int card_idx
= -1;
696 int drv_flags
, io_size
;
699 /* when built into the kernel, we only print version if device is found */
701 static int printed_version
;
702 if (!printed_version
++)
708 if (pci_enable_device (pdev
))
711 ioaddr
= pci_resource_start(pdev
, 0);
712 io_size
= pci_resource_len(pdev
, 0);
713 if (!ioaddr
|| ((pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
) == 0)) {
714 printk(KERN_ERR DRV_NAME
" %d: no PCI MEM resources, aborting\n", card_idx
);
718 dev
= alloc_etherdev(sizeof(*np
));
720 printk(KERN_ERR DRV_NAME
" %d: cannot alloc etherdev, aborting\n", card_idx
);
723 SET_MODULE_OWNER(dev
);
724 SET_NETDEV_DEV(dev
, &pdev
->dev
);
728 if (pci_request_regions (pdev
, DRV_NAME
)) {
729 printk(KERN_ERR DRV_NAME
" %d: cannot reserve PCI resources, aborting\n", card_idx
);
730 goto err_out_free_netdev
;
733 /* ioremap is borken in Linux-2.2.x/sparc64 */
734 base
= ioremap(ioaddr
, io_size
);
736 printk(KERN_ERR DRV_NAME
" %d: cannot remap %#x @ %#lx, aborting\n",
737 card_idx
, io_size
, ioaddr
);
738 goto err_out_free_res
;
741 pci_set_master(pdev
);
743 /* enable MWI -- it vastly improves Rx performance on sparc64 */
747 /* Starfire can do TCP/UDP checksumming */
749 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
750 #endif /* ZEROCOPY */
752 dev
->features
|= NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_FILTER
;
753 dev
->vlan_rx_register
= netdev_vlan_rx_register
;
754 dev
->vlan_rx_add_vid
= netdev_vlan_rx_add_vid
;
755 dev
->vlan_rx_kill_vid
= netdev_vlan_rx_kill_vid
;
756 #endif /* VLAN_RX_KILL_VID */
758 dev
->features
|= NETIF_F_HIGHDMA
;
759 #endif /* ADDR_64BITS */
761 /* Serial EEPROM reads are hidden by the hardware. */
762 for (i
= 0; i
< 6; i
++)
763 dev
->dev_addr
[i
] = readb(base
+ EEPROMCtrl
+ 20 - i
);
765 #if ! defined(final_version) /* Dump the EEPROM contents during development. */
767 for (i
= 0; i
< 0x20; i
++)
769 (unsigned int)readb(base
+ EEPROMCtrl
+ i
),
770 i
% 16 != 15 ? " " : "\n");
773 /* Issue soft reset */
774 writel(MiiSoftReset
, base
+ TxMode
);
776 writel(0, base
+ TxMode
);
778 /* Reset the chip to erase previous misconfiguration. */
779 writel(1, base
+ PCIDeviceConfig
);
781 while (--boguscnt
> 0) {
783 if ((readl(base
+ PCIDeviceConfig
) & 1) == 0)
787 printk("%s: chipset reset never completed!\n", dev
->name
);
788 /* wait a little longer */
791 dev
->base_addr
= (unsigned long)base
;
794 np
= netdev_priv(dev
);
796 spin_lock_init(&np
->lock
);
797 pci_set_drvdata(pdev
, dev
);
801 np
->mii_if
.dev
= dev
;
802 np
->mii_if
.mdio_read
= mdio_read
;
803 np
->mii_if
.mdio_write
= mdio_write
;
804 np
->mii_if
.phy_id_mask
= 0x1f;
805 np
->mii_if
.reg_num_mask
= 0x1f;
807 drv_flags
= netdrv_tbl
[chip_idx
].drv_flags
;
809 option
= card_idx
< MAX_UNITS
? options
[card_idx
] : 0;
811 option
= dev
->mem_start
;
813 /* The lower four bits are the media type. */
815 np
->mii_if
.full_duplex
= 1;
817 if (card_idx
< MAX_UNITS
&& full_duplex
[card_idx
] > 0)
818 np
->mii_if
.full_duplex
= 1;
820 if (np
->mii_if
.full_duplex
)
821 np
->mii_if
.force_media
= 1;
823 np
->mii_if
.force_media
= 0;
826 /* timer resolution is 128 * 0.8us */
827 np
->intr_timer_ctrl
= (((intr_latency
* 10) / 1024) & IntrLatencyMask
) |
828 Timer10X
| EnableIntrMasking
;
830 if (small_frames
> 0) {
831 np
->intr_timer_ctrl
|= SmallFrameBypass
;
832 switch (small_frames
) {
834 np
->intr_timer_ctrl
|= SmallFrame64
;
837 np
->intr_timer_ctrl
|= SmallFrame128
;
840 np
->intr_timer_ctrl
|= SmallFrame256
;
843 np
->intr_timer_ctrl
|= SmallFrame512
;
844 if (small_frames
> 512)
845 printk("Adjusting small_frames down to 512\n");
850 /* The chip-specific entries in the device structure. */
851 dev
->open
= &netdev_open
;
852 dev
->hard_start_xmit
= &start_tx
;
853 dev
->tx_timeout
= tx_timeout
;
854 dev
->watchdog_timeo
= TX_TIMEOUT
;
856 dev
->stop
= &netdev_close
;
857 dev
->get_stats
= &get_stats
;
858 dev
->set_multicast_list
= &set_rx_mode
;
859 dev
->do_ioctl
= &netdev_ioctl
;
860 SET_ETHTOOL_OPS(dev
, ðtool_ops
);
865 if (register_netdev(dev
))
866 goto err_out_cleardev
;
868 printk(KERN_INFO
"%s: %s at %p, ",
869 dev
->name
, netdrv_tbl
[chip_idx
].name
, base
);
870 for (i
= 0; i
< 5; i
++)
871 printk("%2.2x:", dev
->dev_addr
[i
]);
872 printk("%2.2x, IRQ %d.\n", dev
->dev_addr
[i
], irq
);
874 if (drv_flags
& CanHaveMII
) {
875 int phy
, phy_idx
= 0;
877 for (phy
= 0; phy
< 32 && phy_idx
< PHY_CNT
; phy
++) {
878 mdio_write(dev
, phy
, MII_BMCR
, BMCR_RESET
);
881 while (--boguscnt
> 0)
882 if ((mdio_read(dev
, phy
, MII_BMCR
) & BMCR_RESET
) == 0)
885 printk("%s: PHY#%d reset never completed!\n", dev
->name
, phy
);
888 mii_status
= mdio_read(dev
, phy
, MII_BMSR
);
889 if (mii_status
!= 0) {
890 np
->phys
[phy_idx
++] = phy
;
891 np
->mii_if
.advertising
= mdio_read(dev
, phy
, MII_ADVERTISE
);
892 printk(KERN_INFO
"%s: MII PHY found at address %d, status "
893 "%#4.4x advertising %#4.4x.\n",
894 dev
->name
, phy
, mii_status
, np
->mii_if
.advertising
);
895 /* there can be only one PHY on-board */
899 np
->phy_cnt
= phy_idx
;
901 np
->mii_if
.phy_id
= np
->phys
[0];
903 memset(&np
->mii_if
, 0, sizeof(np
->mii_if
));
906 printk(KERN_INFO
"%s: scatter-gather and hardware TCP cksumming %s.\n",
907 dev
->name
, enable_hw_cksum
? "enabled" : "disabled");
911 pci_set_drvdata(pdev
, NULL
);
914 pci_release_regions (pdev
);
921 /* Read the MII Management Data I/O (MDIO) interfaces. */
922 static int mdio_read(struct net_device
*dev
, int phy_id
, int location
)
924 struct netdev_private
*np
= netdev_priv(dev
);
925 void __iomem
*mdio_addr
= np
->base
+ MIICtrl
+ (phy_id
<<7) + (location
<<2);
926 int result
, boguscnt
=1000;
927 /* ??? Should we add a busy-wait here? */
929 result
= readl(mdio_addr
);
930 while ((result
& 0xC0000000) != 0x80000000 && --boguscnt
> 0);
933 if ((result
& 0xffff) == 0xffff)
935 return result
& 0xffff;
939 static void mdio_write(struct net_device
*dev
, int phy_id
, int location
, int value
)
941 struct netdev_private
*np
= netdev_priv(dev
);
942 void __iomem
*mdio_addr
= np
->base
+ MIICtrl
+ (phy_id
<<7) + (location
<<2);
943 writel(value
, mdio_addr
);
944 /* The busy-wait will occur before a read. */
948 static int netdev_open(struct net_device
*dev
)
950 struct netdev_private
*np
= netdev_priv(dev
);
951 void __iomem
*ioaddr
= np
->base
;
953 size_t tx_done_q_size
, rx_done_q_size
, tx_ring_size
, rx_ring_size
;
955 /* Do we ever need to reset the chip??? */
957 retval
= request_irq(dev
->irq
, &intr_handler
, IRQF_SHARED
, dev
->name
, dev
);
961 /* Disable the Rx and Tx, and reset the chip. */
962 writel(0, ioaddr
+ GenCtrl
);
963 writel(1, ioaddr
+ PCIDeviceConfig
);
965 printk(KERN_DEBUG
"%s: netdev_open() irq %d.\n",
966 dev
->name
, dev
->irq
);
968 /* Allocate the various queues. */
969 if (np
->queue_mem
== 0) {
970 tx_done_q_size
= ((sizeof(struct tx_done_desc
) * DONE_Q_SIZE
+ QUEUE_ALIGN
- 1) / QUEUE_ALIGN
) * QUEUE_ALIGN
;
971 rx_done_q_size
= ((sizeof(rx_done_desc
) * DONE_Q_SIZE
+ QUEUE_ALIGN
- 1) / QUEUE_ALIGN
) * QUEUE_ALIGN
;
972 tx_ring_size
= ((sizeof(starfire_tx_desc
) * TX_RING_SIZE
+ QUEUE_ALIGN
- 1) / QUEUE_ALIGN
) * QUEUE_ALIGN
;
973 rx_ring_size
= sizeof(struct starfire_rx_desc
) * RX_RING_SIZE
;
974 np
->queue_mem_size
= tx_done_q_size
+ rx_done_q_size
+ tx_ring_size
+ rx_ring_size
;
975 np
->queue_mem
= pci_alloc_consistent(np
->pci_dev
, np
->queue_mem_size
, &np
->queue_mem_dma
);
976 if (np
->queue_mem
== NULL
) {
977 free_irq(dev
->irq
, dev
);
981 np
->tx_done_q
= np
->queue_mem
;
982 np
->tx_done_q_dma
= np
->queue_mem_dma
;
983 np
->rx_done_q
= (void *) np
->tx_done_q
+ tx_done_q_size
;
984 np
->rx_done_q_dma
= np
->tx_done_q_dma
+ tx_done_q_size
;
985 np
->tx_ring
= (void *) np
->rx_done_q
+ rx_done_q_size
;
986 np
->tx_ring_dma
= np
->rx_done_q_dma
+ rx_done_q_size
;
987 np
->rx_ring
= (void *) np
->tx_ring
+ tx_ring_size
;
988 np
->rx_ring_dma
= np
->tx_ring_dma
+ tx_ring_size
;
991 /* Start with no carrier, it gets adjusted later */
992 netif_carrier_off(dev
);
994 /* Set the size of the Rx buffers. */
995 writel((np
->rx_buf_sz
<< RxBufferLenShift
) |
996 (0 << RxMinDescrThreshShift
) |
997 RxPrefetchMode
| RxVariableQ
|
999 RX_DESC_Q_ADDR_SIZE
| RX_DESC_ADDR_SIZE
|
1001 ioaddr
+ RxDescQCtrl
);
1003 /* Set up the Rx DMA controller. */
1004 writel(RxChecksumIgnore
|
1005 (0 << RxEarlyIntThreshShift
) |
1006 (6 << RxHighPrioThreshShift
) |
1007 ((DMA_BURST_SIZE
/ 32) << RxBurstSizeShift
),
1008 ioaddr
+ RxDMACtrl
);
1010 /* Set Tx descriptor */
1011 writel((2 << TxHiPriFIFOThreshShift
) |
1012 (0 << TxPadLenShift
) |
1013 ((DMA_BURST_SIZE
/ 32) << TxDMABurstSizeShift
) |
1014 TX_DESC_Q_ADDR_SIZE
|
1015 TX_DESC_SPACING
| TX_DESC_TYPE
,
1016 ioaddr
+ TxDescCtrl
);
1018 writel( (np
->queue_mem_dma
>> 16) >> 16, ioaddr
+ RxDescQHiAddr
);
1019 writel( (np
->queue_mem_dma
>> 16) >> 16, ioaddr
+ TxRingHiAddr
);
1020 writel( (np
->queue_mem_dma
>> 16) >> 16, ioaddr
+ CompletionHiAddr
);
1021 writel(np
->rx_ring_dma
, ioaddr
+ RxDescQAddr
);
1022 writel(np
->tx_ring_dma
, ioaddr
+ TxRingPtr
);
1024 writel(np
->tx_done_q_dma
, ioaddr
+ TxCompletionAddr
);
1025 writel(np
->rx_done_q_dma
|
1027 (0 << RxComplThreshShift
),
1028 ioaddr
+ RxCompletionAddr
);
1031 printk(KERN_DEBUG
"%s: Filling in the station address.\n", dev
->name
);
1033 /* Fill both the Tx SA register and the Rx perfect filter. */
1034 for (i
= 0; i
< 6; i
++)
1035 writeb(dev
->dev_addr
[i
], ioaddr
+ TxStationAddr
+ 5 - i
);
1036 /* The first entry is special because it bypasses the VLAN filter.
1038 writew(0, ioaddr
+ PerfFilterTable
);
1039 writew(0, ioaddr
+ PerfFilterTable
+ 4);
1040 writew(0, ioaddr
+ PerfFilterTable
+ 8);
1041 for (i
= 1; i
< 16; i
++) {
1042 u16
*eaddrs
= (u16
*)dev
->dev_addr
;
1043 void __iomem
*setup_frm
= ioaddr
+ PerfFilterTable
+ i
* 16;
1044 writew(cpu_to_be16(eaddrs
[2]), setup_frm
); setup_frm
+= 4;
1045 writew(cpu_to_be16(eaddrs
[1]), setup_frm
); setup_frm
+= 4;
1046 writew(cpu_to_be16(eaddrs
[0]), setup_frm
); setup_frm
+= 8;
1049 /* Initialize other registers. */
1050 /* Configure the PCI bus bursts and FIFO thresholds. */
1051 np
->tx_mode
= TxFlowEnable
|RxFlowEnable
|PadEnable
; /* modified when link is up. */
1052 writel(MiiSoftReset
| np
->tx_mode
, ioaddr
+ TxMode
);
1054 writel(np
->tx_mode
, ioaddr
+ TxMode
);
1055 np
->tx_threshold
= 4;
1056 writel(np
->tx_threshold
, ioaddr
+ TxThreshold
);
1058 writel(np
->intr_timer_ctrl
, ioaddr
+ IntrTimerCtrl
);
1060 netif_start_queue(dev
);
1063 printk(KERN_DEBUG
"%s: Setting the Rx and Tx modes.\n", dev
->name
);
1066 np
->mii_if
.advertising
= mdio_read(dev
, np
->phys
[0], MII_ADVERTISE
);
1069 /* Enable GPIO interrupts on link change */
1070 writel(0x0f00ff00, ioaddr
+ GPIOCtrl
);
1072 /* Set the interrupt mask */
1073 writel(IntrRxDone
| IntrRxEmpty
| IntrDMAErr
|
1074 IntrTxDMADone
| IntrStatsMax
| IntrLinkChange
|
1075 IntrRxGFPDead
| IntrNoTxCsum
| IntrTxBadID
,
1076 ioaddr
+ IntrEnable
);
1077 /* Enable PCI interrupts. */
1078 writel(0x00800000 | readl(ioaddr
+ PCIDeviceConfig
),
1079 ioaddr
+ PCIDeviceConfig
);
1082 /* Set VLAN type to 802.1q */
1083 writel(ETH_P_8021Q
, ioaddr
+ VlanType
);
1084 #endif /* VLAN_SUPPORT */
1086 /* Load Rx/Tx firmware into the frame processors */
1087 for (i
= 0; i
< FIRMWARE_RX_SIZE
* 2; i
++)
1088 writel(firmware_rx
[i
], ioaddr
+ RxGfpMem
+ i
* 4);
1089 for (i
= 0; i
< FIRMWARE_TX_SIZE
* 2; i
++)
1090 writel(firmware_tx
[i
], ioaddr
+ TxGfpMem
+ i
* 4);
1091 if (enable_hw_cksum
)
1092 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */
1093 writel(TxEnable
|TxGFPEnable
|RxEnable
|RxGFPEnable
, ioaddr
+ GenCtrl
);
1095 /* Enable the Rx and Tx units only. */
1096 writel(TxEnable
|RxEnable
, ioaddr
+ GenCtrl
);
1099 printk(KERN_DEBUG
"%s: Done netdev_open().\n",
1106 static void check_duplex(struct net_device
*dev
)
1108 struct netdev_private
*np
= netdev_priv(dev
);
1110 int silly_count
= 1000;
1112 mdio_write(dev
, np
->phys
[0], MII_ADVERTISE
, np
->mii_if
.advertising
);
1113 mdio_write(dev
, np
->phys
[0], MII_BMCR
, BMCR_RESET
);
1115 while (--silly_count
&& mdio_read(dev
, np
->phys
[0], MII_BMCR
) & BMCR_RESET
)
1118 printk("%s: MII reset failed!\n", dev
->name
);
1122 reg0
= mdio_read(dev
, np
->phys
[0], MII_BMCR
);
1124 if (!np
->mii_if
.force_media
) {
1125 reg0
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
1127 reg0
&= ~(BMCR_ANENABLE
| BMCR_ANRESTART
);
1129 reg0
|= BMCR_SPEED100
;
1130 if (np
->mii_if
.full_duplex
)
1131 reg0
|= BMCR_FULLDPLX
;
1132 printk(KERN_DEBUG
"%s: Link forced to %sMbit %s-duplex\n",
1134 np
->speed100
? "100" : "10",
1135 np
->mii_if
.full_duplex
? "full" : "half");
1137 mdio_write(dev
, np
->phys
[0], MII_BMCR
, reg0
);
1141 static void tx_timeout(struct net_device
*dev
)
1143 struct netdev_private
*np
= netdev_priv(dev
);
1144 void __iomem
*ioaddr
= np
->base
;
1147 printk(KERN_WARNING
"%s: Transmit timed out, status %#8.8x, "
1148 "resetting...\n", dev
->name
, (int) readl(ioaddr
+ IntrStatus
));
1150 /* Perhaps we should reinitialize the hardware here. */
1153 * Stop and restart the interface.
1154 * Cheat and increase the debug level temporarily.
1162 /* Trigger an immediate transmit demand. */
1164 dev
->trans_start
= jiffies
;
1165 np
->stats
.tx_errors
++;
1166 netif_wake_queue(dev
);
1170 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1171 static void init_ring(struct net_device
*dev
)
1173 struct netdev_private
*np
= netdev_priv(dev
);
1176 np
->cur_rx
= np
->cur_tx
= np
->reap_tx
= 0;
1177 np
->dirty_rx
= np
->dirty_tx
= np
->rx_done
= np
->tx_done
= 0;
1179 np
->rx_buf_sz
= (dev
->mtu
<= 1500 ? PKT_BUF_SZ
: dev
->mtu
+ 32);
1181 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1182 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1183 struct sk_buff
*skb
= dev_alloc_skb(np
->rx_buf_sz
);
1184 np
->rx_info
[i
].skb
= skb
;
1187 np
->rx_info
[i
].mapping
= pci_map_single(np
->pci_dev
, skb
->data
, np
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1188 skb
->dev
= dev
; /* Mark as being used by this device. */
1189 /* Grrr, we cannot offset to correctly align the IP header. */
1190 np
->rx_ring
[i
].rxaddr
= cpu_to_dma(np
->rx_info
[i
].mapping
| RxDescValid
);
1192 writew(i
- 1, np
->base
+ RxDescQIdx
);
1193 np
->dirty_rx
= (unsigned int)(i
- RX_RING_SIZE
);
1195 /* Clear the remainder of the Rx buffer ring. */
1196 for ( ; i
< RX_RING_SIZE
; i
++) {
1197 np
->rx_ring
[i
].rxaddr
= 0;
1198 np
->rx_info
[i
].skb
= NULL
;
1199 np
->rx_info
[i
].mapping
= 0;
1201 /* Mark the last entry as wrapping the ring. */
1202 np
->rx_ring
[RX_RING_SIZE
- 1].rxaddr
|= cpu_to_dma(RxDescEndRing
);
1204 /* Clear the completion rings. */
1205 for (i
= 0; i
< DONE_Q_SIZE
; i
++) {
1206 np
->rx_done_q
[i
].status
= 0;
1207 np
->tx_done_q
[i
].status
= 0;
1210 for (i
= 0; i
< TX_RING_SIZE
; i
++)
1211 memset(&np
->tx_info
[i
], 0, sizeof(np
->tx_info
[i
]));
1217 static int start_tx(struct sk_buff
*skb
, struct net_device
*dev
)
1219 struct netdev_private
*np
= netdev_priv(dev
);
1225 * be cautious here, wrapping the queue has weird semantics
1226 * and we may not have enough slots even when it seems we do.
1228 if ((np
->cur_tx
- np
->dirty_tx
) + skb_num_frags(skb
) * 2 > TX_RING_SIZE
) {
1229 netif_stop_queue(dev
);
1233 #if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE)
1234 if (skb
->ip_summed
== CHECKSUM_HW
) {
1235 if (skb_padto(skb
, (skb
->len
+ PADDING_MASK
) & ~PADDING_MASK
))
1236 return NETDEV_TX_OK
;
1238 #endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */
1240 entry
= np
->cur_tx
% TX_RING_SIZE
;
1241 for (i
= 0; i
< skb_num_frags(skb
); i
++) {
1246 np
->tx_info
[entry
].skb
= skb
;
1248 if (entry
>= TX_RING_SIZE
- skb_num_frags(skb
)) {
1249 status
|= TxRingWrap
;
1253 status
|= TxDescIntr
;
1256 if (skb
->ip_summed
== CHECKSUM_HW
) {
1258 np
->stats
.tx_compressed
++;
1260 status
|= skb_first_frag_len(skb
) | (skb_num_frags(skb
) << 16);
1262 np
->tx_info
[entry
].mapping
=
1263 pci_map_single(np
->pci_dev
, skb
->data
, skb_first_frag_len(skb
), PCI_DMA_TODEVICE
);
1265 skb_frag_t
*this_frag
= &skb_shinfo(skb
)->frags
[i
- 1];
1266 status
|= this_frag
->size
;
1267 np
->tx_info
[entry
].mapping
=
1268 pci_map_single(np
->pci_dev
, page_address(this_frag
->page
) + this_frag
->page_offset
, this_frag
->size
, PCI_DMA_TODEVICE
);
1271 np
->tx_ring
[entry
].addr
= cpu_to_dma(np
->tx_info
[entry
].mapping
);
1272 np
->tx_ring
[entry
].status
= cpu_to_le32(status
);
1274 printk(KERN_DEBUG
"%s: Tx #%d/#%d slot %d status %#8.8x.\n",
1275 dev
->name
, np
->cur_tx
, np
->dirty_tx
,
1278 np
->tx_info
[entry
].used_slots
= TX_RING_SIZE
- entry
;
1279 np
->cur_tx
+= np
->tx_info
[entry
].used_slots
;
1282 np
->tx_info
[entry
].used_slots
= 1;
1283 np
->cur_tx
+= np
->tx_info
[entry
].used_slots
;
1286 /* scavenge the tx descriptors twice per TX_RING_SIZE */
1287 if (np
->cur_tx
% (TX_RING_SIZE
/ 2) == 0)
1291 /* Non-x86: explicitly flush descriptor cache lines here. */
1292 /* Ensure all descriptors are written back before the transmit is
1296 /* Update the producer index. */
1297 writel(entry
* (sizeof(starfire_tx_desc
) / 8), np
->base
+ TxProducerIdx
);
1299 /* 4 is arbitrary, but should be ok */
1300 if ((np
->cur_tx
- np
->dirty_tx
) + 4 > TX_RING_SIZE
)
1301 netif_stop_queue(dev
);
1303 dev
->trans_start
= jiffies
;
1309 /* The interrupt handler does all of the Rx thread work and cleans up
1310 after the Tx thread. */
1311 static irqreturn_t
intr_handler(int irq
, void *dev_instance
, struct pt_regs
*rgs
)
1313 struct net_device
*dev
= dev_instance
;
1314 struct netdev_private
*np
= netdev_priv(dev
);
1315 void __iomem
*ioaddr
= np
->base
;
1316 int boguscnt
= max_interrupt_work
;
1322 u32 intr_status
= readl(ioaddr
+ IntrClear
);
1325 printk(KERN_DEBUG
"%s: Interrupt status %#8.8x.\n",
1326 dev
->name
, intr_status
);
1328 if (intr_status
== 0 || intr_status
== (u32
) -1)
1333 if (intr_status
& (IntrRxDone
| IntrRxEmpty
))
1334 netdev_rx(dev
, ioaddr
);
1336 /* Scavenge the skbuff list based on the Tx-done queue.
1337 There are redundant checks here that may be cleaned up
1338 after the driver has proven to be reliable. */
1339 consumer
= readl(ioaddr
+ TxConsumerIdx
);
1341 printk(KERN_DEBUG
"%s: Tx Consumer index is %d.\n",
1342 dev
->name
, consumer
);
1344 while ((tx_status
= le32_to_cpu(np
->tx_done_q
[np
->tx_done
].status
)) != 0) {
1346 printk(KERN_DEBUG
"%s: Tx completion #%d entry %d is %#8.8x.\n",
1347 dev
->name
, np
->dirty_tx
, np
->tx_done
, tx_status
);
1348 if ((tx_status
& 0xe0000000) == 0xa0000000) {
1349 np
->stats
.tx_packets
++;
1350 } else if ((tx_status
& 0xe0000000) == 0x80000000) {
1351 u16 entry
= (tx_status
& 0x7fff) / sizeof(starfire_tx_desc
);
1352 struct sk_buff
*skb
= np
->tx_info
[entry
].skb
;
1353 np
->tx_info
[entry
].skb
= NULL
;
1354 pci_unmap_single(np
->pci_dev
,
1355 np
->tx_info
[entry
].mapping
,
1356 skb_first_frag_len(skb
),
1358 np
->tx_info
[entry
].mapping
= 0;
1359 np
->dirty_tx
+= np
->tx_info
[entry
].used_slots
;
1360 entry
= (entry
+ np
->tx_info
[entry
].used_slots
) % TX_RING_SIZE
;
1363 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1364 pci_unmap_single(np
->pci_dev
,
1365 np
->tx_info
[entry
].mapping
,
1366 skb_shinfo(skb
)->frags
[i
].size
,
1373 dev_kfree_skb_irq(skb
);
1375 np
->tx_done_q
[np
->tx_done
].status
= 0;
1376 np
->tx_done
= (np
->tx_done
+ 1) % DONE_Q_SIZE
;
1378 writew(np
->tx_done
, ioaddr
+ CompletionQConsumerIdx
+ 2);
1380 if (netif_queue_stopped(dev
) &&
1381 (np
->cur_tx
- np
->dirty_tx
+ 4 < TX_RING_SIZE
)) {
1382 /* The ring is no longer full, wake the queue. */
1383 netif_wake_queue(dev
);
1386 /* Stats overflow */
1387 if (intr_status
& IntrStatsMax
)
1390 /* Media change interrupt. */
1391 if (intr_status
& IntrLinkChange
)
1392 netdev_media_change(dev
);
1394 /* Abnormal error summary/uncommon events handlers. */
1395 if (intr_status
& IntrAbnormalSummary
)
1396 netdev_error(dev
, intr_status
);
1398 if (--boguscnt
< 0) {
1400 printk(KERN_WARNING
"%s: Too much work at interrupt, "
1402 dev
->name
, intr_status
);
1408 printk(KERN_DEBUG
"%s: exiting interrupt, status=%#8.8x.\n",
1409 dev
->name
, (int) readl(ioaddr
+ IntrStatus
));
1410 return IRQ_RETVAL(handled
);
1414 /* This routine is logically part of the interrupt/poll handler, but separated
1415 for clarity, code sharing between NAPI/non-NAPI, and better register allocation. */
1416 static int __netdev_rx(struct net_device
*dev
, int *quota
)
1418 struct netdev_private
*np
= netdev_priv(dev
);
1422 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1423 while ((desc_status
= le32_to_cpu(np
->rx_done_q
[np
->rx_done
].status
)) != 0) {
1424 struct sk_buff
*skb
;
1427 rx_done_desc
*desc
= &np
->rx_done_q
[np
->rx_done
];
1430 printk(KERN_DEBUG
" netdev_rx() status of %d was %#8.8x.\n", np
->rx_done
, desc_status
);
1431 if (!(desc_status
& RxOK
)) {
1432 /* There was an error. */
1434 printk(KERN_DEBUG
" netdev_rx() Rx error was %#8.8x.\n", desc_status
);
1435 np
->stats
.rx_errors
++;
1436 if (desc_status
& RxFIFOErr
)
1437 np
->stats
.rx_fifo_errors
++;
1441 if (*quota
<= 0) { /* out of rx quota */
1447 pkt_len
= desc_status
; /* Implicitly Truncate */
1448 entry
= (desc_status
>> 16) & 0x7ff;
1451 printk(KERN_DEBUG
" netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len
, *quota
);
1452 /* Check if the packet is long enough to accept without copying
1453 to a minimally-sized skbuff. */
1454 if (pkt_len
< rx_copybreak
1455 && (skb
= dev_alloc_skb(pkt_len
+ 2)) != NULL
) {
1457 skb_reserve(skb
, 2); /* 16 byte align the IP header */
1458 pci_dma_sync_single_for_cpu(np
->pci_dev
,
1459 np
->rx_info
[entry
].mapping
,
1460 pkt_len
, PCI_DMA_FROMDEVICE
);
1461 eth_copy_and_sum(skb
, np
->rx_info
[entry
].skb
->data
, pkt_len
, 0);
1462 pci_dma_sync_single_for_device(np
->pci_dev
,
1463 np
->rx_info
[entry
].mapping
,
1464 pkt_len
, PCI_DMA_FROMDEVICE
);
1465 skb_put(skb
, pkt_len
);
1467 pci_unmap_single(np
->pci_dev
, np
->rx_info
[entry
].mapping
, np
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1468 skb
= np
->rx_info
[entry
].skb
;
1469 skb_put(skb
, pkt_len
);
1470 np
->rx_info
[entry
].skb
= NULL
;
1471 np
->rx_info
[entry
].mapping
= 0;
1473 #ifndef final_version /* Remove after testing. */
1474 /* You will want this info for the initial debug. */
1476 printk(KERN_DEBUG
" Rx data %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:"
1477 "%2.2x %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x %2.2x%2.2x.\n",
1478 skb
->data
[0], skb
->data
[1], skb
->data
[2], skb
->data
[3],
1479 skb
->data
[4], skb
->data
[5], skb
->data
[6], skb
->data
[7],
1480 skb
->data
[8], skb
->data
[9], skb
->data
[10],
1481 skb
->data
[11], skb
->data
[12], skb
->data
[13]);
1484 skb
->protocol
= eth_type_trans(skb
, dev
);
1487 printk(KERN_DEBUG
" netdev_rx() status2 of %d was %#4.4x.\n", np
->rx_done
, le16_to_cpu(desc
->status2
));
1489 if (le16_to_cpu(desc
->status2
) & 0x0100) {
1490 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1491 np
->stats
.rx_compressed
++;
1494 * This feature doesn't seem to be working, at least
1495 * with the two firmware versions I have. If the GFP sees
1496 * an IP fragment, it either ignores it completely, or reports
1497 * "bad checksum" on it.
1499 * Maybe I missed something -- corrections are welcome.
1500 * Until then, the printk stays. :-) -Ion
1502 else if (le16_to_cpu(desc
->status2
) & 0x0040) {
1503 skb
->ip_summed
= CHECKSUM_HW
;
1504 skb
->csum
= le16_to_cpu(desc
->csum
);
1505 printk(KERN_DEBUG
"%s: checksum_hw, status2 = %#x\n", dev
->name
, le16_to_cpu(desc
->status2
));
1508 if (np
->vlgrp
&& le16_to_cpu(desc
->status2
) & 0x0200) {
1510 printk(KERN_DEBUG
" netdev_rx() vlanid = %d\n", le16_to_cpu(desc
->vlanid
));
1511 /* vlan_netdev_receive_skb() expects a packet with the VLAN tag stripped out */
1512 vlan_netdev_receive_skb(skb
, np
->vlgrp
, le16_to_cpu(desc
->vlanid
) & VLAN_VID_MASK
);
1514 #endif /* VLAN_SUPPORT */
1515 netdev_receive_skb(skb
);
1516 dev
->last_rx
= jiffies
;
1517 np
->stats
.rx_packets
++;
1522 np
->rx_done
= (np
->rx_done
+ 1) % DONE_Q_SIZE
;
1524 writew(np
->rx_done
, np
->base
+ CompletionQConsumerIdx
);
1527 refill_rx_ring(dev
);
1529 printk(KERN_DEBUG
" exiting netdev_rx(): %d, status of %d was %#8.8x.\n",
1530 retcode
, np
->rx_done
, desc_status
);
1535 #ifdef HAVE_NETDEV_POLL
1536 static int netdev_poll(struct net_device
*dev
, int *budget
)
1539 struct netdev_private
*np
= netdev_priv(dev
);
1540 void __iomem
*ioaddr
= np
->base
;
1541 int retcode
= 0, quota
= dev
->quota
;
1544 writel(IntrRxDone
| IntrRxEmpty
, ioaddr
+ IntrClear
);
1546 retcode
= __netdev_rx(dev
, "a
);
1547 *budget
-= (dev
->quota
- quota
);
1552 intr_status
= readl(ioaddr
+ IntrStatus
);
1553 } while (intr_status
& (IntrRxDone
| IntrRxEmpty
));
1555 netif_rx_complete(dev
);
1556 intr_status
= readl(ioaddr
+ IntrEnable
);
1557 intr_status
|= IntrRxDone
| IntrRxEmpty
;
1558 writel(intr_status
, ioaddr
+ IntrEnable
);
1562 printk(KERN_DEBUG
" exiting netdev_poll(): %d.\n", retcode
);
1564 /* Restart Rx engine if stopped. */
1567 #endif /* HAVE_NETDEV_POLL */
1570 static void refill_rx_ring(struct net_device
*dev
)
1572 struct netdev_private
*np
= netdev_priv(dev
);
1573 struct sk_buff
*skb
;
1576 /* Refill the Rx ring buffers. */
1577 for (; np
->cur_rx
- np
->dirty_rx
> 0; np
->dirty_rx
++) {
1578 entry
= np
->dirty_rx
% RX_RING_SIZE
;
1579 if (np
->rx_info
[entry
].skb
== NULL
) {
1580 skb
= dev_alloc_skb(np
->rx_buf_sz
);
1581 np
->rx_info
[entry
].skb
= skb
;
1583 break; /* Better luck next round. */
1584 np
->rx_info
[entry
].mapping
=
1585 pci_map_single(np
->pci_dev
, skb
->data
, np
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1586 skb
->dev
= dev
; /* Mark as being used by this device. */
1587 np
->rx_ring
[entry
].rxaddr
=
1588 cpu_to_dma(np
->rx_info
[entry
].mapping
| RxDescValid
);
1590 if (entry
== RX_RING_SIZE
- 1)
1591 np
->rx_ring
[entry
].rxaddr
|= cpu_to_dma(RxDescEndRing
);
1594 writew(entry
, np
->base
+ RxDescQIdx
);
1598 static void netdev_media_change(struct net_device
*dev
)
1600 struct netdev_private
*np
= netdev_priv(dev
);
1601 void __iomem
*ioaddr
= np
->base
;
1602 u16 reg0
, reg1
, reg4
, reg5
;
1604 u32 new_intr_timer_ctrl
;
1606 /* reset status first */
1607 mdio_read(dev
, np
->phys
[0], MII_BMCR
);
1608 mdio_read(dev
, np
->phys
[0], MII_BMSR
);
1610 reg0
= mdio_read(dev
, np
->phys
[0], MII_BMCR
);
1611 reg1
= mdio_read(dev
, np
->phys
[0], MII_BMSR
);
1613 if (reg1
& BMSR_LSTATUS
) {
1615 if (reg0
& BMCR_ANENABLE
) {
1616 /* autonegotiation is enabled */
1617 reg4
= mdio_read(dev
, np
->phys
[0], MII_ADVERTISE
);
1618 reg5
= mdio_read(dev
, np
->phys
[0], MII_LPA
);
1619 if (reg4
& ADVERTISE_100FULL
&& reg5
& LPA_100FULL
) {
1621 np
->mii_if
.full_duplex
= 1;
1622 } else if (reg4
& ADVERTISE_100HALF
&& reg5
& LPA_100HALF
) {
1624 np
->mii_if
.full_duplex
= 0;
1625 } else if (reg4
& ADVERTISE_10FULL
&& reg5
& LPA_10FULL
) {
1627 np
->mii_if
.full_duplex
= 1;
1630 np
->mii_if
.full_duplex
= 0;
1633 /* autonegotiation is disabled */
1634 if (reg0
& BMCR_SPEED100
)
1638 if (reg0
& BMCR_FULLDPLX
)
1639 np
->mii_if
.full_duplex
= 1;
1641 np
->mii_if
.full_duplex
= 0;
1643 netif_carrier_on(dev
);
1644 printk(KERN_DEBUG
"%s: Link is up, running at %sMbit %s-duplex\n",
1646 np
->speed100
? "100" : "10",
1647 np
->mii_if
.full_duplex
? "full" : "half");
1649 new_tx_mode
= np
->tx_mode
& ~FullDuplex
; /* duplex setting */
1650 if (np
->mii_if
.full_duplex
)
1651 new_tx_mode
|= FullDuplex
;
1652 if (np
->tx_mode
!= new_tx_mode
) {
1653 np
->tx_mode
= new_tx_mode
;
1654 writel(np
->tx_mode
| MiiSoftReset
, ioaddr
+ TxMode
);
1656 writel(np
->tx_mode
, ioaddr
+ TxMode
);
1659 new_intr_timer_ctrl
= np
->intr_timer_ctrl
& ~Timer10X
;
1661 new_intr_timer_ctrl
|= Timer10X
;
1662 if (np
->intr_timer_ctrl
!= new_intr_timer_ctrl
) {
1663 np
->intr_timer_ctrl
= new_intr_timer_ctrl
;
1664 writel(new_intr_timer_ctrl
, ioaddr
+ IntrTimerCtrl
);
1667 netif_carrier_off(dev
);
1668 printk(KERN_DEBUG
"%s: Link is down\n", dev
->name
);
1673 static void netdev_error(struct net_device
*dev
, int intr_status
)
1675 struct netdev_private
*np
= netdev_priv(dev
);
1677 /* Came close to underrunning the Tx FIFO, increase threshold. */
1678 if (intr_status
& IntrTxDataLow
) {
1679 if (np
->tx_threshold
<= PKT_BUF_SZ
/ 16) {
1680 writel(++np
->tx_threshold
, np
->base
+ TxThreshold
);
1681 printk(KERN_NOTICE
"%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n",
1682 dev
->name
, np
->tx_threshold
* 16);
1684 printk(KERN_WARNING
"%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev
->name
);
1686 if (intr_status
& IntrRxGFPDead
) {
1687 np
->stats
.rx_fifo_errors
++;
1688 np
->stats
.rx_errors
++;
1690 if (intr_status
& (IntrNoTxCsum
| IntrDMAErr
)) {
1691 np
->stats
.tx_fifo_errors
++;
1692 np
->stats
.tx_errors
++;
1694 if ((intr_status
& ~(IntrNormalMask
| IntrAbnormalSummary
| IntrLinkChange
| IntrStatsMax
| IntrTxDataLow
| IntrRxGFPDead
| IntrNoTxCsum
| IntrPCIPad
)) && debug
)
1695 printk(KERN_ERR
"%s: Something Wicked happened! %#8.8x.\n",
1696 dev
->name
, intr_status
);
1700 static struct net_device_stats
*get_stats(struct net_device
*dev
)
1702 struct netdev_private
*np
= netdev_priv(dev
);
1703 void __iomem
*ioaddr
= np
->base
;
1705 /* This adapter architecture needs no SMP locks. */
1706 np
->stats
.tx_bytes
= readl(ioaddr
+ 0x57010);
1707 np
->stats
.rx_bytes
= readl(ioaddr
+ 0x57044);
1708 np
->stats
.tx_packets
= readl(ioaddr
+ 0x57000);
1709 np
->stats
.tx_aborted_errors
=
1710 readl(ioaddr
+ 0x57024) + readl(ioaddr
+ 0x57028);
1711 np
->stats
.tx_window_errors
= readl(ioaddr
+ 0x57018);
1712 np
->stats
.collisions
=
1713 readl(ioaddr
+ 0x57004) + readl(ioaddr
+ 0x57008);
1715 /* The chip only need report frame silently dropped. */
1716 np
->stats
.rx_dropped
+= readw(ioaddr
+ RxDMAStatus
);
1717 writew(0, ioaddr
+ RxDMAStatus
);
1718 np
->stats
.rx_crc_errors
= readl(ioaddr
+ 0x5703C);
1719 np
->stats
.rx_frame_errors
= readl(ioaddr
+ 0x57040);
1720 np
->stats
.rx_length_errors
= readl(ioaddr
+ 0x57058);
1721 np
->stats
.rx_missed_errors
= readl(ioaddr
+ 0x5707C);
1727 static void set_rx_mode(struct net_device
*dev
)
1729 struct netdev_private
*np
= netdev_priv(dev
);
1730 void __iomem
*ioaddr
= np
->base
;
1731 u32 rx_mode
= MinVLANPrio
;
1732 struct dev_mc_list
*mclist
;
1736 rx_mode
|= VlanMode
;
1739 void __iomem
*filter_addr
= ioaddr
+ HashTable
+ 8;
1740 for (i
= 0; i
< VLAN_VID_MASK
; i
++) {
1741 if (np
->vlgrp
->vlan_devices
[i
]) {
1742 if (vlan_count
>= 32)
1744 writew(cpu_to_be16(i
), filter_addr
);
1749 if (i
== VLAN_VID_MASK
) {
1750 rx_mode
|= PerfectFilterVlan
;
1751 while (vlan_count
< 32) {
1752 writew(0, filter_addr
);
1758 #endif /* VLAN_SUPPORT */
1760 if (dev
->flags
& IFF_PROMISC
) { /* Set promiscuous. */
1761 rx_mode
|= AcceptAll
;
1762 } else if ((dev
->mc_count
> multicast_filter_limit
)
1763 || (dev
->flags
& IFF_ALLMULTI
)) {
1764 /* Too many to match, or accept all multicasts. */
1765 rx_mode
|= AcceptBroadcast
|AcceptAllMulticast
|PerfectFilter
;
1766 } else if (dev
->mc_count
<= 14) {
1767 /* Use the 16 element perfect filter, skip first two entries. */
1768 void __iomem
*filter_addr
= ioaddr
+ PerfFilterTable
+ 2 * 16;
1770 for (i
= 2, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
+ 2;
1771 i
++, mclist
= mclist
->next
) {
1772 eaddrs
= (u16
*)mclist
->dmi_addr
;
1773 writew(cpu_to_be16(eaddrs
[2]), filter_addr
); filter_addr
+= 4;
1774 writew(cpu_to_be16(eaddrs
[1]), filter_addr
); filter_addr
+= 4;
1775 writew(cpu_to_be16(eaddrs
[0]), filter_addr
); filter_addr
+= 8;
1777 eaddrs
= (u16
*)dev
->dev_addr
;
1779 writew(cpu_to_be16(eaddrs
[0]), filter_addr
); filter_addr
+= 4;
1780 writew(cpu_to_be16(eaddrs
[1]), filter_addr
); filter_addr
+= 4;
1781 writew(cpu_to_be16(eaddrs
[2]), filter_addr
); filter_addr
+= 8;
1783 rx_mode
|= AcceptBroadcast
|PerfectFilter
;
1785 /* Must use a multicast hash table. */
1786 void __iomem
*filter_addr
;
1788 u16 mc_filter
[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */
1790 memset(mc_filter
, 0, sizeof(mc_filter
));
1791 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
1792 i
++, mclist
= mclist
->next
) {
1793 /* The chip uses the upper 9 CRC bits
1794 as index into the hash table */
1795 int bit_nr
= ether_crc_le(ETH_ALEN
, mclist
->dmi_addr
) >> 23;
1796 __u32
*fptr
= (__u32
*) &mc_filter
[(bit_nr
>> 4) & ~1];
1798 *fptr
|= cpu_to_le32(1 << (bit_nr
& 31));
1800 /* Clear the perfect filter list, skip first two entries. */
1801 filter_addr
= ioaddr
+ PerfFilterTable
+ 2 * 16;
1802 eaddrs
= (u16
*)dev
->dev_addr
;
1803 for (i
= 2; i
< 16; i
++) {
1804 writew(cpu_to_be16(eaddrs
[0]), filter_addr
); filter_addr
+= 4;
1805 writew(cpu_to_be16(eaddrs
[1]), filter_addr
); filter_addr
+= 4;
1806 writew(cpu_to_be16(eaddrs
[2]), filter_addr
); filter_addr
+= 8;
1808 for (filter_addr
= ioaddr
+ HashTable
, i
= 0; i
< 32; filter_addr
+= 16, i
++)
1809 writew(mc_filter
[i
], filter_addr
);
1810 rx_mode
|= AcceptBroadcast
|PerfectFilter
|HashFilter
;
1812 writel(rx_mode
, ioaddr
+ RxFilterMode
);
1815 static int check_if_running(struct net_device
*dev
)
1817 if (!netif_running(dev
))
1822 static void get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1824 struct netdev_private
*np
= netdev_priv(dev
);
1825 strcpy(info
->driver
, DRV_NAME
);
1826 strcpy(info
->version
, DRV_VERSION
);
1827 strcpy(info
->bus_info
, pci_name(np
->pci_dev
));
1830 static int get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
1832 struct netdev_private
*np
= netdev_priv(dev
);
1833 spin_lock_irq(&np
->lock
);
1834 mii_ethtool_gset(&np
->mii_if
, ecmd
);
1835 spin_unlock_irq(&np
->lock
);
1839 static int set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
1841 struct netdev_private
*np
= netdev_priv(dev
);
1843 spin_lock_irq(&np
->lock
);
1844 res
= mii_ethtool_sset(&np
->mii_if
, ecmd
);
1845 spin_unlock_irq(&np
->lock
);
1850 static int nway_reset(struct net_device
*dev
)
1852 struct netdev_private
*np
= netdev_priv(dev
);
1853 return mii_nway_restart(&np
->mii_if
);
1856 static u32
get_link(struct net_device
*dev
)
1858 struct netdev_private
*np
= netdev_priv(dev
);
1859 return mii_link_ok(&np
->mii_if
);
1862 static u32
get_msglevel(struct net_device
*dev
)
1867 static void set_msglevel(struct net_device
*dev
, u32 val
)
1872 static struct ethtool_ops ethtool_ops
= {
1873 .begin
= check_if_running
,
1874 .get_drvinfo
= get_drvinfo
,
1875 .get_settings
= get_settings
,
1876 .set_settings
= set_settings
,
1877 .nway_reset
= nway_reset
,
1878 .get_link
= get_link
,
1879 .get_msglevel
= get_msglevel
,
1880 .set_msglevel
= set_msglevel
,
1883 static int netdev_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
1885 struct netdev_private
*np
= netdev_priv(dev
);
1886 struct mii_ioctl_data
*data
= if_mii(rq
);
1889 if (!netif_running(dev
))
1892 spin_lock_irq(&np
->lock
);
1893 rc
= generic_mii_ioctl(&np
->mii_if
, data
, cmd
, NULL
);
1894 spin_unlock_irq(&np
->lock
);
1896 if ((cmd
== SIOCSMIIREG
) && (data
->phy_id
== np
->phys
[0]))
1902 static int netdev_close(struct net_device
*dev
)
1904 struct netdev_private
*np
= netdev_priv(dev
);
1905 void __iomem
*ioaddr
= np
->base
;
1908 netif_stop_queue(dev
);
1911 printk(KERN_DEBUG
"%s: Shutting down ethercard, Intr status %#8.8x.\n",
1912 dev
->name
, (int) readl(ioaddr
+ IntrStatus
));
1913 printk(KERN_DEBUG
"%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1914 dev
->name
, np
->cur_tx
, np
->dirty_tx
,
1915 np
->cur_rx
, np
->dirty_rx
);
1918 /* Disable interrupts by clearing the interrupt mask. */
1919 writel(0, ioaddr
+ IntrEnable
);
1921 /* Stop the chip's Tx and Rx processes. */
1922 writel(0, ioaddr
+ GenCtrl
);
1923 readl(ioaddr
+ GenCtrl
);
1926 printk(KERN_DEBUG
" Tx ring at %#llx:\n",
1927 (long long) np
->tx_ring_dma
);
1928 for (i
= 0; i
< 8 /* TX_RING_SIZE is huge! */; i
++)
1929 printk(KERN_DEBUG
" #%d desc. %#8.8x %#llx -> %#8.8x.\n",
1930 i
, le32_to_cpu(np
->tx_ring
[i
].status
),
1931 (long long) dma_to_cpu(np
->tx_ring
[i
].addr
),
1932 le32_to_cpu(np
->tx_done_q
[i
].status
));
1933 printk(KERN_DEBUG
" Rx ring at %#llx -> %p:\n",
1934 (long long) np
->rx_ring_dma
, np
->rx_done_q
);
1936 for (i
= 0; i
< 8 /* RX_RING_SIZE */; i
++) {
1937 printk(KERN_DEBUG
" #%d desc. %#llx -> %#8.8x\n",
1938 i
, (long long) dma_to_cpu(np
->rx_ring
[i
].rxaddr
), le32_to_cpu(np
->rx_done_q
[i
].status
));
1942 free_irq(dev
->irq
, dev
);
1944 /* Free all the skbuffs in the Rx queue. */
1945 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1946 np
->rx_ring
[i
].rxaddr
= cpu_to_dma(0xBADF00D0); /* An invalid address. */
1947 if (np
->rx_info
[i
].skb
!= NULL
) {
1948 pci_unmap_single(np
->pci_dev
, np
->rx_info
[i
].mapping
, np
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1949 dev_kfree_skb(np
->rx_info
[i
].skb
);
1951 np
->rx_info
[i
].skb
= NULL
;
1952 np
->rx_info
[i
].mapping
= 0;
1954 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1955 struct sk_buff
*skb
= np
->tx_info
[i
].skb
;
1958 pci_unmap_single(np
->pci_dev
,
1959 np
->tx_info
[i
].mapping
,
1960 skb_first_frag_len(skb
), PCI_DMA_TODEVICE
);
1961 np
->tx_info
[i
].mapping
= 0;
1963 np
->tx_info
[i
].skb
= NULL
;
1970 static int starfire_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1972 struct net_device
*dev
= pci_get_drvdata(pdev
);
1974 if (netif_running(dev
)) {
1975 netif_device_detach(dev
);
1979 pci_save_state(pdev
);
1980 pci_set_power_state(pdev
, pci_choose_state(pdev
,state
));
1985 static int starfire_resume(struct pci_dev
*pdev
)
1987 struct net_device
*dev
= pci_get_drvdata(pdev
);
1989 pci_set_power_state(pdev
, PCI_D0
);
1990 pci_restore_state(pdev
);
1992 if (netif_running(dev
)) {
1994 netif_device_attach(dev
);
1999 #endif /* CONFIG_PM */
2002 static void __devexit
starfire_remove_one (struct pci_dev
*pdev
)
2004 struct net_device
*dev
= pci_get_drvdata(pdev
);
2005 struct netdev_private
*np
= netdev_priv(dev
);
2009 unregister_netdev(dev
);
2012 pci_free_consistent(pdev
, np
->queue_mem_size
, np
->queue_mem
, np
->queue_mem_dma
);
2015 /* XXX: add wakeup code -- requires firmware for MagicPacket */
2016 pci_set_power_state(pdev
, PCI_D3hot
); /* go to sleep in D3 mode */
2017 pci_disable_device(pdev
);
2020 pci_release_regions(pdev
);
2022 pci_set_drvdata(pdev
, NULL
);
2023 free_netdev(dev
); /* Will also free np!! */
2027 static struct pci_driver starfire_driver
= {
2029 .probe
= starfire_init_one
,
2030 .remove
= __devexit_p(starfire_remove_one
),
2032 .suspend
= starfire_suspend
,
2033 .resume
= starfire_resume
,
2034 #endif /* CONFIG_PM */
2035 .id_table
= starfire_pci_tbl
,
2039 static int __init
starfire_init (void)
2041 /* when a module, this is printed whether or not devices are found in probe */
2044 #ifdef HAVE_NETDEV_POLL
2045 printk(KERN_INFO DRV_NAME
": polling (NAPI) enabled\n");
2047 printk(KERN_INFO DRV_NAME
": polling (NAPI) disabled\n");
2051 /* we can do this test only at run-time... sigh */
2052 if (sizeof(dma_addr_t
) != sizeof(netdrv_addr_t
)) {
2053 printk("This driver has dma_addr_t issues, please send email to maintainer\n");
2057 return pci_module_init (&starfire_driver
);
2061 static void __exit
starfire_cleanup (void)
2063 pci_unregister_driver (&starfire_driver
);
2067 module_init(starfire_init
);
2068 module_exit(starfire_cleanup
);