arch/arm/mach-versatile/pci.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/pci.c
   3  *
   4  * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
   5  * You can redistribute and/or modify this software under the terms of version 2
   6  * of the GNU General Public License as published by the Free Software Foundation.
   7  * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
   8  * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   9  * General Public License for more details.
  10  * Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
  11  *
  12  * ARM Versatile PCI driver.
  13  *
  14  * 14/04/2005 Initial version, colin.king@philips.com
  15  *
  16  */
  17 #include <linux/config.h>
  18 #include <linux/kernel.h>
  19 #include <linux/pci.h>
  20 #include <linux/ptrace.h>
  21 #include <linux/slab.h>
  22 #include <linux/ioport.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/init.h>
  26
  27 #include <asm/hardware.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30 #include <asm/system.h>
  31 #include <asm/mach/pci.h>
  32
  33 /*
  34  * these spaces are mapped using the following base registers:
  35  *
  36  * Usage Local Bus Memory         Base/Map registers used
  37  *
  38  * Mem   50000000 - 5FFFFFFF      LB_BASE0/LB_MAP0,  non prefetch
  39  * Mem   60000000 - 6FFFFFFF      LB_BASE1/LB_MAP1,  prefetch
  40  * IO    44000000 - 4FFFFFFF      LB_BASE2/LB_MAP2,  IO
  41  * Cfg   42000000 - 42FFFFFF      PCI config
  42  *
  43  */
  44 #define SYS_PCICTL                      IO_ADDRESS(VERSATILE_SYS_PCICTL)
  45 #define PCI_IMAP0                       IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
  46 #define PCI_IMAP1                       IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
  47 #define PCI_IMAP2                       IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
  48 #define PCI_SMAP0                       IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
  49 #define PCI_SMAP1                       IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
  50 #define PCI_SMAP2                       IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
  51 #define PCI_SELFID                      IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
  52
  53 #define DEVICE_ID_OFFSET                0x00
  54 #define CSR_OFFSET                      0x04
  55 #define CLASS_ID_OFFSET                 0x08
  56
  57 #define VP_PCI_DEVICE_ID                0x030010ee
  58 #define VP_PCI_CLASS_ID                 0x0b400000
  59
  60 static unsigned long pci_slot_ignore = 0;
  61
  62 static int __init versatile_pci_slot_ignore(char *str)
  63 {
  64         int retval;
  65         int slot;
  66
  67         while ((retval = get_option(&str,&slot))) {
  68                 if ((slot < 0) || (slot > 31)) {
  69                         printk("Illegal slot value: %d\n",slot);
  70                 } else {
  71                         pci_slot_ignore |= (1 << slot);
  72                 }
  73         }
  74         return 1;
  75 }
  76
  77 __setup("pci_slot_ignore=", versatile_pci_slot_ignore);
  78
  79
  80 static unsigned long __pci_addr(struct pci_bus *bus,
  81                                 unsigned int devfn, int offset)
  82 {
  83         unsigned int busnr = bus->number;
  84
  85         /*
  86          * Trap out illegal values
  87          */
  88         if (offset > 255)
  89                 BUG();
  90         if (busnr > 255)
  91                 BUG();
  92         if (devfn > 255)
  93                 BUG();
  94
  95         return (VERSATILE_PCI_CFG_VIRT_BASE | (busnr << 16) |
  96                 (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
  97 }
  98
  99 static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
 100                                  int size, u32 *val)
 101 {
 102         unsigned long addr = __pci_addr(bus, devfn, where);
 103         u32 v;
 104         int slot = PCI_SLOT(devfn);
 105
 106         if (pci_slot_ignore & (1 << slot)) {
 107                 /* Ignore this slot */
 108                 switch (size) {
 109                 case 1:
 110                         v = 0xff;
 111                         break;
 112                 case 2:
 113                         v = 0xffff;
 114                         break;
 115                 default:
 116                         v = 0xffffffff;
 117                 }
 118         } else {
 119                 switch (size) {
 120                 case 1:
 121                         addr &= ~3;
 122                         v = __raw_readb(addr);
 123                         break;
 124
 125                 case 2:
 126                         v = __raw_readl(addr & ~3);
 127                         if (addr & 2) v >>= 16;
 128                         v &= 0xffff;
 129                         break;
 130
 131                 default:
 132                         addr &= ~3;
 133                         v = __raw_readl(addr);
 134                         break;
 135                 }
 136         }
 137
 138         *val = v;
 139         return PCIBIOS_SUCCESSFUL;
 140 }
 141
 142 static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
 143                                   int size, u32 val)
 144 {
 145         unsigned long addr = __pci_addr(bus, devfn, where);
 146         int slot = PCI_SLOT(devfn);
 147
 148         if (pci_slot_ignore & (1 << slot)) {
 149                 return PCIBIOS_SUCCESSFUL;
 150         }
 151
 152         switch (size) {
 153         case 1:
 154                 __raw_writeb((u8)val, addr);
 155                 break;
 156
 157         case 2:
 158                 __raw_writew((u16)val, addr);
 159                 break;
 160
 161         case 4:
 162                 __raw_writel(val, addr);
 163                 break;
 164         }
 165
 166         return PCIBIOS_SUCCESSFUL;
 167 }
 168
 169 static struct pci_ops pci_versatile_ops = {
 170         .read   = versatile_read_config,
 171         .write  = versatile_write_config,
 172 };
 173
 174 static struct resource io_mem = {
 175         .name   = "PCI I/O space",
 176         .start  = VERSATILE_PCI_MEM_BASE0,
 177         .end    = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
 178         .flags  = IORESOURCE_IO,
 179 };
 180
 181 static struct resource non_mem = {
 182         .name   = "PCI non-prefetchable",
 183         .start  = VERSATILE_PCI_MEM_BASE1,
 184         .end    = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
 185         .flags  = IORESOURCE_MEM,
 186 };
 187
 188 static struct resource pre_mem = {
 189         .name   = "PCI prefetchable",
 190         .start  = VERSATILE_PCI_MEM_BASE2,
 191         .end    = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
 192         .flags  = IORESOURCE_MEM | IORESOURCE_PREFETCH,
 193 };
 194
 195 static int __init pci_versatile_setup_resources(struct resource **resource)
 196 {
 197         int ret = 0;
 198
 199         ret = request_resource(&iomem_resource, &io_mem);
 200         if (ret) {
 201                 printk(KERN_ERR "PCI: unable to allocate I/O "
 202                        "memory region (%d)\n", ret);
 203                 goto out;
 204         }
 205         ret = request_resource(&iomem_resource, &non_mem);
 206         if (ret) {
 207                 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
 208                        "memory region (%d)\n", ret);
 209                 goto release_io_mem;
 210         }
 211         ret = request_resource(&iomem_resource, &pre_mem);
 212         if (ret) {
 213                 printk(KERN_ERR "PCI: unable to allocate prefetchable "
 214                        "memory region (%d)\n", ret);
 215                 goto release_non_mem;
 216         }
 217
 218         /*
 219          * bus->resource[0] is the IO resource for this bus
 220          * bus->resource[1] is the mem resource for this bus
 221          * bus->resource[2] is the prefetch mem resource for this bus
 222          */
 223         resource[0] = &io_mem;
 224         resource[1] = &non_mem;
 225         resource[2] = &pre_mem;
 226
 227         goto out;
 228
 229  release_non_mem:
 230         release_resource(&non_mem);
 231  release_io_mem:
 232         release_resource(&io_mem);
 233  out:
 234         return ret;
 235 }
 236
 237 int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 238 {
 239         int ret = 0;
 240         int i;
 241         int myslot = -1;
 242         unsigned long val;
 243
 244         if (nr == 0) {
 245                 sys->mem_offset = 0;
 246                 ret = pci_versatile_setup_resources(sys->resource);
 247                 if (ret < 0) {
 248                         printk("pci_versatile_setup: resources... oops?\n");
 249                         goto out;
 250                 }
 251         } else {
 252                 printk("pci_versatile_setup: resources... nr == 0??\n");
 253                 goto out;
 254         }
 255
 256         __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28,PCI_IMAP0);
 257         __raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28,PCI_IMAP1);
 258         __raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28,PCI_IMAP2);
 259
 260         __raw_writel(1, SYS_PCICTL);
 261
 262         val = __raw_readl(SYS_PCICTL);
 263         if (!(val & 1)) {
 264                 printk("Not plugged into PCI backplane!\n");
 265                 ret = -EIO;
 266                 goto out;
 267         }
 268
 269         /*
 270          *  We need to discover the PCI core first to configure itself
 271          *  before the main PCI probing is performed
 272          */
 273         for (i=0; i<32; i++) {
 274                 if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
 275                     (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
 276                         myslot = i;
 277
 278                         __raw_writel(myslot, PCI_SELFID);
 279                         val = __raw_readl(VERSATILE_PCI_CFG_VIRT_BASE+(myslot<<11)+CSR_OFFSET);
 280                         val |= (1<<2);
 281                         __raw_writel(val, VERSATILE_PCI_CFG_VIRT_BASE+(myslot<<11)+CSR_OFFSET);
 282                         break;
 283                 }
 284         }
 285
 286         if (myslot == -1) {
 287                 printk("Cannot find PCI core!\n");
 288                 ret = -EIO;
 289         } else {
 290                 printk("PCI core found (slot %d)\n",myslot);
 291                 /* Do not to map Versatile FPGA PCI device
 292                    into memory space as we are short of
 293                    mappable memory */
 294                 pci_slot_ignore |= (1 << myslot);
 295                 ret = 1;
 296         }
 297
 298  out:
 299         return ret;
 300 }
 301
 302
 303 struct pci_bus *pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
 304 {
 305         return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
 306 }
 307
 308 /*
 309  * V3_LB_BASE? - local bus address
 310  * V3_LB_MAP?  - pci bus address
 311  */
 312 void __init pci_versatile_preinit(void)
 313 {
 314 }
 315
 316 void __init pci_versatile_postinit(void)
 317 {
 318 }
 319
 320
 321 /*
 322  * map the specified device/slot/pin to an IRQ.   Different backplanes may need to modify this.
 323  */
 324 static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 325 {
 326         int irq;
 327         int devslot = PCI_SLOT(dev->devfn);
 328
 329         /* slot,  pin,  irq
 330             24    1     27
 331             25    1     28      untested
 332             26    1     29
 333             27    1     30      untested
 334         */
 335
 336         irq = 27 + ((slot + pin + 2) % 3);      /* Fudged */
 337
 338         printk("map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);
 339
 340         return irq;
 341 }
 342
 343 static struct hw_pci versatile_pci __initdata = {
 344         .swizzle                = NULL,
 345         .map_irq                = versatile_map_irq,
 346         .nr_controllers         = 1,
 347         .setup                  = pci_versatile_setup,
 348         .scan                   = pci_versatile_scan_bus,
 349         .preinit                = pci_versatile_preinit,
 350         .postinit               = pci_versatile_postinit,
 351 };
 352
 353 static int __init versatile_pci_init(void)
 354 {
 355         pci_common_init(&versatile_pci);
 356         return 0;
 357 }
 358
 359 subsys_initcall(versatile_pci_init);