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cxgb4: implement the ETHTOOL_GRXFH command
[linux-2.6/libata-dev.git] / drivers / net / cxgb4 / cxgb4_main.c
blob110843c5fde25884d91fc20943eb23bf88636a0a
1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
44 #include <linux/if_vlan.h>
45 #include <linux/init.h>
46 #include <linux/log2.h>
47 #include <linux/mdio.h>
48 #include <linux/module.h>
49 #include <linux/moduleparam.h>
50 #include <linux/mutex.h>
51 #include <linux/netdevice.h>
52 #include <linux/pci.h>
53 #include <linux/aer.h>
54 #include <linux/rtnetlink.h>
55 #include <linux/sched.h>
56 #include <linux/seq_file.h>
57 #include <linux/sockios.h>
58 #include <linux/vmalloc.h>
59 #include <linux/workqueue.h>
60 #include <net/neighbour.h>
61 #include <net/netevent.h>
62 #include <asm/uaccess.h>
63
64 #include "cxgb4.h"
65 #include "t4_regs.h"
66 #include "t4_msg.h"
67 #include "t4fw_api.h"
68 #include "l2t.h"
69
70 #define DRV_VERSION "1.0.0-ko"
71 #define DRV_DESC "Chelsio T4 Network Driver"
72
73 /*
74 * Max interrupt hold-off timer value in us. Queues fall back to this value
75 * under extreme memory pressure so it's largish to give the system time to
76 * recover.
77 */
78 #define MAX_SGE_TIMERVAL 200U
79
80 #ifdef CONFIG_PCI_IOV
81 /*
82 * Virtual Function provisioning constants. We need two extra Ingress Queues
83 * with Interrupt capability to serve as the VF's Firmware Event Queue and
84 * Forwarded Interrupt Queue (when using MSI mode) -- neither will have Free
85 * Lists associated with them). For each Ethernet/Control Egress Queue and
86 * for each Free List, we need an Egress Context.
87 */
88 enum {
89 VFRES_NPORTS = 1, /* # of "ports" per VF */
90 VFRES_NQSETS = 2, /* # of "Queue Sets" per VF */
91
92 VFRES_NVI = VFRES_NPORTS, /* # of Virtual Interfaces */
93 VFRES_NETHCTRL = VFRES_NQSETS, /* # of EQs used for ETH or CTRL Qs */
94 VFRES_NIQFLINT = VFRES_NQSETS+2,/* # of ingress Qs/w Free List(s)/intr */
95 VFRES_NIQ = 0, /* # of non-fl/int ingress queues */
96 VFRES_NEQ = VFRES_NQSETS*2, /* # of egress queues */
97 VFRES_TC = 0, /* PCI-E traffic class */
98 VFRES_NEXACTF = 16, /* # of exact MPS filters */
99
100 VFRES_R_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF|FW_CMD_CAP_PORT,
101 VFRES_WX_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF,
102 };
103
104 /*
105 * Provide a Port Access Rights Mask for the specified PF/VF. This is very
106 * static and likely not to be useful in the long run. We really need to
107 * implement some form of persistent configuration which the firmware
108 * controls.
109 */
110 static unsigned int pfvfres_pmask(struct adapter *adapter,
111 unsigned int pf, unsigned int vf)
112 {
113 unsigned int portn, portvec;
114
115 /*
116 * Give PF's access to all of the ports.
117 */
118 if (vf == 0)
119 return FW_PFVF_CMD_PMASK_MASK;
120
121 /*
122 * For VFs, we'll assign them access to the ports based purely on the
123 * PF. We assign active ports in order, wrapping around if there are
124 * fewer active ports than PFs: e.g. active port[pf % nports].
125 * Unfortunately the adapter's port_info structs haven't been
126 * initialized yet so we have to compute this.
127 */
128 if (adapter->params.nports == 0)
129 return 0;
130
131 portn = pf % adapter->params.nports;
132 portvec = adapter->params.portvec;
133 for (;;) {
134 /*
135 * Isolate the lowest set bit in the port vector. If we're at
136 * the port number that we want, return that as the pmask.
137 * otherwise mask that bit out of the port vector and
138 * decrement our port number ...
139 */
140 unsigned int pmask = portvec ^ (portvec & (portvec-1));
141 if (portn == 0)
142 return pmask;
143 portn--;
144 portvec &= ~pmask;
145 }
146 /*NOTREACHED*/
147 }
148 #endif
149
150 enum {
151 MEMWIN0_APERTURE = 65536,
152 MEMWIN0_BASE = 0x30000,
153 MEMWIN1_APERTURE = 32768,
154 MEMWIN1_BASE = 0x28000,
155 MEMWIN2_APERTURE = 2048,
156 MEMWIN2_BASE = 0x1b800,
157 };
158
159 enum {
160 MAX_TXQ_ENTRIES = 16384,
161 MAX_CTRL_TXQ_ENTRIES = 1024,
162 MAX_RSPQ_ENTRIES = 16384,
163 MAX_RX_BUFFERS = 16384,
164 MIN_TXQ_ENTRIES = 32,
165 MIN_CTRL_TXQ_ENTRIES = 32,
166 MIN_RSPQ_ENTRIES = 128,
167 MIN_FL_ENTRIES = 16
168 };
169
170 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
171 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
172 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
173
174 #define CH_DEVICE(devid) { PCI_VDEVICE(CHELSIO, devid), 0 }
175
176 static DEFINE_PCI_DEVICE_TABLE(cxgb4_pci_tbl) = {
177 CH_DEVICE(0xa000), /* PE10K */
178 { 0, }
179 };
180
181 #define FW_FNAME "cxgb4/t4fw.bin"
182
183 MODULE_DESCRIPTION(DRV_DESC);
184 MODULE_AUTHOR("Chelsio Communications");
185 MODULE_LICENSE("Dual BSD/GPL");
186 MODULE_VERSION(DRV_VERSION);
187 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
188 MODULE_FIRMWARE(FW_FNAME);
189
190 static int dflt_msg_enable = DFLT_MSG_ENABLE;
191
192 module_param(dflt_msg_enable, int, 0644);
193 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
194
195 /*
196 * The driver uses the best interrupt scheme available on a platform in the
197 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
198 * of these schemes the driver may consider as follows:
199 *
200 * msi = 2: choose from among all three options
201 * msi = 1: only consider MSI and INTx interrupts
202 * msi = 0: force INTx interrupts
203 */
204 static int msi = 2;
205
206 module_param(msi, int, 0644);
207 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
208
209 /*
210 * Queue interrupt hold-off timer values. Queues default to the first of these
211 * upon creation.
212 */
213 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
214
215 module_param_array(intr_holdoff, uint, NULL, 0644);
216 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
217 "0..4 in microseconds");
218
219 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
220
221 module_param_array(intr_cnt, uint, NULL, 0644);
222 MODULE_PARM_DESC(intr_cnt,
223 "thresholds 1..3 for queue interrupt packet counters");
224
225 static int vf_acls;
226
227 #ifdef CONFIG_PCI_IOV
228 module_param(vf_acls, bool, 0644);
229 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
230
231 static unsigned int num_vf[4];
232
233 module_param_array(num_vf, uint, NULL, 0644);
234 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
235 #endif
236
237 static struct dentry *cxgb4_debugfs_root;
238
239 static LIST_HEAD(adapter_list);
240 static DEFINE_MUTEX(uld_mutex);
241 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
242 static const char *uld_str[] = { "RDMA", "iSCSI" };
243
244 static void link_report(struct net_device *dev)
245 {
246 if (!netif_carrier_ok(dev))
247 netdev_info(dev, "link down\n");
248 else {
249 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
250
251 const char *s = "10Mbps";
252 const struct port_info *p = netdev_priv(dev);
253
254 switch (p->link_cfg.speed) {
255 case SPEED_10000:
256 s = "10Gbps";
257 break;
258 case SPEED_1000:
259 s = "1000Mbps";
260 break;
261 case SPEED_100:
262 s = "100Mbps";
263 break;
264 }
265
266 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
267 fc[p->link_cfg.fc]);
268 }
269 }
270
271 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
272 {
273 struct net_device *dev = adapter->port[port_id];
274
275 /* Skip changes from disabled ports. */
276 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
277 if (link_stat)
278 netif_carrier_on(dev);
279 else
280 netif_carrier_off(dev);
281
282 link_report(dev);
283 }
284 }
285
286 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
287 {
288 static const char *mod_str[] = {
289 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
290 };
291
292 const struct net_device *dev = adap->port[port_id];
293 const struct port_info *pi = netdev_priv(dev);
294
295 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
296 netdev_info(dev, "port module unplugged\n");
297 else if (pi->mod_type < ARRAY_SIZE(mod_str))
298 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
299 }
300
301 /*
302 * Configure the exact and hash address filters to handle a port's multicast
303 * and secondary unicast MAC addresses.
304 */
305 static int set_addr_filters(const struct net_device *dev, bool sleep)
306 {
307 u64 mhash = 0;
308 u64 uhash = 0;
309 bool free = true;
310 u16 filt_idx[7];
311 const u8 *addr[7];
312 int ret, naddr = 0;
313 const struct netdev_hw_addr *ha;
314 int uc_cnt = netdev_uc_count(dev);
315 int mc_cnt = netdev_mc_count(dev);
316 const struct port_info *pi = netdev_priv(dev);
317
318 /* first do the secondary unicast addresses */
319 netdev_for_each_uc_addr(ha, dev) {
320 addr[naddr++] = ha->addr;
321 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
322 ret = t4_alloc_mac_filt(pi->adapter, 0, pi->viid, free,
323 naddr, addr, filt_idx, &uhash, sleep);
324 if (ret < 0)
325 return ret;
326
327 free = false;
328 naddr = 0;
329 }
330 }
331
332 /* next set up the multicast addresses */
333 netdev_for_each_mc_addr(ha, dev) {
334 addr[naddr++] = ha->addr;
335 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
336 ret = t4_alloc_mac_filt(pi->adapter, 0, pi->viid, free,
337 naddr, addr, filt_idx, &mhash, sleep);
338 if (ret < 0)
339 return ret;
340
341 free = false;
342 naddr = 0;
343 }
344 }
345
346 return t4_set_addr_hash(pi->adapter, 0, pi->viid, uhash != 0,
347 uhash | mhash, sleep);
348 }
349
350 /*
351 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
352 * If @mtu is -1 it is left unchanged.
353 */
354 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
355 {
356 int ret;
357 struct port_info *pi = netdev_priv(dev);
358
359 ret = set_addr_filters(dev, sleep_ok);
360 if (ret == 0)
361 ret = t4_set_rxmode(pi->adapter, 0, pi->viid, mtu,
362 (dev->flags & IFF_PROMISC) ? 1 : 0,
363 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
364 sleep_ok);
365 return ret;
366 }
367
368 /**
369 * link_start - enable a port
370 * @dev: the port to enable
371 *
372 * Performs the MAC and PHY actions needed to enable a port.
373 */
374 static int link_start(struct net_device *dev)
375 {
376 int ret;
377 struct port_info *pi = netdev_priv(dev);
378
379 /*
380 * We do not set address filters and promiscuity here, the stack does
381 * that step explicitly.
382 */
383 ret = t4_set_rxmode(pi->adapter, 0, pi->viid, dev->mtu, -1, -1, -1,
384 pi->vlan_grp != NULL, true);
385 if (ret == 0) {
386 ret = t4_change_mac(pi->adapter, 0, pi->viid,
387 pi->xact_addr_filt, dev->dev_addr, true,
388 true);
389 if (ret >= 0) {
390 pi->xact_addr_filt = ret;
391 ret = 0;
392 }
393 }
394 if (ret == 0)
395 ret = t4_link_start(pi->adapter, 0, pi->tx_chan, &pi->link_cfg);
396 if (ret == 0)
397 ret = t4_enable_vi(pi->adapter, 0, pi->viid, true, true);
398 return ret;
399 }
400
401 /*
402 * Response queue handler for the FW event queue.
403 */
404 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
405 const struct pkt_gl *gl)
406 {
407 u8 opcode = ((const struct rss_header *)rsp)->opcode;
408
409 rsp++; /* skip RSS header */
410 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
411 const struct cpl_sge_egr_update *p = (void *)rsp;
412 unsigned int qid = EGR_QID(ntohl(p->opcode_qid));
413 struct sge_txq *txq = q->adap->sge.egr_map[qid];
414
415 txq->restarts++;
416 if ((u8 *)txq < (u8 *)q->adap->sge.ethrxq) {
417 struct sge_eth_txq *eq;
418
419 eq = container_of(txq, struct sge_eth_txq, q);
420 netif_tx_wake_queue(eq->txq);
421 } else {
422 struct sge_ofld_txq *oq;
423
424 oq = container_of(txq, struct sge_ofld_txq, q);
425 tasklet_schedule(&oq->qresume_tsk);
426 }
427 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
428 const struct cpl_fw6_msg *p = (void *)rsp;
429
430 if (p->type == 0)
431 t4_handle_fw_rpl(q->adap, p->data);
432 } else if (opcode == CPL_L2T_WRITE_RPL) {
433 const struct cpl_l2t_write_rpl *p = (void *)rsp;
434
435 do_l2t_write_rpl(q->adap, p);
436 } else
437 dev_err(q->adap->pdev_dev,
438 "unexpected CPL %#x on FW event queue\n", opcode);
439 return 0;
440 }
441
442 /**
443 * uldrx_handler - response queue handler for ULD queues
444 * @q: the response queue that received the packet
445 * @rsp: the response queue descriptor holding the offload message
446 * @gl: the gather list of packet fragments
447 *
448 * Deliver an ingress offload packet to a ULD. All processing is done by
449 * the ULD, we just maintain statistics.
450 */
451 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
452 const struct pkt_gl *gl)
453 {
454 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
455
456 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
457 rxq->stats.nomem++;
458 return -1;
459 }
460 if (gl == NULL)
461 rxq->stats.imm++;
462 else if (gl == CXGB4_MSG_AN)
463 rxq->stats.an++;
464 else
465 rxq->stats.pkts++;
466 return 0;
467 }
468
469 static void disable_msi(struct adapter *adapter)
470 {
471 if (adapter->flags & USING_MSIX) {
472 pci_disable_msix(adapter->pdev);
473 adapter->flags &= ~USING_MSIX;
474 } else if (adapter->flags & USING_MSI) {
475 pci_disable_msi(adapter->pdev);
476 adapter->flags &= ~USING_MSI;
477 }
478 }
479
480 /*
481 * Interrupt handler for non-data events used with MSI-X.
482 */
483 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
484 {
485 struct adapter *adap = cookie;
486
487 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
488 if (v & PFSW) {
489 adap->swintr = 1;
490 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
491 }
492 t4_slow_intr_handler(adap);
493 return IRQ_HANDLED;
494 }
495
496 /*
497 * Name the MSI-X interrupts.
498 */
499 static void name_msix_vecs(struct adapter *adap)
500 {
501 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc) - 1;
502
503 /* non-data interrupts */
504 snprintf(adap->msix_info[0].desc, n, "%s", adap->name);
505 adap->msix_info[0].desc[n] = 0;
506
507 /* FW events */
508 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq", adap->name);
509 adap->msix_info[1].desc[n] = 0;
510
511 /* Ethernet queues */
512 for_each_port(adap, j) {
513 struct net_device *d = adap->port[j];
514 const struct port_info *pi = netdev_priv(d);
515
516 for (i = 0; i < pi->nqsets; i++, msi_idx++) {
517 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
518 d->name, i);
519 adap->msix_info[msi_idx].desc[n] = 0;
520 }
521 }
522
523 /* offload queues */
524 for_each_ofldrxq(&adap->sge, i) {
525 snprintf(adap->msix_info[msi_idx].desc, n, "%s-ofld%d",
526 adap->name, i);
527 adap->msix_info[msi_idx++].desc[n] = 0;
528 }
529 for_each_rdmarxq(&adap->sge, i) {
530 snprintf(adap->msix_info[msi_idx].desc, n, "%s-rdma%d",
531 adap->name, i);
532 adap->msix_info[msi_idx++].desc[n] = 0;
533 }
534 }
535
536 static int request_msix_queue_irqs(struct adapter *adap)
537 {
538 struct sge *s = &adap->sge;
539 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, msi = 2;
540
541 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
542 adap->msix_info[1].desc, &s->fw_evtq);
543 if (err)
544 return err;
545
546 for_each_ethrxq(s, ethqidx) {
547 err = request_irq(adap->msix_info[msi].vec, t4_sge_intr_msix, 0,
548 adap->msix_info[msi].desc,
549 &s->ethrxq[ethqidx].rspq);
550 if (err)
551 goto unwind;
552 msi++;
553 }
554 for_each_ofldrxq(s, ofldqidx) {
555 err = request_irq(adap->msix_info[msi].vec, t4_sge_intr_msix, 0,
556 adap->msix_info[msi].desc,
557 &s->ofldrxq[ofldqidx].rspq);
558 if (err)
559 goto unwind;
560 msi++;
561 }
562 for_each_rdmarxq(s, rdmaqidx) {
563 err = request_irq(adap->msix_info[msi].vec, t4_sge_intr_msix, 0,
564 adap->msix_info[msi].desc,
565 &s->rdmarxq[rdmaqidx].rspq);
566 if (err)
567 goto unwind;
568 msi++;
569 }
570 return 0;
571
572 unwind:
573 while (--rdmaqidx >= 0)
574 free_irq(adap->msix_info[--msi].vec,
575 &s->rdmarxq[rdmaqidx].rspq);
576 while (--ofldqidx >= 0)
577 free_irq(adap->msix_info[--msi].vec,
578 &s->ofldrxq[ofldqidx].rspq);
579 while (--ethqidx >= 0)
580 free_irq(adap->msix_info[--msi].vec, &s->ethrxq[ethqidx].rspq);
581 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
582 return err;
583 }
584
585 static void free_msix_queue_irqs(struct adapter *adap)
586 {
587 int i, msi = 2;
588 struct sge *s = &adap->sge;
589
590 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
591 for_each_ethrxq(s, i)
592 free_irq(adap->msix_info[msi++].vec, &s->ethrxq[i].rspq);
593 for_each_ofldrxq(s, i)
594 free_irq(adap->msix_info[msi++].vec, &s->ofldrxq[i].rspq);
595 for_each_rdmarxq(s, i)
596 free_irq(adap->msix_info[msi++].vec, &s->rdmarxq[i].rspq);
597 }
598
599 /**
600 * write_rss - write the RSS table for a given port
601 * @pi: the port
602 * @queues: array of queue indices for RSS
603 *
604 * Sets up the portion of the HW RSS table for the port's VI to distribute
605 * packets to the Rx queues in @queues.
606 */
607 static int write_rss(const struct port_info *pi, const u16 *queues)
608 {
609 u16 *rss;
610 int i, err;
611 const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
612
613 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
614 if (!rss)
615 return -ENOMEM;
616
617 /* map the queue indices to queue ids */
618 for (i = 0; i < pi->rss_size; i++, queues++)
619 rss[i] = q[*queues].rspq.abs_id;
620
621 err = t4_config_rss_range(pi->adapter, 0, pi->viid, 0, pi->rss_size,
622 rss, pi->rss_size);
623 kfree(rss);
624 return err;
625 }
626
627 /**
628 * setup_rss - configure RSS
629 * @adap: the adapter
630 *
631 * Sets up RSS for each port.
632 */
633 static int setup_rss(struct adapter *adap)
634 {
635 int i, err;
636
637 for_each_port(adap, i) {
638 const struct port_info *pi = adap2pinfo(adap, i);
639
640 err = write_rss(pi, pi->rss);
641 if (err)
642 return err;
643 }
644 return 0;
645 }
646
647 /*
648 * Wait until all NAPI handlers are descheduled.
649 */
650 static void quiesce_rx(struct adapter *adap)
651 {
652 int i;
653
654 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
655 struct sge_rspq *q = adap->sge.ingr_map[i];
656
657 if (q && q->handler)
658 napi_disable(&q->napi);
659 }
660 }
661
662 /*
663 * Enable NAPI scheduling and interrupt generation for all Rx queues.
664 */
665 static void enable_rx(struct adapter *adap)
666 {
667 int i;
668
669 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
670 struct sge_rspq *q = adap->sge.ingr_map[i];
671
672 if (!q)
673 continue;
674 if (q->handler)
675 napi_enable(&q->napi);
676 /* 0-increment GTS to start the timer and enable interrupts */
677 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
678 SEINTARM(q->intr_params) |
679 INGRESSQID(q->cntxt_id));
680 }
681 }
682
683 /**
684 * setup_sge_queues - configure SGE Tx/Rx/response queues
685 * @adap: the adapter
686 *
687 * Determines how many sets of SGE queues to use and initializes them.
688 * We support multiple queue sets per port if we have MSI-X, otherwise
689 * just one queue set per port.
690 */
691 static int setup_sge_queues(struct adapter *adap)
692 {
693 int err, msi_idx, i, j;
694 struct sge *s = &adap->sge;
695
696 bitmap_zero(s->starving_fl, MAX_EGRQ);
697 bitmap_zero(s->txq_maperr, MAX_EGRQ);
698
699 if (adap->flags & USING_MSIX)
700 msi_idx = 1; /* vector 0 is for non-queue interrupts */
701 else {
702 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
703 NULL, NULL);
704 if (err)
705 return err;
706 msi_idx = -((int)s->intrq.abs_id + 1);
707 }
708
709 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
710 msi_idx, NULL, fwevtq_handler);
711 if (err) {
712 freeout: t4_free_sge_resources(adap);
713 return err;
714 }
715
716 for_each_port(adap, i) {
717 struct net_device *dev = adap->port[i];
718 struct port_info *pi = netdev_priv(dev);
719 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
720 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
721
722 for (j = 0; j < pi->nqsets; j++, q++) {
723 if (msi_idx > 0)
724 msi_idx++;
725 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
726 msi_idx, &q->fl,
727 t4_ethrx_handler);
728 if (err)
729 goto freeout;
730 q->rspq.idx = j;
731 memset(&q->stats, 0, sizeof(q->stats));
732 }
733 for (j = 0; j < pi->nqsets; j++, t++) {
734 err = t4_sge_alloc_eth_txq(adap, t, dev,
735 netdev_get_tx_queue(dev, j),
736 s->fw_evtq.cntxt_id);
737 if (err)
738 goto freeout;
739 }
740 }
741
742 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
743 for_each_ofldrxq(s, i) {
744 struct sge_ofld_rxq *q = &s->ofldrxq[i];
745 struct net_device *dev = adap->port[i / j];
746
747 if (msi_idx > 0)
748 msi_idx++;
749 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, msi_idx,
750 &q->fl, uldrx_handler);
751 if (err)
752 goto freeout;
753 memset(&q->stats, 0, sizeof(q->stats));
754 s->ofld_rxq[i] = q->rspq.abs_id;
755 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], dev,
756 s->fw_evtq.cntxt_id);
757 if (err)
758 goto freeout;
759 }
760
761 for_each_rdmarxq(s, i) {
762 struct sge_ofld_rxq *q = &s->rdmarxq[i];
763
764 if (msi_idx > 0)
765 msi_idx++;
766 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
767 msi_idx, &q->fl, uldrx_handler);
768 if (err)
769 goto freeout;
770 memset(&q->stats, 0, sizeof(q->stats));
771 s->rdma_rxq[i] = q->rspq.abs_id;
772 }
773
774 for_each_port(adap, i) {
775 /*
776 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
777 * have RDMA queues, and that's the right value.
778 */
779 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
780 s->fw_evtq.cntxt_id,
781 s->rdmarxq[i].rspq.cntxt_id);
782 if (err)
783 goto freeout;
784 }
785
786 t4_write_reg(adap, MPS_TRC_RSS_CONTROL,
787 RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
788 QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
789 return 0;
790 }
791
792 /*
793 * Returns 0 if new FW was successfully loaded, a positive errno if a load was
794 * started but failed, and a negative errno if flash load couldn't start.
795 */
796 static int upgrade_fw(struct adapter *adap)
797 {
798 int ret;
799 u32 vers;
800 const struct fw_hdr *hdr;
801 const struct firmware *fw;
802 struct device *dev = adap->pdev_dev;
803
804 ret = request_firmware(&fw, FW_FNAME, dev);
805 if (ret < 0) {
806 dev_err(dev, "unable to load firmware image " FW_FNAME
807 ", error %d\n", ret);
808 return ret;
809 }
810
811 hdr = (const struct fw_hdr *)fw->data;
812 vers = ntohl(hdr->fw_ver);
813 if (FW_HDR_FW_VER_MAJOR_GET(vers) != FW_VERSION_MAJOR) {
814 ret = -EINVAL; /* wrong major version, won't do */
815 goto out;
816 }
817
818 /*
819 * If the flash FW is unusable or we found something newer, load it.
820 */
821 if (FW_HDR_FW_VER_MAJOR_GET(adap->params.fw_vers) != FW_VERSION_MAJOR ||
822 vers > adap->params.fw_vers) {
823 ret = -t4_load_fw(adap, fw->data, fw->size);
824 if (!ret)
825 dev_info(dev, "firmware upgraded to version %pI4 from "
826 FW_FNAME "\n", &hdr->fw_ver);
827 }
828 out: release_firmware(fw);
829 return ret;
830 }
831
832 /*
833 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
834 * The allocated memory is cleared.
835 */
836 void *t4_alloc_mem(size_t size)
837 {
838 void *p = kmalloc(size, GFP_KERNEL);
839
840 if (!p)
841 p = vmalloc(size);
842 if (p)
843 memset(p, 0, size);
844 return p;
845 }
846
847 /*
848 * Free memory allocated through alloc_mem().
849 */
850 void t4_free_mem(void *addr)
851 {
852 if (is_vmalloc_addr(addr))
853 vfree(addr);
854 else
855 kfree(addr);
856 }
857
858 static inline int is_offload(const struct adapter *adap)
859 {
860 return adap->params.offload;
861 }
862
863 /*
864 * Implementation of ethtool operations.
865 */
866
867 static u32 get_msglevel(struct net_device *dev)
868 {
869 return netdev2adap(dev)->msg_enable;
870 }
871
872 static void set_msglevel(struct net_device *dev, u32 val)
873 {
874 netdev2adap(dev)->msg_enable = val;
875 }
876
877 static char stats_strings[][ETH_GSTRING_LEN] = {
878 "TxOctetsOK ",
879 "TxFramesOK ",
880 "TxBroadcastFrames ",
881 "TxMulticastFrames ",
882 "TxUnicastFrames ",
883 "TxErrorFrames ",
884
885 "TxFrames64 ",
886 "TxFrames65To127 ",
887 "TxFrames128To255 ",
888 "TxFrames256To511 ",
889 "TxFrames512To1023 ",
890 "TxFrames1024To1518 ",
891 "TxFrames1519ToMax ",
892
893 "TxFramesDropped ",
894 "TxPauseFrames ",
895 "TxPPP0Frames ",
896 "TxPPP1Frames ",
897 "TxPPP2Frames ",
898 "TxPPP3Frames ",
899 "TxPPP4Frames ",
900 "TxPPP5Frames ",
901 "TxPPP6Frames ",
902 "TxPPP7Frames ",
903
904 "RxOctetsOK ",
905 "RxFramesOK ",
906 "RxBroadcastFrames ",
907 "RxMulticastFrames ",
908 "RxUnicastFrames ",
909
910 "RxFramesTooLong ",
911 "RxJabberErrors ",
912 "RxFCSErrors ",
913 "RxLengthErrors ",
914 "RxSymbolErrors ",
915 "RxRuntFrames ",
916
917 "RxFrames64 ",
918 "RxFrames65To127 ",
919 "RxFrames128To255 ",
920 "RxFrames256To511 ",
921 "RxFrames512To1023 ",
922 "RxFrames1024To1518 ",
923 "RxFrames1519ToMax ",
924
925 "RxPauseFrames ",
926 "RxPPP0Frames ",
927 "RxPPP1Frames ",
928 "RxPPP2Frames ",
929 "RxPPP3Frames ",
930 "RxPPP4Frames ",
931 "RxPPP5Frames ",
932 "RxPPP6Frames ",
933 "RxPPP7Frames ",
934
935 "RxBG0FramesDropped ",
936 "RxBG1FramesDropped ",
937 "RxBG2FramesDropped ",
938 "RxBG3FramesDropped ",
939 "RxBG0FramesTrunc ",
940 "RxBG1FramesTrunc ",
941 "RxBG2FramesTrunc ",
942 "RxBG3FramesTrunc ",
943
944 "TSO ",
945 "TxCsumOffload ",
946 "RxCsumGood ",
947 "VLANextractions ",
948 "VLANinsertions ",
949 "GROpackets ",
950 "GROmerged ",
951 };
952
953 static int get_sset_count(struct net_device *dev, int sset)
954 {
955 switch (sset) {
956 case ETH_SS_STATS:
957 return ARRAY_SIZE(stats_strings);
958 default:
959 return -EOPNOTSUPP;
960 }
961 }
962
963 #define T4_REGMAP_SIZE (160 * 1024)
964
965 static int get_regs_len(struct net_device *dev)
966 {
967 return T4_REGMAP_SIZE;
968 }
969
970 static int get_eeprom_len(struct net_device *dev)
971 {
972 return EEPROMSIZE;
973 }
974
975 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
976 {
977 struct adapter *adapter = netdev2adap(dev);
978
979 strcpy(info->driver, KBUILD_MODNAME);
980 strcpy(info->version, DRV_VERSION);
981 strcpy(info->bus_info, pci_name(adapter->pdev));
982
983 if (!adapter->params.fw_vers)
984 strcpy(info->fw_version, "N/A");
985 else
986 snprintf(info->fw_version, sizeof(info->fw_version),
987 "%u.%u.%u.%u, TP %u.%u.%u.%u",
988 FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers),
989 FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers),
990 FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers),
991 FW_HDR_FW_VER_BUILD_GET(adapter->params.fw_vers),
992 FW_HDR_FW_VER_MAJOR_GET(adapter->params.tp_vers),
993 FW_HDR_FW_VER_MINOR_GET(adapter->params.tp_vers),
994 FW_HDR_FW_VER_MICRO_GET(adapter->params.tp_vers),
995 FW_HDR_FW_VER_BUILD_GET(adapter->params.tp_vers));
996 }
997
998 static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
999 {
1000 if (stringset == ETH_SS_STATS)
1001 memcpy(data, stats_strings, sizeof(stats_strings));
1002 }
1003
1004 /*
1005 * port stats maintained per queue of the port. They should be in the same
1006 * order as in stats_strings above.
1007 */
1008 struct queue_port_stats {
1009 u64 tso;
1010 u64 tx_csum;
1011 u64 rx_csum;
1012 u64 vlan_ex;
1013 u64 vlan_ins;
1014 u64 gro_pkts;
1015 u64 gro_merged;
1016 };
1017
1018 static void collect_sge_port_stats(const struct adapter *adap,
1019 const struct port_info *p, struct queue_port_stats *s)
1020 {
1021 int i;
1022 const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
1023 const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
1024
1025 memset(s, 0, sizeof(*s));
1026 for (i = 0; i < p->nqsets; i++, rx++, tx++) {
1027 s->tso += tx->tso;
1028 s->tx_csum += tx->tx_cso;
1029 s->rx_csum += rx->stats.rx_cso;
1030 s->vlan_ex += rx->stats.vlan_ex;
1031 s->vlan_ins += tx->vlan_ins;
1032 s->gro_pkts += rx->stats.lro_pkts;
1033 s->gro_merged += rx->stats.lro_merged;
1034 }
1035 }
1036
1037 static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1038 u64 *data)
1039 {
1040 struct port_info *pi = netdev_priv(dev);
1041 struct adapter *adapter = pi->adapter;
1042
1043 t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data);
1044
1045 data += sizeof(struct port_stats) / sizeof(u64);
1046 collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
1047 }
1048
1049 /*
1050 * Return a version number to identify the type of adapter. The scheme is:
1051 * - bits 0..9: chip version
1052 * - bits 10..15: chip revision
1053 */
1054 static inline unsigned int mk_adap_vers(const struct adapter *ap)
1055 {
1056 return 4 | (ap->params.rev << 10);
1057 }
1058
1059 static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
1060 unsigned int end)
1061 {
1062 u32 *p = buf + start;
1063
1064 for ( ; start <= end; start += sizeof(u32))
1065 *p++ = t4_read_reg(ap, start);
1066 }
1067
1068 static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1069 void *buf)
1070 {
1071 static const unsigned int reg_ranges[] = {
1072 0x1008, 0x1108,
1073 0x1180, 0x11b4,
1074 0x11fc, 0x123c,
1075 0x1300, 0x173c,
1076 0x1800, 0x18fc,
1077 0x3000, 0x30d8,
1078 0x30e0, 0x5924,
1079 0x5960, 0x59d4,
1080 0x5a00, 0x5af8,
1081 0x6000, 0x6098,
1082 0x6100, 0x6150,
1083 0x6200, 0x6208,
1084 0x6240, 0x6248,
1085 0x6280, 0x6338,
1086 0x6370, 0x638c,
1087 0x6400, 0x643c,
1088 0x6500, 0x6524,
1089 0x6a00, 0x6a38,
1090 0x6a60, 0x6a78,
1091 0x6b00, 0x6b84,
1092 0x6bf0, 0x6c84,
1093 0x6cf0, 0x6d84,
1094 0x6df0, 0x6e84,
1095 0x6ef0, 0x6f84,
1096 0x6ff0, 0x7084,
1097 0x70f0, 0x7184,
1098 0x71f0, 0x7284,
1099 0x72f0, 0x7384,
1100 0x73f0, 0x7450,
1101 0x7500, 0x7530,
1102 0x7600, 0x761c,
1103 0x7680, 0x76cc,
1104 0x7700, 0x7798,
1105 0x77c0, 0x77fc,
1106 0x7900, 0x79fc,
1107 0x7b00, 0x7c38,
1108 0x7d00, 0x7efc,
1109 0x8dc0, 0x8e1c,
1110 0x8e30, 0x8e78,
1111 0x8ea0, 0x8f6c,
1112 0x8fc0, 0x9074,
1113 0x90fc, 0x90fc,
1114 0x9400, 0x9458,
1115 0x9600, 0x96bc,
1116 0x9800, 0x9808,
1117 0x9820, 0x983c,
1118 0x9850, 0x9864,
1119 0x9c00, 0x9c6c,
1120 0x9c80, 0x9cec,
1121 0x9d00, 0x9d6c,
1122 0x9d80, 0x9dec,
1123 0x9e00, 0x9e6c,
1124 0x9e80, 0x9eec,
1125 0x9f00, 0x9f6c,
1126 0x9f80, 0x9fec,
1127 0xd004, 0xd03c,
1128 0xdfc0, 0xdfe0,
1129 0xe000, 0xea7c,
1130 0xf000, 0x11190,
1131 0x19040, 0x19124,
1132 0x19150, 0x191b0,
1133 0x191d0, 0x191e8,
1134 0x19238, 0x1924c,
1135 0x193f8, 0x19474,
1136 0x19490, 0x194f8,
1137 0x19800, 0x19f30,
1138 0x1a000, 0x1a06c,
1139 0x1a0b0, 0x1a120,
1140 0x1a128, 0x1a138,
1141 0x1a190, 0x1a1c4,
1142 0x1a1fc, 0x1a1fc,
1143 0x1e040, 0x1e04c,
1144 0x1e240, 0x1e28c,
1145 0x1e2c0, 0x1e2c0,
1146 0x1e2e0, 0x1e2e0,
1147 0x1e300, 0x1e384,
1148 0x1e3c0, 0x1e3c8,
1149 0x1e440, 0x1e44c,
1150 0x1e640, 0x1e68c,
1151 0x1e6c0, 0x1e6c0,
1152 0x1e6e0, 0x1e6e0,
1153 0x1e700, 0x1e784,
1154 0x1e7c0, 0x1e7c8,
1155 0x1e840, 0x1e84c,
1156 0x1ea40, 0x1ea8c,
1157 0x1eac0, 0x1eac0,
1158 0x1eae0, 0x1eae0,
1159 0x1eb00, 0x1eb84,
1160 0x1ebc0, 0x1ebc8,
1161 0x1ec40, 0x1ec4c,
1162 0x1ee40, 0x1ee8c,
1163 0x1eec0, 0x1eec0,
1164 0x1eee0, 0x1eee0,
1165 0x1ef00, 0x1ef84,
1166 0x1efc0, 0x1efc8,
1167 0x1f040, 0x1f04c,
1168 0x1f240, 0x1f28c,
1169 0x1f2c0, 0x1f2c0,
1170 0x1f2e0, 0x1f2e0,
1171 0x1f300, 0x1f384,
1172 0x1f3c0, 0x1f3c8,
1173 0x1f440, 0x1f44c,
1174 0x1f640, 0x1f68c,
1175 0x1f6c0, 0x1f6c0,
1176 0x1f6e0, 0x1f6e0,
1177 0x1f700, 0x1f784,
1178 0x1f7c0, 0x1f7c8,
1179 0x1f840, 0x1f84c,
1180 0x1fa40, 0x1fa8c,
1181 0x1fac0, 0x1fac0,
1182 0x1fae0, 0x1fae0,
1183 0x1fb00, 0x1fb84,
1184 0x1fbc0, 0x1fbc8,
1185 0x1fc40, 0x1fc4c,
1186 0x1fe40, 0x1fe8c,
1187 0x1fec0, 0x1fec0,
1188 0x1fee0, 0x1fee0,
1189 0x1ff00, 0x1ff84,
1190 0x1ffc0, 0x1ffc8,
1191 0x20000, 0x2002c,
1192 0x20100, 0x2013c,
1193 0x20190, 0x201c8,
1194 0x20200, 0x20318,
1195 0x20400, 0x20528,
1196 0x20540, 0x20614,
1197 0x21000, 0x21040,
1198 0x2104c, 0x21060,
1199 0x210c0, 0x210ec,
1200 0x21200, 0x21268,
1201 0x21270, 0x21284,
1202 0x212fc, 0x21388,
1203 0x21400, 0x21404,
1204 0x21500, 0x21518,
1205 0x2152c, 0x2153c,
1206 0x21550, 0x21554,
1207 0x21600, 0x21600,
1208 0x21608, 0x21628,
1209 0x21630, 0x2163c,
1210 0x21700, 0x2171c,
1211 0x21780, 0x2178c,
1212 0x21800, 0x21c38,
1213 0x21c80, 0x21d7c,
1214 0x21e00, 0x21e04,
1215 0x22000, 0x2202c,
1216 0x22100, 0x2213c,
1217 0x22190, 0x221c8,
1218 0x22200, 0x22318,
1219 0x22400, 0x22528,
1220 0x22540, 0x22614,
1221 0x23000, 0x23040,
1222 0x2304c, 0x23060,
1223 0x230c0, 0x230ec,
1224 0x23200, 0x23268,
1225 0x23270, 0x23284,
1226 0x232fc, 0x23388,
1227 0x23400, 0x23404,
1228 0x23500, 0x23518,
1229 0x2352c, 0x2353c,
1230 0x23550, 0x23554,
1231 0x23600, 0x23600,
1232 0x23608, 0x23628,
1233 0x23630, 0x2363c,
1234 0x23700, 0x2371c,
1235 0x23780, 0x2378c,
1236 0x23800, 0x23c38,
1237 0x23c80, 0x23d7c,
1238 0x23e00, 0x23e04,
1239 0x24000, 0x2402c,
1240 0x24100, 0x2413c,
1241 0x24190, 0x241c8,
1242 0x24200, 0x24318,
1243 0x24400, 0x24528,
1244 0x24540, 0x24614,
1245 0x25000, 0x25040,
1246 0x2504c, 0x25060,
1247 0x250c0, 0x250ec,
1248 0x25200, 0x25268,
1249 0x25270, 0x25284,
1250 0x252fc, 0x25388,
1251 0x25400, 0x25404,
1252 0x25500, 0x25518,
1253 0x2552c, 0x2553c,
1254 0x25550, 0x25554,
1255 0x25600, 0x25600,
1256 0x25608, 0x25628,
1257 0x25630, 0x2563c,
1258 0x25700, 0x2571c,
1259 0x25780, 0x2578c,
1260 0x25800, 0x25c38,
1261 0x25c80, 0x25d7c,
1262 0x25e00, 0x25e04,
1263 0x26000, 0x2602c,
1264 0x26100, 0x2613c,
1265 0x26190, 0x261c8,
1266 0x26200, 0x26318,
1267 0x26400, 0x26528,
1268 0x26540, 0x26614,
1269 0x27000, 0x27040,
1270 0x2704c, 0x27060,
1271 0x270c0, 0x270ec,
1272 0x27200, 0x27268,
1273 0x27270, 0x27284,
1274 0x272fc, 0x27388,
1275 0x27400, 0x27404,
1276 0x27500, 0x27518,
1277 0x2752c, 0x2753c,
1278 0x27550, 0x27554,
1279 0x27600, 0x27600,
1280 0x27608, 0x27628,
1281 0x27630, 0x2763c,
1282 0x27700, 0x2771c,
1283 0x27780, 0x2778c,
1284 0x27800, 0x27c38,
1285 0x27c80, 0x27d7c,
1286 0x27e00, 0x27e04
1287 };
1288
1289 int i;
1290 struct adapter *ap = netdev2adap(dev);
1291
1292 regs->version = mk_adap_vers(ap);
1293
1294 memset(buf, 0, T4_REGMAP_SIZE);
1295 for (i = 0; i < ARRAY_SIZE(reg_ranges); i += 2)
1296 reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]);
1297 }
1298
1299 static int restart_autoneg(struct net_device *dev)
1300 {
1301 struct port_info *p = netdev_priv(dev);
1302
1303 if (!netif_running(dev))
1304 return -EAGAIN;
1305 if (p->link_cfg.autoneg != AUTONEG_ENABLE)
1306 return -EINVAL;
1307 t4_restart_aneg(p->adapter, 0, p->tx_chan);
1308 return 0;
1309 }
1310
1311 static int identify_port(struct net_device *dev, u32 data)
1312 {
1313 if (data == 0)
1314 data = 2; /* default to 2 seconds */
1315
1316 return t4_identify_port(netdev2adap(dev), 0, netdev2pinfo(dev)->viid,
1317 data * 5);
1318 }
1319
1320 static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
1321 {
1322 unsigned int v = 0;
1323
1324 if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XFI ||
1325 type == FW_PORT_TYPE_BT_XAUI) {
1326 v |= SUPPORTED_TP;
1327 if (caps & FW_PORT_CAP_SPEED_100M)
1328 v |= SUPPORTED_100baseT_Full;
1329 if (caps & FW_PORT_CAP_SPEED_1G)
1330 v |= SUPPORTED_1000baseT_Full;
1331 if (caps & FW_PORT_CAP_SPEED_10G)
1332 v |= SUPPORTED_10000baseT_Full;
1333 } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
1334 v |= SUPPORTED_Backplane;
1335 if (caps & FW_PORT_CAP_SPEED_1G)
1336 v |= SUPPORTED_1000baseKX_Full;
1337 if (caps & FW_PORT_CAP_SPEED_10G)
1338 v |= SUPPORTED_10000baseKX4_Full;
1339 } else if (type == FW_PORT_TYPE_KR)
1340 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
1341 else if (type == FW_PORT_TYPE_BP_AP)
1342 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC;
1343 else if (type == FW_PORT_TYPE_FIBER_XFI ||
1344 type == FW_PORT_TYPE_FIBER_XAUI || type == FW_PORT_TYPE_SFP)
1345 v |= SUPPORTED_FIBRE;
1346
1347 if (caps & FW_PORT_CAP_ANEG)
1348 v |= SUPPORTED_Autoneg;
1349 return v;
1350 }
1351
1352 static unsigned int to_fw_linkcaps(unsigned int caps)
1353 {
1354 unsigned int v = 0;
1355
1356 if (caps & ADVERTISED_100baseT_Full)
1357 v |= FW_PORT_CAP_SPEED_100M;
1358 if (caps & ADVERTISED_1000baseT_Full)
1359 v |= FW_PORT_CAP_SPEED_1G;
1360 if (caps & ADVERTISED_10000baseT_Full)
1361 v |= FW_PORT_CAP_SPEED_10G;
1362 return v;
1363 }
1364
1365 static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1366 {
1367 const struct port_info *p = netdev_priv(dev);
1368
1369 if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
1370 p->port_type == FW_PORT_TYPE_BT_XFI ||
1371 p->port_type == FW_PORT_TYPE_BT_XAUI)
1372 cmd->port = PORT_TP;
1373 else if (p->port_type == FW_PORT_TYPE_FIBER_XFI ||
1374 p->port_type == FW_PORT_TYPE_FIBER_XAUI)
1375 cmd->port = PORT_FIBRE;
1376 else if (p->port_type == FW_PORT_TYPE_SFP) {
1377 if (p->mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
1378 p->mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
1379 cmd->port = PORT_DA;
1380 else
1381 cmd->port = PORT_FIBRE;
1382 } else
1383 cmd->port = PORT_OTHER;
1384
1385 if (p->mdio_addr >= 0) {
1386 cmd->phy_address = p->mdio_addr;
1387 cmd->transceiver = XCVR_EXTERNAL;
1388 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
1389 MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
1390 } else {
1391 cmd->phy_address = 0; /* not really, but no better option */
1392 cmd->transceiver = XCVR_INTERNAL;
1393 cmd->mdio_support = 0;
1394 }
1395
1396 cmd->supported = from_fw_linkcaps(p->port_type, p->link_cfg.supported);
1397 cmd->advertising = from_fw_linkcaps(p->port_type,
1398 p->link_cfg.advertising);
1399 cmd->speed = netif_carrier_ok(dev) ? p->link_cfg.speed : 0;
1400 cmd->duplex = DUPLEX_FULL;
1401 cmd->autoneg = p->link_cfg.autoneg;
1402 cmd->maxtxpkt = 0;
1403 cmd->maxrxpkt = 0;
1404 return 0;
1405 }
1406
1407 static unsigned int speed_to_caps(int speed)
1408 {
1409 if (speed == SPEED_100)
1410 return FW_PORT_CAP_SPEED_100M;
1411 if (speed == SPEED_1000)
1412 return FW_PORT_CAP_SPEED_1G;
1413 if (speed == SPEED_10000)
1414 return FW_PORT_CAP_SPEED_10G;
1415 return 0;
1416 }
1417
1418 static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1419 {
1420 unsigned int cap;
1421 struct port_info *p = netdev_priv(dev);
1422 struct link_config *lc = &p->link_cfg;
1423
1424 if (cmd->duplex != DUPLEX_FULL) /* only full-duplex supported */
1425 return -EINVAL;
1426
1427 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
1428 /*
1429 * PHY offers a single speed. See if that's what's
1430 * being requested.
1431 */
1432 if (cmd->autoneg == AUTONEG_DISABLE &&
1433 (lc->supported & speed_to_caps(cmd->speed)))
1434 return 0;
1435 return -EINVAL;
1436 }
1437
1438 if (cmd->autoneg == AUTONEG_DISABLE) {
1439 cap = speed_to_caps(cmd->speed);
1440
1441 if (!(lc->supported & cap) || cmd->speed == SPEED_1000 ||
1442 cmd->speed == SPEED_10000)
1443 return -EINVAL;
1444 lc->requested_speed = cap;
1445 lc->advertising = 0;
1446 } else {
1447 cap = to_fw_linkcaps(cmd->advertising);
1448 if (!(lc->supported & cap))
1449 return -EINVAL;
1450 lc->requested_speed = 0;
1451 lc->advertising = cap | FW_PORT_CAP_ANEG;
1452 }
1453 lc->autoneg = cmd->autoneg;
1454
1455 if (netif_running(dev))
1456 return t4_link_start(p->adapter, 0, p->tx_chan, lc);
1457 return 0;
1458 }
1459
1460 static void get_pauseparam(struct net_device *dev,
1461 struct ethtool_pauseparam *epause)
1462 {
1463 struct port_info *p = netdev_priv(dev);
1464
1465 epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
1466 epause->rx_pause = (p->link_cfg.fc & PAUSE_RX) != 0;
1467 epause->tx_pause = (p->link_cfg.fc & PAUSE_TX) != 0;
1468 }
1469
1470 static int set_pauseparam(struct net_device *dev,
1471 struct ethtool_pauseparam *epause)
1472 {
1473 struct port_info *p = netdev_priv(dev);
1474 struct link_config *lc = &p->link_cfg;
1475
1476 if (epause->autoneg == AUTONEG_DISABLE)
1477 lc->requested_fc = 0;
1478 else if (lc->supported & FW_PORT_CAP_ANEG)
1479 lc->requested_fc = PAUSE_AUTONEG;
1480 else
1481 return -EINVAL;
1482
1483 if (epause->rx_pause)
1484 lc->requested_fc |= PAUSE_RX;
1485 if (epause->tx_pause)
1486 lc->requested_fc |= PAUSE_TX;
1487 if (netif_running(dev))
1488 return t4_link_start(p->adapter, 0, p->tx_chan, lc);
1489 return 0;
1490 }
1491
1492 static u32 get_rx_csum(struct net_device *dev)
1493 {
1494 struct port_info *p = netdev_priv(dev);
1495
1496 return p->rx_offload & RX_CSO;
1497 }
1498
1499 static int set_rx_csum(struct net_device *dev, u32 data)
1500 {
1501 struct port_info *p = netdev_priv(dev);
1502
1503 if (data)
1504 p->rx_offload |= RX_CSO;
1505 else
1506 p->rx_offload &= ~RX_CSO;
1507 return 0;
1508 }
1509
1510 static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1511 {
1512 const struct port_info *pi = netdev_priv(dev);
1513 const struct sge *s = &pi->adapter->sge;
1514
1515 e->rx_max_pending = MAX_RX_BUFFERS;
1516 e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
1517 e->rx_jumbo_max_pending = 0;
1518 e->tx_max_pending = MAX_TXQ_ENTRIES;
1519
1520 e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
1521 e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
1522 e->rx_jumbo_pending = 0;
1523 e->tx_pending = s->ethtxq[pi->first_qset].q.size;
1524 }
1525
1526 static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1527 {
1528 int i;
1529 const struct port_info *pi = netdev_priv(dev);
1530 struct adapter *adapter = pi->adapter;
1531 struct sge *s = &adapter->sge;
1532
1533 if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
1534 e->tx_pending > MAX_TXQ_ENTRIES ||
1535 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
1536 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
1537 e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
1538 return -EINVAL;
1539
1540 if (adapter->flags & FULL_INIT_DONE)
1541 return -EBUSY;
1542
1543 for (i = 0; i < pi->nqsets; ++i) {
1544 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
1545 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
1546 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
1547 }
1548 return 0;
1549 }
1550
1551 static int closest_timer(const struct sge *s, int time)
1552 {
1553 int i, delta, match = 0, min_delta = INT_MAX;
1554
1555 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1556 delta = time - s->timer_val[i];
1557 if (delta < 0)
1558 delta = -delta;
1559 if (delta < min_delta) {
1560 min_delta = delta;
1561 match = i;
1562 }
1563 }
1564 return match;
1565 }
1566
1567 static int closest_thres(const struct sge *s, int thres)
1568 {
1569 int i, delta, match = 0, min_delta = INT_MAX;
1570
1571 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1572 delta = thres - s->counter_val[i];
1573 if (delta < 0)
1574 delta = -delta;
1575 if (delta < min_delta) {
1576 min_delta = delta;
1577 match = i;
1578 }
1579 }
1580 return match;
1581 }
1582
1583 /*
1584 * Return a queue's interrupt hold-off time in us. 0 means no timer.
1585 */
1586 static unsigned int qtimer_val(const struct adapter *adap,
1587 const struct sge_rspq *q)
1588 {
1589 unsigned int idx = q->intr_params >> 1;
1590
1591 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1592 }
1593
1594 /**
1595 * set_rxq_intr_params - set a queue's interrupt holdoff parameters
1596 * @adap: the adapter
1597 * @q: the Rx queue
1598 * @us: the hold-off time in us, or 0 to disable timer
1599 * @cnt: the hold-off packet count, or 0 to disable counter
1600 *
1601 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1602 * one of the two needs to be enabled for the queue to generate interrupts.
1603 */
1604 static int set_rxq_intr_params(struct adapter *adap, struct sge_rspq *q,
1605 unsigned int us, unsigned int cnt)
1606 {
1607 if ((us | cnt) == 0)
1608 cnt = 1;
1609
1610 if (cnt) {
1611 int err;
1612 u32 v, new_idx;
1613
1614 new_idx = closest_thres(&adap->sge, cnt);
1615 if (q->desc && q->pktcnt_idx != new_idx) {
1616 /* the queue has already been created, update it */
1617 v = FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
1618 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1619 FW_PARAMS_PARAM_YZ(q->cntxt_id);
1620 err = t4_set_params(adap, 0, 0, 0, 1, &v, &new_idx);
1621 if (err)
1622 return err;
1623 }
1624 q->pktcnt_idx = new_idx;
1625 }
1626
1627 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1628 q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
1629 return 0;
1630 }
1631
1632 static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1633 {
1634 const struct port_info *pi = netdev_priv(dev);
1635 struct adapter *adap = pi->adapter;
1636
1637 return set_rxq_intr_params(adap, &adap->sge.ethrxq[pi->first_qset].rspq,
1638 c->rx_coalesce_usecs, c->rx_max_coalesced_frames);
1639 }
1640
1641 static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1642 {
1643 const struct port_info *pi = netdev_priv(dev);
1644 const struct adapter *adap = pi->adapter;
1645 const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
1646
1647 c->rx_coalesce_usecs = qtimer_val(adap, rq);
1648 c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN) ?
1649 adap->sge.counter_val[rq->pktcnt_idx] : 0;
1650 return 0;
1651 }
1652
1653 /*
1654 * Translate a physical EEPROM address to virtual. The first 1K is accessed
1655 * through virtual addresses starting at 31K, the rest is accessed through
1656 * virtual addresses starting at 0. This mapping is correct only for PF0.
1657 */
1658 static int eeprom_ptov(unsigned int phys_addr)
1659 {
1660 if (phys_addr < 1024)
1661 return phys_addr + (31 << 10);
1662 if (phys_addr < EEPROMSIZE)
1663 return phys_addr - 1024;
1664 return -EINVAL;
1665 }
1666
1667 /*
1668 * The next two routines implement eeprom read/write from physical addresses.
1669 * The physical->virtual translation is correct only for PF0.
1670 */
1671 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
1672 {
1673 int vaddr = eeprom_ptov(phys_addr);
1674
1675 if (vaddr >= 0)
1676 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
1677 return vaddr < 0 ? vaddr : 0;
1678 }
1679
1680 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
1681 {
1682 int vaddr = eeprom_ptov(phys_addr);
1683
1684 if (vaddr >= 0)
1685 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
1686 return vaddr < 0 ? vaddr : 0;
1687 }
1688
1689 #define EEPROM_MAGIC 0x38E2F10C
1690
1691 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
1692 u8 *data)
1693 {
1694 int i, err = 0;
1695 struct adapter *adapter = netdev2adap(dev);
1696
1697 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
1698 if (!buf)
1699 return -ENOMEM;
1700
1701 e->magic = EEPROM_MAGIC;
1702 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
1703 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
1704
1705 if (!err)
1706 memcpy(data, buf + e->offset, e->len);
1707 kfree(buf);
1708 return err;
1709 }
1710
1711 static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
1712 u8 *data)
1713 {
1714 u8 *buf;
1715 int err = 0;
1716 u32 aligned_offset, aligned_len, *p;
1717 struct adapter *adapter = netdev2adap(dev);
1718
1719 if (eeprom->magic != EEPROM_MAGIC)
1720 return -EINVAL;
1721
1722 aligned_offset = eeprom->offset & ~3;
1723 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
1724
1725 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
1726 /*
1727 * RMW possibly needed for first or last words.
1728 */
1729 buf = kmalloc(aligned_len, GFP_KERNEL);
1730 if (!buf)
1731 return -ENOMEM;
1732 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1733 if (!err && aligned_len > 4)
1734 err = eeprom_rd_phys(adapter,
1735 aligned_offset + aligned_len - 4,
1736 (u32 *)&buf[aligned_len - 4]);
1737 if (err)
1738 goto out;
1739 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
1740 } else
1741 buf = data;
1742
1743 err = t4_seeprom_wp(adapter, false);
1744 if (err)
1745 goto out;
1746
1747 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1748 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1749 aligned_offset += 4;
1750 }
1751
1752 if (!err)
1753 err = t4_seeprom_wp(adapter, true);
1754 out:
1755 if (buf != data)
1756 kfree(buf);
1757 return err;
1758 }
1759
1760 static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
1761 {
1762 int ret;
1763 const struct firmware *fw;
1764 struct adapter *adap = netdev2adap(netdev);
1765
1766 ef->data[sizeof(ef->data) - 1] = '\0';
1767 ret = request_firmware(&fw, ef->data, adap->pdev_dev);
1768 if (ret < 0)
1769 return ret;
1770
1771 ret = t4_load_fw(adap, fw->data, fw->size);
1772 release_firmware(fw);
1773 if (!ret)
1774 dev_info(adap->pdev_dev, "loaded firmware %s\n", ef->data);
1775 return ret;
1776 }
1777
1778 #define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
1779 #define BCAST_CRC 0xa0ccc1a6
1780
1781 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1782 {
1783 wol->supported = WAKE_BCAST | WAKE_MAGIC;
1784 wol->wolopts = netdev2adap(dev)->wol;
1785 memset(&wol->sopass, 0, sizeof(wol->sopass));
1786 }
1787
1788 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1789 {
1790 int err = 0;
1791 struct port_info *pi = netdev_priv(dev);
1792
1793 if (wol->wolopts & ~WOL_SUPPORTED)
1794 return -EINVAL;
1795 t4_wol_magic_enable(pi->adapter, pi->tx_chan,
1796 (wol->wolopts & WAKE_MAGIC) ? dev->dev_addr : NULL);
1797 if (wol->wolopts & WAKE_BCAST) {
1798 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0xfe, ~0ULL,
1799 ~0ULL, 0, false);
1800 if (!err)
1801 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 1,
1802 ~6ULL, ~0ULL, BCAST_CRC, true);
1803 } else
1804 t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0, 0, 0, 0, false);
1805 return err;
1806 }
1807
1808 static int set_tso(struct net_device *dev, u32 value)
1809 {
1810 if (value)
1811 dev->features |= NETIF_F_TSO | NETIF_F_TSO6;
1812 else
1813 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
1814 return 0;
1815 }
1816
1817 static int set_flags(struct net_device *dev, u32 flags)
1818 {
1819 return ethtool_op_set_flags(dev, flags, ETH_FLAG_RXHASH);
1820 }
1821
1822 static int get_rss_table(struct net_device *dev, struct ethtool_rxfh_indir *p)
1823 {
1824 const struct port_info *pi = netdev_priv(dev);
1825 unsigned int n = min_t(unsigned int, p->size, pi->rss_size);
1826
1827 p->size = pi->rss_size;
1828 while (n--)
1829 p->ring_index[n] = pi->rss[n];
1830 return 0;
1831 }
1832
1833 static int set_rss_table(struct net_device *dev,
1834 const struct ethtool_rxfh_indir *p)
1835 {
1836 unsigned int i;
1837 struct port_info *pi = netdev_priv(dev);
1838
1839 if (p->size != pi->rss_size)
1840 return -EINVAL;
1841 for (i = 0; i < p->size; i++)
1842 if (p->ring_index[i] >= pi->nqsets)
1843 return -EINVAL;
1844 for (i = 0; i < p->size; i++)
1845 pi->rss[i] = p->ring_index[i];
1846 if (pi->adapter->flags & FULL_INIT_DONE)
1847 return write_rss(pi, pi->rss);
1848 return 0;
1849 }
1850
1851 static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
1852 void *rules)
1853 {
1854 const struct port_info *pi = netdev_priv(dev);
1855
1856 switch (info->cmd) {
1857 case ETHTOOL_GRXFH: {
1858 unsigned int v = pi->rss_mode;
1859
1860 info->data = 0;
1861 switch (info->flow_type) {
1862 case TCP_V4_FLOW:
1863 if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
1864 info->data = RXH_IP_SRC | RXH_IP_DST |
1865 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1866 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1867 info->data = RXH_IP_SRC | RXH_IP_DST;
1868 break;
1869 case UDP_V4_FLOW:
1870 if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) &&
1871 (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
1872 info->data = RXH_IP_SRC | RXH_IP_DST |
1873 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1874 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1875 info->data = RXH_IP_SRC | RXH_IP_DST;
1876 break;
1877 case SCTP_V4_FLOW:
1878 case AH_ESP_V4_FLOW:
1879 case IPV4_FLOW:
1880 if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
1881 info->data = RXH_IP_SRC | RXH_IP_DST;
1882 break;
1883 case TCP_V6_FLOW:
1884 if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
1885 info->data = RXH_IP_SRC | RXH_IP_DST |
1886 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1887 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1888 info->data = RXH_IP_SRC | RXH_IP_DST;
1889 break;
1890 case UDP_V6_FLOW:
1891 if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) &&
1892 (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
1893 info->data = RXH_IP_SRC | RXH_IP_DST |
1894 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1895 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1896 info->data = RXH_IP_SRC | RXH_IP_DST;
1897 break;
1898 case SCTP_V6_FLOW:
1899 case AH_ESP_V6_FLOW:
1900 case IPV6_FLOW:
1901 if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
1902 info->data = RXH_IP_SRC | RXH_IP_DST;
1903 break;
1904 }
1905 return 0;
1906 }
1907 case ETHTOOL_GRXRINGS:
1908 info->data = pi->nqsets;
1909 return 0;
1910 }
1911 return -EOPNOTSUPP;
1912 }
1913
1914 static struct ethtool_ops cxgb_ethtool_ops = {
1915 .get_settings = get_settings,
1916 .set_settings = set_settings,
1917 .get_drvinfo = get_drvinfo,
1918 .get_msglevel = get_msglevel,
1919 .set_msglevel = set_msglevel,
1920 .get_ringparam = get_sge_param,
1921 .set_ringparam = set_sge_param,
1922 .get_coalesce = get_coalesce,
1923 .set_coalesce = set_coalesce,
1924 .get_eeprom_len = get_eeprom_len,
1925 .get_eeprom = get_eeprom,
1926 .set_eeprom = set_eeprom,
1927 .get_pauseparam = get_pauseparam,
1928 .set_pauseparam = set_pauseparam,
1929 .get_rx_csum = get_rx_csum,
1930 .set_rx_csum = set_rx_csum,
1931 .set_tx_csum = ethtool_op_set_tx_ipv6_csum,
1932 .set_sg = ethtool_op_set_sg,
1933 .get_link = ethtool_op_get_link,
1934 .get_strings = get_strings,
1935 .phys_id = identify_port,
1936 .nway_reset = restart_autoneg,
1937 .get_sset_count = get_sset_count,
1938 .get_ethtool_stats = get_stats,
1939 .get_regs_len = get_regs_len,
1940 .get_regs = get_regs,
1941 .get_wol = get_wol,
1942 .set_wol = set_wol,
1943 .set_tso = set_tso,
1944 .set_flags = set_flags,
1945 .get_rxnfc = get_rxnfc,
1946 .get_rxfh_indir = get_rss_table,
1947 .set_rxfh_indir = set_rss_table,
1948 .flash_device = set_flash,
1949 };
1950
1951 /*
1952 * debugfs support
1953 */
1954
1955 static int mem_open(struct inode *inode, struct file *file)
1956 {
1957 file->private_data = inode->i_private;
1958 return 0;
1959 }
1960
1961 static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
1962 loff_t *ppos)
1963 {
1964 loff_t pos = *ppos;
1965 loff_t avail = file->f_path.dentry->d_inode->i_size;
1966 unsigned int mem = (uintptr_t)file->private_data & 3;
1967 struct adapter *adap = file->private_data - mem;
1968
1969 if (pos < 0)
1970 return -EINVAL;
1971 if (pos >= avail)
1972 return 0;
1973 if (count > avail - pos)
1974 count = avail - pos;
1975
1976 while (count) {
1977 size_t len;
1978 int ret, ofst;
1979 __be32 data[16];
1980
1981 if (mem == MEM_MC)
1982 ret = t4_mc_read(adap, pos, data, NULL);
1983 else
1984 ret = t4_edc_read(adap, mem, pos, data, NULL);
1985 if (ret)
1986 return ret;
1987
1988 ofst = pos % sizeof(data);
1989 len = min(count, sizeof(data) - ofst);
1990 if (copy_to_user(buf, (u8 *)data + ofst, len))
1991 return -EFAULT;
1992
1993 buf += len;
1994 pos += len;
1995 count -= len;
1996 }
1997 count = pos - *ppos;
1998 *ppos = pos;
1999 return count;
2000 }
2001
2002 static const struct file_operations mem_debugfs_fops = {
2003 .owner = THIS_MODULE,
2004 .open = mem_open,
2005 .read = mem_read,
2006 };
2007
2008 static void __devinit add_debugfs_mem(struct adapter *adap, const char *name,
2009 unsigned int idx, unsigned int size_mb)
2010 {
2011 struct dentry *de;
2012
2013 de = debugfs_create_file(name, S_IRUSR, adap->debugfs_root,
2014 (void *)adap + idx, &mem_debugfs_fops);
2015 if (de && de->d_inode)
2016 de->d_inode->i_size = size_mb << 20;
2017 }
2018
2019 static int __devinit setup_debugfs(struct adapter *adap)
2020 {
2021 int i;
2022
2023 if (IS_ERR_OR_NULL(adap->debugfs_root))
2024 return -1;
2025
2026 i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE);
2027 if (i & EDRAM0_ENABLE)
2028 add_debugfs_mem(adap, "edc0", MEM_EDC0, 5);
2029 if (i & EDRAM1_ENABLE)
2030 add_debugfs_mem(adap, "edc1", MEM_EDC1, 5);
2031 if (i & EXT_MEM_ENABLE)
2032 add_debugfs_mem(adap, "mc", MEM_MC,
2033 EXT_MEM_SIZE_GET(t4_read_reg(adap, MA_EXT_MEMORY_BAR)));
2034 if (adap->l2t)
2035 debugfs_create_file("l2t", S_IRUSR, adap->debugfs_root, adap,
2036 &t4_l2t_fops);
2037 return 0;
2038 }
2039
2040 /*
2041 * upper-layer driver support
2042 */
2043
2044 /*
2045 * Allocate an active-open TID and set it to the supplied value.
2046 */
2047 int cxgb4_alloc_atid(struct tid_info *t, void *data)
2048 {
2049 int atid = -1;
2050
2051 spin_lock_bh(&t->atid_lock);
2052 if (t->afree) {
2053 union aopen_entry *p = t->afree;
2054
2055 atid = p - t->atid_tab;
2056 t->afree = p->next;
2057 p->data = data;
2058 t->atids_in_use++;
2059 }
2060 spin_unlock_bh(&t->atid_lock);
2061 return atid;
2062 }
2063 EXPORT_SYMBOL(cxgb4_alloc_atid);
2064
2065 /*
2066 * Release an active-open TID.
2067 */
2068 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
2069 {
2070 union aopen_entry *p = &t->atid_tab[atid];
2071
2072 spin_lock_bh(&t->atid_lock);
2073 p->next = t->afree;
2074 t->afree = p;
2075 t->atids_in_use--;
2076 spin_unlock_bh(&t->atid_lock);
2077 }
2078 EXPORT_SYMBOL(cxgb4_free_atid);
2079
2080 /*
2081 * Allocate a server TID and set it to the supplied value.
2082 */
2083 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
2084 {
2085 int stid;
2086
2087 spin_lock_bh(&t->stid_lock);
2088 if (family == PF_INET) {
2089 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
2090 if (stid < t->nstids)
2091 __set_bit(stid, t->stid_bmap);
2092 else
2093 stid = -1;
2094 } else {
2095 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
2096 if (stid < 0)
2097 stid = -1;
2098 }
2099 if (stid >= 0) {
2100 t->stid_tab[stid].data = data;
2101 stid += t->stid_base;
2102 t->stids_in_use++;
2103 }
2104 spin_unlock_bh(&t->stid_lock);
2105 return stid;
2106 }
2107 EXPORT_SYMBOL(cxgb4_alloc_stid);
2108
2109 /*
2110 * Release a server TID.
2111 */
2112 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
2113 {
2114 stid -= t->stid_base;
2115 spin_lock_bh(&t->stid_lock);
2116 if (family == PF_INET)
2117 __clear_bit(stid, t->stid_bmap);
2118 else
2119 bitmap_release_region(t->stid_bmap, stid, 2);
2120 t->stid_tab[stid].data = NULL;
2121 t->stids_in_use--;
2122 spin_unlock_bh(&t->stid_lock);
2123 }
2124 EXPORT_SYMBOL(cxgb4_free_stid);
2125
2126 /*
2127 * Populate a TID_RELEASE WR. Caller must properly size the skb.
2128 */
2129 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
2130 unsigned int tid)
2131 {
2132 struct cpl_tid_release *req;
2133
2134 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
2135 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
2136 INIT_TP_WR(req, tid);
2137 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
2138 }
2139
2140 /*
2141 * Queue a TID release request and if necessary schedule a work queue to
2142 * process it.
2143 */
2144 void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
2145 unsigned int tid)
2146 {
2147 void **p = &t->tid_tab[tid];
2148 struct adapter *adap = container_of(t, struct adapter, tids);
2149
2150 spin_lock_bh(&adap->tid_release_lock);
2151 *p = adap->tid_release_head;
2152 /* Low 2 bits encode the Tx channel number */
2153 adap->tid_release_head = (void **)((uintptr_t)p | chan);
2154 if (!adap->tid_release_task_busy) {
2155 adap->tid_release_task_busy = true;
2156 schedule_work(&adap->tid_release_task);
2157 }
2158 spin_unlock_bh(&adap->tid_release_lock);
2159 }
2160 EXPORT_SYMBOL(cxgb4_queue_tid_release);
2161
2162 /*
2163 * Process the list of pending TID release requests.
2164 */
2165 static void process_tid_release_list(struct work_struct *work)
2166 {
2167 struct sk_buff *skb;
2168 struct adapter *adap;
2169
2170 adap = container_of(work, struct adapter, tid_release_task);
2171
2172 spin_lock_bh(&adap->tid_release_lock);
2173 while (adap->tid_release_head) {
2174 void **p = adap->tid_release_head;
2175 unsigned int chan = (uintptr_t)p & 3;
2176 p = (void *)p - chan;
2177
2178 adap->tid_release_head = *p;
2179 *p = NULL;
2180 spin_unlock_bh(&adap->tid_release_lock);
2181
2182 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
2183 GFP_KERNEL)))
2184 schedule_timeout_uninterruptible(1);
2185
2186 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
2187 t4_ofld_send(adap, skb);
2188 spin_lock_bh(&adap->tid_release_lock);
2189 }
2190 adap->tid_release_task_busy = false;
2191 spin_unlock_bh(&adap->tid_release_lock);
2192 }
2193
2194 /*
2195 * Release a TID and inform HW. If we are unable to allocate the release
2196 * message we defer to a work queue.
2197 */
2198 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
2199 {
2200 void *old;
2201 struct sk_buff *skb;
2202 struct adapter *adap = container_of(t, struct adapter, tids);
2203
2204 old = t->tid_tab[tid];
2205 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
2206 if (likely(skb)) {
2207 t->tid_tab[tid] = NULL;
2208 mk_tid_release(skb, chan, tid);
2209 t4_ofld_send(adap, skb);
2210 } else
2211 cxgb4_queue_tid_release(t, chan, tid);
2212 if (old)
2213 atomic_dec(&t->tids_in_use);
2214 }
2215 EXPORT_SYMBOL(cxgb4_remove_tid);
2216
2217 /*
2218 * Allocate and initialize the TID tables. Returns 0 on success.
2219 */
2220 static int tid_init(struct tid_info *t)
2221 {
2222 size_t size;
2223 unsigned int natids = t->natids;
2224
2225 size = t->ntids * sizeof(*t->tid_tab) + natids * sizeof(*t->atid_tab) +
2226 t->nstids * sizeof(*t->stid_tab) +
2227 BITS_TO_LONGS(t->nstids) * sizeof(long);
2228 t->tid_tab = t4_alloc_mem(size);
2229 if (!t->tid_tab)
2230 return -ENOMEM;
2231
2232 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
2233 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
2234 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids];
2235 spin_lock_init(&t->stid_lock);
2236 spin_lock_init(&t->atid_lock);
2237
2238 t->stids_in_use = 0;
2239 t->afree = NULL;
2240 t->atids_in_use = 0;
2241 atomic_set(&t->tids_in_use, 0);
2242
2243 /* Setup the free list for atid_tab and clear the stid bitmap. */
2244 if (natids) {
2245 while (--natids)
2246 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
2247 t->afree = t->atid_tab;
2248 }
2249 bitmap_zero(t->stid_bmap, t->nstids);
2250 return 0;
2251 }
2252
2253 /**
2254 * cxgb4_create_server - create an IP server
2255 * @dev: the device
2256 * @stid: the server TID
2257 * @sip: local IP address to bind server to
2258 * @sport: the server's TCP port
2259 * @queue: queue to direct messages from this server to
2260 *
2261 * Create an IP server for the given port and address.
2262 * Returns <0 on error and one of the %NET_XMIT_* values on success.
2263 */
2264 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
2265 __be32 sip, __be16 sport, unsigned int queue)
2266 {
2267 unsigned int chan;
2268 struct sk_buff *skb;
2269 struct adapter *adap;
2270 struct cpl_pass_open_req *req;
2271
2272 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
2273 if (!skb)
2274 return -ENOMEM;
2275
2276 adap = netdev2adap(dev);
2277 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
2278 INIT_TP_WR(req, 0);
2279 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
2280 req->local_port = sport;
2281 req->peer_port = htons(0);
2282 req->local_ip = sip;
2283 req->peer_ip = htonl(0);
2284 chan = netdev2pinfo(adap->sge.ingr_map[queue]->netdev)->tx_chan;
2285 req->opt0 = cpu_to_be64(TX_CHAN(chan));
2286 req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
2287 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
2288 return t4_mgmt_tx(adap, skb);
2289 }
2290 EXPORT_SYMBOL(cxgb4_create_server);
2291
2292 /**
2293 * cxgb4_create_server6 - create an IPv6 server
2294 * @dev: the device
2295 * @stid: the server TID
2296 * @sip: local IPv6 address to bind server to
2297 * @sport: the server's TCP port
2298 * @queue: queue to direct messages from this server to
2299 *
2300 * Create an IPv6 server for the given port and address.
2301 * Returns <0 on error and one of the %NET_XMIT_* values on success.
2302 */
2303 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
2304 const struct in6_addr *sip, __be16 sport,
2305 unsigned int queue)
2306 {
2307 unsigned int chan;
2308 struct sk_buff *skb;
2309 struct adapter *adap;
2310 struct cpl_pass_open_req6 *req;
2311
2312 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
2313 if (!skb)
2314 return -ENOMEM;
2315
2316 adap = netdev2adap(dev);
2317 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
2318 INIT_TP_WR(req, 0);
2319 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
2320 req->local_port = sport;
2321 req->peer_port = htons(0);
2322 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
2323 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
2324 req->peer_ip_hi = cpu_to_be64(0);
2325 req->peer_ip_lo = cpu_to_be64(0);
2326 chan = netdev2pinfo(adap->sge.ingr_map[queue]->netdev)->tx_chan;
2327 req->opt0 = cpu_to_be64(TX_CHAN(chan));
2328 req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
2329 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
2330 return t4_mgmt_tx(adap, skb);
2331 }
2332 EXPORT_SYMBOL(cxgb4_create_server6);
2333
2334 /**
2335 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
2336 * @mtus: the HW MTU table
2337 * @mtu: the target MTU
2338 * @idx: index of selected entry in the MTU table
2339 *
2340 * Returns the index and the value in the HW MTU table that is closest to
2341 * but does not exceed @mtu, unless @mtu is smaller than any value in the
2342 * table, in which case that smallest available value is selected.
2343 */
2344 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
2345 unsigned int *idx)
2346 {
2347 unsigned int i = 0;
2348
2349 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
2350 ++i;
2351 if (idx)
2352 *idx = i;
2353 return mtus[i];
2354 }
2355 EXPORT_SYMBOL(cxgb4_best_mtu);
2356
2357 /**
2358 * cxgb4_port_chan - get the HW channel of a port
2359 * @dev: the net device for the port
2360 *
2361 * Return the HW Tx channel of the given port.
2362 */
2363 unsigned int cxgb4_port_chan(const struct net_device *dev)
2364 {
2365 return netdev2pinfo(dev)->tx_chan;
2366 }
2367 EXPORT_SYMBOL(cxgb4_port_chan);
2368
2369 /**
2370 * cxgb4_port_viid - get the VI id of a port
2371 * @dev: the net device for the port
2372 *
2373 * Return the VI id of the given port.
2374 */
2375 unsigned int cxgb4_port_viid(const struct net_device *dev)
2376 {
2377 return netdev2pinfo(dev)->viid;
2378 }
2379 EXPORT_SYMBOL(cxgb4_port_viid);
2380
2381 /**
2382 * cxgb4_port_idx - get the index of a port
2383 * @dev: the net device for the port
2384 *
2385 * Return the index of the given port.
2386 */
2387 unsigned int cxgb4_port_idx(const struct net_device *dev)
2388 {
2389 return netdev2pinfo(dev)->port_id;
2390 }
2391 EXPORT_SYMBOL(cxgb4_port_idx);
2392
2393 /**
2394 * cxgb4_netdev_by_hwid - return the net device of a HW port
2395 * @pdev: identifies the adapter
2396 * @id: the HW port id
2397 *
2398 * Return the net device associated with the interface with the given HW
2399 * id.
2400 */
2401 struct net_device *cxgb4_netdev_by_hwid(struct pci_dev *pdev, unsigned int id)
2402 {
2403 const struct adapter *adap = pci_get_drvdata(pdev);
2404
2405 if (!adap || id >= NCHAN)
2406 return NULL;
2407 id = adap->chan_map[id];
2408 return id < MAX_NPORTS ? adap->port[id] : NULL;
2409 }
2410 EXPORT_SYMBOL(cxgb4_netdev_by_hwid);
2411
2412 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
2413 struct tp_tcp_stats *v6)
2414 {
2415 struct adapter *adap = pci_get_drvdata(pdev);
2416
2417 spin_lock(&adap->stats_lock);
2418 t4_tp_get_tcp_stats(adap, v4, v6);
2419 spin_unlock(&adap->stats_lock);
2420 }
2421 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
2422
2423 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
2424 const unsigned int *pgsz_order)
2425 {
2426 struct adapter *adap = netdev2adap(dev);
2427
2428 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask);
2429 t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) |
2430 HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) |
2431 HPZ3(pgsz_order[3]));
2432 }
2433 EXPORT_SYMBOL(cxgb4_iscsi_init);
2434
2435 static struct pci_driver cxgb4_driver;
2436
2437 static void check_neigh_update(struct neighbour *neigh)
2438 {
2439 const struct device *parent;
2440 const struct net_device *netdev = neigh->dev;
2441
2442 if (netdev->priv_flags & IFF_802_1Q_VLAN)
2443 netdev = vlan_dev_real_dev(netdev);
2444 parent = netdev->dev.parent;
2445 if (parent && parent->driver == &cxgb4_driver.driver)
2446 t4_l2t_update(dev_get_drvdata(parent), neigh);
2447 }
2448
2449 static int netevent_cb(struct notifier_block *nb, unsigned long event,
2450 void *data)
2451 {
2452 switch (event) {
2453 case NETEVENT_NEIGH_UPDATE:
2454 check_neigh_update(data);
2455 break;
2456 case NETEVENT_PMTU_UPDATE:
2457 case NETEVENT_REDIRECT:
2458 default:
2459 break;
2460 }
2461 return 0;
2462 }
2463
2464 static bool netevent_registered;
2465 static struct notifier_block cxgb4_netevent_nb = {
2466 .notifier_call = netevent_cb
2467 };
2468
2469 static void uld_attach(struct adapter *adap, unsigned int uld)
2470 {
2471 void *handle;
2472 struct cxgb4_lld_info lli;
2473
2474 lli.pdev = adap->pdev;
2475 lli.l2t = adap->l2t;
2476 lli.tids = &adap->tids;
2477 lli.ports = adap->port;
2478 lli.vr = &adap->vres;
2479 lli.mtus = adap->params.mtus;
2480 if (uld == CXGB4_ULD_RDMA) {
2481 lli.rxq_ids = adap->sge.rdma_rxq;
2482 lli.nrxq = adap->sge.rdmaqs;
2483 } else if (uld == CXGB4_ULD_ISCSI) {
2484 lli.rxq_ids = adap->sge.ofld_rxq;
2485 lli.nrxq = adap->sge.ofldqsets;
2486 }
2487 lli.ntxq = adap->sge.ofldqsets;
2488 lli.nchan = adap->params.nports;
2489 lli.nports = adap->params.nports;
2490 lli.wr_cred = adap->params.ofldq_wr_cred;
2491 lli.adapter_type = adap->params.rev;
2492 lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
2493 lli.udb_density = 1 << QUEUESPERPAGEPF0_GET(
2494 t4_read_reg(adap, SGE_EGRESS_QUEUES_PER_PAGE_PF));
2495 lli.ucq_density = 1 << QUEUESPERPAGEPF0_GET(
2496 t4_read_reg(adap, SGE_INGRESS_QUEUES_PER_PAGE_PF));
2497 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
2498 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
2499 lli.fw_vers = adap->params.fw_vers;
2500
2501 handle = ulds[uld].add(&lli);
2502 if (IS_ERR(handle)) {
2503 dev_warn(adap->pdev_dev,
2504 "could not attach to the %s driver, error %ld\n",
2505 uld_str[uld], PTR_ERR(handle));
2506 return;
2507 }
2508
2509 adap->uld_handle[uld] = handle;
2510
2511 if (!netevent_registered) {
2512 register_netevent_notifier(&cxgb4_netevent_nb);
2513 netevent_registered = true;
2514 }
2515
2516 if (adap->flags & FULL_INIT_DONE)
2517 ulds[uld].state_change(handle, CXGB4_STATE_UP);
2518 }
2519
2520 static void attach_ulds(struct adapter *adap)
2521 {
2522 unsigned int i;
2523
2524 mutex_lock(&uld_mutex);
2525 list_add_tail(&adap->list_node, &adapter_list);
2526 for (i = 0; i < CXGB4_ULD_MAX; i++)
2527 if (ulds[i].add)
2528 uld_attach(adap, i);
2529 mutex_unlock(&uld_mutex);
2530 }
2531
2532 static void detach_ulds(struct adapter *adap)
2533 {
2534 unsigned int i;
2535
2536 mutex_lock(&uld_mutex);
2537 list_del(&adap->list_node);
2538 for (i = 0; i < CXGB4_ULD_MAX; i++)
2539 if (adap->uld_handle[i]) {
2540 ulds[i].state_change(adap->uld_handle[i],
2541 CXGB4_STATE_DETACH);
2542 adap->uld_handle[i] = NULL;
2543 }
2544 if (netevent_registered && list_empty(&adapter_list)) {
2545 unregister_netevent_notifier(&cxgb4_netevent_nb);
2546 netevent_registered = false;
2547 }
2548 mutex_unlock(&uld_mutex);
2549 }
2550
2551 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2552 {
2553 unsigned int i;
2554
2555 mutex_lock(&uld_mutex);
2556 for (i = 0; i < CXGB4_ULD_MAX; i++)
2557 if (adap->uld_handle[i])
2558 ulds[i].state_change(adap->uld_handle[i], new_state);
2559 mutex_unlock(&uld_mutex);
2560 }
2561
2562 /**
2563 * cxgb4_register_uld - register an upper-layer driver
2564 * @type: the ULD type
2565 * @p: the ULD methods
2566 *
2567 * Registers an upper-layer driver with this driver and notifies the ULD
2568 * about any presently available devices that support its type. Returns
2569 * %-EBUSY if a ULD of the same type is already registered.
2570 */
2571 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
2572 {
2573 int ret = 0;
2574 struct adapter *adap;
2575
2576 if (type >= CXGB4_ULD_MAX)
2577 return -EINVAL;
2578 mutex_lock(&uld_mutex);
2579 if (ulds[type].add) {
2580 ret = -EBUSY;
2581 goto out;
2582 }
2583 ulds[type] = *p;
2584 list_for_each_entry(adap, &adapter_list, list_node)
2585 uld_attach(adap, type);
2586 out: mutex_unlock(&uld_mutex);
2587 return ret;
2588 }
2589 EXPORT_SYMBOL(cxgb4_register_uld);
2590
2591 /**
2592 * cxgb4_unregister_uld - unregister an upper-layer driver
2593 * @type: the ULD type
2594 *
2595 * Unregisters an existing upper-layer driver.
2596 */
2597 int cxgb4_unregister_uld(enum cxgb4_uld type)
2598 {
2599 struct adapter *adap;
2600
2601 if (type >= CXGB4_ULD_MAX)
2602 return -EINVAL;
2603 mutex_lock(&uld_mutex);
2604 list_for_each_entry(adap, &adapter_list, list_node)
2605 adap->uld_handle[type] = NULL;
2606 ulds[type].add = NULL;
2607 mutex_unlock(&uld_mutex);
2608 return 0;
2609 }
2610 EXPORT_SYMBOL(cxgb4_unregister_uld);
2611
2612 /**
2613 * cxgb_up - enable the adapter
2614 * @adap: adapter being enabled
2615 *
2616 * Called when the first port is enabled, this function performs the
2617 * actions necessary to make an adapter operational, such as completing
2618 * the initialization of HW modules, and enabling interrupts.
2619 *
2620 * Must be called with the rtnl lock held.
2621 */
2622 static int cxgb_up(struct adapter *adap)
2623 {
2624 int err;
2625
2626 err = setup_sge_queues(adap);
2627 if (err)
2628 goto out;
2629 err = setup_rss(adap);
2630 if (err)
2631 goto freeq;
2632
2633 if (adap->flags & USING_MSIX) {
2634 name_msix_vecs(adap);
2635 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2636 adap->msix_info[0].desc, adap);
2637 if (err)
2638 goto irq_err;
2639
2640 err = request_msix_queue_irqs(adap);
2641 if (err) {
2642 free_irq(adap->msix_info[0].vec, adap);
2643 goto irq_err;
2644 }
2645 } else {
2646 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2647 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
2648 adap->name, adap);
2649 if (err)
2650 goto irq_err;
2651 }
2652 enable_rx(adap);
2653 t4_sge_start(adap);
2654 t4_intr_enable(adap);
2655 adap->flags |= FULL_INIT_DONE;
2656 notify_ulds(adap, CXGB4_STATE_UP);
2657 out:
2658 return err;
2659 irq_err:
2660 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2661 freeq:
2662 t4_free_sge_resources(adap);
2663 goto out;
2664 }
2665
2666 static void cxgb_down(struct adapter *adapter)
2667 {
2668 t4_intr_disable(adapter);
2669 cancel_work_sync(&adapter->tid_release_task);
2670 adapter->tid_release_task_busy = false;
2671 adapter->tid_release_head = NULL;
2672
2673 if (adapter->flags & USING_MSIX) {
2674 free_msix_queue_irqs(adapter);
2675 free_irq(adapter->msix_info[0].vec, adapter);
2676 } else
2677 free_irq(adapter->pdev->irq, adapter);
2678 quiesce_rx(adapter);
2679 t4_sge_stop(adapter);
2680 t4_free_sge_resources(adapter);
2681 adapter->flags &= ~FULL_INIT_DONE;
2682 }
2683
2684 /*
2685 * net_device operations
2686 */
2687 static int cxgb_open(struct net_device *dev)
2688 {
2689 int err;
2690 struct port_info *pi = netdev_priv(dev);
2691 struct adapter *adapter = pi->adapter;
2692
2693 if (!(adapter->flags & FULL_INIT_DONE)) {
2694 err = cxgb_up(adapter);
2695 if (err < 0)
2696 return err;
2697 }
2698
2699 dev->real_num_tx_queues = pi->nqsets;
2700 err = link_start(dev);
2701 if (!err)
2702 netif_tx_start_all_queues(dev);
2703 return err;
2704 }
2705
2706 static int cxgb_close(struct net_device *dev)
2707 {
2708 struct port_info *pi = netdev_priv(dev);
2709 struct adapter *adapter = pi->adapter;
2710
2711 netif_tx_stop_all_queues(dev);
2712 netif_carrier_off(dev);
2713 return t4_enable_vi(adapter, 0, pi->viid, false, false);
2714 }
2715
2716 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
2717 struct rtnl_link_stats64 *ns)
2718 {
2719 struct port_stats stats;
2720 struct port_info *p = netdev_priv(dev);
2721 struct adapter *adapter = p->adapter;
2722
2723 spin_lock(&adapter->stats_lock);
2724 t4_get_port_stats(adapter, p->tx_chan, &stats);
2725 spin_unlock(&adapter->stats_lock);
2726
2727 ns->tx_bytes = stats.tx_octets;
2728 ns->tx_packets = stats.tx_frames;
2729 ns->rx_bytes = stats.rx_octets;
2730 ns->rx_packets = stats.rx_frames;
2731 ns->multicast = stats.rx_mcast_frames;
2732
2733 /* detailed rx_errors */
2734 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2735 stats.rx_runt;
2736 ns->rx_over_errors = 0;
2737 ns->rx_crc_errors = stats.rx_fcs_err;
2738 ns->rx_frame_errors = stats.rx_symbol_err;
2739 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
2740 stats.rx_ovflow2 + stats.rx_ovflow3 +
2741 stats.rx_trunc0 + stats.rx_trunc1 +
2742 stats.rx_trunc2 + stats.rx_trunc3;
2743 ns->rx_missed_errors = 0;
2744
2745 /* detailed tx_errors */
2746 ns->tx_aborted_errors = 0;
2747 ns->tx_carrier_errors = 0;
2748 ns->tx_fifo_errors = 0;
2749 ns->tx_heartbeat_errors = 0;
2750 ns->tx_window_errors = 0;
2751
2752 ns->tx_errors = stats.tx_error_frames;
2753 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2754 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2755 return ns;
2756 }
2757
2758 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2759 {
2760 int ret = 0, prtad, devad;
2761 struct port_info *pi = netdev_priv(dev);
2762 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2763
2764 switch (cmd) {
2765 case SIOCGMIIPHY:
2766 if (pi->mdio_addr < 0)
2767 return -EOPNOTSUPP;
2768 data->phy_id = pi->mdio_addr;
2769 break;
2770 case SIOCGMIIREG:
2771 case SIOCSMIIREG:
2772 if (mdio_phy_id_is_c45(data->phy_id)) {
2773 prtad = mdio_phy_id_prtad(data->phy_id);
2774 devad = mdio_phy_id_devad(data->phy_id);
2775 } else if (data->phy_id < 32) {
2776 prtad = data->phy_id;
2777 devad = 0;
2778 data->reg_num &= 0x1f;
2779 } else
2780 return -EINVAL;
2781
2782 if (cmd == SIOCGMIIREG)
2783 ret = t4_mdio_rd(pi->adapter, 0, prtad, devad,
2784 data->reg_num, &data->val_out);
2785 else
2786 ret = t4_mdio_wr(pi->adapter, 0, prtad, devad,
2787 data->reg_num, data->val_in);
2788 break;
2789 default:
2790 return -EOPNOTSUPP;
2791 }
2792 return ret;
2793 }
2794
2795 static void cxgb_set_rxmode(struct net_device *dev)
2796 {
2797 /* unfortunately we can't return errors to the stack */
2798 set_rxmode(dev, -1, false);
2799 }
2800
2801 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2802 {
2803 int ret;
2804 struct port_info *pi = netdev_priv(dev);
2805
2806 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
2807 return -EINVAL;
2808 ret = t4_set_rxmode(pi->adapter, 0, pi->viid, new_mtu, -1, -1, -1, -1,
2809 true);
2810 if (!ret)
2811 dev->mtu = new_mtu;
2812 return ret;
2813 }
2814
2815 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2816 {
2817 int ret;
2818 struct sockaddr *addr = p;
2819 struct port_info *pi = netdev_priv(dev);
2820
2821 if (!is_valid_ether_addr(addr->sa_data))
2822 return -EINVAL;
2823
2824 ret = t4_change_mac(pi->adapter, 0, pi->viid, pi->xact_addr_filt,
2825 addr->sa_data, true, true);
2826 if (ret < 0)
2827 return ret;
2828
2829 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2830 pi->xact_addr_filt = ret;
2831 return 0;
2832 }
2833
2834 static void vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2835 {
2836 struct port_info *pi = netdev_priv(dev);
2837
2838 pi->vlan_grp = grp;
2839 t4_set_rxmode(pi->adapter, 0, pi->viid, -1, -1, -1, -1, grp != NULL,
2840 true);
2841 }
2842
2843 #ifdef CONFIG_NET_POLL_CONTROLLER
2844 static void cxgb_netpoll(struct net_device *dev)
2845 {
2846 struct port_info *pi = netdev_priv(dev);
2847 struct adapter *adap = pi->adapter;
2848
2849 if (adap->flags & USING_MSIX) {
2850 int i;
2851 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
2852
2853 for (i = pi->nqsets; i; i--, rx++)
2854 t4_sge_intr_msix(0, &rx->rspq);
2855 } else
2856 t4_intr_handler(adap)(0, adap);
2857 }
2858 #endif
2859
2860 static const struct net_device_ops cxgb4_netdev_ops = {
2861 .ndo_open = cxgb_open,
2862 .ndo_stop = cxgb_close,
2863 .ndo_start_xmit = t4_eth_xmit,
2864 .ndo_get_stats64 = cxgb_get_stats,
2865 .ndo_set_rx_mode = cxgb_set_rxmode,
2866 .ndo_set_mac_address = cxgb_set_mac_addr,
2867 .ndo_validate_addr = eth_validate_addr,
2868 .ndo_do_ioctl = cxgb_ioctl,
2869 .ndo_change_mtu = cxgb_change_mtu,
2870 .ndo_vlan_rx_register = vlan_rx_register,
2871 #ifdef CONFIG_NET_POLL_CONTROLLER
2872 .ndo_poll_controller = cxgb_netpoll,
2873 #endif
2874 };
2875
2876 void t4_fatal_err(struct adapter *adap)
2877 {
2878 t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);
2879 t4_intr_disable(adap);
2880 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
2881 }
2882
2883 static void setup_memwin(struct adapter *adap)
2884 {
2885 u32 bar0;
2886
2887 bar0 = pci_resource_start(adap->pdev, 0); /* truncation intentional */
2888 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
2889 (bar0 + MEMWIN0_BASE) | BIR(0) |
2890 WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
2891 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
2892 (bar0 + MEMWIN1_BASE) | BIR(0) |
2893 WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
2894 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
2895 (bar0 + MEMWIN2_BASE) | BIR(0) |
2896 WINDOW(ilog2(MEMWIN2_APERTURE) - 10));
2897 }
2898
2899 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
2900 {
2901 u32 v;
2902 int ret;
2903
2904 /* get device capabilities */
2905 memset(c, 0, sizeof(*c));
2906 c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2907 FW_CMD_REQUEST | FW_CMD_READ);
2908 c->retval_len16 = htonl(FW_LEN16(*c));
2909 ret = t4_wr_mbox(adap, 0, c, sizeof(*c), c);
2910 if (ret < 0)
2911 return ret;
2912
2913 /* select capabilities we'll be using */
2914 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
2915 if (!vf_acls)
2916 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
2917 else
2918 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
2919 } else if (vf_acls) {
2920 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
2921 return ret;
2922 }
2923 c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2924 FW_CMD_REQUEST | FW_CMD_WRITE);
2925 ret = t4_wr_mbox(adap, 0, c, sizeof(*c), NULL);
2926 if (ret < 0)
2927 return ret;
2928
2929 ret = t4_config_glbl_rss(adap, 0,
2930 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
2931 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
2932 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP);
2933 if (ret < 0)
2934 return ret;
2935
2936 ret = t4_cfg_pfvf(adap, 0, 0, 0, MAX_EGRQ, 64, MAX_INGQ, 0, 0, 4,
2937 0xf, 0xf, 16, FW_CMD_CAP_PF, FW_CMD_CAP_PF);
2938 if (ret < 0)
2939 return ret;
2940
2941 t4_sge_init(adap);
2942
2943 /* get basic stuff going */
2944 ret = t4_early_init(adap, 0);
2945 if (ret < 0)
2946 return ret;
2947
2948 /* tweak some settings */
2949 t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
2950 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
2951 t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
2952 v = t4_read_reg(adap, TP_PIO_DATA);
2953 t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
2954 setup_memwin(adap);
2955 return 0;
2956 }
2957
2958 /*
2959 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
2960 */
2961 #define MAX_ATIDS 8192U
2962
2963 /*
2964 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
2965 */
2966 static int adap_init0(struct adapter *adap)
2967 {
2968 int ret;
2969 u32 v, port_vec;
2970 enum dev_state state;
2971 u32 params[7], val[7];
2972 struct fw_caps_config_cmd c;
2973
2974 ret = t4_check_fw_version(adap);
2975 if (ret == -EINVAL || ret > 0) {
2976 if (upgrade_fw(adap) >= 0) /* recache FW version */
2977 ret = t4_check_fw_version(adap);
2978 }
2979 if (ret < 0)
2980 return ret;
2981
2982 /* contact FW, request master */
2983 ret = t4_fw_hello(adap, 0, 0, MASTER_MUST, &state);
2984 if (ret < 0) {
2985 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
2986 ret);
2987 return ret;
2988 }
2989
2990 /* reset device */
2991 ret = t4_fw_reset(adap, 0, PIORSTMODE | PIORST);
2992 if (ret < 0)
2993 goto bye;
2994
2995 for (v = 0; v < SGE_NTIMERS - 1; v++)
2996 adap->sge.timer_val[v] = min(intr_holdoff[v], MAX_SGE_TIMERVAL);
2997 adap->sge.timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;
2998 adap->sge.counter_val[0] = 1;
2999 for (v = 1; v < SGE_NCOUNTERS; v++)
3000 adap->sge.counter_val[v] = min(intr_cnt[v - 1],
3001 THRESHOLD_3_MASK);
3002 #define FW_PARAM_DEV(param) \
3003 (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
3004 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
3005
3006 params[0] = FW_PARAM_DEV(CCLK);
3007 ret = t4_query_params(adap, 0, 0, 0, 1, params, val);
3008 if (ret < 0)
3009 goto bye;
3010 adap->params.vpd.cclk = val[0];
3011
3012 ret = adap_init1(adap, &c);
3013 if (ret < 0)
3014 goto bye;
3015
3016 #define FW_PARAM_PFVF(param) \
3017 (FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
3018 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
3019
3020 params[0] = FW_PARAM_DEV(PORTVEC);
3021 params[1] = FW_PARAM_PFVF(L2T_START);
3022 params[2] = FW_PARAM_PFVF(L2T_END);
3023 params[3] = FW_PARAM_PFVF(FILTER_START);
3024 params[4] = FW_PARAM_PFVF(FILTER_END);
3025 ret = t4_query_params(adap, 0, 0, 0, 5, params, val);
3026 if (ret < 0)
3027 goto bye;
3028 port_vec = val[0];
3029 adap->tids.ftid_base = val[3];
3030 adap->tids.nftids = val[4] - val[3] + 1;
3031
3032 if (c.ofldcaps) {
3033 /* query offload-related parameters */
3034 params[0] = FW_PARAM_DEV(NTID);
3035 params[1] = FW_PARAM_PFVF(SERVER_START);
3036 params[2] = FW_PARAM_PFVF(SERVER_END);
3037 params[3] = FW_PARAM_PFVF(TDDP_START);
3038 params[4] = FW_PARAM_PFVF(TDDP_END);
3039 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3040 ret = t4_query_params(adap, 0, 0, 0, 6, params, val);
3041 if (ret < 0)
3042 goto bye;
3043 adap->tids.ntids = val[0];
3044 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
3045 adap->tids.stid_base = val[1];
3046 adap->tids.nstids = val[2] - val[1] + 1;
3047 adap->vres.ddp.start = val[3];
3048 adap->vres.ddp.size = val[4] - val[3] + 1;
3049 adap->params.ofldq_wr_cred = val[5];
3050 adap->params.offload = 1;
3051 }
3052 if (c.rdmacaps) {
3053 params[0] = FW_PARAM_PFVF(STAG_START);
3054 params[1] = FW_PARAM_PFVF(STAG_END);
3055 params[2] = FW_PARAM_PFVF(RQ_START);
3056 params[3] = FW_PARAM_PFVF(RQ_END);
3057 params[4] = FW_PARAM_PFVF(PBL_START);
3058 params[5] = FW_PARAM_PFVF(PBL_END);
3059 ret = t4_query_params(adap, 0, 0, 0, 6, params, val);
3060 if (ret < 0)
3061 goto bye;
3062 adap->vres.stag.start = val[0];
3063 adap->vres.stag.size = val[1] - val[0] + 1;
3064 adap->vres.rq.start = val[2];
3065 adap->vres.rq.size = val[3] - val[2] + 1;
3066 adap->vres.pbl.start = val[4];
3067 adap->vres.pbl.size = val[5] - val[4] + 1;
3068
3069 params[0] = FW_PARAM_PFVF(SQRQ_START);
3070 params[1] = FW_PARAM_PFVF(SQRQ_END);
3071 params[2] = FW_PARAM_PFVF(CQ_START);
3072 params[3] = FW_PARAM_PFVF(CQ_END);
3073 ret = t4_query_params(adap, 0, 0, 0, 4, params, val);
3074 if (ret < 0)
3075 goto bye;
3076 adap->vres.qp.start = val[0];
3077 adap->vres.qp.size = val[1] - val[0] + 1;
3078 adap->vres.cq.start = val[2];
3079 adap->vres.cq.size = val[3] - val[2] + 1;
3080 }
3081 if (c.iscsicaps) {
3082 params[0] = FW_PARAM_PFVF(ISCSI_START);
3083 params[1] = FW_PARAM_PFVF(ISCSI_END);
3084 ret = t4_query_params(adap, 0, 0, 0, 2, params, val);
3085 if (ret < 0)
3086 goto bye;
3087 adap->vres.iscsi.start = val[0];
3088 adap->vres.iscsi.size = val[1] - val[0] + 1;
3089 }
3090 #undef FW_PARAM_PFVF
3091 #undef FW_PARAM_DEV
3092
3093 adap->params.nports = hweight32(port_vec);
3094 adap->params.portvec = port_vec;
3095 adap->flags |= FW_OK;
3096
3097 /* These are finalized by FW initialization, load their values now */
3098 v = t4_read_reg(adap, TP_TIMER_RESOLUTION);
3099 adap->params.tp.tre = TIMERRESOLUTION_GET(v);
3100 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
3101 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
3102 adap->params.b_wnd);
3103
3104 #ifdef CONFIG_PCI_IOV
3105 /*
3106 * Provision resource limits for Virtual Functions. We currently
3107 * grant them all the same static resource limits except for the Port
3108 * Access Rights Mask which we're assigning based on the PF. All of
3109 * the static provisioning stuff for both the PF and VF really needs
3110 * to be managed in a persistent manner for each device which the
3111 * firmware controls.
3112 */
3113 {
3114 int pf, vf;
3115
3116 for (pf = 0; pf < ARRAY_SIZE(num_vf); pf++) {
3117 if (num_vf[pf] <= 0)
3118 continue;
3119
3120 /* VF numbering starts at 1! */
3121 for (vf = 1; vf <= num_vf[pf]; vf++) {
3122 ret = t4_cfg_pfvf(adap, 0, pf, vf,
3123 VFRES_NEQ, VFRES_NETHCTRL,
3124 VFRES_NIQFLINT, VFRES_NIQ,
3125 VFRES_TC, VFRES_NVI,
3126 FW_PFVF_CMD_CMASK_MASK,
3127 pfvfres_pmask(adap, pf, vf),
3128 VFRES_NEXACTF,
3129 VFRES_R_CAPS, VFRES_WX_CAPS);
3130 if (ret < 0)
3131 dev_warn(adap->pdev_dev, "failed to "
3132 "provision pf/vf=%d/%d; "
3133 "err=%d\n", pf, vf, ret);
3134 }
3135 }
3136 }
3137 #endif
3138
3139 return 0;
3140
3141 /*
3142 * If a command timed out or failed with EIO FW does not operate within
3143 * its spec or something catastrophic happened to HW/FW, stop issuing
3144 * commands.
3145 */
3146 bye: if (ret != -ETIMEDOUT && ret != -EIO)
3147 t4_fw_bye(adap, 0);
3148 return ret;
3149 }
3150
3151 /* EEH callbacks */
3152
3153 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
3154 pci_channel_state_t state)
3155 {
3156 int i;
3157 struct adapter *adap = pci_get_drvdata(pdev);
3158
3159 if (!adap)
3160 goto out;
3161
3162 rtnl_lock();
3163 adap->flags &= ~FW_OK;
3164 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
3165 for_each_port(adap, i) {
3166 struct net_device *dev = adap->port[i];
3167
3168 netif_device_detach(dev);
3169 netif_carrier_off(dev);
3170 }
3171 if (adap->flags & FULL_INIT_DONE)
3172 cxgb_down(adap);
3173 rtnl_unlock();
3174 pci_disable_device(pdev);
3175 out: return state == pci_channel_io_perm_failure ?
3176 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
3177 }
3178
3179 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
3180 {
3181 int i, ret;
3182 struct fw_caps_config_cmd c;
3183 struct adapter *adap = pci_get_drvdata(pdev);
3184
3185 if (!adap) {
3186 pci_restore_state(pdev);
3187 pci_save_state(pdev);
3188 return PCI_ERS_RESULT_RECOVERED;
3189 }
3190
3191 if (pci_enable_device(pdev)) {
3192 dev_err(&pdev->dev, "cannot reenable PCI device after reset\n");
3193 return PCI_ERS_RESULT_DISCONNECT;
3194 }
3195
3196 pci_set_master(pdev);
3197 pci_restore_state(pdev);
3198 pci_save_state(pdev);
3199 pci_cleanup_aer_uncorrect_error_status(pdev);
3200
3201 if (t4_wait_dev_ready(adap) < 0)
3202 return PCI_ERS_RESULT_DISCONNECT;
3203 if (t4_fw_hello(adap, 0, 0, MASTER_MUST, NULL))
3204 return PCI_ERS_RESULT_DISCONNECT;
3205 adap->flags |= FW_OK;
3206 if (adap_init1(adap, &c))
3207 return PCI_ERS_RESULT_DISCONNECT;
3208
3209 for_each_port(adap, i) {
3210 struct port_info *p = adap2pinfo(adap, i);
3211
3212 ret = t4_alloc_vi(adap, 0, p->tx_chan, 0, 0, 1, NULL, NULL);
3213 if (ret < 0)
3214 return PCI_ERS_RESULT_DISCONNECT;
3215 p->viid = ret;
3216 p->xact_addr_filt = -1;
3217 }
3218
3219 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
3220 adap->params.b_wnd);
3221 if (cxgb_up(adap))
3222 return PCI_ERS_RESULT_DISCONNECT;
3223 return PCI_ERS_RESULT_RECOVERED;
3224 }
3225
3226 static void eeh_resume(struct pci_dev *pdev)
3227 {
3228 int i;
3229 struct adapter *adap = pci_get_drvdata(pdev);
3230
3231 if (!adap)
3232 return;
3233
3234 rtnl_lock();
3235 for_each_port(adap, i) {
3236 struct net_device *dev = adap->port[i];
3237
3238 if (netif_running(dev)) {
3239 link_start(dev);
3240 cxgb_set_rxmode(dev);
3241 }
3242 netif_device_attach(dev);
3243 }
3244 rtnl_unlock();
3245 }
3246
3247 static struct pci_error_handlers cxgb4_eeh = {
3248 .error_detected = eeh_err_detected,
3249 .slot_reset = eeh_slot_reset,
3250 .resume = eeh_resume,
3251 };
3252
3253 static inline bool is_10g_port(const struct link_config *lc)
3254 {
3255 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0;
3256 }
3257
3258 static inline void init_rspq(struct sge_rspq *q, u8 timer_idx, u8 pkt_cnt_idx,
3259 unsigned int size, unsigned int iqe_size)
3260 {
3261 q->intr_params = QINTR_TIMER_IDX(timer_idx) |
3262 (pkt_cnt_idx < SGE_NCOUNTERS ? QINTR_CNT_EN : 0);
3263 q->pktcnt_idx = pkt_cnt_idx < SGE_NCOUNTERS ? pkt_cnt_idx : 0;
3264 q->iqe_len = iqe_size;
3265 q->size = size;
3266 }
3267
3268 /*
3269 * Perform default configuration of DMA queues depending on the number and type
3270 * of ports we found and the number of available CPUs. Most settings can be
3271 * modified by the admin prior to actual use.
3272 */
3273 static void __devinit cfg_queues(struct adapter *adap)
3274 {
3275 struct sge *s = &adap->sge;
3276 int i, q10g = 0, n10g = 0, qidx = 0;
3277
3278 for_each_port(adap, i)
3279 n10g += is_10g_port(&adap2pinfo(adap, i)->link_cfg);
3280
3281 /*
3282 * We default to 1 queue per non-10G port and up to # of cores queues
3283 * per 10G port.
3284 */
3285 if (n10g)
3286 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
3287 if (q10g > num_online_cpus())
3288 q10g = num_online_cpus();
3289
3290 for_each_port(adap, i) {
3291 struct port_info *pi = adap2pinfo(adap, i);
3292
3293 pi->first_qset = qidx;
3294 pi->nqsets = is_10g_port(&pi->link_cfg) ? q10g : 1;
3295 qidx += pi->nqsets;
3296 }
3297
3298 s->ethqsets = qidx;
3299 s->max_ethqsets = qidx; /* MSI-X may lower it later */
3300
3301 if (is_offload(adap)) {
3302 /*
3303 * For offload we use 1 queue/channel if all ports are up to 1G,
3304 * otherwise we divide all available queues amongst the channels
3305 * capped by the number of available cores.
3306 */
3307 if (n10g) {
3308 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
3309 num_online_cpus());
3310 s->ofldqsets = roundup(i, adap->params.nports);
3311 } else
3312 s->ofldqsets = adap->params.nports;
3313 /* For RDMA one Rx queue per channel suffices */
3314 s->rdmaqs = adap->params.nports;
3315 }
3316
3317 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
3318 struct sge_eth_rxq *r = &s->ethrxq[i];
3319
3320 init_rspq(&r->rspq, 0, 0, 1024, 64);
3321 r->fl.size = 72;
3322 }
3323
3324 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
3325 s->ethtxq[i].q.size = 1024;
3326
3327 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
3328 s->ctrlq[i].q.size = 512;
3329
3330 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
3331 s->ofldtxq[i].q.size = 1024;
3332
3333 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
3334 struct sge_ofld_rxq *r = &s->ofldrxq[i];
3335
3336 init_rspq(&r->rspq, 0, 0, 1024, 64);
3337 r->rspq.uld = CXGB4_ULD_ISCSI;
3338 r->fl.size = 72;
3339 }
3340
3341 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
3342 struct sge_ofld_rxq *r = &s->rdmarxq[i];
3343
3344 init_rspq(&r->rspq, 0, 0, 511, 64);
3345 r->rspq.uld = CXGB4_ULD_RDMA;
3346 r->fl.size = 72;
3347 }
3348
3349 init_rspq(&s->fw_evtq, 6, 0, 512, 64);
3350 init_rspq(&s->intrq, 6, 0, 2 * MAX_INGQ, 64);
3351 }
3352
3353 /*
3354 * Reduce the number of Ethernet queues across all ports to at most n.
3355 * n provides at least one queue per port.
3356 */
3357 static void __devinit reduce_ethqs(struct adapter *adap, int n)
3358 {
3359 int i;
3360 struct port_info *pi;
3361
3362 while (n < adap->sge.ethqsets)
3363 for_each_port(adap, i) {
3364 pi = adap2pinfo(adap, i);
3365 if (pi->nqsets > 1) {
3366 pi->nqsets--;
3367 adap->sge.ethqsets--;
3368 if (adap->sge.ethqsets <= n)
3369 break;
3370 }
3371 }
3372
3373 n = 0;
3374 for_each_port(adap, i) {
3375 pi = adap2pinfo(adap, i);
3376 pi->first_qset = n;
3377 n += pi->nqsets;
3378 }
3379 }
3380
3381 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
3382 #define EXTRA_VECS 2
3383
3384 static int __devinit enable_msix(struct adapter *adap)
3385 {
3386 int ofld_need = 0;
3387 int i, err, want, need;
3388 struct sge *s = &adap->sge;
3389 unsigned int nchan = adap->params.nports;
3390 struct msix_entry entries[MAX_INGQ + 1];
3391
3392 for (i = 0; i < ARRAY_SIZE(entries); ++i)
3393 entries[i].entry = i;
3394
3395 want = s->max_ethqsets + EXTRA_VECS;
3396 if (is_offload(adap)) {
3397 want += s->rdmaqs + s->ofldqsets;
3398 /* need nchan for each possible ULD */
3399 ofld_need = 2 * nchan;
3400 }
3401 need = adap->params.nports + EXTRA_VECS + ofld_need;
3402
3403 while ((err = pci_enable_msix(adap->pdev, entries, want)) >= need)
3404 want = err;
3405
3406 if (!err) {
3407 /*
3408 * Distribute available vectors to the various queue groups.
3409 * Every group gets its minimum requirement and NIC gets top
3410 * priority for leftovers.
3411 */
3412 i = want - EXTRA_VECS - ofld_need;
3413 if (i < s->max_ethqsets) {
3414 s->max_ethqsets = i;
3415 if (i < s->ethqsets)
3416 reduce_ethqs(adap, i);
3417 }
3418 if (is_offload(adap)) {
3419 i = want - EXTRA_VECS - s->max_ethqsets;
3420 i -= ofld_need - nchan;
3421 s->ofldqsets = (i / nchan) * nchan; /* round down */
3422 }
3423 for (i = 0; i < want; ++i)
3424 adap->msix_info[i].vec = entries[i].vector;
3425 } else if (err > 0)
3426 dev_info(adap->pdev_dev,
3427 "only %d MSI-X vectors left, not using MSI-X\n", err);
3428 return err;
3429 }
3430
3431 #undef EXTRA_VECS
3432
3433 static int __devinit init_rss(struct adapter *adap)
3434 {
3435 unsigned int i, j;
3436
3437 for_each_port(adap, i) {
3438 struct port_info *pi = adap2pinfo(adap, i);
3439
3440 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
3441 if (!pi->rss)
3442 return -ENOMEM;
3443 for (j = 0; j < pi->rss_size; j++)
3444 pi->rss[j] = j % pi->nqsets;
3445 }
3446 return 0;
3447 }
3448
3449 static void __devinit print_port_info(struct adapter *adap)
3450 {
3451 static const char *base[] = {
3452 "R XFI", "R XAUI", "T SGMII", "T XFI", "T XAUI", "KX4", "CX4",
3453 "KX", "KR", "KR SFP+", "KR FEC"
3454 };
3455
3456 int i;
3457 char buf[80];
3458 const char *spd = "";
3459
3460 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
3461 spd = " 2.5 GT/s";
3462 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
3463 spd = " 5 GT/s";
3464
3465 for_each_port(adap, i) {
3466 struct net_device *dev = adap->port[i];
3467 const struct port_info *pi = netdev_priv(dev);
3468 char *bufp = buf;
3469
3470 if (!test_bit(i, &adap->registered_device_map))
3471 continue;
3472
3473 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
3474 bufp += sprintf(bufp, "100/");
3475 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
3476 bufp += sprintf(bufp, "1000/");
3477 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
3478 bufp += sprintf(bufp, "10G/");
3479 if (bufp != buf)
3480 --bufp;
3481 sprintf(bufp, "BASE-%s", base[pi->port_type]);
3482
3483 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
3484 adap->params.vpd.id, adap->params.rev,
3485 buf, is_offload(adap) ? "R" : "",
3486 adap->params.pci.width, spd,
3487 (adap->flags & USING_MSIX) ? " MSI-X" :
3488 (adap->flags & USING_MSI) ? " MSI" : "");
3489 if (adap->name == dev->name)
3490 netdev_info(dev, "S/N: %s, E/C: %s\n",
3491 adap->params.vpd.sn, adap->params.vpd.ec);
3492 }
3493 }
3494
3495 /*
3496 * Free the following resources:
3497 * - memory used for tables
3498 * - MSI/MSI-X
3499 * - net devices
3500 * - resources FW is holding for us
3501 */
3502 static void free_some_resources(struct adapter *adapter)
3503 {
3504 unsigned int i;
3505
3506 t4_free_mem(adapter->l2t);
3507 t4_free_mem(adapter->tids.tid_tab);
3508 disable_msi(adapter);
3509
3510 for_each_port(adapter, i)
3511 if (adapter->port[i]) {
3512 kfree(adap2pinfo(adapter, i)->rss);
3513 free_netdev(adapter->port[i]);
3514 }
3515 if (adapter->flags & FW_OK)
3516 t4_fw_bye(adapter, 0);
3517 }
3518
3519 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | NETIF_F_TSO6 |\
3520 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
3521
3522 static int __devinit init_one(struct pci_dev *pdev,
3523 const struct pci_device_id *ent)
3524 {
3525 int func, i, err;
3526 struct port_info *pi;
3527 unsigned int highdma = 0;
3528 struct adapter *adapter = NULL;
3529
3530 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
3531
3532 err = pci_request_regions(pdev, KBUILD_MODNAME);
3533 if (err) {
3534 /* Just info, some other driver may have claimed the device. */
3535 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
3536 return err;
3537 }
3538
3539 /* We control everything through PF 0 */
3540 func = PCI_FUNC(pdev->devfn);
3541 if (func > 0) {
3542 pci_save_state(pdev); /* to restore SR-IOV later */
3543 goto sriov;
3544 }
3545
3546 err = pci_enable_device(pdev);
3547 if (err) {
3548 dev_err(&pdev->dev, "cannot enable PCI device\n");
3549 goto out_release_regions;
3550 }
3551
3552 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3553 highdma = NETIF_F_HIGHDMA;
3554 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3555 if (err) {
3556 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
3557 "coherent allocations\n");
3558 goto out_disable_device;
3559 }
3560 } else {
3561 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3562 if (err) {
3563 dev_err(&pdev->dev, "no usable DMA configuration\n");
3564 goto out_disable_device;
3565 }
3566 }
3567
3568 pci_enable_pcie_error_reporting(pdev);
3569 pci_set_master(pdev);
3570 pci_save_state(pdev);
3571
3572 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
3573 if (!adapter) {
3574 err = -ENOMEM;
3575 goto out_disable_device;
3576 }
3577
3578 adapter->regs = pci_ioremap_bar(pdev, 0);
3579 if (!adapter->regs) {
3580 dev_err(&pdev->dev, "cannot map device registers\n");
3581 err = -ENOMEM;
3582 goto out_free_adapter;
3583 }
3584
3585 adapter->pdev = pdev;
3586 adapter->pdev_dev = &pdev->dev;
3587 adapter->name = pci_name(pdev);
3588 adapter->msg_enable = dflt_msg_enable;
3589 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
3590
3591 spin_lock_init(&adapter->stats_lock);
3592 spin_lock_init(&adapter->tid_release_lock);
3593
3594 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
3595
3596 err = t4_prep_adapter(adapter);
3597 if (err)
3598 goto out_unmap_bar;
3599 err = adap_init0(adapter);
3600 if (err)
3601 goto out_unmap_bar;
3602
3603 for_each_port(adapter, i) {
3604 struct net_device *netdev;
3605
3606 netdev = alloc_etherdev_mq(sizeof(struct port_info),
3607 MAX_ETH_QSETS);
3608 if (!netdev) {
3609 err = -ENOMEM;
3610 goto out_free_dev;
3611 }
3612
3613 SET_NETDEV_DEV(netdev, &pdev->dev);
3614
3615 adapter->port[i] = netdev;
3616 pi = netdev_priv(netdev);
3617 pi->adapter = adapter;
3618 pi->xact_addr_filt = -1;
3619 pi->rx_offload = RX_CSO;
3620 pi->port_id = i;
3621 netif_carrier_off(netdev);
3622 netif_tx_stop_all_queues(netdev);
3623 netdev->irq = pdev->irq;
3624
3625 netdev->features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
3626 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3627 netdev->features |= NETIF_F_GRO | NETIF_F_RXHASH | highdma;
3628 netdev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3629 netdev->vlan_features = netdev->features & VLAN_FEAT;
3630
3631 netdev->netdev_ops = &cxgb4_netdev_ops;
3632 SET_ETHTOOL_OPS(netdev, &cxgb_ethtool_ops);
3633 }
3634
3635 pci_set_drvdata(pdev, adapter);
3636
3637 if (adapter->flags & FW_OK) {
3638 err = t4_port_init(adapter, 0, 0, 0);
3639 if (err)
3640 goto out_free_dev;
3641 }
3642
3643 /*
3644 * Configure queues and allocate tables now, they can be needed as
3645 * soon as the first register_netdev completes.
3646 */
3647 cfg_queues(adapter);
3648
3649 adapter->l2t = t4_init_l2t();
3650 if (!adapter->l2t) {
3651 /* We tolerate a lack of L2T, giving up some functionality */
3652 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
3653 adapter->params.offload = 0;
3654 }
3655
3656 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
3657 dev_warn(&pdev->dev, "could not allocate TID table, "
3658 "continuing\n");
3659 adapter->params.offload = 0;
3660 }
3661
3662 /* See what interrupts we'll be using */
3663 if (msi > 1 && enable_msix(adapter) == 0)
3664 adapter->flags |= USING_MSIX;
3665 else if (msi > 0 && pci_enable_msi(pdev) == 0)
3666 adapter->flags |= USING_MSI;
3667
3668 err = init_rss(adapter);
3669 if (err)
3670 goto out_free_dev;
3671
3672 /*
3673 * The card is now ready to go. If any errors occur during device
3674 * registration we do not fail the whole card but rather proceed only
3675 * with the ports we manage to register successfully. However we must
3676 * register at least one net device.
3677 */
3678 for_each_port(adapter, i) {
3679 err = register_netdev(adapter->port[i]);
3680 if (err)
3681 dev_warn(&pdev->dev,
3682 "cannot register net device %s, skipping\n",
3683 adapter->port[i]->name);
3684 else {
3685 /*
3686 * Change the name we use for messages to the name of
3687 * the first successfully registered interface.
3688 */
3689 if (!adapter->registered_device_map)
3690 adapter->name = adapter->port[i]->name;
3691
3692 __set_bit(i, &adapter->registered_device_map);
3693 adapter->chan_map[adap2pinfo(adapter, i)->tx_chan] = i;
3694 }
3695 }
3696 if (!adapter->registered_device_map) {
3697 dev_err(&pdev->dev, "could not register any net devices\n");
3698 goto out_free_dev;
3699 }
3700
3701 if (cxgb4_debugfs_root) {
3702 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
3703 cxgb4_debugfs_root);
3704 setup_debugfs(adapter);
3705 }
3706
3707 if (is_offload(adapter))
3708 attach_ulds(adapter);
3709
3710 print_port_info(adapter);
3711
3712 sriov:
3713 #ifdef CONFIG_PCI_IOV
3714 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
3715 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
3716 dev_info(&pdev->dev,
3717 "instantiated %u virtual functions\n",
3718 num_vf[func]);
3719 #endif
3720 return 0;
3721
3722 out_free_dev:
3723 free_some_resources(adapter);
3724 out_unmap_bar:
3725 iounmap(adapter->regs);
3726 out_free_adapter:
3727 kfree(adapter);
3728 out_disable_device:
3729 pci_disable_pcie_error_reporting(pdev);
3730 pci_disable_device(pdev);
3731 out_release_regions:
3732 pci_release_regions(pdev);
3733 pci_set_drvdata(pdev, NULL);
3734 return err;
3735 }
3736
3737 static void __devexit remove_one(struct pci_dev *pdev)
3738 {
3739 struct adapter *adapter = pci_get_drvdata(pdev);
3740
3741 pci_disable_sriov(pdev);
3742
3743 if (adapter) {
3744 int i;
3745
3746 if (is_offload(adapter))
3747 detach_ulds(adapter);
3748
3749 for_each_port(adapter, i)
3750 if (test_bit(i, &adapter->registered_device_map))
3751 unregister_netdev(adapter->port[i]);
3752
3753 if (adapter->debugfs_root)
3754 debugfs_remove_recursive(adapter->debugfs_root);
3755
3756 if (adapter->flags & FULL_INIT_DONE)
3757 cxgb_down(adapter);
3758
3759 free_some_resources(adapter);
3760 iounmap(adapter->regs);
3761 kfree(adapter);
3762 pci_disable_pcie_error_reporting(pdev);
3763 pci_disable_device(pdev);
3764 pci_release_regions(pdev);
3765 pci_set_drvdata(pdev, NULL);
3766 } else if (PCI_FUNC(pdev->devfn) > 0)
3767 pci_release_regions(pdev);
3768 }
3769
3770 static struct pci_driver cxgb4_driver = {
3771 .name = KBUILD_MODNAME,
3772 .id_table = cxgb4_pci_tbl,
3773 .probe = init_one,
3774 .remove = __devexit_p(remove_one),
3775 .err_handler = &cxgb4_eeh,
3776 };
3777
3778 static int __init cxgb4_init_module(void)
3779 {
3780 int ret;
3781
3782 /* Debugfs support is optional, just warn if this fails */
3783 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
3784 if (!cxgb4_debugfs_root)
3785 pr_warning("could not create debugfs entry, continuing\n");
3786
3787 ret = pci_register_driver(&cxgb4_driver);
3788 if (ret < 0)
3789 debugfs_remove(cxgb4_debugfs_root);
3790 return ret;
3791 }
3792
3793 static void __exit cxgb4_cleanup_module(void)
3794 {
3795 pci_unregister_driver(&cxgb4_driver);
3796 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
3797 }
3798
3799 module_init(cxgb4_init_module);
3800 module_exit(cxgb4_cleanup_module);
Linux 2.6 libata-dev (mirror)