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RDMA: Remove subversion $Id tags
[linux-2.6/libata-dev.git] / drivers / infiniband / hw / mthca / mthca_qp.c
blob3b1c5baf13b19cb236b959afa08711c7ef0b531d
1 /*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36 #include <linux/string.h>
37 #include <linux/slab.h>
38 #include <linux/sched.h>
39
40 #include <asm/io.h>
41
42 #include <rdma/ib_verbs.h>
43 #include <rdma/ib_cache.h>
44 #include <rdma/ib_pack.h>
45
46 #include "mthca_dev.h"
47 #include "mthca_cmd.h"
48 #include "mthca_memfree.h"
49 #include "mthca_wqe.h"
50
51 enum {
52 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
53 MTHCA_ACK_REQ_FREQ = 10,
54 MTHCA_FLIGHT_LIMIT = 9,
55 MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */
56 MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */
57 MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */
58 };
59
60 enum {
61 MTHCA_QP_STATE_RST = 0,
62 MTHCA_QP_STATE_INIT = 1,
63 MTHCA_QP_STATE_RTR = 2,
64 MTHCA_QP_STATE_RTS = 3,
65 MTHCA_QP_STATE_SQE = 4,
66 MTHCA_QP_STATE_SQD = 5,
67 MTHCA_QP_STATE_ERR = 6,
68 MTHCA_QP_STATE_DRAINING = 7
69 };
70
71 enum {
72 MTHCA_QP_ST_RC = 0x0,
73 MTHCA_QP_ST_UC = 0x1,
74 MTHCA_QP_ST_RD = 0x2,
75 MTHCA_QP_ST_UD = 0x3,
76 MTHCA_QP_ST_MLX = 0x7
77 };
78
79 enum {
80 MTHCA_QP_PM_MIGRATED = 0x3,
81 MTHCA_QP_PM_ARMED = 0x0,
82 MTHCA_QP_PM_REARM = 0x1
83 };
84
85 enum {
86 /* qp_context flags */
87 MTHCA_QP_BIT_DE = 1 << 8,
88 /* params1 */
89 MTHCA_QP_BIT_SRE = 1 << 15,
90 MTHCA_QP_BIT_SWE = 1 << 14,
91 MTHCA_QP_BIT_SAE = 1 << 13,
92 MTHCA_QP_BIT_SIC = 1 << 4,
93 MTHCA_QP_BIT_SSC = 1 << 3,
94 /* params2 */
95 MTHCA_QP_BIT_RRE = 1 << 15,
96 MTHCA_QP_BIT_RWE = 1 << 14,
97 MTHCA_QP_BIT_RAE = 1 << 13,
98 MTHCA_QP_BIT_RIC = 1 << 4,
99 MTHCA_QP_BIT_RSC = 1 << 3
100 };
101
102 enum {
103 MTHCA_SEND_DOORBELL_FENCE = 1 << 5
104 };
105
106 struct mthca_qp_path {
107 __be32 port_pkey;
108 u8 rnr_retry;
109 u8 g_mylmc;
110 __be16 rlid;
111 u8 ackto;
112 u8 mgid_index;
113 u8 static_rate;
114 u8 hop_limit;
115 __be32 sl_tclass_flowlabel;
116 u8 rgid[16];
117 } __attribute__((packed));
118
119 struct mthca_qp_context {
120 __be32 flags;
121 __be32 tavor_sched_queue; /* Reserved on Arbel */
122 u8 mtu_msgmax;
123 u8 rq_size_stride; /* Reserved on Tavor */
124 u8 sq_size_stride; /* Reserved on Tavor */
125 u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */
126 __be32 usr_page;
127 __be32 local_qpn;
128 __be32 remote_qpn;
129 u32 reserved1[2];
130 struct mthca_qp_path pri_path;
131 struct mthca_qp_path alt_path;
132 __be32 rdd;
133 __be32 pd;
134 __be32 wqe_base;
135 __be32 wqe_lkey;
136 __be32 params1;
137 __be32 reserved2;
138 __be32 next_send_psn;
139 __be32 cqn_snd;
140 __be32 snd_wqe_base_l; /* Next send WQE on Tavor */
141 __be32 snd_db_index; /* (debugging only entries) */
142 __be32 last_acked_psn;
143 __be32 ssn;
144 __be32 params2;
145 __be32 rnr_nextrecvpsn;
146 __be32 ra_buff_indx;
147 __be32 cqn_rcv;
148 __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */
149 __be32 rcv_db_index; /* (debugging only entries) */
150 __be32 qkey;
151 __be32 srqn;
152 __be32 rmsn;
153 __be16 rq_wqe_counter; /* reserved on Tavor */
154 __be16 sq_wqe_counter; /* reserved on Tavor */
155 u32 reserved3[18];
156 } __attribute__((packed));
157
158 struct mthca_qp_param {
159 __be32 opt_param_mask;
160 u32 reserved1;
161 struct mthca_qp_context context;
162 u32 reserved2[62];
163 } __attribute__((packed));
164
165 enum {
166 MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
167 MTHCA_QP_OPTPAR_RRE = 1 << 1,
168 MTHCA_QP_OPTPAR_RAE = 1 << 2,
169 MTHCA_QP_OPTPAR_RWE = 1 << 3,
170 MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4,
171 MTHCA_QP_OPTPAR_Q_KEY = 1 << 5,
172 MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
173 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
174 MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8,
175 MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9,
176 MTHCA_QP_OPTPAR_PM_STATE = 1 << 10,
177 MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11,
178 MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12,
179 MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13,
180 MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
181 MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15,
182 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16
183 };
184
185 static const u8 mthca_opcode[] = {
186 [IB_WR_SEND] = MTHCA_OPCODE_SEND,
187 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM,
188 [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE,
189 [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM,
190 [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ,
191 [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS,
192 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
193 };
194
195 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
196 {
197 return qp->qpn >= dev->qp_table.sqp_start &&
198 qp->qpn <= dev->qp_table.sqp_start + 3;
199 }
200
201 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
202 {
203 return qp->qpn >= dev->qp_table.sqp_start &&
204 qp->qpn <= dev->qp_table.sqp_start + 1;
205 }
206
207 static void *get_recv_wqe(struct mthca_qp *qp, int n)
208 {
209 if (qp->is_direct)
210 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
211 else
212 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
213 ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
214 }
215
216 static void *get_send_wqe(struct mthca_qp *qp, int n)
217 {
218 if (qp->is_direct)
219 return qp->queue.direct.buf + qp->send_wqe_offset +
220 (n << qp->sq.wqe_shift);
221 else
222 return qp->queue.page_list[(qp->send_wqe_offset +
223 (n << qp->sq.wqe_shift)) >>
224 PAGE_SHIFT].buf +
225 ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
226 (PAGE_SIZE - 1));
227 }
228
229 static void mthca_wq_reset(struct mthca_wq *wq)
230 {
231 wq->next_ind = 0;
232 wq->last_comp = wq->max - 1;
233 wq->head = 0;
234 wq->tail = 0;
235 }
236
237 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
238 enum ib_event_type event_type)
239 {
240 struct mthca_qp *qp;
241 struct ib_event event;
242
243 spin_lock(&dev->qp_table.lock);
244 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
245 if (qp)
246 ++qp->refcount;
247 spin_unlock(&dev->qp_table.lock);
248
249 if (!qp) {
250 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
251 return;
252 }
253
254 if (event_type == IB_EVENT_PATH_MIG)
255 qp->port = qp->alt_port;
256
257 event.device = &dev->ib_dev;
258 event.event = event_type;
259 event.element.qp = &qp->ibqp;
260 if (qp->ibqp.event_handler)
261 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
262
263 spin_lock(&dev->qp_table.lock);
264 if (!--qp->refcount)
265 wake_up(&qp->wait);
266 spin_unlock(&dev->qp_table.lock);
267 }
268
269 static int to_mthca_state(enum ib_qp_state ib_state)
270 {
271 switch (ib_state) {
272 case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
273 case IB_QPS_INIT: return MTHCA_QP_STATE_INIT;
274 case IB_QPS_RTR: return MTHCA_QP_STATE_RTR;
275 case IB_QPS_RTS: return MTHCA_QP_STATE_RTS;
276 case IB_QPS_SQD: return MTHCA_QP_STATE_SQD;
277 case IB_QPS_SQE: return MTHCA_QP_STATE_SQE;
278 case IB_QPS_ERR: return MTHCA_QP_STATE_ERR;
279 default: return -1;
280 }
281 }
282
283 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
284
285 static int to_mthca_st(int transport)
286 {
287 switch (transport) {
288 case RC: return MTHCA_QP_ST_RC;
289 case UC: return MTHCA_QP_ST_UC;
290 case UD: return MTHCA_QP_ST_UD;
291 case RD: return MTHCA_QP_ST_RD;
292 case MLX: return MTHCA_QP_ST_MLX;
293 default: return -1;
294 }
295 }
296
297 static void store_attrs(struct mthca_sqp *sqp, const struct ib_qp_attr *attr,
298 int attr_mask)
299 {
300 if (attr_mask & IB_QP_PKEY_INDEX)
301 sqp->pkey_index = attr->pkey_index;
302 if (attr_mask & IB_QP_QKEY)
303 sqp->qkey = attr->qkey;
304 if (attr_mask & IB_QP_SQ_PSN)
305 sqp->send_psn = attr->sq_psn;
306 }
307
308 static void init_port(struct mthca_dev *dev, int port)
309 {
310 int err;
311 u8 status;
312 struct mthca_init_ib_param param;
313
314 memset(&param, 0, sizeof param);
315
316 param.port_width = dev->limits.port_width_cap;
317 param.vl_cap = dev->limits.vl_cap;
318 param.mtu_cap = dev->limits.mtu_cap;
319 param.gid_cap = dev->limits.gid_table_len;
320 param.pkey_cap = dev->limits.pkey_table_len;
321
322 err = mthca_INIT_IB(dev, &param, port, &status);
323 if (err)
324 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
325 if (status)
326 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
327 }
328
329 static __be32 get_hw_access_flags(struct mthca_qp *qp, const struct ib_qp_attr *attr,
330 int attr_mask)
331 {
332 u8 dest_rd_atomic;
333 u32 access_flags;
334 u32 hw_access_flags = 0;
335
336 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
337 dest_rd_atomic = attr->max_dest_rd_atomic;
338 else
339 dest_rd_atomic = qp->resp_depth;
340
341 if (attr_mask & IB_QP_ACCESS_FLAGS)
342 access_flags = attr->qp_access_flags;
343 else
344 access_flags = qp->atomic_rd_en;
345
346 if (!dest_rd_atomic)
347 access_flags &= IB_ACCESS_REMOTE_WRITE;
348
349 if (access_flags & IB_ACCESS_REMOTE_READ)
350 hw_access_flags |= MTHCA_QP_BIT_RRE;
351 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
352 hw_access_flags |= MTHCA_QP_BIT_RAE;
353 if (access_flags & IB_ACCESS_REMOTE_WRITE)
354 hw_access_flags |= MTHCA_QP_BIT_RWE;
355
356 return cpu_to_be32(hw_access_flags);
357 }
358
359 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
360 {
361 switch (mthca_state) {
362 case MTHCA_QP_STATE_RST: return IB_QPS_RESET;
363 case MTHCA_QP_STATE_INIT: return IB_QPS_INIT;
364 case MTHCA_QP_STATE_RTR: return IB_QPS_RTR;
365 case MTHCA_QP_STATE_RTS: return IB_QPS_RTS;
366 case MTHCA_QP_STATE_DRAINING:
367 case MTHCA_QP_STATE_SQD: return IB_QPS_SQD;
368 case MTHCA_QP_STATE_SQE: return IB_QPS_SQE;
369 case MTHCA_QP_STATE_ERR: return IB_QPS_ERR;
370 default: return -1;
371 }
372 }
373
374 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
375 {
376 switch (mthca_mig_state) {
377 case 0: return IB_MIG_ARMED;
378 case 1: return IB_MIG_REARM;
379 case 3: return IB_MIG_MIGRATED;
380 default: return -1;
381 }
382 }
383
384 static int to_ib_qp_access_flags(int mthca_flags)
385 {
386 int ib_flags = 0;
387
388 if (mthca_flags & MTHCA_QP_BIT_RRE)
389 ib_flags |= IB_ACCESS_REMOTE_READ;
390 if (mthca_flags & MTHCA_QP_BIT_RWE)
391 ib_flags |= IB_ACCESS_REMOTE_WRITE;
392 if (mthca_flags & MTHCA_QP_BIT_RAE)
393 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
394
395 return ib_flags;
396 }
397
398 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
399 struct mthca_qp_path *path)
400 {
401 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
402 ib_ah_attr->port_num = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
403
404 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
405 return;
406
407 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
408 ib_ah_attr->sl = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
409 ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
410 ib_ah_attr->static_rate = mthca_rate_to_ib(dev,
411 path->static_rate & 0xf,
412 ib_ah_attr->port_num);
413 ib_ah_attr->ah_flags = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
414 if (ib_ah_attr->ah_flags) {
415 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
416 ib_ah_attr->grh.hop_limit = path->hop_limit;
417 ib_ah_attr->grh.traffic_class =
418 (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
419 ib_ah_attr->grh.flow_label =
420 be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
421 memcpy(ib_ah_attr->grh.dgid.raw,
422 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
423 }
424 }
425
426 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
427 struct ib_qp_init_attr *qp_init_attr)
428 {
429 struct mthca_dev *dev = to_mdev(ibqp->device);
430 struct mthca_qp *qp = to_mqp(ibqp);
431 int err = 0;
432 struct mthca_mailbox *mailbox = NULL;
433 struct mthca_qp_param *qp_param;
434 struct mthca_qp_context *context;
435 int mthca_state;
436 u8 status;
437
438 mutex_lock(&qp->mutex);
439
440 if (qp->state == IB_QPS_RESET) {
441 qp_attr->qp_state = IB_QPS_RESET;
442 goto done;
443 }
444
445 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
446 if (IS_ERR(mailbox)) {
447 err = PTR_ERR(mailbox);
448 goto out;
449 }
450
451 err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
452 if (err)
453 goto out_mailbox;
454 if (status) {
455 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
456 err = -EINVAL;
457 goto out_mailbox;
458 }
459
460 qp_param = mailbox->buf;
461 context = &qp_param->context;
462 mthca_state = be32_to_cpu(context->flags) >> 28;
463
464 qp->state = to_ib_qp_state(mthca_state);
465 qp_attr->qp_state = qp->state;
466 qp_attr->path_mtu = context->mtu_msgmax >> 5;
467 qp_attr->path_mig_state =
468 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
469 qp_attr->qkey = be32_to_cpu(context->qkey);
470 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
471 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
472 qp_attr->dest_qp_num = be32_to_cpu(context->remote_qpn) & 0xffffff;
473 qp_attr->qp_access_flags =
474 to_ib_qp_access_flags(be32_to_cpu(context->params2));
475
476 if (qp->transport == RC || qp->transport == UC) {
477 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
478 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
479 qp_attr->alt_pkey_index =
480 be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
481 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
482 }
483
484 qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
485 qp_attr->port_num =
486 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3;
487
488 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
489 qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
490
491 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
492
493 qp_attr->max_dest_rd_atomic =
494 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
495 qp_attr->min_rnr_timer =
496 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
497 qp_attr->timeout = context->pri_path.ackto >> 3;
498 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
499 qp_attr->rnr_retry = context->pri_path.rnr_retry >> 5;
500 qp_attr->alt_timeout = context->alt_path.ackto >> 3;
501
502 done:
503 qp_attr->cur_qp_state = qp_attr->qp_state;
504 qp_attr->cap.max_send_wr = qp->sq.max;
505 qp_attr->cap.max_recv_wr = qp->rq.max;
506 qp_attr->cap.max_send_sge = qp->sq.max_gs;
507 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
508 qp_attr->cap.max_inline_data = qp->max_inline_data;
509
510 qp_init_attr->cap = qp_attr->cap;
511
512 out_mailbox:
513 mthca_free_mailbox(dev, mailbox);
514
515 out:
516 mutex_unlock(&qp->mutex);
517 return err;
518 }
519
520 static int mthca_path_set(struct mthca_dev *dev, const struct ib_ah_attr *ah,
521 struct mthca_qp_path *path, u8 port)
522 {
523 path->g_mylmc = ah->src_path_bits & 0x7f;
524 path->rlid = cpu_to_be16(ah->dlid);
525 path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
526
527 if (ah->ah_flags & IB_AH_GRH) {
528 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
529 mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
530 ah->grh.sgid_index, dev->limits.gid_table_len-1);
531 return -1;
532 }
533
534 path->g_mylmc |= 1 << 7;
535 path->mgid_index = ah->grh.sgid_index;
536 path->hop_limit = ah->grh.hop_limit;
537 path->sl_tclass_flowlabel =
538 cpu_to_be32((ah->sl << 28) |
539 (ah->grh.traffic_class << 20) |
540 (ah->grh.flow_label));
541 memcpy(path->rgid, ah->grh.dgid.raw, 16);
542 } else
543 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
544
545 return 0;
546 }
547
548 static int __mthca_modify_qp(struct ib_qp *ibqp,
549 const struct ib_qp_attr *attr, int attr_mask,
550 enum ib_qp_state cur_state, enum ib_qp_state new_state)
551 {
552 struct mthca_dev *dev = to_mdev(ibqp->device);
553 struct mthca_qp *qp = to_mqp(ibqp);
554 struct mthca_mailbox *mailbox;
555 struct mthca_qp_param *qp_param;
556 struct mthca_qp_context *qp_context;
557 u32 sqd_event = 0;
558 u8 status;
559 int err = -EINVAL;
560
561 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
562 if (IS_ERR(mailbox)) {
563 err = PTR_ERR(mailbox);
564 goto out;
565 }
566 qp_param = mailbox->buf;
567 qp_context = &qp_param->context;
568 memset(qp_param, 0, sizeof *qp_param);
569
570 qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) |
571 (to_mthca_st(qp->transport) << 16));
572 qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE);
573 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
574 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
575 else {
576 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
577 switch (attr->path_mig_state) {
578 case IB_MIG_MIGRATED:
579 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
580 break;
581 case IB_MIG_REARM:
582 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
583 break;
584 case IB_MIG_ARMED:
585 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
586 break;
587 }
588 }
589
590 /* leave tavor_sched_queue as 0 */
591
592 if (qp->transport == MLX || qp->transport == UD)
593 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
594 else if (attr_mask & IB_QP_PATH_MTU) {
595 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
596 mthca_dbg(dev, "path MTU (%u) is invalid\n",
597 attr->path_mtu);
598 goto out_mailbox;
599 }
600 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
601 }
602
603 if (mthca_is_memfree(dev)) {
604 if (qp->rq.max)
605 qp_context->rq_size_stride = ilog2(qp->rq.max) << 3;
606 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
607
608 if (qp->sq.max)
609 qp_context->sq_size_stride = ilog2(qp->sq.max) << 3;
610 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
611 }
612
613 /* leave arbel_sched_queue as 0 */
614
615 if (qp->ibqp.uobject)
616 qp_context->usr_page =
617 cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
618 else
619 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
620 qp_context->local_qpn = cpu_to_be32(qp->qpn);
621 if (attr_mask & IB_QP_DEST_QPN) {
622 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
623 }
624
625 if (qp->transport == MLX)
626 qp_context->pri_path.port_pkey |=
627 cpu_to_be32(qp->port << 24);
628 else {
629 if (attr_mask & IB_QP_PORT) {
630 qp_context->pri_path.port_pkey |=
631 cpu_to_be32(attr->port_num << 24);
632 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
633 }
634 }
635
636 if (attr_mask & IB_QP_PKEY_INDEX) {
637 qp_context->pri_path.port_pkey |=
638 cpu_to_be32(attr->pkey_index);
639 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
640 }
641
642 if (attr_mask & IB_QP_RNR_RETRY) {
643 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
644 attr->rnr_retry << 5;
645 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
646 MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
647 }
648
649 if (attr_mask & IB_QP_AV) {
650 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
651 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
652 goto out_mailbox;
653
654 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
655 }
656
657 if (ibqp->qp_type == IB_QPT_RC &&
658 cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
659 u8 sched_queue = ibqp->uobject ? 0x2 : 0x1;
660
661 if (mthca_is_memfree(dev))
662 qp_context->rlkey_arbel_sched_queue |= sched_queue;
663 else
664 qp_context->tavor_sched_queue |= cpu_to_be32(sched_queue);
665
666 qp_param->opt_param_mask |=
667 cpu_to_be32(MTHCA_QP_OPTPAR_SCHED_QUEUE);
668 }
669
670 if (attr_mask & IB_QP_TIMEOUT) {
671 qp_context->pri_path.ackto = attr->timeout << 3;
672 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
673 }
674
675 if (attr_mask & IB_QP_ALT_PATH) {
676 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
677 mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
678 attr->alt_pkey_index, dev->limits.pkey_table_len-1);
679 goto out_mailbox;
680 }
681
682 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
683 mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
684 attr->alt_port_num);
685 goto out_mailbox;
686 }
687
688 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
689 attr->alt_ah_attr.port_num))
690 goto out_mailbox;
691
692 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
693 attr->alt_port_num << 24);
694 qp_context->alt_path.ackto = attr->alt_timeout << 3;
695 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
696 }
697
698 /* leave rdd as 0 */
699 qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
700 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
701 qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey);
702 qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
703 (MTHCA_FLIGHT_LIMIT << 24) |
704 MTHCA_QP_BIT_SWE);
705 if (qp->sq_policy == IB_SIGNAL_ALL_WR)
706 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
707 if (attr_mask & IB_QP_RETRY_CNT) {
708 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
709 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
710 }
711
712 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
713 if (attr->max_rd_atomic) {
714 qp_context->params1 |=
715 cpu_to_be32(MTHCA_QP_BIT_SRE |
716 MTHCA_QP_BIT_SAE);
717 qp_context->params1 |=
718 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
719 }
720 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
721 }
722
723 if (attr_mask & IB_QP_SQ_PSN)
724 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
725 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
726
727 if (mthca_is_memfree(dev)) {
728 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
729 qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index);
730 }
731
732 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
733 if (attr->max_dest_rd_atomic)
734 qp_context->params2 |=
735 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
736
737 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
738 }
739
740 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
741 qp_context->params2 |= get_hw_access_flags(qp, attr, attr_mask);
742 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
743 MTHCA_QP_OPTPAR_RRE |
744 MTHCA_QP_OPTPAR_RAE);
745 }
746
747 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
748
749 if (ibqp->srq)
750 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
751
752 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
753 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
754 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
755 }
756 if (attr_mask & IB_QP_RQ_PSN)
757 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
758
759 qp_context->ra_buff_indx =
760 cpu_to_be32(dev->qp_table.rdb_base +
761 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
762 dev->qp_table.rdb_shift));
763
764 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
765
766 if (mthca_is_memfree(dev))
767 qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index);
768
769 if (attr_mask & IB_QP_QKEY) {
770 qp_context->qkey = cpu_to_be32(attr->qkey);
771 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
772 }
773
774 if (ibqp->srq)
775 qp_context->srqn = cpu_to_be32(1 << 24 |
776 to_msrq(ibqp->srq)->srqn);
777
778 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
779 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY &&
780 attr->en_sqd_async_notify)
781 sqd_event = 1 << 31;
782
783 err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
784 mailbox, sqd_event, &status);
785 if (err)
786 goto out_mailbox;
787 if (status) {
788 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
789 cur_state, new_state, status);
790 err = -EINVAL;
791 goto out_mailbox;
792 }
793
794 qp->state = new_state;
795 if (attr_mask & IB_QP_ACCESS_FLAGS)
796 qp->atomic_rd_en = attr->qp_access_flags;
797 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
798 qp->resp_depth = attr->max_dest_rd_atomic;
799 if (attr_mask & IB_QP_PORT)
800 qp->port = attr->port_num;
801 if (attr_mask & IB_QP_ALT_PATH)
802 qp->alt_port = attr->alt_port_num;
803
804 if (is_sqp(dev, qp))
805 store_attrs(to_msqp(qp), attr, attr_mask);
806
807 /*
808 * If we moved QP0 to RTR, bring the IB link up; if we moved
809 * QP0 to RESET or ERROR, bring the link back down.
810 */
811 if (is_qp0(dev, qp)) {
812 if (cur_state != IB_QPS_RTR &&
813 new_state == IB_QPS_RTR)
814 init_port(dev, qp->port);
815
816 if (cur_state != IB_QPS_RESET &&
817 cur_state != IB_QPS_ERR &&
818 (new_state == IB_QPS_RESET ||
819 new_state == IB_QPS_ERR))
820 mthca_CLOSE_IB(dev, qp->port, &status);
821 }
822
823 /*
824 * If we moved a kernel QP to RESET, clean up all old CQ
825 * entries and reinitialize the QP.
826 */
827 if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
828 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
829 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
830 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
831 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL);
832
833 mthca_wq_reset(&qp->sq);
834 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
835
836 mthca_wq_reset(&qp->rq);
837 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
838
839 if (mthca_is_memfree(dev)) {
840 *qp->sq.db = 0;
841 *qp->rq.db = 0;
842 }
843 }
844
845 out_mailbox:
846 mthca_free_mailbox(dev, mailbox);
847 out:
848 return err;
849 }
850
851 static const struct ib_qp_attr dummy_init_attr = { .port_num = 1 };
852 static const int dummy_init_attr_mask[] = {
853 [IB_QPT_UD] = (IB_QP_PKEY_INDEX |
854 IB_QP_PORT |
855 IB_QP_QKEY),
856 [IB_QPT_UC] = (IB_QP_PKEY_INDEX |
857 IB_QP_PORT |
858 IB_QP_ACCESS_FLAGS),
859 [IB_QPT_RC] = (IB_QP_PKEY_INDEX |
860 IB_QP_PORT |
861 IB_QP_ACCESS_FLAGS),
862 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX |
863 IB_QP_QKEY),
864 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX |
865 IB_QP_QKEY),
866 };
867
868 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
869 struct ib_udata *udata)
870 {
871 struct mthca_dev *dev = to_mdev(ibqp->device);
872 struct mthca_qp *qp = to_mqp(ibqp);
873 enum ib_qp_state cur_state, new_state;
874 int err = -EINVAL;
875
876 mutex_lock(&qp->mutex);
877 if (attr_mask & IB_QP_CUR_STATE) {
878 cur_state = attr->cur_qp_state;
879 } else {
880 spin_lock_irq(&qp->sq.lock);
881 spin_lock(&qp->rq.lock);
882 cur_state = qp->state;
883 spin_unlock(&qp->rq.lock);
884 spin_unlock_irq(&qp->sq.lock);
885 }
886
887 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
888
889 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
890 mthca_dbg(dev, "Bad QP transition (transport %d) "
891 "%d->%d with attr 0x%08x\n",
892 qp->transport, cur_state, new_state,
893 attr_mask);
894 goto out;
895 }
896
897 if ((attr_mask & IB_QP_PKEY_INDEX) &&
898 attr->pkey_index >= dev->limits.pkey_table_len) {
899 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
900 attr->pkey_index, dev->limits.pkey_table_len-1);
901 goto out;
902 }
903
904 if ((attr_mask & IB_QP_PORT) &&
905 (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
906 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
907 goto out;
908 }
909
910 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
911 attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
912 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
913 attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
914 goto out;
915 }
916
917 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
918 attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
919 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
920 attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
921 goto out;
922 }
923
924 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
925 err = 0;
926 goto out;
927 }
928
929 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) {
930 err = __mthca_modify_qp(ibqp, &dummy_init_attr,
931 dummy_init_attr_mask[ibqp->qp_type],
932 IB_QPS_RESET, IB_QPS_INIT);
933 if (err)
934 goto out;
935 cur_state = IB_QPS_INIT;
936 }
937
938 err = __mthca_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
939
940 out:
941 mutex_unlock(&qp->mutex);
942 return err;
943 }
944
945 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
946 {
947 /*
948 * Calculate the maximum size of WQE s/g segments, excluding
949 * the next segment and other non-data segments.
950 */
951 int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
952
953 switch (qp->transport) {
954 case MLX:
955 max_data_size -= 2 * sizeof (struct mthca_data_seg);
956 break;
957
958 case UD:
959 if (mthca_is_memfree(dev))
960 max_data_size -= sizeof (struct mthca_arbel_ud_seg);
961 else
962 max_data_size -= sizeof (struct mthca_tavor_ud_seg);
963 break;
964
965 default:
966 max_data_size -= sizeof (struct mthca_raddr_seg);
967 break;
968 }
969
970 return max_data_size;
971 }
972
973 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
974 {
975 /* We don't support inline data for kernel QPs (yet). */
976 return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
977 }
978
979 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
980 struct mthca_pd *pd,
981 struct mthca_qp *qp)
982 {
983 int max_data_size = mthca_max_data_size(dev, qp,
984 min(dev->limits.max_desc_sz,
985 1 << qp->sq.wqe_shift));
986
987 qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
988
989 qp->sq.max_gs = min_t(int, dev->limits.max_sg,
990 max_data_size / sizeof (struct mthca_data_seg));
991 qp->rq.max_gs = min_t(int, dev->limits.max_sg,
992 (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
993 sizeof (struct mthca_next_seg)) /
994 sizeof (struct mthca_data_seg));
995 }
996
997 /*
998 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
999 * rq.max_gs and sq.max_gs must all be assigned.
1000 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
1001 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
1002 * queue)
1003 */
1004 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
1005 struct mthca_pd *pd,
1006 struct mthca_qp *qp)
1007 {
1008 int size;
1009 int err = -ENOMEM;
1010
1011 size = sizeof (struct mthca_next_seg) +
1012 qp->rq.max_gs * sizeof (struct mthca_data_seg);
1013
1014 if (size > dev->limits.max_desc_sz)
1015 return -EINVAL;
1016
1017 for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
1018 qp->rq.wqe_shift++)
1019 ; /* nothing */
1020
1021 size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
1022 switch (qp->transport) {
1023 case MLX:
1024 size += 2 * sizeof (struct mthca_data_seg);
1025 break;
1026
1027 case UD:
1028 size += mthca_is_memfree(dev) ?
1029 sizeof (struct mthca_arbel_ud_seg) :
1030 sizeof (struct mthca_tavor_ud_seg);
1031 break;
1032
1033 case UC:
1034 size += sizeof (struct mthca_raddr_seg);
1035 break;
1036
1037 case RC:
1038 size += sizeof (struct mthca_raddr_seg);
1039 /*
1040 * An atomic op will require an atomic segment, a
1041 * remote address segment and one scatter entry.
1042 */
1043 size = max_t(int, size,
1044 sizeof (struct mthca_atomic_seg) +
1045 sizeof (struct mthca_raddr_seg) +
1046 sizeof (struct mthca_data_seg));
1047 break;
1048
1049 default:
1050 break;
1051 }
1052
1053 /* Make sure that we have enough space for a bind request */
1054 size = max_t(int, size, sizeof (struct mthca_bind_seg));
1055
1056 size += sizeof (struct mthca_next_seg);
1057
1058 if (size > dev->limits.max_desc_sz)
1059 return -EINVAL;
1060
1061 for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
1062 qp->sq.wqe_shift++)
1063 ; /* nothing */
1064
1065 qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1066 1 << qp->sq.wqe_shift);
1067
1068 /*
1069 * If this is a userspace QP, we don't actually have to
1070 * allocate anything. All we need is to calculate the WQE
1071 * sizes and the send_wqe_offset, so we're done now.
1072 */
1073 if (pd->ibpd.uobject)
1074 return 0;
1075
1076 size = PAGE_ALIGN(qp->send_wqe_offset +
1077 (qp->sq.max << qp->sq.wqe_shift));
1078
1079 qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1080 GFP_KERNEL);
1081 if (!qp->wrid)
1082 goto err_out;
1083
1084 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1085 &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1086 if (err)
1087 goto err_out;
1088
1089 return 0;
1090
1091 err_out:
1092 kfree(qp->wrid);
1093 return err;
1094 }
1095
1096 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1097 struct mthca_qp *qp)
1098 {
1099 mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1100 (qp->sq.max << qp->sq.wqe_shift)),
1101 &qp->queue, qp->is_direct, &qp->mr);
1102 kfree(qp->wrid);
1103 }
1104
1105 static int mthca_map_memfree(struct mthca_dev *dev,
1106 struct mthca_qp *qp)
1107 {
1108 int ret;
1109
1110 if (mthca_is_memfree(dev)) {
1111 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1112 if (ret)
1113 return ret;
1114
1115 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1116 if (ret)
1117 goto err_qpc;
1118
1119 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1120 qp->qpn << dev->qp_table.rdb_shift);
1121 if (ret)
1122 goto err_eqpc;
1123
1124 }
1125
1126 return 0;
1127
1128 err_eqpc:
1129 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1130
1131 err_qpc:
1132 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1133
1134 return ret;
1135 }
1136
1137 static void mthca_unmap_memfree(struct mthca_dev *dev,
1138 struct mthca_qp *qp)
1139 {
1140 mthca_table_put(dev, dev->qp_table.rdb_table,
1141 qp->qpn << dev->qp_table.rdb_shift);
1142 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1143 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1144 }
1145
1146 static int mthca_alloc_memfree(struct mthca_dev *dev,
1147 struct mthca_qp *qp)
1148 {
1149 if (mthca_is_memfree(dev)) {
1150 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1151 qp->qpn, &qp->rq.db);
1152 if (qp->rq.db_index < 0)
1153 return -ENOMEM;
1154
1155 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1156 qp->qpn, &qp->sq.db);
1157 if (qp->sq.db_index < 0) {
1158 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1159 return -ENOMEM;
1160 }
1161 }
1162
1163 return 0;
1164 }
1165
1166 static void mthca_free_memfree(struct mthca_dev *dev,
1167 struct mthca_qp *qp)
1168 {
1169 if (mthca_is_memfree(dev)) {
1170 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1171 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1172 }
1173 }
1174
1175 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1176 struct mthca_pd *pd,
1177 struct mthca_cq *send_cq,
1178 struct mthca_cq *recv_cq,
1179 enum ib_sig_type send_policy,
1180 struct mthca_qp *qp)
1181 {
1182 int ret;
1183 int i;
1184 struct mthca_next_seg *next;
1185
1186 qp->refcount = 1;
1187 init_waitqueue_head(&qp->wait);
1188 mutex_init(&qp->mutex);
1189 qp->state = IB_QPS_RESET;
1190 qp->atomic_rd_en = 0;
1191 qp->resp_depth = 0;
1192 qp->sq_policy = send_policy;
1193 mthca_wq_reset(&qp->sq);
1194 mthca_wq_reset(&qp->rq);
1195
1196 spin_lock_init(&qp->sq.lock);
1197 spin_lock_init(&qp->rq.lock);
1198
1199 ret = mthca_map_memfree(dev, qp);
1200 if (ret)
1201 return ret;
1202
1203 ret = mthca_alloc_wqe_buf(dev, pd, qp);
1204 if (ret) {
1205 mthca_unmap_memfree(dev, qp);
1206 return ret;
1207 }
1208
1209 mthca_adjust_qp_caps(dev, pd, qp);
1210
1211 /*
1212 * If this is a userspace QP, we're done now. The doorbells
1213 * will be allocated and buffers will be initialized in
1214 * userspace.
1215 */
1216 if (pd->ibpd.uobject)
1217 return 0;
1218
1219 ret = mthca_alloc_memfree(dev, qp);
1220 if (ret) {
1221 mthca_free_wqe_buf(dev, qp);
1222 mthca_unmap_memfree(dev, qp);
1223 return ret;
1224 }
1225
1226 if (mthca_is_memfree(dev)) {
1227 struct mthca_data_seg *scatter;
1228 int size = (sizeof (struct mthca_next_seg) +
1229 qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1230
1231 for (i = 0; i < qp->rq.max; ++i) {
1232 next = get_recv_wqe(qp, i);
1233 next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1234 qp->rq.wqe_shift);
1235 next->ee_nds = cpu_to_be32(size);
1236
1237 for (scatter = (void *) (next + 1);
1238 (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1239 ++scatter)
1240 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1241 }
1242
1243 for (i = 0; i < qp->sq.max; ++i) {
1244 next = get_send_wqe(qp, i);
1245 next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1246 qp->sq.wqe_shift) +
1247 qp->send_wqe_offset);
1248 }
1249 } else {
1250 for (i = 0; i < qp->rq.max; ++i) {
1251 next = get_recv_wqe(qp, i);
1252 next->nda_op = htonl((((i + 1) % qp->rq.max) <<
1253 qp->rq.wqe_shift) | 1);
1254 }
1255
1256 }
1257
1258 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1259 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1260
1261 return 0;
1262 }
1263
1264 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1265 struct mthca_pd *pd, struct mthca_qp *qp)
1266 {
1267 int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1268
1269 /* Sanity check QP size before proceeding */
1270 if (cap->max_send_wr > dev->limits.max_wqes ||
1271 cap->max_recv_wr > dev->limits.max_wqes ||
1272 cap->max_send_sge > dev->limits.max_sg ||
1273 cap->max_recv_sge > dev->limits.max_sg ||
1274 cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1275 return -EINVAL;
1276
1277 /*
1278 * For MLX transport we need 2 extra S/G entries:
1279 * one for the header and one for the checksum at the end
1280 */
1281 if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1282 return -EINVAL;
1283
1284 if (mthca_is_memfree(dev)) {
1285 qp->rq.max = cap->max_recv_wr ?
1286 roundup_pow_of_two(cap->max_recv_wr) : 0;
1287 qp->sq.max = cap->max_send_wr ?
1288 roundup_pow_of_two(cap->max_send_wr) : 0;
1289 } else {
1290 qp->rq.max = cap->max_recv_wr;
1291 qp->sq.max = cap->max_send_wr;
1292 }
1293
1294 qp->rq.max_gs = cap->max_recv_sge;
1295 qp->sq.max_gs = max_t(int, cap->max_send_sge,
1296 ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1297 MTHCA_INLINE_CHUNK_SIZE) /
1298 sizeof (struct mthca_data_seg));
1299
1300 return 0;
1301 }
1302
1303 int mthca_alloc_qp(struct mthca_dev *dev,
1304 struct mthca_pd *pd,
1305 struct mthca_cq *send_cq,
1306 struct mthca_cq *recv_cq,
1307 enum ib_qp_type type,
1308 enum ib_sig_type send_policy,
1309 struct ib_qp_cap *cap,
1310 struct mthca_qp *qp)
1311 {
1312 int err;
1313
1314 switch (type) {
1315 case IB_QPT_RC: qp->transport = RC; break;
1316 case IB_QPT_UC: qp->transport = UC; break;
1317 case IB_QPT_UD: qp->transport = UD; break;
1318 default: return -EINVAL;
1319 }
1320
1321 err = mthca_set_qp_size(dev, cap, pd, qp);
1322 if (err)
1323 return err;
1324
1325 qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1326 if (qp->qpn == -1)
1327 return -ENOMEM;
1328
1329 /* initialize port to zero for error-catching. */
1330 qp->port = 0;
1331
1332 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1333 send_policy, qp);
1334 if (err) {
1335 mthca_free(&dev->qp_table.alloc, qp->qpn);
1336 return err;
1337 }
1338
1339 spin_lock_irq(&dev->qp_table.lock);
1340 mthca_array_set(&dev->qp_table.qp,
1341 qp->qpn & (dev->limits.num_qps - 1), qp);
1342 spin_unlock_irq(&dev->qp_table.lock);
1343
1344 return 0;
1345 }
1346
1347 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1348 {
1349 if (send_cq == recv_cq)
1350 spin_lock_irq(&send_cq->lock);
1351 else if (send_cq->cqn < recv_cq->cqn) {
1352 spin_lock_irq(&send_cq->lock);
1353 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1354 } else {
1355 spin_lock_irq(&recv_cq->lock);
1356 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1357 }
1358 }
1359
1360 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1361 {
1362 if (send_cq == recv_cq)
1363 spin_unlock_irq(&send_cq->lock);
1364 else if (send_cq->cqn < recv_cq->cqn) {
1365 spin_unlock(&recv_cq->lock);
1366 spin_unlock_irq(&send_cq->lock);
1367 } else {
1368 spin_unlock(&send_cq->lock);
1369 spin_unlock_irq(&recv_cq->lock);
1370 }
1371 }
1372
1373 int mthca_alloc_sqp(struct mthca_dev *dev,
1374 struct mthca_pd *pd,
1375 struct mthca_cq *send_cq,
1376 struct mthca_cq *recv_cq,
1377 enum ib_sig_type send_policy,
1378 struct ib_qp_cap *cap,
1379 int qpn,
1380 int port,
1381 struct mthca_sqp *sqp)
1382 {
1383 u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1384 int err;
1385
1386 sqp->qp.transport = MLX;
1387 err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1388 if (err)
1389 return err;
1390
1391 sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1392 sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1393 &sqp->header_dma, GFP_KERNEL);
1394 if (!sqp->header_buf)
1395 return -ENOMEM;
1396
1397 spin_lock_irq(&dev->qp_table.lock);
1398 if (mthca_array_get(&dev->qp_table.qp, mqpn))
1399 err = -EBUSY;
1400 else
1401 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1402 spin_unlock_irq(&dev->qp_table.lock);
1403
1404 if (err)
1405 goto err_out;
1406
1407 sqp->qp.port = port;
1408 sqp->qp.qpn = mqpn;
1409 sqp->qp.transport = MLX;
1410
1411 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1412 send_policy, &sqp->qp);
1413 if (err)
1414 goto err_out_free;
1415
1416 atomic_inc(&pd->sqp_count);
1417
1418 return 0;
1419
1420 err_out_free:
1421 /*
1422 * Lock CQs here, so that CQ polling code can do QP lookup
1423 * without taking a lock.
1424 */
1425 mthca_lock_cqs(send_cq, recv_cq);
1426
1427 spin_lock(&dev->qp_table.lock);
1428 mthca_array_clear(&dev->qp_table.qp, mqpn);
1429 spin_unlock(&dev->qp_table.lock);
1430
1431 mthca_unlock_cqs(send_cq, recv_cq);
1432
1433 err_out:
1434 dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1435 sqp->header_buf, sqp->header_dma);
1436
1437 return err;
1438 }
1439
1440 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1441 {
1442 int c;
1443
1444 spin_lock_irq(&dev->qp_table.lock);
1445 c = qp->refcount;
1446 spin_unlock_irq(&dev->qp_table.lock);
1447
1448 return c;
1449 }
1450
1451 void mthca_free_qp(struct mthca_dev *dev,
1452 struct mthca_qp *qp)
1453 {
1454 u8 status;
1455 struct mthca_cq *send_cq;
1456 struct mthca_cq *recv_cq;
1457
1458 send_cq = to_mcq(qp->ibqp.send_cq);
1459 recv_cq = to_mcq(qp->ibqp.recv_cq);
1460
1461 /*
1462 * Lock CQs here, so that CQ polling code can do QP lookup
1463 * without taking a lock.
1464 */
1465 mthca_lock_cqs(send_cq, recv_cq);
1466
1467 spin_lock(&dev->qp_table.lock);
1468 mthca_array_clear(&dev->qp_table.qp,
1469 qp->qpn & (dev->limits.num_qps - 1));
1470 --qp->refcount;
1471 spin_unlock(&dev->qp_table.lock);
1472
1473 mthca_unlock_cqs(send_cq, recv_cq);
1474
1475 wait_event(qp->wait, !get_qp_refcount(dev, qp));
1476
1477 if (qp->state != IB_QPS_RESET)
1478 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1479 NULL, 0, &status);
1480
1481 /*
1482 * If this is a userspace QP, the buffers, MR, CQs and so on
1483 * will be cleaned up in userspace, so all we have to do is
1484 * unref the mem-free tables and free the QPN in our table.
1485 */
1486 if (!qp->ibqp.uobject) {
1487 mthca_cq_clean(dev, recv_cq, qp->qpn,
1488 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1489 if (send_cq != recv_cq)
1490 mthca_cq_clean(dev, send_cq, qp->qpn, NULL);
1491
1492 mthca_free_memfree(dev, qp);
1493 mthca_free_wqe_buf(dev, qp);
1494 }
1495
1496 mthca_unmap_memfree(dev, qp);
1497
1498 if (is_sqp(dev, qp)) {
1499 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1500 dma_free_coherent(&dev->pdev->dev,
1501 to_msqp(qp)->header_buf_size,
1502 to_msqp(qp)->header_buf,
1503 to_msqp(qp)->header_dma);
1504 } else
1505 mthca_free(&dev->qp_table.alloc, qp->qpn);
1506 }
1507
1508 /* Create UD header for an MLX send and build a data segment for it */
1509 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1510 int ind, struct ib_send_wr *wr,
1511 struct mthca_mlx_seg *mlx,
1512 struct mthca_data_seg *data)
1513 {
1514 int header_size;
1515 int err;
1516 u16 pkey;
1517
1518 ib_ud_header_init(256, /* assume a MAD */
1519 mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1520 &sqp->ud_header);
1521
1522 err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1523 if (err)
1524 return err;
1525 mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1526 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1527 (sqp->ud_header.lrh.destination_lid ==
1528 IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1529 (sqp->ud_header.lrh.service_level << 8));
1530 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1531 mlx->vcrc = 0;
1532
1533 switch (wr->opcode) {
1534 case IB_WR_SEND:
1535 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1536 sqp->ud_header.immediate_present = 0;
1537 break;
1538 case IB_WR_SEND_WITH_IMM:
1539 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1540 sqp->ud_header.immediate_present = 1;
1541 sqp->ud_header.immediate_data = wr->ex.imm_data;
1542 break;
1543 default:
1544 return -EINVAL;
1545 }
1546
1547 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1548 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1549 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1550 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1551 if (!sqp->qp.ibqp.qp_num)
1552 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1553 sqp->pkey_index, &pkey);
1554 else
1555 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1556 wr->wr.ud.pkey_index, &pkey);
1557 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1558 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1559 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1560 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1561 sqp->qkey : wr->wr.ud.remote_qkey);
1562 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1563
1564 header_size = ib_ud_header_pack(&sqp->ud_header,
1565 sqp->header_buf +
1566 ind * MTHCA_UD_HEADER_SIZE);
1567
1568 data->byte_count = cpu_to_be32(header_size);
1569 data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1570 data->addr = cpu_to_be64(sqp->header_dma +
1571 ind * MTHCA_UD_HEADER_SIZE);
1572
1573 return 0;
1574 }
1575
1576 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1577 struct ib_cq *ib_cq)
1578 {
1579 unsigned cur;
1580 struct mthca_cq *cq;
1581
1582 cur = wq->head - wq->tail;
1583 if (likely(cur + nreq < wq->max))
1584 return 0;
1585
1586 cq = to_mcq(ib_cq);
1587 spin_lock(&cq->lock);
1588 cur = wq->head - wq->tail;
1589 spin_unlock(&cq->lock);
1590
1591 return cur + nreq >= wq->max;
1592 }
1593
1594 static __always_inline void set_raddr_seg(struct mthca_raddr_seg *rseg,
1595 u64 remote_addr, u32 rkey)
1596 {
1597 rseg->raddr = cpu_to_be64(remote_addr);
1598 rseg->rkey = cpu_to_be32(rkey);
1599 rseg->reserved = 0;
1600 }
1601
1602 static __always_inline void set_atomic_seg(struct mthca_atomic_seg *aseg,
1603 struct ib_send_wr *wr)
1604 {
1605 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1606 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1607 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
1608 } else {
1609 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1610 aseg->compare = 0;
1611 }
1612
1613 }
1614
1615 static void set_tavor_ud_seg(struct mthca_tavor_ud_seg *useg,
1616 struct ib_send_wr *wr)
1617 {
1618 useg->lkey = cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1619 useg->av_addr = cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1620 useg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1621 useg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1622
1623 }
1624
1625 static void set_arbel_ud_seg(struct mthca_arbel_ud_seg *useg,
1626 struct ib_send_wr *wr)
1627 {
1628 memcpy(useg->av, to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1629 useg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1630 useg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1631 }
1632
1633 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1634 struct ib_send_wr **bad_wr)
1635 {
1636 struct mthca_dev *dev = to_mdev(ibqp->device);
1637 struct mthca_qp *qp = to_mqp(ibqp);
1638 void *wqe;
1639 void *prev_wqe;
1640 unsigned long flags;
1641 int err = 0;
1642 int nreq;
1643 int i;
1644 int size;
1645 /*
1646 * f0 and size0 are only used if nreq != 0, and they will
1647 * always be initialized the first time through the main loop
1648 * before nreq is incremented. So nreq cannot become non-zero
1649 * without initializing f0 and size0, and they are in fact
1650 * never used uninitialized.
1651 */
1652 int uninitialized_var(size0);
1653 u32 uninitialized_var(f0);
1654 int ind;
1655 u8 op0 = 0;
1656
1657 spin_lock_irqsave(&qp->sq.lock, flags);
1658
1659 /* XXX check that state is OK to post send */
1660
1661 ind = qp->sq.next_ind;
1662
1663 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1664 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1665 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1666 " %d max, %d nreq)\n", qp->qpn,
1667 qp->sq.head, qp->sq.tail,
1668 qp->sq.max, nreq);
1669 err = -ENOMEM;
1670 *bad_wr = wr;
1671 goto out;
1672 }
1673
1674 wqe = get_send_wqe(qp, ind);
1675 prev_wqe = qp->sq.last;
1676 qp->sq.last = wqe;
1677
1678 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1679 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1680 ((struct mthca_next_seg *) wqe)->flags =
1681 ((wr->send_flags & IB_SEND_SIGNALED) ?
1682 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1683 ((wr->send_flags & IB_SEND_SOLICITED) ?
1684 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1685 cpu_to_be32(1);
1686 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1687 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1688 ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
1689
1690 wqe += sizeof (struct mthca_next_seg);
1691 size = sizeof (struct mthca_next_seg) / 16;
1692
1693 switch (qp->transport) {
1694 case RC:
1695 switch (wr->opcode) {
1696 case IB_WR_ATOMIC_CMP_AND_SWP:
1697 case IB_WR_ATOMIC_FETCH_AND_ADD:
1698 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1699 wr->wr.atomic.rkey);
1700 wqe += sizeof (struct mthca_raddr_seg);
1701
1702 set_atomic_seg(wqe, wr);
1703 wqe += sizeof (struct mthca_atomic_seg);
1704 size += (sizeof (struct mthca_raddr_seg) +
1705 sizeof (struct mthca_atomic_seg)) / 16;
1706 break;
1707
1708 case IB_WR_RDMA_WRITE:
1709 case IB_WR_RDMA_WRITE_WITH_IMM:
1710 case IB_WR_RDMA_READ:
1711 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1712 wr->wr.rdma.rkey);
1713 wqe += sizeof (struct mthca_raddr_seg);
1714 size += sizeof (struct mthca_raddr_seg) / 16;
1715 break;
1716
1717 default:
1718 /* No extra segments required for sends */
1719 break;
1720 }
1721
1722 break;
1723
1724 case UC:
1725 switch (wr->opcode) {
1726 case IB_WR_RDMA_WRITE:
1727 case IB_WR_RDMA_WRITE_WITH_IMM:
1728 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1729 wr->wr.rdma.rkey);
1730 wqe += sizeof (struct mthca_raddr_seg);
1731 size += sizeof (struct mthca_raddr_seg) / 16;
1732 break;
1733
1734 default:
1735 /* No extra segments required for sends */
1736 break;
1737 }
1738
1739 break;
1740
1741 case UD:
1742 set_tavor_ud_seg(wqe, wr);
1743 wqe += sizeof (struct mthca_tavor_ud_seg);
1744 size += sizeof (struct mthca_tavor_ud_seg) / 16;
1745 break;
1746
1747 case MLX:
1748 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1749 wqe - sizeof (struct mthca_next_seg),
1750 wqe);
1751 if (err) {
1752 *bad_wr = wr;
1753 goto out;
1754 }
1755 wqe += sizeof (struct mthca_data_seg);
1756 size += sizeof (struct mthca_data_seg) / 16;
1757 break;
1758 }
1759
1760 if (wr->num_sge > qp->sq.max_gs) {
1761 mthca_err(dev, "too many gathers\n");
1762 err = -EINVAL;
1763 *bad_wr = wr;
1764 goto out;
1765 }
1766
1767 for (i = 0; i < wr->num_sge; ++i) {
1768 mthca_set_data_seg(wqe, wr->sg_list + i);
1769 wqe += sizeof (struct mthca_data_seg);
1770 size += sizeof (struct mthca_data_seg) / 16;
1771 }
1772
1773 /* Add one more inline data segment for ICRC */
1774 if (qp->transport == MLX) {
1775 ((struct mthca_data_seg *) wqe)->byte_count =
1776 cpu_to_be32((1 << 31) | 4);
1777 ((u32 *) wqe)[1] = 0;
1778 wqe += sizeof (struct mthca_data_seg);
1779 size += sizeof (struct mthca_data_seg) / 16;
1780 }
1781
1782 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1783
1784 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1785 mthca_err(dev, "opcode invalid\n");
1786 err = -EINVAL;
1787 *bad_wr = wr;
1788 goto out;
1789 }
1790
1791 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1792 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1793 qp->send_wqe_offset) |
1794 mthca_opcode[wr->opcode]);
1795 wmb();
1796 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1797 cpu_to_be32((nreq ? 0 : MTHCA_NEXT_DBD) | size |
1798 ((wr->send_flags & IB_SEND_FENCE) ?
1799 MTHCA_NEXT_FENCE : 0));
1800
1801 if (!nreq) {
1802 size0 = size;
1803 op0 = mthca_opcode[wr->opcode];
1804 f0 = wr->send_flags & IB_SEND_FENCE ?
1805 MTHCA_SEND_DOORBELL_FENCE : 0;
1806 }
1807
1808 ++ind;
1809 if (unlikely(ind >= qp->sq.max))
1810 ind -= qp->sq.max;
1811 }
1812
1813 out:
1814 if (likely(nreq)) {
1815 wmb();
1816
1817 mthca_write64(((qp->sq.next_ind << qp->sq.wqe_shift) +
1818 qp->send_wqe_offset) | f0 | op0,
1819 (qp->qpn << 8) | size0,
1820 dev->kar + MTHCA_SEND_DOORBELL,
1821 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1822 /*
1823 * Make sure doorbells don't leak out of SQ spinlock
1824 * and reach the HCA out of order:
1825 */
1826 mmiowb();
1827 }
1828
1829 qp->sq.next_ind = ind;
1830 qp->sq.head += nreq;
1831
1832 spin_unlock_irqrestore(&qp->sq.lock, flags);
1833 return err;
1834 }
1835
1836 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1837 struct ib_recv_wr **bad_wr)
1838 {
1839 struct mthca_dev *dev = to_mdev(ibqp->device);
1840 struct mthca_qp *qp = to_mqp(ibqp);
1841 unsigned long flags;
1842 int err = 0;
1843 int nreq;
1844 int i;
1845 int size;
1846 /*
1847 * size0 is only used if nreq != 0, and it will always be
1848 * initialized the first time through the main loop before
1849 * nreq is incremented. So nreq cannot become non-zero
1850 * without initializing size0, and it is in fact never used
1851 * uninitialized.
1852 */
1853 int uninitialized_var(size0);
1854 int ind;
1855 void *wqe;
1856 void *prev_wqe;
1857
1858 spin_lock_irqsave(&qp->rq.lock, flags);
1859
1860 /* XXX check that state is OK to post receive */
1861
1862 ind = qp->rq.next_ind;
1863
1864 for (nreq = 0; wr; wr = wr->next) {
1865 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1866 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1867 " %d max, %d nreq)\n", qp->qpn,
1868 qp->rq.head, qp->rq.tail,
1869 qp->rq.max, nreq);
1870 err = -ENOMEM;
1871 *bad_wr = wr;
1872 goto out;
1873 }
1874
1875 wqe = get_recv_wqe(qp, ind);
1876 prev_wqe = qp->rq.last;
1877 qp->rq.last = wqe;
1878
1879 ((struct mthca_next_seg *) wqe)->ee_nds =
1880 cpu_to_be32(MTHCA_NEXT_DBD);
1881 ((struct mthca_next_seg *) wqe)->flags = 0;
1882
1883 wqe += sizeof (struct mthca_next_seg);
1884 size = sizeof (struct mthca_next_seg) / 16;
1885
1886 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1887 err = -EINVAL;
1888 *bad_wr = wr;
1889 goto out;
1890 }
1891
1892 for (i = 0; i < wr->num_sge; ++i) {
1893 mthca_set_data_seg(wqe, wr->sg_list + i);
1894 wqe += sizeof (struct mthca_data_seg);
1895 size += sizeof (struct mthca_data_seg) / 16;
1896 }
1897
1898 qp->wrid[ind] = wr->wr_id;
1899
1900 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1901 cpu_to_be32(MTHCA_NEXT_DBD | size);
1902
1903 if (!nreq)
1904 size0 = size;
1905
1906 ++ind;
1907 if (unlikely(ind >= qp->rq.max))
1908 ind -= qp->rq.max;
1909
1910 ++nreq;
1911 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1912 nreq = 0;
1913
1914 wmb();
1915
1916 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1917 qp->qpn << 8, dev->kar + MTHCA_RECEIVE_DOORBELL,
1918 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1919
1920 qp->rq.next_ind = ind;
1921 qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1922 }
1923 }
1924
1925 out:
1926 if (likely(nreq)) {
1927 wmb();
1928
1929 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1930 qp->qpn << 8 | nreq, dev->kar + MTHCA_RECEIVE_DOORBELL,
1931 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1932 }
1933
1934 qp->rq.next_ind = ind;
1935 qp->rq.head += nreq;
1936
1937 /*
1938 * Make sure doorbells don't leak out of RQ spinlock and reach
1939 * the HCA out of order:
1940 */
1941 mmiowb();
1942
1943 spin_unlock_irqrestore(&qp->rq.lock, flags);
1944 return err;
1945 }
1946
1947 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1948 struct ib_send_wr **bad_wr)
1949 {
1950 struct mthca_dev *dev = to_mdev(ibqp->device);
1951 struct mthca_qp *qp = to_mqp(ibqp);
1952 u32 dbhi;
1953 void *wqe;
1954 void *prev_wqe;
1955 unsigned long flags;
1956 int err = 0;
1957 int nreq;
1958 int i;
1959 int size;
1960 /*
1961 * f0 and size0 are only used if nreq != 0, and they will
1962 * always be initialized the first time through the main loop
1963 * before nreq is incremented. So nreq cannot become non-zero
1964 * without initializing f0 and size0, and they are in fact
1965 * never used uninitialized.
1966 */
1967 int uninitialized_var(size0);
1968 u32 uninitialized_var(f0);
1969 int ind;
1970 u8 op0 = 0;
1971
1972 spin_lock_irqsave(&qp->sq.lock, flags);
1973
1974 /* XXX check that state is OK to post send */
1975
1976 ind = qp->sq.head & (qp->sq.max - 1);
1977
1978 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1979 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1980 nreq = 0;
1981
1982 dbhi = (MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1983 ((qp->sq.head & 0xffff) << 8) | f0 | op0;
1984
1985 qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1986
1987 /*
1988 * Make sure that descriptors are written before
1989 * doorbell record.
1990 */
1991 wmb();
1992 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1993
1994 /*
1995 * Make sure doorbell record is written before we
1996 * write MMIO send doorbell.
1997 */
1998 wmb();
1999
2000 mthca_write64(dbhi, (qp->qpn << 8) | size0,
2001 dev->kar + MTHCA_SEND_DOORBELL,
2002 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2003 }
2004
2005 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2006 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
2007 " %d max, %d nreq)\n", qp->qpn,
2008 qp->sq.head, qp->sq.tail,
2009 qp->sq.max, nreq);
2010 err = -ENOMEM;
2011 *bad_wr = wr;
2012 goto out;
2013 }
2014
2015 wqe = get_send_wqe(qp, ind);
2016 prev_wqe = qp->sq.last;
2017 qp->sq.last = wqe;
2018
2019 ((struct mthca_next_seg *) wqe)->flags =
2020 ((wr->send_flags & IB_SEND_SIGNALED) ?
2021 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
2022 ((wr->send_flags & IB_SEND_SOLICITED) ?
2023 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
2024 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2025 cpu_to_be32(MTHCA_NEXT_IP_CSUM | MTHCA_NEXT_TCP_UDP_CSUM) : 0) |
2026 cpu_to_be32(1);
2027 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
2028 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
2029 ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
2030
2031 wqe += sizeof (struct mthca_next_seg);
2032 size = sizeof (struct mthca_next_seg) / 16;
2033
2034 switch (qp->transport) {
2035 case RC:
2036 switch (wr->opcode) {
2037 case IB_WR_ATOMIC_CMP_AND_SWP:
2038 case IB_WR_ATOMIC_FETCH_AND_ADD:
2039 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2040 wr->wr.atomic.rkey);
2041 wqe += sizeof (struct mthca_raddr_seg);
2042
2043 set_atomic_seg(wqe, wr);
2044 wqe += sizeof (struct mthca_atomic_seg);
2045 size += (sizeof (struct mthca_raddr_seg) +
2046 sizeof (struct mthca_atomic_seg)) / 16;
2047 break;
2048
2049 case IB_WR_RDMA_READ:
2050 case IB_WR_RDMA_WRITE:
2051 case IB_WR_RDMA_WRITE_WITH_IMM:
2052 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2053 wr->wr.rdma.rkey);
2054 wqe += sizeof (struct mthca_raddr_seg);
2055 size += sizeof (struct mthca_raddr_seg) / 16;
2056 break;
2057
2058 default:
2059 /* No extra segments required for sends */
2060 break;
2061 }
2062
2063 break;
2064
2065 case UC:
2066 switch (wr->opcode) {
2067 case IB_WR_RDMA_WRITE:
2068 case IB_WR_RDMA_WRITE_WITH_IMM:
2069 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2070 wr->wr.rdma.rkey);
2071 wqe += sizeof (struct mthca_raddr_seg);
2072 size += sizeof (struct mthca_raddr_seg) / 16;
2073 break;
2074
2075 default:
2076 /* No extra segments required for sends */
2077 break;
2078 }
2079
2080 break;
2081
2082 case UD:
2083 set_arbel_ud_seg(wqe, wr);
2084 wqe += sizeof (struct mthca_arbel_ud_seg);
2085 size += sizeof (struct mthca_arbel_ud_seg) / 16;
2086 break;
2087
2088 case MLX:
2089 err = build_mlx_header(dev, to_msqp(qp), ind, wr,
2090 wqe - sizeof (struct mthca_next_seg),
2091 wqe);
2092 if (err) {
2093 *bad_wr = wr;
2094 goto out;
2095 }
2096 wqe += sizeof (struct mthca_data_seg);
2097 size += sizeof (struct mthca_data_seg) / 16;
2098 break;
2099 }
2100
2101 if (wr->num_sge > qp->sq.max_gs) {
2102 mthca_err(dev, "too many gathers\n");
2103 err = -EINVAL;
2104 *bad_wr = wr;
2105 goto out;
2106 }
2107
2108 for (i = 0; i < wr->num_sge; ++i) {
2109 mthca_set_data_seg(wqe, wr->sg_list + i);
2110 wqe += sizeof (struct mthca_data_seg);
2111 size += sizeof (struct mthca_data_seg) / 16;
2112 }
2113
2114 /* Add one more inline data segment for ICRC */
2115 if (qp->transport == MLX) {
2116 ((struct mthca_data_seg *) wqe)->byte_count =
2117 cpu_to_be32((1 << 31) | 4);
2118 ((u32 *) wqe)[1] = 0;
2119 wqe += sizeof (struct mthca_data_seg);
2120 size += sizeof (struct mthca_data_seg) / 16;
2121 }
2122
2123 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2124
2125 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2126 mthca_err(dev, "opcode invalid\n");
2127 err = -EINVAL;
2128 *bad_wr = wr;
2129 goto out;
2130 }
2131
2132 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2133 cpu_to_be32(((ind << qp->sq.wqe_shift) +
2134 qp->send_wqe_offset) |
2135 mthca_opcode[wr->opcode]);
2136 wmb();
2137 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2138 cpu_to_be32(MTHCA_NEXT_DBD | size |
2139 ((wr->send_flags & IB_SEND_FENCE) ?
2140 MTHCA_NEXT_FENCE : 0));
2141
2142 if (!nreq) {
2143 size0 = size;
2144 op0 = mthca_opcode[wr->opcode];
2145 f0 = wr->send_flags & IB_SEND_FENCE ?
2146 MTHCA_SEND_DOORBELL_FENCE : 0;
2147 }
2148
2149 ++ind;
2150 if (unlikely(ind >= qp->sq.max))
2151 ind -= qp->sq.max;
2152 }
2153
2154 out:
2155 if (likely(nreq)) {
2156 dbhi = (nreq << 24) | ((qp->sq.head & 0xffff) << 8) | f0 | op0;
2157
2158 qp->sq.head += nreq;
2159
2160 /*
2161 * Make sure that descriptors are written before
2162 * doorbell record.
2163 */
2164 wmb();
2165 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2166
2167 /*
2168 * Make sure doorbell record is written before we
2169 * write MMIO send doorbell.
2170 */
2171 wmb();
2172
2173 mthca_write64(dbhi, (qp->qpn << 8) | size0, dev->kar + MTHCA_SEND_DOORBELL,
2174 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2175 }
2176
2177 /*
2178 * Make sure doorbells don't leak out of SQ spinlock and reach
2179 * the HCA out of order:
2180 */
2181 mmiowb();
2182
2183 spin_unlock_irqrestore(&qp->sq.lock, flags);
2184 return err;
2185 }
2186
2187 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2188 struct ib_recv_wr **bad_wr)
2189 {
2190 struct mthca_dev *dev = to_mdev(ibqp->device);
2191 struct mthca_qp *qp = to_mqp(ibqp);
2192 unsigned long flags;
2193 int err = 0;
2194 int nreq;
2195 int ind;
2196 int i;
2197 void *wqe;
2198
2199 spin_lock_irqsave(&qp->rq.lock, flags);
2200
2201 /* XXX check that state is OK to post receive */
2202
2203 ind = qp->rq.head & (qp->rq.max - 1);
2204
2205 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2206 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2207 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2208 " %d max, %d nreq)\n", qp->qpn,
2209 qp->rq.head, qp->rq.tail,
2210 qp->rq.max, nreq);
2211 err = -ENOMEM;
2212 *bad_wr = wr;
2213 goto out;
2214 }
2215
2216 wqe = get_recv_wqe(qp, ind);
2217
2218 ((struct mthca_next_seg *) wqe)->flags = 0;
2219
2220 wqe += sizeof (struct mthca_next_seg);
2221
2222 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2223 err = -EINVAL;
2224 *bad_wr = wr;
2225 goto out;
2226 }
2227
2228 for (i = 0; i < wr->num_sge; ++i) {
2229 mthca_set_data_seg(wqe, wr->sg_list + i);
2230 wqe += sizeof (struct mthca_data_seg);
2231 }
2232
2233 if (i < qp->rq.max_gs)
2234 mthca_set_data_seg_inval(wqe);
2235
2236 qp->wrid[ind] = wr->wr_id;
2237
2238 ++ind;
2239 if (unlikely(ind >= qp->rq.max))
2240 ind -= qp->rq.max;
2241 }
2242 out:
2243 if (likely(nreq)) {
2244 qp->rq.head += nreq;
2245
2246 /*
2247 * Make sure that descriptors are written before
2248 * doorbell record.
2249 */
2250 wmb();
2251 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2252 }
2253
2254 spin_unlock_irqrestore(&qp->rq.lock, flags);
2255 return err;
2256 }
2257
2258 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2259 int index, int *dbd, __be32 *new_wqe)
2260 {
2261 struct mthca_next_seg *next;
2262
2263 /*
2264 * For SRQs, all receive WQEs generate a CQE, so we're always
2265 * at the end of the doorbell chain.
2266 */
2267 if (qp->ibqp.srq && !is_send) {
2268 *new_wqe = 0;
2269 return;
2270 }
2271
2272 if (is_send)
2273 next = get_send_wqe(qp, index);
2274 else
2275 next = get_recv_wqe(qp, index);
2276
2277 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2278 if (next->ee_nds & cpu_to_be32(0x3f))
2279 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2280 (next->ee_nds & cpu_to_be32(0x3f));
2281 else
2282 *new_wqe = 0;
2283 }
2284
2285 int mthca_init_qp_table(struct mthca_dev *dev)
2286 {
2287 int err;
2288 u8 status;
2289 int i;
2290
2291 spin_lock_init(&dev->qp_table.lock);
2292
2293 /*
2294 * We reserve 2 extra QPs per port for the special QPs. The
2295 * special QP for port 1 has to be even, so round up.
2296 */
2297 dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2298 err = mthca_alloc_init(&dev->qp_table.alloc,
2299 dev->limits.num_qps,
2300 (1 << 24) - 1,
2301 dev->qp_table.sqp_start +
2302 MTHCA_MAX_PORTS * 2);
2303 if (err)
2304 return err;
2305
2306 err = mthca_array_init(&dev->qp_table.qp,
2307 dev->limits.num_qps);
2308 if (err) {
2309 mthca_alloc_cleanup(&dev->qp_table.alloc);
2310 return err;
2311 }
2312
2313 for (i = 0; i < 2; ++i) {
2314 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2315 dev->qp_table.sqp_start + i * 2,
2316 &status);
2317 if (err)
2318 goto err_out;
2319 if (status) {
2320 mthca_warn(dev, "CONF_SPECIAL_QP returned "
2321 "status %02x, aborting.\n",
2322 status);
2323 err = -EINVAL;
2324 goto err_out;
2325 }
2326 }
2327 return 0;
2328
2329 err_out:
2330 for (i = 0; i < 2; ++i)
2331 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2332
2333 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2334 mthca_alloc_cleanup(&dev->qp_table.alloc);
2335
2336 return err;
2337 }
2338
2339 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2340 {
2341 int i;
2342 u8 status;
2343
2344 for (i = 0; i < 2; ++i)
2345 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2346
2347 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2348 mthca_alloc_cleanup(&dev->qp_table.alloc);
2349 }
Linux 2.6 libata-dev (mirror)