2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/completion.h>
36 #include <linux/pci.h>
37 #include <linux/errno.h>
38 #include <linux/sched.h>
40 #include <rdma/ib_mad.h>
42 #include "mthca_dev.h"
43 #include "mthca_config_reg.h"
44 #include "mthca_cmd.h"
45 #include "mthca_memfree.h"
47 #define CMD_POLL_TOKEN 0xffff
50 HCR_IN_PARAM_OFFSET
= 0x00,
51 HCR_IN_MODIFIER_OFFSET
= 0x08,
52 HCR_OUT_PARAM_OFFSET
= 0x0c,
53 HCR_TOKEN_OFFSET
= 0x14,
54 HCR_STATUS_OFFSET
= 0x18,
62 /* initialization and general commands */
68 CMD_MOD_STAT_CFG
= 0x34,
69 CMD_QUERY_DEV_LIM
= 0x3,
71 CMD_ENABLE_LAM
= 0xff8,
72 CMD_DISABLE_LAM
= 0xff7,
74 CMD_QUERY_ADAPTER
= 0x6,
81 CMD_ACCESS_DDR
= 0x2e,
83 CMD_UNMAP_ICM
= 0xff9,
84 CMD_MAP_ICM_AUX
= 0xffc,
85 CMD_UNMAP_ICM_AUX
= 0xffb,
86 CMD_SET_ICM_SIZE
= 0xffd,
106 CMD_RESIZE_CQ
= 0x2c,
109 CMD_SW2HW_SRQ
= 0x35,
110 CMD_HW2SW_SRQ
= 0x36,
111 CMD_QUERY_SRQ
= 0x37,
115 CMD_RST2INIT_QPEE
= 0x19,
116 CMD_INIT2RTR_QPEE
= 0x1a,
117 CMD_RTR2RTS_QPEE
= 0x1b,
118 CMD_RTS2RTS_QPEE
= 0x1c,
119 CMD_SQERR2RTS_QPEE
= 0x1d,
120 CMD_2ERR_QPEE
= 0x1e,
121 CMD_RTS2SQD_QPEE
= 0x1f,
122 CMD_SQD2SQD_QPEE
= 0x38,
123 CMD_SQD2RTS_QPEE
= 0x20,
124 CMD_ERR2RST_QPEE
= 0x21,
125 CMD_QUERY_QPEE
= 0x22,
126 CMD_INIT2INIT_QPEE
= 0x2d,
127 CMD_SUSPEND_QPEE
= 0x32,
128 CMD_UNSUSPEND_QPEE
= 0x33,
129 /* special QPs and management commands */
130 CMD_CONF_SPECIAL_QP
= 0x23,
133 /* multicast commands */
135 CMD_WRITE_MGM
= 0x26,
136 CMD_MGID_HASH
= 0x27,
138 /* miscellaneous commands */
139 CMD_DIAG_RPRT
= 0x30,
143 CMD_QUERY_DEBUG_MSG
= 0x2a,
144 CMD_SET_DEBUG_MSG
= 0x2b,
148 * According to Mellanox code, FW may be starved and never complete
149 * commands. So we can't use strict timeouts described in PRM -- we
150 * just arbitrarily select 60 seconds for now.
154 * Round up and add 1 to make sure we get the full wait time (since we
155 * will be starting in the middle of a jiffy)
158 CMD_TIME_CLASS_A
= (HZ
+ 999) / 1000 + 1,
159 CMD_TIME_CLASS_B
= (HZ
+ 99) / 100 + 1,
160 CMD_TIME_CLASS_C
= (HZ
+ 9) / 10 + 1
164 CMD_TIME_CLASS_A
= 60 * HZ
,
165 CMD_TIME_CLASS_B
= 60 * HZ
,
166 CMD_TIME_CLASS_C
= 60 * HZ
171 GO_BIT_TIMEOUT
= HZ
* 10
174 struct mthca_cmd_context
{
175 struct completion done
;
183 static int fw_cmd_doorbell
= 0;
184 module_param(fw_cmd_doorbell
, int, 0644);
185 MODULE_PARM_DESC(fw_cmd_doorbell
, "post FW commands through doorbell page if nonzero "
186 "(and supported by FW)");
188 static inline int go_bit(struct mthca_dev
*dev
)
190 return readl(dev
->hcr
+ HCR_STATUS_OFFSET
) &
191 swab32(1 << HCR_GO_BIT
);
194 static void mthca_cmd_post_dbell(struct mthca_dev
*dev
,
202 void __iomem
*ptr
= dev
->cmd
.dbell_map
;
203 u16
*offs
= dev
->cmd
.dbell_offsets
;
205 __raw_writel((__force u32
) cpu_to_be32(in_param
>> 32), ptr
+ offs
[0]);
207 __raw_writel((__force u32
) cpu_to_be32(in_param
& 0xfffffffful
), ptr
+ offs
[1]);
209 __raw_writel((__force u32
) cpu_to_be32(in_modifier
), ptr
+ offs
[2]);
211 __raw_writel((__force u32
) cpu_to_be32(out_param
>> 32), ptr
+ offs
[3]);
213 __raw_writel((__force u32
) cpu_to_be32(out_param
& 0xfffffffful
), ptr
+ offs
[4]);
215 __raw_writel((__force u32
) cpu_to_be32(token
<< 16), ptr
+ offs
[5]);
217 __raw_writel((__force u32
) cpu_to_be32((1 << HCR_GO_BIT
) |
219 (op_modifier
<< HCR_OPMOD_SHIFT
) |
222 __raw_writel((__force u32
) 0, ptr
+ offs
[7]);
226 static int mthca_cmd_post_hcr(struct mthca_dev
*dev
,
236 unsigned long end
= jiffies
+ GO_BIT_TIMEOUT
;
238 while (go_bit(dev
) && time_before(jiffies
, end
)) {
239 set_current_state(TASK_RUNNING
);
248 * We use writel (instead of something like memcpy_toio)
249 * because writes of less than 32 bits to the HCR don't work
250 * (and some architectures such as ia64 implement memcpy_toio
251 * in terms of writeb).
253 __raw_writel((__force u32
) cpu_to_be32(in_param
>> 32), dev
->hcr
+ 0 * 4);
254 __raw_writel((__force u32
) cpu_to_be32(in_param
& 0xfffffffful
), dev
->hcr
+ 1 * 4);
255 __raw_writel((__force u32
) cpu_to_be32(in_modifier
), dev
->hcr
+ 2 * 4);
256 __raw_writel((__force u32
) cpu_to_be32(out_param
>> 32), dev
->hcr
+ 3 * 4);
257 __raw_writel((__force u32
) cpu_to_be32(out_param
& 0xfffffffful
), dev
->hcr
+ 4 * 4);
258 __raw_writel((__force u32
) cpu_to_be32(token
<< 16), dev
->hcr
+ 5 * 4);
260 /* __raw_writel may not order writes. */
263 __raw_writel((__force u32
) cpu_to_be32((1 << HCR_GO_BIT
) |
264 (event
? (1 << HCA_E_BIT
) : 0) |
265 (op_modifier
<< HCR_OPMOD_SHIFT
) |
266 op
), dev
->hcr
+ 6 * 4);
271 static int mthca_cmd_post(struct mthca_dev
*dev
,
282 mutex_lock(&dev
->cmd
.hcr_mutex
);
284 if (event
&& dev
->cmd
.flags
& MTHCA_CMD_POST_DOORBELLS
&& fw_cmd_doorbell
)
285 mthca_cmd_post_dbell(dev
, in_param
, out_param
, in_modifier
,
286 op_modifier
, op
, token
);
288 err
= mthca_cmd_post_hcr(dev
, in_param
, out_param
, in_modifier
,
289 op_modifier
, op
, token
, event
);
292 * Make sure that our HCR writes don't get mixed in with
293 * writes from another CPU starting a FW command.
297 mutex_unlock(&dev
->cmd
.hcr_mutex
);
301 static int mthca_cmd_poll(struct mthca_dev
*dev
,
308 unsigned long timeout
,
314 down(&dev
->cmd
.poll_sem
);
316 err
= mthca_cmd_post(dev
, in_param
,
317 out_param
? *out_param
: 0,
318 in_modifier
, op_modifier
,
319 op
, CMD_POLL_TOKEN
, 0);
323 end
= timeout
+ jiffies
;
324 while (go_bit(dev
) && time_before(jiffies
, end
)) {
325 set_current_state(TASK_RUNNING
);
336 (u64
) be32_to_cpu((__force __be32
)
337 __raw_readl(dev
->hcr
+ HCR_OUT_PARAM_OFFSET
)) << 32 |
338 (u64
) be32_to_cpu((__force __be32
)
339 __raw_readl(dev
->hcr
+ HCR_OUT_PARAM_OFFSET
+ 4));
341 *status
= be32_to_cpu((__force __be32
) __raw_readl(dev
->hcr
+ HCR_STATUS_OFFSET
)) >> 24;
344 up(&dev
->cmd
.poll_sem
);
348 void mthca_cmd_event(struct mthca_dev
*dev
,
353 struct mthca_cmd_context
*context
=
354 &dev
->cmd
.context
[token
& dev
->cmd
.token_mask
];
356 /* previously timed out command completing at long last */
357 if (token
!= context
->token
)
361 context
->status
= status
;
362 context
->out_param
= out_param
;
364 complete(&context
->done
);
367 static int mthca_cmd_wait(struct mthca_dev
*dev
,
374 unsigned long timeout
,
378 struct mthca_cmd_context
*context
;
380 down(&dev
->cmd
.event_sem
);
382 spin_lock(&dev
->cmd
.context_lock
);
383 BUG_ON(dev
->cmd
.free_head
< 0);
384 context
= &dev
->cmd
.context
[dev
->cmd
.free_head
];
385 context
->token
+= dev
->cmd
.token_mask
+ 1;
386 dev
->cmd
.free_head
= context
->next
;
387 spin_unlock(&dev
->cmd
.context_lock
);
389 init_completion(&context
->done
);
391 err
= mthca_cmd_post(dev
, in_param
,
392 out_param
? *out_param
: 0,
393 in_modifier
, op_modifier
,
394 op
, context
->token
, 1);
398 if (!wait_for_completion_timeout(&context
->done
, timeout
)) {
403 err
= context
->result
;
407 *status
= context
->status
;
409 mthca_dbg(dev
, "Command %02x completed with status %02x\n",
413 *out_param
= context
->out_param
;
416 spin_lock(&dev
->cmd
.context_lock
);
417 context
->next
= dev
->cmd
.free_head
;
418 dev
->cmd
.free_head
= context
- dev
->cmd
.context
;
419 spin_unlock(&dev
->cmd
.context_lock
);
421 up(&dev
->cmd
.event_sem
);
425 /* Invoke a command with an output mailbox */
426 static int mthca_cmd_box(struct mthca_dev
*dev
,
432 unsigned long timeout
,
435 if (dev
->cmd
.flags
& MTHCA_CMD_USE_EVENTS
)
436 return mthca_cmd_wait(dev
, in_param
, &out_param
, 0,
437 in_modifier
, op_modifier
, op
,
440 return mthca_cmd_poll(dev
, in_param
, &out_param
, 0,
441 in_modifier
, op_modifier
, op
,
445 /* Invoke a command with no output parameter */
446 static int mthca_cmd(struct mthca_dev
*dev
,
451 unsigned long timeout
,
454 return mthca_cmd_box(dev
, in_param
, 0, in_modifier
,
455 op_modifier
, op
, timeout
, status
);
459 * Invoke a command with an immediate output parameter (and copy the
460 * output into the caller's out_param pointer after the command
463 static int mthca_cmd_imm(struct mthca_dev
*dev
,
469 unsigned long timeout
,
472 if (dev
->cmd
.flags
& MTHCA_CMD_USE_EVENTS
)
473 return mthca_cmd_wait(dev
, in_param
, out_param
, 1,
474 in_modifier
, op_modifier
, op
,
477 return mthca_cmd_poll(dev
, in_param
, out_param
, 1,
478 in_modifier
, op_modifier
, op
,
482 int mthca_cmd_init(struct mthca_dev
*dev
)
484 mutex_init(&dev
->cmd
.hcr_mutex
);
485 sema_init(&dev
->cmd
.poll_sem
, 1);
488 dev
->hcr
= ioremap(pci_resource_start(dev
->pdev
, 0) + MTHCA_HCR_BASE
,
491 mthca_err(dev
, "Couldn't map command register.");
495 dev
->cmd
.pool
= pci_pool_create("mthca_cmd", dev
->pdev
,
497 MTHCA_MAILBOX_SIZE
, 0);
498 if (!dev
->cmd
.pool
) {
506 void mthca_cmd_cleanup(struct mthca_dev
*dev
)
508 pci_pool_destroy(dev
->cmd
.pool
);
510 if (dev
->cmd
.flags
& MTHCA_CMD_POST_DOORBELLS
)
511 iounmap(dev
->cmd
.dbell_map
);
515 * Switch to using events to issue FW commands (should be called after
516 * event queue to command events has been initialized).
518 int mthca_cmd_use_events(struct mthca_dev
*dev
)
522 dev
->cmd
.context
= kmalloc(dev
->cmd
.max_cmds
*
523 sizeof (struct mthca_cmd_context
),
525 if (!dev
->cmd
.context
)
528 for (i
= 0; i
< dev
->cmd
.max_cmds
; ++i
) {
529 dev
->cmd
.context
[i
].token
= i
;
530 dev
->cmd
.context
[i
].next
= i
+ 1;
533 dev
->cmd
.context
[dev
->cmd
.max_cmds
- 1].next
= -1;
534 dev
->cmd
.free_head
= 0;
536 sema_init(&dev
->cmd
.event_sem
, dev
->cmd
.max_cmds
);
537 spin_lock_init(&dev
->cmd
.context_lock
);
539 for (dev
->cmd
.token_mask
= 1;
540 dev
->cmd
.token_mask
< dev
->cmd
.max_cmds
;
541 dev
->cmd
.token_mask
<<= 1)
543 --dev
->cmd
.token_mask
;
545 dev
->cmd
.flags
|= MTHCA_CMD_USE_EVENTS
;
547 down(&dev
->cmd
.poll_sem
);
553 * Switch back to polling (used when shutting down the device)
555 void mthca_cmd_use_polling(struct mthca_dev
*dev
)
559 dev
->cmd
.flags
&= ~MTHCA_CMD_USE_EVENTS
;
561 for (i
= 0; i
< dev
->cmd
.max_cmds
; ++i
)
562 down(&dev
->cmd
.event_sem
);
564 kfree(dev
->cmd
.context
);
566 up(&dev
->cmd
.poll_sem
);
569 struct mthca_mailbox
*mthca_alloc_mailbox(struct mthca_dev
*dev
,
572 struct mthca_mailbox
*mailbox
;
574 mailbox
= kmalloc(sizeof *mailbox
, gfp_mask
);
576 return ERR_PTR(-ENOMEM
);
578 mailbox
->buf
= pci_pool_alloc(dev
->cmd
.pool
, gfp_mask
, &mailbox
->dma
);
581 return ERR_PTR(-ENOMEM
);
587 void mthca_free_mailbox(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
)
592 pci_pool_free(dev
->cmd
.pool
, mailbox
->buf
, mailbox
->dma
);
596 int mthca_SYS_EN(struct mthca_dev
*dev
, u8
*status
)
601 ret
= mthca_cmd_imm(dev
, 0, &out
, 0, 0, CMD_SYS_EN
, HZ
, status
);
603 if (*status
== MTHCA_CMD_STAT_DDR_MEM_ERR
)
604 mthca_warn(dev
, "SYS_EN DDR error: syn=%x, sock=%d, "
605 "sladdr=%d, SPD source=%s\n",
606 (int) (out
>> 6) & 0xf, (int) (out
>> 4) & 3,
607 (int) (out
>> 1) & 7, (int) out
& 1 ? "NVMEM" : "DIMM");
612 int mthca_SYS_DIS(struct mthca_dev
*dev
, u8
*status
)
614 return mthca_cmd(dev
, 0, 0, 0, CMD_SYS_DIS
, HZ
, status
);
617 static int mthca_map_cmd(struct mthca_dev
*dev
, u16 op
, struct mthca_icm
*icm
,
618 u64 virt
, u8
*status
)
620 struct mthca_mailbox
*mailbox
;
621 struct mthca_icm_iter iter
;
629 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
631 return PTR_ERR(mailbox
);
632 memset(mailbox
->buf
, 0, MTHCA_MAILBOX_SIZE
);
633 pages
= mailbox
->buf
;
635 for (mthca_icm_first(icm
, &iter
);
636 !mthca_icm_last(&iter
);
637 mthca_icm_next(&iter
)) {
639 * We have to pass pages that are aligned to their
640 * size, so find the least significant 1 in the
641 * address or size and use that as our log2 size.
643 lg
= ffs(mthca_icm_addr(&iter
) | mthca_icm_size(&iter
)) - 1;
644 if (lg
< MTHCA_ICM_PAGE_SHIFT
) {
645 mthca_warn(dev
, "Got FW area not aligned to %d (%llx/%lx).\n",
647 (unsigned long long) mthca_icm_addr(&iter
),
648 mthca_icm_size(&iter
));
652 for (i
= 0; i
< mthca_icm_size(&iter
) >> lg
; ++i
) {
654 pages
[nent
* 2] = cpu_to_be64(virt
);
658 pages
[nent
* 2 + 1] =
659 cpu_to_be64((mthca_icm_addr(&iter
) + (i
<< lg
)) |
660 (lg
- MTHCA_ICM_PAGE_SHIFT
));
661 ts
+= 1 << (lg
- 10);
664 if (++nent
== MTHCA_MAILBOX_SIZE
/ 16) {
665 err
= mthca_cmd(dev
, mailbox
->dma
, nent
, 0, op
,
666 CMD_TIME_CLASS_B
, status
);
675 err
= mthca_cmd(dev
, mailbox
->dma
, nent
, 0, op
,
676 CMD_TIME_CLASS_B
, status
);
680 mthca_dbg(dev
, "Mapped %d chunks/%d KB for FW.\n", tc
, ts
);
682 case CMD_MAP_ICM_AUX
:
683 mthca_dbg(dev
, "Mapped %d chunks/%d KB for ICM aux.\n", tc
, ts
);
686 mthca_dbg(dev
, "Mapped %d chunks/%d KB at %llx for ICM.\n",
687 tc
, ts
, (unsigned long long) virt
- (ts
<< 10));
692 mthca_free_mailbox(dev
, mailbox
);
696 int mthca_MAP_FA(struct mthca_dev
*dev
, struct mthca_icm
*icm
, u8
*status
)
698 return mthca_map_cmd(dev
, CMD_MAP_FA
, icm
, -1, status
);
701 int mthca_UNMAP_FA(struct mthca_dev
*dev
, u8
*status
)
703 return mthca_cmd(dev
, 0, 0, 0, CMD_UNMAP_FA
, CMD_TIME_CLASS_B
, status
);
706 int mthca_RUN_FW(struct mthca_dev
*dev
, u8
*status
)
708 return mthca_cmd(dev
, 0, 0, 0, CMD_RUN_FW
, CMD_TIME_CLASS_A
, status
);
711 static void mthca_setup_cmd_doorbells(struct mthca_dev
*dev
, u64 base
)
717 for (i
= 0; i
< 8; ++i
)
718 max_off
= max(max_off
, dev
->cmd
.dbell_offsets
[i
]);
720 if ((base
& PAGE_MASK
) != ((base
+ max_off
) & PAGE_MASK
)) {
721 mthca_warn(dev
, "Firmware doorbell region at 0x%016llx, "
722 "length 0x%x crosses a page boundary\n",
723 (unsigned long long) base
, max_off
);
727 addr
= pci_resource_start(dev
->pdev
, 2) +
728 ((pci_resource_len(dev
->pdev
, 2) - 1) & base
);
729 dev
->cmd
.dbell_map
= ioremap(addr
, max_off
+ sizeof(u32
));
730 if (!dev
->cmd
.dbell_map
)
733 dev
->cmd
.flags
|= MTHCA_CMD_POST_DOORBELLS
;
734 mthca_dbg(dev
, "Mapped doorbell page for posting FW commands\n");
737 int mthca_QUERY_FW(struct mthca_dev
*dev
, u8
*status
)
739 struct mthca_mailbox
*mailbox
;
747 #define QUERY_FW_OUT_SIZE 0x100
748 #define QUERY_FW_VER_OFFSET 0x00
749 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
750 #define QUERY_FW_ERR_START_OFFSET 0x30
751 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
753 #define QUERY_FW_CMD_DB_EN_OFFSET 0x10
754 #define QUERY_FW_CMD_DB_OFFSET 0x50
755 #define QUERY_FW_CMD_DB_BASE 0x60
757 #define QUERY_FW_START_OFFSET 0x20
758 #define QUERY_FW_END_OFFSET 0x28
760 #define QUERY_FW_SIZE_OFFSET 0x00
761 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
762 #define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40
763 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
765 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
767 return PTR_ERR(mailbox
);
768 outbox
= mailbox
->buf
;
770 err
= mthca_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, CMD_QUERY_FW
,
771 CMD_TIME_CLASS_A
, status
);
776 MTHCA_GET(dev
->fw_ver
, outbox
, QUERY_FW_VER_OFFSET
);
778 * FW subminor version is at more significant bits than minor
779 * version, so swap here.
781 dev
->fw_ver
= (dev
->fw_ver
& 0xffff00000000ull
) |
782 ((dev
->fw_ver
& 0xffff0000ull
) >> 16) |
783 ((dev
->fw_ver
& 0x0000ffffull
) << 16);
785 MTHCA_GET(lg
, outbox
, QUERY_FW_MAX_CMD_OFFSET
);
786 dev
->cmd
.max_cmds
= 1 << lg
;
788 mthca_dbg(dev
, "FW version %012llx, max commands %d\n",
789 (unsigned long long) dev
->fw_ver
, dev
->cmd
.max_cmds
);
791 MTHCA_GET(dev
->catas_err
.addr
, outbox
, QUERY_FW_ERR_START_OFFSET
);
792 MTHCA_GET(dev
->catas_err
.size
, outbox
, QUERY_FW_ERR_SIZE_OFFSET
);
794 mthca_dbg(dev
, "Catastrophic error buffer at 0x%llx, size 0x%x\n",
795 (unsigned long long) dev
->catas_err
.addr
, dev
->catas_err
.size
);
797 MTHCA_GET(tmp
, outbox
, QUERY_FW_CMD_DB_EN_OFFSET
);
799 mthca_dbg(dev
, "FW supports commands through doorbells\n");
801 MTHCA_GET(base
, outbox
, QUERY_FW_CMD_DB_BASE
);
802 for (i
= 0; i
< MTHCA_CMD_NUM_DBELL_DWORDS
; ++i
)
803 MTHCA_GET(dev
->cmd
.dbell_offsets
[i
], outbox
,
804 QUERY_FW_CMD_DB_OFFSET
+ (i
<< 1));
806 mthca_setup_cmd_doorbells(dev
, base
);
809 if (mthca_is_memfree(dev
)) {
810 MTHCA_GET(dev
->fw
.arbel
.fw_pages
, outbox
, QUERY_FW_SIZE_OFFSET
);
811 MTHCA_GET(dev
->fw
.arbel
.clr_int_base
, outbox
, QUERY_FW_CLR_INT_BASE_OFFSET
);
812 MTHCA_GET(dev
->fw
.arbel
.eq_arm_base
, outbox
, QUERY_FW_EQ_ARM_BASE_OFFSET
);
813 MTHCA_GET(dev
->fw
.arbel
.eq_set_ci_base
, outbox
, QUERY_FW_EQ_SET_CI_BASE_OFFSET
);
814 mthca_dbg(dev
, "FW size %d KB\n", dev
->fw
.arbel
.fw_pages
<< 2);
817 * Round up number of system pages needed in case
818 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
820 dev
->fw
.arbel
.fw_pages
=
821 ALIGN(dev
->fw
.arbel
.fw_pages
, PAGE_SIZE
/ MTHCA_ICM_PAGE_SIZE
) >>
822 (PAGE_SHIFT
- MTHCA_ICM_PAGE_SHIFT
);
824 mthca_dbg(dev
, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
825 (unsigned long long) dev
->fw
.arbel
.clr_int_base
,
826 (unsigned long long) dev
->fw
.arbel
.eq_arm_base
,
827 (unsigned long long) dev
->fw
.arbel
.eq_set_ci_base
);
829 MTHCA_GET(dev
->fw
.tavor
.fw_start
, outbox
, QUERY_FW_START_OFFSET
);
830 MTHCA_GET(dev
->fw
.tavor
.fw_end
, outbox
, QUERY_FW_END_OFFSET
);
832 mthca_dbg(dev
, "FW size %d KB (start %llx, end %llx)\n",
833 (int) ((dev
->fw
.tavor
.fw_end
- dev
->fw
.tavor
.fw_start
) >> 10),
834 (unsigned long long) dev
->fw
.tavor
.fw_start
,
835 (unsigned long long) dev
->fw
.tavor
.fw_end
);
839 mthca_free_mailbox(dev
, mailbox
);
843 int mthca_ENABLE_LAM(struct mthca_dev
*dev
, u8
*status
)
845 struct mthca_mailbox
*mailbox
;
850 #define ENABLE_LAM_OUT_SIZE 0x100
851 #define ENABLE_LAM_START_OFFSET 0x00
852 #define ENABLE_LAM_END_OFFSET 0x08
853 #define ENABLE_LAM_INFO_OFFSET 0x13
855 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
856 #define ENABLE_LAM_INFO_ECC_MASK 0x3
858 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
860 return PTR_ERR(mailbox
);
861 outbox
= mailbox
->buf
;
863 err
= mthca_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, CMD_ENABLE_LAM
,
864 CMD_TIME_CLASS_C
, status
);
869 if (*status
== MTHCA_CMD_STAT_LAM_NOT_PRE
)
872 MTHCA_GET(dev
->ddr_start
, outbox
, ENABLE_LAM_START_OFFSET
);
873 MTHCA_GET(dev
->ddr_end
, outbox
, ENABLE_LAM_END_OFFSET
);
874 MTHCA_GET(info
, outbox
, ENABLE_LAM_INFO_OFFSET
);
876 if (!!(info
& ENABLE_LAM_INFO_HIDDEN_FLAG
) !=
877 !!(dev
->mthca_flags
& MTHCA_FLAG_DDR_HIDDEN
)) {
878 mthca_info(dev
, "FW reports that HCA-attached memory "
879 "is %s hidden; does not match PCI config\n",
880 (info
& ENABLE_LAM_INFO_HIDDEN_FLAG
) ?
883 if (info
& ENABLE_LAM_INFO_HIDDEN_FLAG
)
884 mthca_dbg(dev
, "HCA-attached memory is hidden.\n");
886 mthca_dbg(dev
, "HCA memory size %d KB (start %llx, end %llx)\n",
887 (int) ((dev
->ddr_end
- dev
->ddr_start
) >> 10),
888 (unsigned long long) dev
->ddr_start
,
889 (unsigned long long) dev
->ddr_end
);
892 mthca_free_mailbox(dev
, mailbox
);
896 int mthca_DISABLE_LAM(struct mthca_dev
*dev
, u8
*status
)
898 return mthca_cmd(dev
, 0, 0, 0, CMD_SYS_DIS
, CMD_TIME_CLASS_C
, status
);
901 int mthca_QUERY_DDR(struct mthca_dev
*dev
, u8
*status
)
903 struct mthca_mailbox
*mailbox
;
908 #define QUERY_DDR_OUT_SIZE 0x100
909 #define QUERY_DDR_START_OFFSET 0x00
910 #define QUERY_DDR_END_OFFSET 0x08
911 #define QUERY_DDR_INFO_OFFSET 0x13
913 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
914 #define QUERY_DDR_INFO_ECC_MASK 0x3
916 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
918 return PTR_ERR(mailbox
);
919 outbox
= mailbox
->buf
;
921 err
= mthca_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, CMD_QUERY_DDR
,
922 CMD_TIME_CLASS_A
, status
);
927 MTHCA_GET(dev
->ddr_start
, outbox
, QUERY_DDR_START_OFFSET
);
928 MTHCA_GET(dev
->ddr_end
, outbox
, QUERY_DDR_END_OFFSET
);
929 MTHCA_GET(info
, outbox
, QUERY_DDR_INFO_OFFSET
);
931 if (!!(info
& QUERY_DDR_INFO_HIDDEN_FLAG
) !=
932 !!(dev
->mthca_flags
& MTHCA_FLAG_DDR_HIDDEN
)) {
933 mthca_info(dev
, "FW reports that HCA-attached memory "
934 "is %s hidden; does not match PCI config\n",
935 (info
& QUERY_DDR_INFO_HIDDEN_FLAG
) ?
938 if (info
& QUERY_DDR_INFO_HIDDEN_FLAG
)
939 mthca_dbg(dev
, "HCA-attached memory is hidden.\n");
941 mthca_dbg(dev
, "HCA memory size %d KB (start %llx, end %llx)\n",
942 (int) ((dev
->ddr_end
- dev
->ddr_start
) >> 10),
943 (unsigned long long) dev
->ddr_start
,
944 (unsigned long long) dev
->ddr_end
);
947 mthca_free_mailbox(dev
, mailbox
);
951 int mthca_QUERY_DEV_LIM(struct mthca_dev
*dev
,
952 struct mthca_dev_lim
*dev_lim
, u8
*status
)
954 struct mthca_mailbox
*mailbox
;
961 #define QUERY_DEV_LIM_OUT_SIZE 0x100
962 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10
963 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11
964 #define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12
965 #define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13
966 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14
967 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15
968 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16
969 #define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17
970 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19
971 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a
972 #define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b
973 #define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d
974 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e
975 #define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f
976 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20
977 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21
978 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22
979 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23
980 #define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27
981 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29
982 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b
983 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f
984 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33
985 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35
986 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36
987 #define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37
988 #define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b
989 #define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c
990 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f
991 #define QUERY_DEV_LIM_FLAGS_OFFSET 0x44
992 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48
993 #define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49
994 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b
995 #define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51
996 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52
997 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55
998 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
999 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61
1000 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62
1001 #define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63
1002 #define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64
1003 #define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65
1004 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66
1005 #define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67
1006 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80
1007 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82
1008 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84
1009 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86
1010 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88
1011 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a
1012 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c
1013 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e
1014 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90
1015 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92
1016 #define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96
1017 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97
1018 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98
1019 #define QUERY_DEV_LIM_LAMR_OFFSET 0x9f
1020 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0
1022 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1023 if (IS_ERR(mailbox
))
1024 return PTR_ERR(mailbox
);
1025 outbox
= mailbox
->buf
;
1027 err
= mthca_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, CMD_QUERY_DEV_LIM
,
1028 CMD_TIME_CLASS_A
, status
);
1033 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_QP_OFFSET
);
1034 dev_lim
->reserved_qps
= 1 << (field
& 0xf);
1035 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_QP_OFFSET
);
1036 dev_lim
->max_qps
= 1 << (field
& 0x1f);
1037 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_SRQ_OFFSET
);
1038 dev_lim
->reserved_srqs
= 1 << (field
>> 4);
1039 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_SRQ_OFFSET
);
1040 dev_lim
->max_srqs
= 1 << (field
& 0x1f);
1041 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_EEC_OFFSET
);
1042 dev_lim
->reserved_eecs
= 1 << (field
& 0xf);
1043 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_EEC_OFFSET
);
1044 dev_lim
->max_eecs
= 1 << (field
& 0x1f);
1045 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET
);
1046 dev_lim
->max_cq_sz
= 1 << field
;
1047 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_CQ_OFFSET
);
1048 dev_lim
->reserved_cqs
= 1 << (field
& 0xf);
1049 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_CQ_OFFSET
);
1050 dev_lim
->max_cqs
= 1 << (field
& 0x1f);
1051 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_MPT_OFFSET
);
1052 dev_lim
->max_mpts
= 1 << (field
& 0x3f);
1053 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_EQ_OFFSET
);
1054 dev_lim
->reserved_eqs
= 1 << (field
& 0xf);
1055 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_EQ_OFFSET
);
1056 dev_lim
->max_eqs
= 1 << (field
& 0x7);
1057 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_MTT_OFFSET
);
1058 if (mthca_is_memfree(dev
))
1059 dev_lim
->reserved_mtts
= ALIGN((1 << (field
>> 4)) * sizeof(u64
),
1060 MTHCA_MTT_SEG_SIZE
) / MTHCA_MTT_SEG_SIZE
;
1062 dev_lim
->reserved_mtts
= 1 << (field
>> 4);
1063 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET
);
1064 dev_lim
->max_mrw_sz
= 1 << field
;
1065 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_MRW_OFFSET
);
1066 dev_lim
->reserved_mrws
= 1 << (field
& 0xf);
1067 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET
);
1068 dev_lim
->max_mtt_seg
= 1 << (field
& 0x3f);
1069 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET
);
1070 dev_lim
->max_requester_per_qp
= 1 << (field
& 0x3f);
1071 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_RES_QP_OFFSET
);
1072 dev_lim
->max_responder_per_qp
= 1 << (field
& 0x3f);
1073 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_RDMA_OFFSET
);
1074 dev_lim
->max_rdma_global
= 1 << (field
& 0x3f);
1075 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_ACK_DELAY_OFFSET
);
1076 dev_lim
->local_ca_ack_delay
= field
& 0x1f;
1077 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MTU_WIDTH_OFFSET
);
1078 dev_lim
->max_mtu
= field
>> 4;
1079 dev_lim
->max_port_width
= field
& 0xf;
1080 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_VL_PORT_OFFSET
);
1081 dev_lim
->max_vl
= field
>> 4;
1082 dev_lim
->num_ports
= field
& 0xf;
1083 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_GID_OFFSET
);
1084 dev_lim
->max_gids
= 1 << (field
& 0xf);
1085 MTHCA_GET(stat_rate
, outbox
, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET
);
1086 dev_lim
->stat_rate_support
= stat_rate
;
1087 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_PKEY_OFFSET
);
1088 dev_lim
->max_pkeys
= 1 << (field
& 0xf);
1089 MTHCA_GET(dev_lim
->flags
, outbox
, QUERY_DEV_LIM_FLAGS_OFFSET
);
1090 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_UAR_OFFSET
);
1091 dev_lim
->reserved_uars
= field
>> 4;
1092 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_UAR_SZ_OFFSET
);
1093 dev_lim
->uar_size
= 1 << ((field
& 0x3f) + 20);
1094 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_PAGE_SZ_OFFSET
);
1095 dev_lim
->min_page_sz
= 1 << field
;
1096 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_SG_OFFSET
);
1097 dev_lim
->max_sg
= field
;
1099 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET
);
1100 dev_lim
->max_desc_sz
= size
;
1102 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET
);
1103 dev_lim
->max_qp_per_mcg
= 1 << field
;
1104 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_MCG_OFFSET
);
1105 dev_lim
->reserved_mgms
= field
& 0xf;
1106 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_MCG_OFFSET
);
1107 dev_lim
->max_mcgs
= 1 << field
;
1108 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_PD_OFFSET
);
1109 dev_lim
->reserved_pds
= field
>> 4;
1110 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_PD_OFFSET
);
1111 dev_lim
->max_pds
= 1 << (field
& 0x3f);
1112 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_RDD_OFFSET
);
1113 dev_lim
->reserved_rdds
= field
>> 4;
1114 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_RDD_OFFSET
);
1115 dev_lim
->max_rdds
= 1 << (field
& 0x3f);
1117 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET
);
1118 dev_lim
->eec_entry_sz
= size
;
1119 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET
);
1120 dev_lim
->qpc_entry_sz
= size
;
1121 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET
);
1122 dev_lim
->eeec_entry_sz
= size
;
1123 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET
);
1124 dev_lim
->eqpc_entry_sz
= size
;
1125 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET
);
1126 dev_lim
->eqc_entry_sz
= size
;
1127 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET
);
1128 dev_lim
->cqc_entry_sz
= size
;
1129 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET
);
1130 dev_lim
->srq_entry_sz
= size
;
1131 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET
);
1132 dev_lim
->uar_scratch_entry_sz
= size
;
1134 if (mthca_is_memfree(dev
)) {
1135 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET
);
1136 dev_lim
->max_srq_sz
= 1 << field
;
1137 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET
);
1138 dev_lim
->max_qp_sz
= 1 << field
;
1139 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSZ_SRQ_OFFSET
);
1140 dev_lim
->hca
.arbel
.resize_srq
= field
& 1;
1141 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET
);
1142 dev_lim
->max_sg
= min_t(int, field
, dev_lim
->max_sg
);
1143 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET
);
1144 dev_lim
->max_desc_sz
= min_t(int, size
, dev_lim
->max_desc_sz
);
1145 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET
);
1146 dev_lim
->mpt_entry_sz
= size
;
1147 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_PBL_SZ_OFFSET
);
1148 dev_lim
->hca
.arbel
.max_pbl_sz
= 1 << (field
& 0x3f);
1149 MTHCA_GET(dev_lim
->hca
.arbel
.bmme_flags
, outbox
,
1150 QUERY_DEV_LIM_BMME_FLAGS_OFFSET
);
1151 MTHCA_GET(dev_lim
->hca
.arbel
.reserved_lkey
, outbox
,
1152 QUERY_DEV_LIM_RSVD_LKEY_OFFSET
);
1153 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_LAMR_OFFSET
);
1154 dev_lim
->hca
.arbel
.lam_required
= field
& 1;
1155 MTHCA_GET(dev_lim
->hca
.arbel
.max_icm_sz
, outbox
,
1156 QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET
);
1158 if (dev_lim
->hca
.arbel
.bmme_flags
& 1)
1159 mthca_dbg(dev
, "Base MM extensions: yes "
1160 "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1161 dev_lim
->hca
.arbel
.bmme_flags
,
1162 dev_lim
->hca
.arbel
.max_pbl_sz
,
1163 dev_lim
->hca
.arbel
.reserved_lkey
);
1165 mthca_dbg(dev
, "Base MM extensions: no\n");
1167 mthca_dbg(dev
, "Max ICM size %lld MB\n",
1168 (unsigned long long) dev_lim
->hca
.arbel
.max_icm_sz
>> 20);
1170 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET
);
1171 dev_lim
->max_srq_sz
= (1 << field
) - 1;
1172 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET
);
1173 dev_lim
->max_qp_sz
= (1 << field
) - 1;
1174 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_AV_OFFSET
);
1175 dev_lim
->hca
.tavor
.max_avs
= 1 << (field
& 0x3f);
1176 dev_lim
->mpt_entry_sz
= MTHCA_MPT_ENTRY_SIZE
;
1179 mthca_dbg(dev
, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1180 dev_lim
->max_qps
, dev_lim
->reserved_qps
, dev_lim
->qpc_entry_sz
);
1181 mthca_dbg(dev
, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1182 dev_lim
->max_srqs
, dev_lim
->reserved_srqs
, dev_lim
->srq_entry_sz
);
1183 mthca_dbg(dev
, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1184 dev_lim
->max_cqs
, dev_lim
->reserved_cqs
, dev_lim
->cqc_entry_sz
);
1185 mthca_dbg(dev
, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1186 dev_lim
->max_eqs
, dev_lim
->reserved_eqs
, dev_lim
->eqc_entry_sz
);
1187 mthca_dbg(dev
, "reserved MPTs: %d, reserved MTTs: %d\n",
1188 dev_lim
->reserved_mrws
, dev_lim
->reserved_mtts
);
1189 mthca_dbg(dev
, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1190 dev_lim
->max_pds
, dev_lim
->reserved_pds
, dev_lim
->reserved_uars
);
1191 mthca_dbg(dev
, "Max QP/MCG: %d, reserved MGMs: %d\n",
1192 dev_lim
->max_pds
, dev_lim
->reserved_mgms
);
1193 mthca_dbg(dev
, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1194 dev_lim
->max_cq_sz
, dev_lim
->max_qp_sz
, dev_lim
->max_srq_sz
);
1196 mthca_dbg(dev
, "Flags: %08x\n", dev_lim
->flags
);
1199 mthca_free_mailbox(dev
, mailbox
);
1203 static void get_board_id(void *vsd
, char *board_id
)
1207 #define VSD_OFFSET_SIG1 0x00
1208 #define VSD_OFFSET_SIG2 0xde
1209 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1210 #define VSD_OFFSET_TS_BOARD_ID 0x20
1212 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1214 memset(board_id
, 0, MTHCA_BOARD_ID_LEN
);
1216 if (be16_to_cpup(vsd
+ VSD_OFFSET_SIG1
) == VSD_SIGNATURE_TOPSPIN
&&
1217 be16_to_cpup(vsd
+ VSD_OFFSET_SIG2
) == VSD_SIGNATURE_TOPSPIN
) {
1218 strlcpy(board_id
, vsd
+ VSD_OFFSET_TS_BOARD_ID
, MTHCA_BOARD_ID_LEN
);
1221 * The board ID is a string but the firmware byte
1222 * swaps each 4-byte word before passing it back to
1223 * us. Therefore we need to swab it before printing.
1225 for (i
= 0; i
< 4; ++i
)
1226 ((u32
*) board_id
)[i
] =
1227 swab32(*(u32
*) (vsd
+ VSD_OFFSET_MLX_BOARD_ID
+ i
* 4));
1231 int mthca_QUERY_ADAPTER(struct mthca_dev
*dev
,
1232 struct mthca_adapter
*adapter
, u8
*status
)
1234 struct mthca_mailbox
*mailbox
;
1238 #define QUERY_ADAPTER_OUT_SIZE 0x100
1239 #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00
1240 #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04
1241 #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08
1242 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1243 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1245 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1246 if (IS_ERR(mailbox
))
1247 return PTR_ERR(mailbox
);
1248 outbox
= mailbox
->buf
;
1250 err
= mthca_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, CMD_QUERY_ADAPTER
,
1251 CMD_TIME_CLASS_A
, status
);
1256 if (!mthca_is_memfree(dev
)) {
1257 MTHCA_GET(adapter
->vendor_id
, outbox
,
1258 QUERY_ADAPTER_VENDOR_ID_OFFSET
);
1259 MTHCA_GET(adapter
->device_id
, outbox
,
1260 QUERY_ADAPTER_DEVICE_ID_OFFSET
);
1261 MTHCA_GET(adapter
->revision_id
, outbox
,
1262 QUERY_ADAPTER_REVISION_ID_OFFSET
);
1264 MTHCA_GET(adapter
->inta_pin
, outbox
, QUERY_ADAPTER_INTA_PIN_OFFSET
);
1266 get_board_id(outbox
+ QUERY_ADAPTER_VSD_OFFSET
/ 4,
1270 mthca_free_mailbox(dev
, mailbox
);
1274 int mthca_INIT_HCA(struct mthca_dev
*dev
,
1275 struct mthca_init_hca_param
*param
,
1278 struct mthca_mailbox
*mailbox
;
1282 #define INIT_HCA_IN_SIZE 0x200
1283 #define INIT_HCA_FLAGS1_OFFSET 0x00c
1284 #define INIT_HCA_FLAGS2_OFFSET 0x014
1285 #define INIT_HCA_QPC_OFFSET 0x020
1286 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1287 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1288 #define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20)
1289 #define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27)
1290 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1291 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1292 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1293 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1294 #define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1295 #define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1296 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1297 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1298 #define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1299 #define INIT_HCA_UDAV_OFFSET 0x0b0
1300 #define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0)
1301 #define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4)
1302 #define INIT_HCA_MCAST_OFFSET 0x0c0
1303 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1304 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1305 #define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1306 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1307 #define INIT_HCA_TPT_OFFSET 0x0f0
1308 #define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1309 #define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09)
1310 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1311 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1312 #define INIT_HCA_UAR_OFFSET 0x120
1313 #define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00)
1314 #define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09)
1315 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1316 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1317 #define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1318 #define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18)
1320 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1321 if (IS_ERR(mailbox
))
1322 return PTR_ERR(mailbox
);
1323 inbox
= mailbox
->buf
;
1325 memset(inbox
, 0, INIT_HCA_IN_SIZE
);
1327 if (dev
->mthca_flags
& MTHCA_FLAG_SINAI_OPT
)
1328 MTHCA_PUT(inbox
, 0x1, INIT_HCA_FLAGS1_OFFSET
);
1330 #if defined(__LITTLE_ENDIAN)
1331 *(inbox
+ INIT_HCA_FLAGS2_OFFSET
/ 4) &= ~cpu_to_be32(1 << 1);
1332 #elif defined(__BIG_ENDIAN)
1333 *(inbox
+ INIT_HCA_FLAGS2_OFFSET
/ 4) |= cpu_to_be32(1 << 1);
1335 #error Host endianness not defined
1337 /* Check port for UD address vector: */
1338 *(inbox
+ INIT_HCA_FLAGS2_OFFSET
/ 4) |= cpu_to_be32(1);
1340 /* Enable IPoIB checksumming if we can: */
1341 if (dev
->device_cap_flags
& IB_DEVICE_UD_IP_CSUM
)
1342 *(inbox
+ INIT_HCA_FLAGS2_OFFSET
/ 4) |= cpu_to_be32(7 << 3);
1344 /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1346 /* QPC/EEC/CQC/EQC/RDB attributes */
1348 MTHCA_PUT(inbox
, param
->qpc_base
, INIT_HCA_QPC_BASE_OFFSET
);
1349 MTHCA_PUT(inbox
, param
->log_num_qps
, INIT_HCA_LOG_QP_OFFSET
);
1350 MTHCA_PUT(inbox
, param
->eec_base
, INIT_HCA_EEC_BASE_OFFSET
);
1351 MTHCA_PUT(inbox
, param
->log_num_eecs
, INIT_HCA_LOG_EEC_OFFSET
);
1352 MTHCA_PUT(inbox
, param
->srqc_base
, INIT_HCA_SRQC_BASE_OFFSET
);
1353 MTHCA_PUT(inbox
, param
->log_num_srqs
, INIT_HCA_LOG_SRQ_OFFSET
);
1354 MTHCA_PUT(inbox
, param
->cqc_base
, INIT_HCA_CQC_BASE_OFFSET
);
1355 MTHCA_PUT(inbox
, param
->log_num_cqs
, INIT_HCA_LOG_CQ_OFFSET
);
1356 MTHCA_PUT(inbox
, param
->eqpc_base
, INIT_HCA_EQPC_BASE_OFFSET
);
1357 MTHCA_PUT(inbox
, param
->eeec_base
, INIT_HCA_EEEC_BASE_OFFSET
);
1358 MTHCA_PUT(inbox
, param
->eqc_base
, INIT_HCA_EQC_BASE_OFFSET
);
1359 MTHCA_PUT(inbox
, param
->log_num_eqs
, INIT_HCA_LOG_EQ_OFFSET
);
1360 MTHCA_PUT(inbox
, param
->rdb_base
, INIT_HCA_RDB_BASE_OFFSET
);
1362 /* UD AV attributes */
1364 /* multicast attributes */
1366 MTHCA_PUT(inbox
, param
->mc_base
, INIT_HCA_MC_BASE_OFFSET
);
1367 MTHCA_PUT(inbox
, param
->log_mc_entry_sz
, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET
);
1368 MTHCA_PUT(inbox
, param
->mc_hash_sz
, INIT_HCA_MC_HASH_SZ_OFFSET
);
1369 MTHCA_PUT(inbox
, param
->log_mc_table_sz
, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET
);
1371 /* TPT attributes */
1373 MTHCA_PUT(inbox
, param
->mpt_base
, INIT_HCA_MPT_BASE_OFFSET
);
1374 if (!mthca_is_memfree(dev
))
1375 MTHCA_PUT(inbox
, param
->mtt_seg_sz
, INIT_HCA_MTT_SEG_SZ_OFFSET
);
1376 MTHCA_PUT(inbox
, param
->log_mpt_sz
, INIT_HCA_LOG_MPT_SZ_OFFSET
);
1377 MTHCA_PUT(inbox
, param
->mtt_base
, INIT_HCA_MTT_BASE_OFFSET
);
1379 /* UAR attributes */
1381 u8 uar_page_sz
= PAGE_SHIFT
- 12;
1382 MTHCA_PUT(inbox
, uar_page_sz
, INIT_HCA_UAR_PAGE_SZ_OFFSET
);
1385 MTHCA_PUT(inbox
, param
->uar_scratch_base
, INIT_HCA_UAR_SCATCH_BASE_OFFSET
);
1387 if (mthca_is_memfree(dev
)) {
1388 MTHCA_PUT(inbox
, param
->log_uarc_sz
, INIT_HCA_UARC_SZ_OFFSET
);
1389 MTHCA_PUT(inbox
, param
->log_uar_sz
, INIT_HCA_LOG_UAR_SZ_OFFSET
);
1390 MTHCA_PUT(inbox
, param
->uarc_base
, INIT_HCA_UAR_CTX_BASE_OFFSET
);
1393 err
= mthca_cmd(dev
, mailbox
->dma
, 0, 0, CMD_INIT_HCA
, HZ
, status
);
1395 mthca_free_mailbox(dev
, mailbox
);
1399 int mthca_INIT_IB(struct mthca_dev
*dev
,
1400 struct mthca_init_ib_param
*param
,
1401 int port
, u8
*status
)
1403 struct mthca_mailbox
*mailbox
;
1408 #define INIT_IB_IN_SIZE 56
1409 #define INIT_IB_FLAGS_OFFSET 0x00
1410 #define INIT_IB_FLAG_SIG (1 << 18)
1411 #define INIT_IB_FLAG_NG (1 << 17)
1412 #define INIT_IB_FLAG_G0 (1 << 16)
1413 #define INIT_IB_VL_SHIFT 4
1414 #define INIT_IB_PORT_WIDTH_SHIFT 8
1415 #define INIT_IB_MTU_SHIFT 12
1416 #define INIT_IB_MAX_GID_OFFSET 0x06
1417 #define INIT_IB_MAX_PKEY_OFFSET 0x0a
1418 #define INIT_IB_GUID0_OFFSET 0x10
1419 #define INIT_IB_NODE_GUID_OFFSET 0x18
1420 #define INIT_IB_SI_GUID_OFFSET 0x20
1422 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1423 if (IS_ERR(mailbox
))
1424 return PTR_ERR(mailbox
);
1425 inbox
= mailbox
->buf
;
1427 memset(inbox
, 0, INIT_IB_IN_SIZE
);
1430 flags
|= param
->set_guid0
? INIT_IB_FLAG_G0
: 0;
1431 flags
|= param
->set_node_guid
? INIT_IB_FLAG_NG
: 0;
1432 flags
|= param
->set_si_guid
? INIT_IB_FLAG_SIG
: 0;
1433 flags
|= param
->vl_cap
<< INIT_IB_VL_SHIFT
;
1434 flags
|= param
->port_width
<< INIT_IB_PORT_WIDTH_SHIFT
;
1435 flags
|= param
->mtu_cap
<< INIT_IB_MTU_SHIFT
;
1436 MTHCA_PUT(inbox
, flags
, INIT_IB_FLAGS_OFFSET
);
1438 MTHCA_PUT(inbox
, param
->gid_cap
, INIT_IB_MAX_GID_OFFSET
);
1439 MTHCA_PUT(inbox
, param
->pkey_cap
, INIT_IB_MAX_PKEY_OFFSET
);
1440 MTHCA_PUT(inbox
, param
->guid0
, INIT_IB_GUID0_OFFSET
);
1441 MTHCA_PUT(inbox
, param
->node_guid
, INIT_IB_NODE_GUID_OFFSET
);
1442 MTHCA_PUT(inbox
, param
->si_guid
, INIT_IB_SI_GUID_OFFSET
);
1444 err
= mthca_cmd(dev
, mailbox
->dma
, port
, 0, CMD_INIT_IB
,
1445 CMD_TIME_CLASS_A
, status
);
1447 mthca_free_mailbox(dev
, mailbox
);
1451 int mthca_CLOSE_IB(struct mthca_dev
*dev
, int port
, u8
*status
)
1453 return mthca_cmd(dev
, 0, port
, 0, CMD_CLOSE_IB
, HZ
, status
);
1456 int mthca_CLOSE_HCA(struct mthca_dev
*dev
, int panic
, u8
*status
)
1458 return mthca_cmd(dev
, 0, 0, panic
, CMD_CLOSE_HCA
, HZ
, status
);
1461 int mthca_SET_IB(struct mthca_dev
*dev
, struct mthca_set_ib_param
*param
,
1462 int port
, u8
*status
)
1464 struct mthca_mailbox
*mailbox
;
1469 #define SET_IB_IN_SIZE 0x40
1470 #define SET_IB_FLAGS_OFFSET 0x00
1471 #define SET_IB_FLAG_SIG (1 << 18)
1472 #define SET_IB_FLAG_RQK (1 << 0)
1473 #define SET_IB_CAP_MASK_OFFSET 0x04
1474 #define SET_IB_SI_GUID_OFFSET 0x08
1476 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1477 if (IS_ERR(mailbox
))
1478 return PTR_ERR(mailbox
);
1479 inbox
= mailbox
->buf
;
1481 memset(inbox
, 0, SET_IB_IN_SIZE
);
1483 flags
|= param
->set_si_guid
? SET_IB_FLAG_SIG
: 0;
1484 flags
|= param
->reset_qkey_viol
? SET_IB_FLAG_RQK
: 0;
1485 MTHCA_PUT(inbox
, flags
, SET_IB_FLAGS_OFFSET
);
1487 MTHCA_PUT(inbox
, param
->cap_mask
, SET_IB_CAP_MASK_OFFSET
);
1488 MTHCA_PUT(inbox
, param
->si_guid
, SET_IB_SI_GUID_OFFSET
);
1490 err
= mthca_cmd(dev
, mailbox
->dma
, port
, 0, CMD_SET_IB
,
1491 CMD_TIME_CLASS_B
, status
);
1493 mthca_free_mailbox(dev
, mailbox
);
1497 int mthca_MAP_ICM(struct mthca_dev
*dev
, struct mthca_icm
*icm
, u64 virt
, u8
*status
)
1499 return mthca_map_cmd(dev
, CMD_MAP_ICM
, icm
, virt
, status
);
1502 int mthca_MAP_ICM_page(struct mthca_dev
*dev
, u64 dma_addr
, u64 virt
, u8
*status
)
1504 struct mthca_mailbox
*mailbox
;
1508 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1509 if (IS_ERR(mailbox
))
1510 return PTR_ERR(mailbox
);
1511 inbox
= mailbox
->buf
;
1513 inbox
[0] = cpu_to_be64(virt
);
1514 inbox
[1] = cpu_to_be64(dma_addr
);
1516 err
= mthca_cmd(dev
, mailbox
->dma
, 1, 0, CMD_MAP_ICM
,
1517 CMD_TIME_CLASS_B
, status
);
1519 mthca_free_mailbox(dev
, mailbox
);
1522 mthca_dbg(dev
, "Mapped page at %llx to %llx for ICM.\n",
1523 (unsigned long long) dma_addr
, (unsigned long long) virt
);
1528 int mthca_UNMAP_ICM(struct mthca_dev
*dev
, u64 virt
, u32 page_count
, u8
*status
)
1530 mthca_dbg(dev
, "Unmapping %d pages at %llx from ICM.\n",
1531 page_count
, (unsigned long long) virt
);
1533 return mthca_cmd(dev
, virt
, page_count
, 0, CMD_UNMAP_ICM
, CMD_TIME_CLASS_B
, status
);
1536 int mthca_MAP_ICM_AUX(struct mthca_dev
*dev
, struct mthca_icm
*icm
, u8
*status
)
1538 return mthca_map_cmd(dev
, CMD_MAP_ICM_AUX
, icm
, -1, status
);
1541 int mthca_UNMAP_ICM_AUX(struct mthca_dev
*dev
, u8
*status
)
1543 return mthca_cmd(dev
, 0, 0, 0, CMD_UNMAP_ICM_AUX
, CMD_TIME_CLASS_B
, status
);
1546 int mthca_SET_ICM_SIZE(struct mthca_dev
*dev
, u64 icm_size
, u64
*aux_pages
,
1549 int ret
= mthca_cmd_imm(dev
, icm_size
, aux_pages
, 0, 0, CMD_SET_ICM_SIZE
,
1550 CMD_TIME_CLASS_A
, status
);
1556 * Round up number of system pages needed in case
1557 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
1559 *aux_pages
= ALIGN(*aux_pages
, PAGE_SIZE
/ MTHCA_ICM_PAGE_SIZE
) >>
1560 (PAGE_SHIFT
- MTHCA_ICM_PAGE_SHIFT
);
1565 int mthca_SW2HW_MPT(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1566 int mpt_index
, u8
*status
)
1568 return mthca_cmd(dev
, mailbox
->dma
, mpt_index
, 0, CMD_SW2HW_MPT
,
1569 CMD_TIME_CLASS_B
, status
);
1572 int mthca_HW2SW_MPT(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1573 int mpt_index
, u8
*status
)
1575 return mthca_cmd_box(dev
, 0, mailbox
? mailbox
->dma
: 0, mpt_index
,
1576 !mailbox
, CMD_HW2SW_MPT
,
1577 CMD_TIME_CLASS_B
, status
);
1580 int mthca_WRITE_MTT(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1581 int num_mtt
, u8
*status
)
1583 return mthca_cmd(dev
, mailbox
->dma
, num_mtt
, 0, CMD_WRITE_MTT
,
1584 CMD_TIME_CLASS_B
, status
);
1587 int mthca_SYNC_TPT(struct mthca_dev
*dev
, u8
*status
)
1589 return mthca_cmd(dev
, 0, 0, 0, CMD_SYNC_TPT
, CMD_TIME_CLASS_B
, status
);
1592 int mthca_MAP_EQ(struct mthca_dev
*dev
, u64 event_mask
, int unmap
,
1593 int eq_num
, u8
*status
)
1595 mthca_dbg(dev
, "%s mask %016llx for eqn %d\n",
1596 unmap
? "Clearing" : "Setting",
1597 (unsigned long long) event_mask
, eq_num
);
1598 return mthca_cmd(dev
, event_mask
, (unmap
<< 31) | eq_num
,
1599 0, CMD_MAP_EQ
, CMD_TIME_CLASS_B
, status
);
1602 int mthca_SW2HW_EQ(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1603 int eq_num
, u8
*status
)
1605 return mthca_cmd(dev
, mailbox
->dma
, eq_num
, 0, CMD_SW2HW_EQ
,
1606 CMD_TIME_CLASS_A
, status
);
1609 int mthca_HW2SW_EQ(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1610 int eq_num
, u8
*status
)
1612 return mthca_cmd_box(dev
, 0, mailbox
->dma
, eq_num
, 0,
1614 CMD_TIME_CLASS_A
, status
);
1617 int mthca_SW2HW_CQ(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1618 int cq_num
, u8
*status
)
1620 return mthca_cmd(dev
, mailbox
->dma
, cq_num
, 0, CMD_SW2HW_CQ
,
1621 CMD_TIME_CLASS_A
, status
);
1624 int mthca_HW2SW_CQ(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1625 int cq_num
, u8
*status
)
1627 return mthca_cmd_box(dev
, 0, mailbox
->dma
, cq_num
, 0,
1629 CMD_TIME_CLASS_A
, status
);
1632 int mthca_RESIZE_CQ(struct mthca_dev
*dev
, int cq_num
, u32 lkey
, u8 log_size
,
1635 struct mthca_mailbox
*mailbox
;
1639 #define RESIZE_CQ_IN_SIZE 0x40
1640 #define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c
1641 #define RESIZE_CQ_LKEY_OFFSET 0x1c
1643 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1644 if (IS_ERR(mailbox
))
1645 return PTR_ERR(mailbox
);
1646 inbox
= mailbox
->buf
;
1648 memset(inbox
, 0, RESIZE_CQ_IN_SIZE
);
1650 * Leave start address fields zeroed out -- mthca assumes that
1651 * MRs for CQs always start at virtual address 0.
1653 MTHCA_PUT(inbox
, log_size
, RESIZE_CQ_LOG_SIZE_OFFSET
);
1654 MTHCA_PUT(inbox
, lkey
, RESIZE_CQ_LKEY_OFFSET
);
1656 err
= mthca_cmd(dev
, mailbox
->dma
, cq_num
, 1, CMD_RESIZE_CQ
,
1657 CMD_TIME_CLASS_B
, status
);
1659 mthca_free_mailbox(dev
, mailbox
);
1663 int mthca_SW2HW_SRQ(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1664 int srq_num
, u8
*status
)
1666 return mthca_cmd(dev
, mailbox
->dma
, srq_num
, 0, CMD_SW2HW_SRQ
,
1667 CMD_TIME_CLASS_A
, status
);
1670 int mthca_HW2SW_SRQ(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1671 int srq_num
, u8
*status
)
1673 return mthca_cmd_box(dev
, 0, mailbox
->dma
, srq_num
, 0,
1675 CMD_TIME_CLASS_A
, status
);
1678 int mthca_QUERY_SRQ(struct mthca_dev
*dev
, u32 num
,
1679 struct mthca_mailbox
*mailbox
, u8
*status
)
1681 return mthca_cmd_box(dev
, 0, mailbox
->dma
, num
, 0,
1682 CMD_QUERY_SRQ
, CMD_TIME_CLASS_A
, status
);
1685 int mthca_ARM_SRQ(struct mthca_dev
*dev
, int srq_num
, int limit
, u8
*status
)
1687 return mthca_cmd(dev
, limit
, srq_num
, 0, CMD_ARM_SRQ
,
1688 CMD_TIME_CLASS_B
, status
);
1691 int mthca_MODIFY_QP(struct mthca_dev
*dev
, enum ib_qp_state cur
,
1692 enum ib_qp_state next
, u32 num
, int is_ee
,
1693 struct mthca_mailbox
*mailbox
, u32 optmask
,
1696 static const u16 op
[IB_QPS_ERR
+ 1][IB_QPS_ERR
+ 1] = {
1698 [IB_QPS_RESET
] = CMD_ERR2RST_QPEE
,
1699 [IB_QPS_ERR
] = CMD_2ERR_QPEE
,
1700 [IB_QPS_INIT
] = CMD_RST2INIT_QPEE
,
1703 [IB_QPS_RESET
] = CMD_ERR2RST_QPEE
,
1704 [IB_QPS_ERR
] = CMD_2ERR_QPEE
,
1705 [IB_QPS_INIT
] = CMD_INIT2INIT_QPEE
,
1706 [IB_QPS_RTR
] = CMD_INIT2RTR_QPEE
,
1709 [IB_QPS_RESET
] = CMD_ERR2RST_QPEE
,
1710 [IB_QPS_ERR
] = CMD_2ERR_QPEE
,
1711 [IB_QPS_RTS
] = CMD_RTR2RTS_QPEE
,
1714 [IB_QPS_RESET
] = CMD_ERR2RST_QPEE
,
1715 [IB_QPS_ERR
] = CMD_2ERR_QPEE
,
1716 [IB_QPS_RTS
] = CMD_RTS2RTS_QPEE
,
1717 [IB_QPS_SQD
] = CMD_RTS2SQD_QPEE
,
1720 [IB_QPS_RESET
] = CMD_ERR2RST_QPEE
,
1721 [IB_QPS_ERR
] = CMD_2ERR_QPEE
,
1722 [IB_QPS_RTS
] = CMD_SQD2RTS_QPEE
,
1723 [IB_QPS_SQD
] = CMD_SQD2SQD_QPEE
,
1726 [IB_QPS_RESET
] = CMD_ERR2RST_QPEE
,
1727 [IB_QPS_ERR
] = CMD_2ERR_QPEE
,
1728 [IB_QPS_RTS
] = CMD_SQERR2RTS_QPEE
,
1731 [IB_QPS_RESET
] = CMD_ERR2RST_QPEE
,
1732 [IB_QPS_ERR
] = CMD_2ERR_QPEE
,
1740 if (op
[cur
][next
] == CMD_ERR2RST_QPEE
) {
1741 op_mod
= 3; /* don't write outbox, any->reset */
1745 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1746 if (!IS_ERR(mailbox
)) {
1748 op_mod
= 2; /* write outbox, any->reset */
1753 err
= mthca_cmd_box(dev
, 0, mailbox
? mailbox
->dma
: 0,
1754 (!!is_ee
<< 24) | num
, op_mod
,
1755 op
[cur
][next
], CMD_TIME_CLASS_C
, status
);
1759 mthca_dbg(dev
, "Dumping QP context:\n");
1760 printk(" %08x\n", be32_to_cpup(mailbox
->buf
));
1761 for (i
= 0; i
< 0x100 / 4; ++i
) {
1763 printk("[%02x] ", i
* 4);
1765 be32_to_cpu(((__be32
*) mailbox
->buf
)[i
+ 2]));
1766 if ((i
+ 1) % 8 == 0)
1772 mthca_free_mailbox(dev
, mailbox
);
1776 mthca_dbg(dev
, "Dumping QP context:\n");
1777 printk(" opt param mask: %08x\n", be32_to_cpup(mailbox
->buf
));
1778 for (i
= 0; i
< 0x100 / 4; ++i
) {
1780 printk(" [%02x] ", i
* 4);
1782 be32_to_cpu(((__be32
*) mailbox
->buf
)[i
+ 2]));
1783 if ((i
+ 1) % 8 == 0)
1788 err
= mthca_cmd(dev
, mailbox
->dma
, optmask
| (!!is_ee
<< 24) | num
,
1789 op_mod
, op
[cur
][next
], CMD_TIME_CLASS_C
, status
);
1795 int mthca_QUERY_QP(struct mthca_dev
*dev
, u32 num
, int is_ee
,
1796 struct mthca_mailbox
*mailbox
, u8
*status
)
1798 return mthca_cmd_box(dev
, 0, mailbox
->dma
, (!!is_ee
<< 24) | num
, 0,
1799 CMD_QUERY_QPEE
, CMD_TIME_CLASS_A
, status
);
1802 int mthca_CONF_SPECIAL_QP(struct mthca_dev
*dev
, int type
, u32 qpn
,
1814 case IB_QPT_RAW_IPV6
:
1817 case IB_QPT_RAW_ETY
:
1824 return mthca_cmd(dev
, 0, qpn
, op_mod
, CMD_CONF_SPECIAL_QP
,
1825 CMD_TIME_CLASS_B
, status
);
1828 int mthca_MAD_IFC(struct mthca_dev
*dev
, int ignore_mkey
, int ignore_bkey
,
1829 int port
, struct ib_wc
*in_wc
, struct ib_grh
*in_grh
,
1830 void *in_mad
, void *response_mad
, u8
*status
)
1832 struct mthca_mailbox
*inmailbox
, *outmailbox
;
1835 u32 in_modifier
= port
;
1838 #define MAD_IFC_BOX_SIZE 0x400
1839 #define MAD_IFC_MY_QPN_OFFSET 0x100
1840 #define MAD_IFC_RQPN_OFFSET 0x108
1841 #define MAD_IFC_SL_OFFSET 0x10c
1842 #define MAD_IFC_G_PATH_OFFSET 0x10d
1843 #define MAD_IFC_RLID_OFFSET 0x10e
1844 #define MAD_IFC_PKEY_OFFSET 0x112
1845 #define MAD_IFC_GRH_OFFSET 0x140
1847 inmailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1848 if (IS_ERR(inmailbox
))
1849 return PTR_ERR(inmailbox
);
1850 inbox
= inmailbox
->buf
;
1852 outmailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1853 if (IS_ERR(outmailbox
)) {
1854 mthca_free_mailbox(dev
, inmailbox
);
1855 return PTR_ERR(outmailbox
);
1858 memcpy(inbox
, in_mad
, 256);
1861 * Key check traps can't be generated unless we have in_wc to
1862 * tell us where to send the trap.
1864 if (ignore_mkey
|| !in_wc
)
1866 if (ignore_bkey
|| !in_wc
)
1872 memset(inbox
+ 256, 0, 256);
1874 MTHCA_PUT(inbox
, in_wc
->qp
->qp_num
, MAD_IFC_MY_QPN_OFFSET
);
1875 MTHCA_PUT(inbox
, in_wc
->src_qp
, MAD_IFC_RQPN_OFFSET
);
1877 val
= in_wc
->sl
<< 4;
1878 MTHCA_PUT(inbox
, val
, MAD_IFC_SL_OFFSET
);
1880 val
= in_wc
->dlid_path_bits
|
1881 (in_wc
->wc_flags
& IB_WC_GRH
? 0x80 : 0);
1882 MTHCA_PUT(inbox
, val
, MAD_IFC_G_PATH_OFFSET
);
1884 MTHCA_PUT(inbox
, in_wc
->slid
, MAD_IFC_RLID_OFFSET
);
1885 MTHCA_PUT(inbox
, in_wc
->pkey_index
, MAD_IFC_PKEY_OFFSET
);
1888 memcpy(inbox
+ MAD_IFC_GRH_OFFSET
, in_grh
, 40);
1892 in_modifier
|= in_wc
->slid
<< 16;
1895 err
= mthca_cmd_box(dev
, inmailbox
->dma
, outmailbox
->dma
,
1896 in_modifier
, op_modifier
,
1897 CMD_MAD_IFC
, CMD_TIME_CLASS_C
, status
);
1899 if (!err
&& !*status
)
1900 memcpy(response_mad
, outmailbox
->buf
, 256);
1902 mthca_free_mailbox(dev
, inmailbox
);
1903 mthca_free_mailbox(dev
, outmailbox
);
1907 int mthca_READ_MGM(struct mthca_dev
*dev
, int index
,
1908 struct mthca_mailbox
*mailbox
, u8
*status
)
1910 return mthca_cmd_box(dev
, 0, mailbox
->dma
, index
, 0,
1911 CMD_READ_MGM
, CMD_TIME_CLASS_A
, status
);
1914 int mthca_WRITE_MGM(struct mthca_dev
*dev
, int index
,
1915 struct mthca_mailbox
*mailbox
, u8
*status
)
1917 return mthca_cmd(dev
, mailbox
->dma
, index
, 0, CMD_WRITE_MGM
,
1918 CMD_TIME_CLASS_A
, status
);
1921 int mthca_MGID_HASH(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1922 u16
*hash
, u8
*status
)
1927 err
= mthca_cmd_imm(dev
, mailbox
->dma
, &imm
, 0, 0, CMD_MGID_HASH
,
1928 CMD_TIME_CLASS_A
, status
);
1934 int mthca_NOP(struct mthca_dev
*dev
, u8
*status
)
1936 return mthca_cmd(dev
, 0, 0x1f, 0, CMD_NOP
, msecs_to_jiffies(100), status
);