2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.20"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
79 #define SKY2_EEPROM_MAGIC 0x9955aabb
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84 static const u32 default_msg
=
85 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
86 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
89 static int debug
= -1; /* defaults above */
90 module_param(debug
, int, 0);
91 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
93 static int copybreak __read_mostly
= 128;
94 module_param(copybreak
, int, 0);
95 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
97 static int disable_msi
= 0;
98 module_param(disable_msi
, int, 0);
99 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
101 static const struct pci_device_id sky2_id_table
[] = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4354) }, /* 88E8040 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436C) }, /* 88E8072 */
140 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
142 /* Avoid conditionals by using array */
143 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
144 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
145 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
147 /* This driver supports yukon2 chipset only */
148 static const char *yukon2_name
[] = {
150 "EC Ultra", /* 0xb4 */
151 "Extreme", /* 0xb5 */
157 static void sky2_set_multicast(struct net_device
*dev
);
159 /* Access to PHY via serial interconnect */
160 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
164 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
165 gma_write16(hw
, port
, GM_SMI_CTRL
,
166 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
168 for (i
= 0; i
< PHY_RETRIES
; i
++) {
169 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
173 if (!(ctrl
& GM_SMI_CT_BUSY
))
179 dev_warn(&hw
->pdev
->dev
,"%s: phy write timeout\n", hw
->dev
[port
]->name
);
183 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
187 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
191 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
192 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
194 for (i
= 0; i
< PHY_RETRIES
; i
++) {
195 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
199 if (ctrl
& GM_SMI_CT_RD_VAL
) {
200 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
207 dev_warn(&hw
->pdev
->dev
, "%s: phy read timeout\n", hw
->dev
[port
]->name
);
210 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
214 static inline u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
217 __gm_phy_read(hw
, port
, reg
, &v
);
222 static void sky2_power_on(struct sky2_hw
*hw
)
224 /* switch power to VCC (WA for VAUX problem) */
225 sky2_write8(hw
, B0_POWER_CTRL
,
226 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
228 /* disable Core Clock Division, */
229 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
231 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
232 /* enable bits are inverted */
233 sky2_write8(hw
, B2_Y2_CLK_GATE
,
234 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
235 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
236 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
238 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
240 if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
) {
243 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
245 reg
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
246 /* set all bits to 0 except bits 15..12 and 8 */
247 reg
&= P_ASPM_CONTROL_MSK
;
248 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg
);
250 reg
= sky2_pci_read32(hw
, PCI_DEV_REG5
);
251 /* set all bits to 0 except bits 28 & 27 */
252 reg
&= P_CTL_TIM_VMAIN_AV_MSK
;
253 sky2_pci_write32(hw
, PCI_DEV_REG5
, reg
);
255 sky2_pci_write32(hw
, PCI_CFG_REG_1
, 0);
257 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
258 reg
= sky2_read32(hw
, B2_GP_IO
);
259 reg
|= GLB_GPIO_STAT_RACE_DIS
;
260 sky2_write32(hw
, B2_GP_IO
, reg
);
262 sky2_read32(hw
, B2_GP_IO
);
266 static void sky2_power_aux(struct sky2_hw
*hw
)
268 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
269 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
271 /* enable bits are inverted */
272 sky2_write8(hw
, B2_Y2_CLK_GATE
,
273 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
274 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
275 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
277 /* switch power to VAUX */
278 if (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
)
279 sky2_write8(hw
, B0_POWER_CTRL
,
280 (PC_VAUX_ENA
| PC_VCC_ENA
|
281 PC_VAUX_ON
| PC_VCC_OFF
));
284 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
288 /* disable all GMAC IRQ's */
289 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
291 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
292 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
293 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
294 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
296 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
297 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
298 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
301 /* flow control to advertise bits */
302 static const u16 copper_fc_adv
[] = {
304 [FC_TX
] = PHY_M_AN_ASP
,
305 [FC_RX
] = PHY_M_AN_PC
,
306 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
309 /* flow control to advertise bits when using 1000BaseX */
310 static const u16 fiber_fc_adv
[] = {
311 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
312 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
313 [FC_RX
] = PHY_M_P_SYM_MD_X
,
314 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
317 /* flow control to GMA disable bits */
318 static const u16 gm_fc_disable
[] = {
319 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
320 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
321 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
326 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
328 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
329 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
331 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
332 !(hw
->flags
& SKY2_HW_NEWER_PHY
)) {
333 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
335 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
337 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
339 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
340 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
341 /* set downshift counter to 3x and enable downshift */
342 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
344 /* set master & slave downshift counter to 1x */
345 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
347 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
350 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
351 if (sky2_is_copper(hw
)) {
352 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
353 /* enable automatic crossover */
354 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
356 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
357 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
360 /* Enable Class A driver for FE+ A0 */
361 spec
= gm_phy_read(hw
, port
, PHY_MARV_FE_SPEC_2
);
362 spec
|= PHY_M_FESC_SEL_CL_A
;
363 gm_phy_write(hw
, port
, PHY_MARV_FE_SPEC_2
, spec
);
366 /* disable energy detect */
367 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
369 /* enable automatic crossover */
370 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
372 /* downshift on PHY 88E1112 and 88E1149 is changed */
373 if (sky2
->autoneg
== AUTONEG_ENABLE
374 && (hw
->flags
& SKY2_HW_NEWER_PHY
)) {
375 /* set downshift counter to 3x and enable downshift */
376 ctrl
&= ~PHY_M_PC_DSC_MSK
;
377 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
381 /* workaround for deviation #4.88 (CRC errors) */
382 /* disable Automatic Crossover */
384 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
387 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
389 /* special setup for PHY 88E1112 Fiber */
390 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& (hw
->flags
& SKY2_HW_FIBRE_PHY
)) {
391 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
393 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
394 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
395 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
396 ctrl
&= ~PHY_M_MAC_MD_MSK
;
397 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
398 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
400 if (hw
->pmd_type
== 'P') {
401 /* select page 1 to access Fiber registers */
402 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
404 /* for SFP-module set SIGDET polarity to low */
405 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
406 ctrl
|= PHY_M_FIB_SIGD_POL
;
407 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
410 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
418 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
419 if (sky2_is_copper(hw
)) {
420 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
421 ct1000
|= PHY_M_1000C_AFD
;
422 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
423 ct1000
|= PHY_M_1000C_AHD
;
424 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
425 adv
|= PHY_M_AN_100_FD
;
426 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
427 adv
|= PHY_M_AN_100_HD
;
428 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
429 adv
|= PHY_M_AN_10_FD
;
430 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
431 adv
|= PHY_M_AN_10_HD
;
433 adv
|= copper_fc_adv
[sky2
->flow_mode
];
434 } else { /* special defines for FIBER (88E1040S only) */
435 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
436 adv
|= PHY_M_AN_1000X_AFD
;
437 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
438 adv
|= PHY_M_AN_1000X_AHD
;
440 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
443 /* Restart Auto-negotiation */
444 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
446 /* forced speed/duplex settings */
447 ct1000
= PHY_M_1000C_MSE
;
449 /* Disable auto update for duplex flow control and speed */
450 reg
|= GM_GPCR_AU_ALL_DIS
;
452 switch (sky2
->speed
) {
454 ctrl
|= PHY_CT_SP1000
;
455 reg
|= GM_GPCR_SPEED_1000
;
458 ctrl
|= PHY_CT_SP100
;
459 reg
|= GM_GPCR_SPEED_100
;
463 if (sky2
->duplex
== DUPLEX_FULL
) {
464 reg
|= GM_GPCR_DUP_FULL
;
465 ctrl
|= PHY_CT_DUP_MD
;
466 } else if (sky2
->speed
< SPEED_1000
)
467 sky2
->flow_mode
= FC_NONE
;
470 reg
|= gm_fc_disable
[sky2
->flow_mode
];
472 /* Forward pause packets to GMAC? */
473 if (sky2
->flow_mode
& FC_RX
)
474 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
476 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
479 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
481 if (hw
->flags
& SKY2_HW_GIGABIT
)
482 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
484 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
485 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
487 /* Setup Phy LED's */
488 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
491 switch (hw
->chip_id
) {
492 case CHIP_ID_YUKON_FE
:
493 /* on 88E3082 these bits are at 11..9 (shifted left) */
494 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
496 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
498 /* delete ACT LED control bits */
499 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
500 /* change ACT LED control to blink mode */
501 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
502 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
505 case CHIP_ID_YUKON_FE_P
:
506 /* Enable Link Partner Next Page */
507 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
508 ctrl
|= PHY_M_PC_ENA_LIP_NP
;
510 /* disable Energy Detect and enable scrambler */
511 ctrl
&= ~(PHY_M_PC_ENA_ENE_DT
| PHY_M_PC_DIS_SCRAMB
);
512 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
514 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
515 ctrl
= PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL
) |
516 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK
) |
517 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED
);
519 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
522 case CHIP_ID_YUKON_XL
:
523 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
525 /* select page 3 to access LED control register */
526 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
528 /* set LED Function Control register */
529 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
530 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
531 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
532 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
533 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
535 /* set Polarity Control register */
536 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
537 (PHY_M_POLC_LS1_P_MIX(4) |
538 PHY_M_POLC_IS0_P_MIX(4) |
539 PHY_M_POLC_LOS_CTRL(2) |
540 PHY_M_POLC_INIT_CTRL(2) |
541 PHY_M_POLC_STA1_CTRL(2) |
542 PHY_M_POLC_STA0_CTRL(2)));
544 /* restore page register */
545 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
548 case CHIP_ID_YUKON_EC_U
:
549 case CHIP_ID_YUKON_EX
:
550 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
552 /* select page 3 to access LED control register */
553 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
555 /* set LED Function Control register */
556 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
557 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
558 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
559 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
560 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
562 /* set Blink Rate in LED Timer Control Register */
563 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
564 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
565 /* restore page register */
566 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
570 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
571 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
572 /* turn off the Rx LED (LED_RX) */
573 ledover
&= ~PHY_M_LED_MO_RX
;
576 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
577 hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
) {
578 /* apply fixes in PHY AFE */
579 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
581 /* increase differential signal amplitude in 10BASE-T */
582 gm_phy_write(hw
, port
, 0x18, 0xaa99);
583 gm_phy_write(hw
, port
, 0x17, 0x2011);
585 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
586 gm_phy_write(hw
, port
, 0x18, 0xa204);
587 gm_phy_write(hw
, port
, 0x17, 0x2002);
589 /* set page register to 0 */
590 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
591 } else if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
592 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
593 /* apply workaround for integrated resistors calibration */
594 gm_phy_write(hw
, port
, PHY_MARV_PAGE_ADDR
, 17);
595 gm_phy_write(hw
, port
, PHY_MARV_PAGE_DATA
, 0x3f60);
596 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
) {
597 /* no effect on Yukon-XL */
598 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
600 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
601 /* turn on 100 Mbps LED (LED_LINK100) */
602 ledover
|= PHY_M_LED_MO_100
;
606 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
610 /* Enable phy interrupt on auto-negotiation complete (or link up) */
611 if (sky2
->autoneg
== AUTONEG_ENABLE
)
612 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
614 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
617 static void sky2_phy_power(struct sky2_hw
*hw
, unsigned port
, int onoff
)
620 static const u32 phy_power
[] = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
621 static const u32 coma_mode
[] = { PCI_Y2_PHY1_COMA
, PCI_Y2_PHY2_COMA
};
623 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
624 /* Turn on/off phy power saving */
626 reg1
&= ~phy_power
[port
];
628 reg1
|= phy_power
[port
];
630 if (onoff
&& hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
631 reg1
|= coma_mode
[port
];
633 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
634 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
639 /* Force a renegotiation */
640 static void sky2_phy_reinit(struct sky2_port
*sky2
)
642 spin_lock_bh(&sky2
->phy_lock
);
643 sky2_phy_init(sky2
->hw
, sky2
->port
);
644 spin_unlock_bh(&sky2
->phy_lock
);
647 /* Put device in state to listen for Wake On Lan */
648 static void sky2_wol_init(struct sky2_port
*sky2
)
650 struct sky2_hw
*hw
= sky2
->hw
;
651 unsigned port
= sky2
->port
;
652 enum flow_control save_mode
;
656 /* Bring hardware out of reset */
657 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
658 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
660 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
661 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
664 * sky2_reset will re-enable on resume
666 save_mode
= sky2
->flow_mode
;
667 ctrl
= sky2
->advertising
;
669 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
670 sky2
->flow_mode
= FC_NONE
;
671 sky2_phy_power(hw
, port
, 1);
672 sky2_phy_reinit(sky2
);
674 sky2
->flow_mode
= save_mode
;
675 sky2
->advertising
= ctrl
;
677 /* Set GMAC to no flow control and auto update for speed/duplex */
678 gma_write16(hw
, port
, GM_GP_CTRL
,
679 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
680 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
682 /* Set WOL address */
683 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
684 sky2
->netdev
->dev_addr
, ETH_ALEN
);
686 /* Turn on appropriate WOL control bits */
687 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
689 if (sky2
->wol
& WAKE_PHY
)
690 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
692 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
694 if (sky2
->wol
& WAKE_MAGIC
)
695 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
697 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;;
699 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
700 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
702 /* Turn on legacy PCI-Express PME mode */
703 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
704 reg1
|= PCI_Y2_PME_LEGACY
;
705 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
708 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
712 static void sky2_set_tx_stfwd(struct sky2_hw
*hw
, unsigned port
)
714 struct net_device
*dev
= hw
->dev
[port
];
716 if (dev
->mtu
<= ETH_DATA_LEN
)
717 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
718 TX_JUMBO_DIS
| TX_STFW_ENA
);
720 else if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
721 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
722 TX_STFW_ENA
| TX_JUMBO_ENA
);
724 /* set Tx GMAC FIFO Almost Empty Threshold */
725 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
726 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
728 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
729 TX_JUMBO_ENA
| TX_STFW_DIS
);
731 /* Can't do offload because of lack of store/forward */
732 dev
->features
&= ~(NETIF_F_TSO
| NETIF_F_SG
| NETIF_F_ALL_CSUM
);
736 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
738 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
742 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
744 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
745 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
747 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
749 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
750 /* WA DEV_472 -- looks like crossed wires on port 2 */
751 /* clear GMAC 1 Control reset */
752 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
754 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
755 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
756 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
757 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
758 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
761 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
763 /* Enable Transmit FIFO Underrun */
764 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
766 spin_lock_bh(&sky2
->phy_lock
);
767 sky2_phy_init(hw
, port
);
768 spin_unlock_bh(&sky2
->phy_lock
);
771 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
772 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
774 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
775 gma_read16(hw
, port
, i
);
776 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
778 /* transmit control */
779 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
781 /* receive control reg: unicast + multicast + no FCS */
782 gma_write16(hw
, port
, GM_RX_CTRL
,
783 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
785 /* transmit flow control */
786 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
788 /* transmit parameter */
789 gma_write16(hw
, port
, GM_TX_PARAM
,
790 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
791 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
792 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
793 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
795 /* serial mode register */
796 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
797 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
799 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
800 reg
|= GM_SMOD_JUMBO_ENA
;
802 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
804 /* virtual address for data */
805 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
807 /* physical address: used for pause frames */
808 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
810 /* ignore counter overflows */
811 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
812 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
813 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
815 /* Configure Rx MAC FIFO */
816 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
817 rx_reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
818 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
819 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
820 rx_reg
|= GMF_RX_OVER_ON
;
822 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), rx_reg
);
824 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
825 /* Hardware errata - clear flush mask */
826 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), 0);
828 /* Flush Rx MAC FIFO on any flow control or error */
829 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
832 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
833 reg
= RX_GMF_FL_THR_DEF
+ 1;
834 /* Another magic mystery workaround from sk98lin */
835 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
836 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
838 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), reg
);
840 /* Configure Tx MAC FIFO */
841 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
842 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
844 /* On chips without ram buffer, pause is controled by MAC level */
845 if (sky2_read8(hw
, B2_E_0
) == 0) {
846 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
847 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
849 sky2_set_tx_stfwd(hw
, port
);
852 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
853 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
854 /* disable dynamic watermark */
855 reg
= sky2_read16(hw
, SK_REG(port
, TX_GMF_EA
));
856 reg
&= ~TX_DYN_WM_ENA
;
857 sky2_write16(hw
, SK_REG(port
, TX_GMF_EA
), reg
);
861 /* Assign Ram Buffer allocation to queue */
862 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
866 /* convert from K bytes to qwords used for hw register */
869 end
= start
+ space
- 1;
871 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
872 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
873 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
874 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
875 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
877 if (q
== Q_R1
|| q
== Q_R2
) {
878 u32 tp
= space
- space
/4;
880 /* On receive queue's set the thresholds
881 * give receiver priority when > 3/4 full
882 * send pause when down to 2K
884 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
885 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
888 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
889 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
891 /* Enable store & forward on Tx queue's because
892 * Tx FIFO is only 1K on Yukon
894 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
897 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
898 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
901 /* Setup Bus Memory Interface */
902 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
904 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
905 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
906 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
907 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
910 /* Setup prefetch unit registers. This is the interface between
911 * hardware and driver list elements
913 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
916 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
917 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
918 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
919 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
920 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
921 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
923 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
926 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
928 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
930 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
935 static void tx_init(struct sky2_port
*sky2
)
937 struct sky2_tx_le
*le
;
939 sky2
->tx_prod
= sky2
->tx_cons
= 0;
941 sky2
->tx_last_mss
= 0;
943 le
= get_tx_le(sky2
);
945 le
->opcode
= OP_ADDR64
| HW_OWNER
;
948 static inline struct tx_ring_info
*tx_le_re(struct sky2_port
*sky2
,
949 struct sky2_tx_le
*le
)
951 return sky2
->tx_ring
+ (le
- sky2
->tx_le
);
954 /* Update chip's next pointer */
955 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
957 /* Make sure write' to descriptors are complete before we tell hardware */
959 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
961 /* Synchronize I/O on since next processor may write to tail */
966 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
968 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
969 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
974 /* Build description to hardware for one receive segment */
975 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
976 dma_addr_t map
, unsigned len
)
978 struct sky2_rx_le
*le
;
980 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
981 le
= sky2_next_rx(sky2
);
982 le
->addr
= cpu_to_le32(upper_32_bits(map
));
983 le
->opcode
= OP_ADDR64
| HW_OWNER
;
986 le
= sky2_next_rx(sky2
);
987 le
->addr
= cpu_to_le32((u32
) map
);
988 le
->length
= cpu_to_le16(len
);
989 le
->opcode
= op
| HW_OWNER
;
992 /* Build description to hardware for one possibly fragmented skb */
993 static void sky2_rx_submit(struct sky2_port
*sky2
,
994 const struct rx_ring_info
*re
)
998 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
1000 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
1001 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
1005 static void sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
1008 struct sk_buff
*skb
= re
->skb
;
1011 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
1012 pci_unmap_len_set(re
, data_size
, size
);
1014 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
1015 re
->frag_addr
[i
] = pci_map_page(pdev
,
1016 skb_shinfo(skb
)->frags
[i
].page
,
1017 skb_shinfo(skb
)->frags
[i
].page_offset
,
1018 skb_shinfo(skb
)->frags
[i
].size
,
1019 PCI_DMA_FROMDEVICE
);
1022 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
1024 struct sk_buff
*skb
= re
->skb
;
1027 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
1028 PCI_DMA_FROMDEVICE
);
1030 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
1031 pci_unmap_page(pdev
, re
->frag_addr
[i
],
1032 skb_shinfo(skb
)->frags
[i
].size
,
1033 PCI_DMA_FROMDEVICE
);
1036 /* Tell chip where to start receive checksum.
1037 * Actually has two checksums, but set both same to avoid possible byte
1040 static void rx_set_checksum(struct sky2_port
*sky2
)
1042 struct sky2_rx_le
*le
= sky2_next_rx(sky2
);
1044 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
1046 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
1048 sky2_write32(sky2
->hw
,
1049 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
1050 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
1054 * The RX Stop command will not work for Yukon-2 if the BMU does not
1055 * reach the end of packet and since we can't make sure that we have
1056 * incoming data, we must reset the BMU while it is not doing a DMA
1057 * transfer. Since it is possible that the RX path is still active,
1058 * the RX RAM buffer will be stopped first, so any possible incoming
1059 * data will not trigger a DMA. After the RAM buffer is stopped, the
1060 * BMU is polled until any DMA in progress is ended and only then it
1063 static void sky2_rx_stop(struct sky2_port
*sky2
)
1065 struct sky2_hw
*hw
= sky2
->hw
;
1066 unsigned rxq
= rxqaddr
[sky2
->port
];
1069 /* disable the RAM Buffer receive queue */
1070 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
1072 for (i
= 0; i
< 0xffff; i
++)
1073 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
1074 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
1077 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
1078 sky2
->netdev
->name
);
1080 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
1082 /* reset the Rx prefetch unit */
1083 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1087 /* Clean out receive buffer area, assumes receiver hardware stopped */
1088 static void sky2_rx_clean(struct sky2_port
*sky2
)
1092 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1093 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1094 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1097 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1104 /* Basic MII support */
1105 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1107 struct mii_ioctl_data
*data
= if_mii(ifr
);
1108 struct sky2_port
*sky2
= netdev_priv(dev
);
1109 struct sky2_hw
*hw
= sky2
->hw
;
1110 int err
= -EOPNOTSUPP
;
1112 if (!netif_running(dev
))
1113 return -ENODEV
; /* Phy still in reset */
1117 data
->phy_id
= PHY_ADDR_MARV
;
1123 spin_lock_bh(&sky2
->phy_lock
);
1124 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1125 spin_unlock_bh(&sky2
->phy_lock
);
1127 data
->val_out
= val
;
1132 if (!capable(CAP_NET_ADMIN
))
1135 spin_lock_bh(&sky2
->phy_lock
);
1136 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1138 spin_unlock_bh(&sky2
->phy_lock
);
1144 #ifdef SKY2_VLAN_TAG_USED
1145 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1147 struct sky2_port
*sky2
= netdev_priv(dev
);
1148 struct sky2_hw
*hw
= sky2
->hw
;
1149 u16 port
= sky2
->port
;
1151 netif_tx_lock_bh(dev
);
1152 napi_disable(&hw
->napi
);
1156 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1158 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1161 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1163 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1167 sky2_read32(hw
, B0_Y2_SP_LISR
);
1168 napi_enable(&hw
->napi
);
1169 netif_tx_unlock_bh(dev
);
1174 * Allocate an skb for receiving. If the MTU is large enough
1175 * make the skb non-linear with a fragment list of pages.
1177 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1179 struct sk_buff
*skb
;
1182 if (sky2
->hw
->flags
& SKY2_HW_FIFO_HANG_CHECK
) {
1183 unsigned char *start
;
1185 * Workaround for a bug in FIFO that cause hang
1186 * if the FIFO if the receive buffer is not 64 byte aligned.
1187 * The buffer returned from netdev_alloc_skb is
1188 * aligned except if slab debugging is enabled.
1190 skb
= netdev_alloc_skb(sky2
->netdev
, sky2
->rx_data_size
+ 8);
1193 start
= PTR_ALIGN(skb
->data
, 8);
1194 skb_reserve(skb
, start
- skb
->data
);
1196 skb
= netdev_alloc_skb(sky2
->netdev
,
1197 sky2
->rx_data_size
+ NET_IP_ALIGN
);
1200 skb_reserve(skb
, NET_IP_ALIGN
);
1203 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1204 struct page
*page
= alloc_page(GFP_ATOMIC
);
1208 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1218 static inline void sky2_rx_update(struct sky2_port
*sky2
, unsigned rxq
)
1220 sky2_put_idx(sky2
->hw
, rxq
, sky2
->rx_put
);
1224 * Allocate and setup receiver buffer pool.
1225 * Normal case this ends up creating one list element for skb
1226 * in the receive ring. Worst case if using large MTU and each
1227 * allocation falls on a different 64 bit region, that results
1228 * in 6 list elements per ring entry.
1229 * One element is used for checksum enable/disable, and one
1230 * extra to avoid wrap.
1232 static int sky2_rx_start(struct sky2_port
*sky2
)
1234 struct sky2_hw
*hw
= sky2
->hw
;
1235 struct rx_ring_info
*re
;
1236 unsigned rxq
= rxqaddr
[sky2
->port
];
1237 unsigned i
, size
, space
, thresh
;
1239 sky2
->rx_put
= sky2
->rx_next
= 0;
1242 /* On PCI express lowering the watermark gives better performance */
1243 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1244 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1246 /* These chips have no ram buffer?
1247 * MAC Rx RAM Read is controlled by hardware */
1248 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1249 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
1250 || hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1251 sky2_write32(hw
, Q_ADDR(rxq
, Q_TEST
), F_M_RX_RAM_DIS
);
1253 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1255 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1256 rx_set_checksum(sky2
);
1258 /* Space needed for frame data + headers rounded up */
1259 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1261 /* Stopping point for hardware truncation */
1262 thresh
= (size
- 8) / sizeof(u32
);
1264 /* Account for overhead of skb - to avoid order > 0 allocation */
1265 space
= SKB_DATA_ALIGN(size
) + NET_SKB_PAD
1266 + sizeof(struct skb_shared_info
);
1268 sky2
->rx_nfrags
= space
>> PAGE_SHIFT
;
1269 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1271 if (sky2
->rx_nfrags
!= 0) {
1272 /* Compute residue after pages */
1273 space
= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1280 /* Optimize to handle small packets and headers */
1281 if (size
< copybreak
)
1283 if (size
< ETH_HLEN
)
1286 sky2
->rx_data_size
= size
;
1289 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1290 re
= sky2
->rx_ring
+ i
;
1292 re
->skb
= sky2_rx_alloc(sky2
);
1296 sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
);
1297 sky2_rx_submit(sky2
, re
);
1301 * The receiver hangs if it receives frames larger than the
1302 * packet buffer. As a workaround, truncate oversize frames, but
1303 * the register is limited to 9 bits, so if you do frames > 2052
1304 * you better get the MTU right!
1307 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1309 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1310 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1313 /* Tell chip about available buffers */
1314 sky2_rx_update(sky2
, rxq
);
1317 sky2_rx_clean(sky2
);
1321 /* Bring up network interface. */
1322 static int sky2_up(struct net_device
*dev
)
1324 struct sky2_port
*sky2
= netdev_priv(dev
);
1325 struct sky2_hw
*hw
= sky2
->hw
;
1326 unsigned port
= sky2
->port
;
1328 int cap
, err
= -ENOMEM
;
1329 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1332 * On dual port PCI-X card, there is an problem where status
1333 * can be received out of order due to split transactions
1335 if (otherdev
&& netif_running(otherdev
) &&
1336 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1339 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1340 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1341 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1345 if (netif_msg_ifup(sky2
))
1346 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1348 netif_carrier_off(dev
);
1350 /* must be power of 2 */
1351 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1353 sizeof(struct sky2_tx_le
),
1358 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1365 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1369 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1371 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1376 sky2_phy_power(hw
, port
, 1);
1378 sky2_mac_init(hw
, port
);
1380 /* Register is number of 4K blocks on internal RAM buffer. */
1381 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1385 pr_debug(PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1387 rxspace
= ramsize
/ 2;
1389 rxspace
= 8 + (2*(ramsize
- 16))/3;
1391 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1392 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1394 /* Make sure SyncQ is disabled */
1395 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1399 sky2_qset(hw
, txqaddr
[port
]);
1401 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1402 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
== CHIP_REV_YU_EX_B0
)
1403 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_TEST
), F_TX_CHK_AUTO_OFF
);
1405 /* Set almost empty threshold */
1406 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1407 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1408 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1410 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1413 err
= sky2_rx_start(sky2
);
1417 /* Enable interrupts from phy/mac for port */
1418 imask
= sky2_read32(hw
, B0_IMSK
);
1419 imask
|= portirq_msk
[port
];
1420 sky2_write32(hw
, B0_IMSK
, imask
);
1426 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1427 sky2
->rx_le
, sky2
->rx_le_map
);
1431 pci_free_consistent(hw
->pdev
,
1432 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1433 sky2
->tx_le
, sky2
->tx_le_map
);
1436 kfree(sky2
->tx_ring
);
1437 kfree(sky2
->rx_ring
);
1439 sky2
->tx_ring
= NULL
;
1440 sky2
->rx_ring
= NULL
;
1444 /* Modular subtraction in ring */
1445 static inline int tx_dist(unsigned tail
, unsigned head
)
1447 return (head
- tail
) & (TX_RING_SIZE
- 1);
1450 /* Number of list elements available for next tx */
1451 static inline int tx_avail(const struct sky2_port
*sky2
)
1453 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1456 /* Estimate of number of transmit list elements required */
1457 static unsigned tx_le_req(const struct sk_buff
*skb
)
1461 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1462 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1464 if (skb_is_gso(skb
))
1467 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1474 * Put one packet in ring for transmit.
1475 * A single packet can generate multiple list elements, and
1476 * the number of ring elements will probably be less than the number
1477 * of list elements used.
1479 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1481 struct sky2_port
*sky2
= netdev_priv(dev
);
1482 struct sky2_hw
*hw
= sky2
->hw
;
1483 struct sky2_tx_le
*le
= NULL
;
1484 struct tx_ring_info
*re
;
1490 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1491 return NETDEV_TX_BUSY
;
1493 if (unlikely(netif_msg_tx_queued(sky2
)))
1494 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1495 dev
->name
, sky2
->tx_prod
, skb
->len
);
1497 len
= skb_headlen(skb
);
1498 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1500 /* Send high bits if needed */
1501 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
1502 le
= get_tx_le(sky2
);
1503 le
->addr
= cpu_to_le32(upper_32_bits(mapping
));
1504 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1507 /* Check for TCP Segmentation Offload */
1508 mss
= skb_shinfo(skb
)->gso_size
;
1511 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1512 mss
+= ETH_HLEN
+ ip_hdrlen(skb
) + tcp_hdrlen(skb
);
1514 if (mss
!= sky2
->tx_last_mss
) {
1515 le
= get_tx_le(sky2
);
1516 le
->addr
= cpu_to_le32(mss
);
1518 if (hw
->flags
& SKY2_HW_NEW_LE
)
1519 le
->opcode
= OP_MSS
| HW_OWNER
;
1521 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1522 sky2
->tx_last_mss
= mss
;
1527 #ifdef SKY2_VLAN_TAG_USED
1528 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1529 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1531 le
= get_tx_le(sky2
);
1533 le
->opcode
= OP_VLAN
|HW_OWNER
;
1535 le
->opcode
|= OP_VLAN
;
1536 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1541 /* Handle TCP checksum offload */
1542 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1543 /* On Yukon EX (some versions) encoding change. */
1544 if (hw
->flags
& SKY2_HW_AUTO_TX_SUM
)
1545 ctrl
|= CALSUM
; /* auto checksum */
1547 const unsigned offset
= skb_transport_offset(skb
);
1550 tcpsum
= offset
<< 16; /* sum start */
1551 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1553 ctrl
|= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1554 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1557 if (tcpsum
!= sky2
->tx_tcpsum
) {
1558 sky2
->tx_tcpsum
= tcpsum
;
1560 le
= get_tx_le(sky2
);
1561 le
->addr
= cpu_to_le32(tcpsum
);
1562 le
->length
= 0; /* initial checksum value */
1563 le
->ctrl
= 1; /* one packet */
1564 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1569 le
= get_tx_le(sky2
);
1570 le
->addr
= cpu_to_le32((u32
) mapping
);
1571 le
->length
= cpu_to_le16(len
);
1573 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1575 re
= tx_le_re(sky2
, le
);
1577 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1578 pci_unmap_len_set(re
, maplen
, len
);
1580 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1581 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1583 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1584 frag
->size
, PCI_DMA_TODEVICE
);
1586 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
1587 le
= get_tx_le(sky2
);
1588 le
->addr
= cpu_to_le32(upper_32_bits(mapping
));
1590 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1593 le
= get_tx_le(sky2
);
1594 le
->addr
= cpu_to_le32((u32
) mapping
);
1595 le
->length
= cpu_to_le16(frag
->size
);
1597 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1599 re
= tx_le_re(sky2
, le
);
1601 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1602 pci_unmap_len_set(re
, maplen
, frag
->size
);
1607 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1608 netif_stop_queue(dev
);
1610 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1612 dev
->trans_start
= jiffies
;
1613 return NETDEV_TX_OK
;
1617 * Free ring elements from starting at tx_cons until "done"
1619 * NB: the hardware will tell us about partial completion of multi-part
1620 * buffers so make sure not to free skb to early.
1622 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1624 struct net_device
*dev
= sky2
->netdev
;
1625 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1628 BUG_ON(done
>= TX_RING_SIZE
);
1630 for (idx
= sky2
->tx_cons
; idx
!= done
;
1631 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
1632 struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
1633 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1635 switch(le
->opcode
& ~HW_OWNER
) {
1638 pci_unmap_single(pdev
,
1639 pci_unmap_addr(re
, mapaddr
),
1640 pci_unmap_len(re
, maplen
),
1644 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1645 pci_unmap_len(re
, maplen
),
1650 if (le
->ctrl
& EOP
) {
1651 if (unlikely(netif_msg_tx_done(sky2
)))
1652 printk(KERN_DEBUG
"%s: tx done %u\n",
1655 dev
->stats
.tx_packets
++;
1656 dev
->stats
.tx_bytes
+= re
->skb
->len
;
1658 dev_kfree_skb_any(re
->skb
);
1659 sky2
->tx_next
= RING_NEXT(idx
, TX_RING_SIZE
);
1663 sky2
->tx_cons
= idx
;
1666 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1667 netif_wake_queue(dev
);
1670 /* Cleanup all untransmitted buffers, assume transmitter not running */
1671 static void sky2_tx_clean(struct net_device
*dev
)
1673 struct sky2_port
*sky2
= netdev_priv(dev
);
1675 netif_tx_lock_bh(dev
);
1676 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1677 netif_tx_unlock_bh(dev
);
1680 /* Network shutdown */
1681 static int sky2_down(struct net_device
*dev
)
1683 struct sky2_port
*sky2
= netdev_priv(dev
);
1684 struct sky2_hw
*hw
= sky2
->hw
;
1685 unsigned port
= sky2
->port
;
1689 /* Never really got started! */
1693 if (netif_msg_ifdown(sky2
))
1694 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1696 /* Stop more packets from being queued */
1697 netif_stop_queue(dev
);
1699 /* Disable port IRQ */
1700 imask
= sky2_read32(hw
, B0_IMSK
);
1701 imask
&= ~portirq_msk
[port
];
1702 sky2_write32(hw
, B0_IMSK
, imask
);
1704 synchronize_irq(hw
->pdev
->irq
);
1706 sky2_gmac_reset(hw
, port
);
1708 /* Stop transmitter */
1709 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1710 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1712 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1713 RB_RST_SET
| RB_DIS_OP_MD
);
1715 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1716 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1717 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1719 /* Make sure no packets are pending */
1720 napi_synchronize(&hw
->napi
);
1722 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1724 /* Workaround shared GMAC reset */
1725 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1726 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1727 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1729 /* Disable Force Sync bit and Enable Alloc bit */
1730 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1731 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1733 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1734 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1735 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1737 /* Reset the PCI FIFO of the async Tx queue */
1738 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1739 BMU_RST_SET
| BMU_FIFO_RST
);
1741 /* Reset the Tx prefetch units */
1742 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1745 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1749 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1750 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1752 sky2_phy_power(hw
, port
, 0);
1754 netif_carrier_off(dev
);
1756 /* turn off LED's */
1757 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1760 sky2_rx_clean(sky2
);
1762 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1763 sky2
->rx_le
, sky2
->rx_le_map
);
1764 kfree(sky2
->rx_ring
);
1766 pci_free_consistent(hw
->pdev
,
1767 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1768 sky2
->tx_le
, sky2
->tx_le_map
);
1769 kfree(sky2
->tx_ring
);
1774 sky2
->rx_ring
= NULL
;
1775 sky2
->tx_ring
= NULL
;
1780 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1782 if (hw
->flags
& SKY2_HW_FIBRE_PHY
)
1785 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
1786 if (aux
& PHY_M_PS_SPEED_100
)
1792 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1793 case PHY_M_PS_SPEED_1000
:
1795 case PHY_M_PS_SPEED_100
:
1802 static void sky2_link_up(struct sky2_port
*sky2
)
1804 struct sky2_hw
*hw
= sky2
->hw
;
1805 unsigned port
= sky2
->port
;
1807 static const char *fc_name
[] = {
1815 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1816 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1817 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1819 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1821 netif_carrier_on(sky2
->netdev
);
1823 mod_timer(&hw
->watchdog_timer
, jiffies
+ 1);
1825 /* Turn on link LED */
1826 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1827 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1829 if (netif_msg_link(sky2
))
1830 printk(KERN_INFO PFX
1831 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1832 sky2
->netdev
->name
, sky2
->speed
,
1833 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1834 fc_name
[sky2
->flow_status
]);
1837 static void sky2_link_down(struct sky2_port
*sky2
)
1839 struct sky2_hw
*hw
= sky2
->hw
;
1840 unsigned port
= sky2
->port
;
1843 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1845 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1846 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1847 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1849 netif_carrier_off(sky2
->netdev
);
1851 /* Turn on link LED */
1852 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1854 if (netif_msg_link(sky2
))
1855 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1857 sky2_phy_init(hw
, port
);
1860 static enum flow_control
sky2_flow(int rx
, int tx
)
1863 return tx
? FC_BOTH
: FC_RX
;
1865 return tx
? FC_TX
: FC_NONE
;
1868 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1870 struct sky2_hw
*hw
= sky2
->hw
;
1871 unsigned port
= sky2
->port
;
1874 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
1875 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1876 if (lpa
& PHY_M_AN_RF
) {
1877 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1881 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1882 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1883 sky2
->netdev
->name
);
1887 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1888 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1890 /* Since the pause result bits seem to in different positions on
1891 * different chips. look at registers.
1893 if (hw
->flags
& SKY2_HW_FIBRE_PHY
) {
1894 /* Shift for bits in fiber PHY */
1895 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
1896 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
1898 if (advert
& ADVERTISE_1000XPAUSE
)
1899 advert
|= ADVERTISE_PAUSE_CAP
;
1900 if (advert
& ADVERTISE_1000XPSE_ASYM
)
1901 advert
|= ADVERTISE_PAUSE_ASYM
;
1902 if (lpa
& LPA_1000XPAUSE
)
1903 lpa
|= LPA_PAUSE_CAP
;
1904 if (lpa
& LPA_1000XPAUSE_ASYM
)
1905 lpa
|= LPA_PAUSE_ASYM
;
1908 sky2
->flow_status
= FC_NONE
;
1909 if (advert
& ADVERTISE_PAUSE_CAP
) {
1910 if (lpa
& LPA_PAUSE_CAP
)
1911 sky2
->flow_status
= FC_BOTH
;
1912 else if (advert
& ADVERTISE_PAUSE_ASYM
)
1913 sky2
->flow_status
= FC_RX
;
1914 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
1915 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
1916 sky2
->flow_status
= FC_TX
;
1919 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
1920 && !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
1921 sky2
->flow_status
= FC_NONE
;
1923 if (sky2
->flow_status
& FC_TX
)
1924 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1926 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1931 /* Interrupt from PHY */
1932 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1934 struct net_device
*dev
= hw
->dev
[port
];
1935 struct sky2_port
*sky2
= netdev_priv(dev
);
1936 u16 istatus
, phystat
;
1938 if (!netif_running(dev
))
1941 spin_lock(&sky2
->phy_lock
);
1942 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1943 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1945 if (netif_msg_intr(sky2
))
1946 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1947 sky2
->netdev
->name
, istatus
, phystat
);
1949 if (sky2
->autoneg
== AUTONEG_ENABLE
&& (istatus
& PHY_M_IS_AN_COMPL
)) {
1950 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1955 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1956 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1958 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1960 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1962 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1963 if (phystat
& PHY_M_PS_LINK_UP
)
1966 sky2_link_down(sky2
);
1969 spin_unlock(&sky2
->phy_lock
);
1972 /* Transmit timeout is only called if we are running, carrier is up
1973 * and tx queue is full (stopped).
1975 static void sky2_tx_timeout(struct net_device
*dev
)
1977 struct sky2_port
*sky2
= netdev_priv(dev
);
1978 struct sky2_hw
*hw
= sky2
->hw
;
1980 if (netif_msg_timer(sky2
))
1981 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1983 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1984 dev
->name
, sky2
->tx_cons
, sky2
->tx_prod
,
1985 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
1986 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
1988 /* can't restart safely under softirq */
1989 schedule_work(&hw
->restart_work
);
1992 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1994 struct sky2_port
*sky2
= netdev_priv(dev
);
1995 struct sky2_hw
*hw
= sky2
->hw
;
1996 unsigned port
= sky2
->port
;
2001 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2004 if (new_mtu
> ETH_DATA_LEN
&&
2005 (hw
->chip_id
== CHIP_ID_YUKON_FE
||
2006 hw
->chip_id
== CHIP_ID_YUKON_FE_P
))
2009 if (!netif_running(dev
)) {
2014 imask
= sky2_read32(hw
, B0_IMSK
);
2015 sky2_write32(hw
, B0_IMSK
, 0);
2017 dev
->trans_start
= jiffies
; /* prevent tx timeout */
2018 netif_stop_queue(dev
);
2019 napi_disable(&hw
->napi
);
2021 synchronize_irq(hw
->pdev
->irq
);
2023 if (sky2_read8(hw
, B2_E_0
) == 0)
2024 sky2_set_tx_stfwd(hw
, port
);
2026 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2027 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
2029 sky2_rx_clean(sky2
);
2033 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
2034 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
2036 if (dev
->mtu
> ETH_DATA_LEN
)
2037 mode
|= GM_SMOD_JUMBO_ENA
;
2039 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
2041 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
2043 err
= sky2_rx_start(sky2
);
2044 sky2_write32(hw
, B0_IMSK
, imask
);
2046 sky2_read32(hw
, B0_Y2_SP_LISR
);
2047 napi_enable(&hw
->napi
);
2052 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
2054 netif_wake_queue(dev
);
2060 /* For small just reuse existing skb for next receive */
2061 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
2062 const struct rx_ring_info
*re
,
2065 struct sk_buff
*skb
;
2067 skb
= netdev_alloc_skb(sky2
->netdev
, length
+ 2);
2069 skb_reserve(skb
, 2);
2070 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
2071 length
, PCI_DMA_FROMDEVICE
);
2072 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
2073 skb
->ip_summed
= re
->skb
->ip_summed
;
2074 skb
->csum
= re
->skb
->csum
;
2075 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
2076 length
, PCI_DMA_FROMDEVICE
);
2077 re
->skb
->ip_summed
= CHECKSUM_NONE
;
2078 skb_put(skb
, length
);
2083 /* Adjust length of skb with fragments to match received data */
2084 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
2085 unsigned int length
)
2090 /* put header into skb */
2091 size
= min(length
, hdr_space
);
2096 num_frags
= skb_shinfo(skb
)->nr_frags
;
2097 for (i
= 0; i
< num_frags
; i
++) {
2098 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2101 /* don't need this page */
2102 __free_page(frag
->page
);
2103 --skb_shinfo(skb
)->nr_frags
;
2105 size
= min(length
, (unsigned) PAGE_SIZE
);
2108 skb
->data_len
+= size
;
2109 skb
->truesize
+= size
;
2116 /* Normal packet - take skb from ring element and put in a new one */
2117 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2118 struct rx_ring_info
*re
,
2119 unsigned int length
)
2121 struct sk_buff
*skb
, *nskb
;
2122 unsigned hdr_space
= sky2
->rx_data_size
;
2124 /* Don't be tricky about reusing pages (yet) */
2125 nskb
= sky2_rx_alloc(sky2
);
2126 if (unlikely(!nskb
))
2130 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2132 prefetch(skb
->data
);
2134 sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
);
2136 if (skb_shinfo(skb
)->nr_frags
)
2137 skb_put_frags(skb
, hdr_space
, length
);
2139 skb_put(skb
, length
);
2144 * Receive one packet.
2145 * For larger packets, get new buffer.
2147 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2148 u16 length
, u32 status
)
2150 struct sky2_port
*sky2
= netdev_priv(dev
);
2151 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2152 struct sk_buff
*skb
= NULL
;
2153 u16 count
= (status
& GMR_FS_LEN
) >> 16;
2155 #ifdef SKY2_VLAN_TAG_USED
2156 /* Account for vlan tag */
2157 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
))
2161 if (unlikely(netif_msg_rx_status(sky2
)))
2162 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
2163 dev
->name
, sky2
->rx_next
, status
, length
);
2165 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2166 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2168 /* This chip has hardware problems that generates bogus status.
2169 * So do only marginal checking and expect higher level protocols
2170 * to handle crap frames.
2172 if (sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
2173 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
&&
2177 if (status
& GMR_FS_ANY_ERR
)
2180 if (!(status
& GMR_FS_RX_OK
))
2183 /* if length reported by DMA does not match PHY, packet was truncated */
2184 if (length
!= count
)
2188 if (length
< copybreak
)
2189 skb
= receive_copy(sky2
, re
, length
);
2191 skb
= receive_new(sky2
, re
, length
);
2193 sky2_rx_submit(sky2
, re
);
2198 /* Truncation of overlength packets
2199 causes PHY length to not match MAC length */
2200 ++dev
->stats
.rx_length_errors
;
2201 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2202 pr_info(PFX
"%s: rx length error: status %#x length %d\n",
2203 dev
->name
, status
, length
);
2207 ++dev
->stats
.rx_errors
;
2208 if (status
& GMR_FS_RX_FF_OV
) {
2209 dev
->stats
.rx_over_errors
++;
2213 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2214 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2215 dev
->name
, status
, length
);
2217 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2218 dev
->stats
.rx_length_errors
++;
2219 if (status
& GMR_FS_FRAGMENT
)
2220 dev
->stats
.rx_frame_errors
++;
2221 if (status
& GMR_FS_CRC_ERR
)
2222 dev
->stats
.rx_crc_errors
++;
2227 /* Transmit complete */
2228 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2230 struct sky2_port
*sky2
= netdev_priv(dev
);
2232 if (netif_running(dev
)) {
2234 sky2_tx_complete(sky2
, last
);
2235 netif_tx_unlock(dev
);
2239 /* Process status response ring */
2240 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
, u16 idx
)
2243 unsigned rx
[2] = { 0, 0 };
2247 struct sky2_port
*sky2
;
2248 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2250 struct net_device
*dev
;
2251 struct sk_buff
*skb
;
2254 u8 opcode
= le
->opcode
;
2256 if (!(opcode
& HW_OWNER
))
2259 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2261 port
= le
->css
& CSS_LINK_BIT
;
2262 dev
= hw
->dev
[port
];
2263 sky2
= netdev_priv(dev
);
2264 length
= le16_to_cpu(le
->length
);
2265 status
= le32_to_cpu(le
->status
);
2268 switch (opcode
& ~HW_OWNER
) {
2271 skb
= sky2_receive(dev
, length
, status
);
2272 if (unlikely(!skb
)) {
2273 dev
->stats
.rx_dropped
++;
2277 /* This chip reports checksum status differently */
2278 if (hw
->flags
& SKY2_HW_NEW_LE
) {
2279 if (sky2
->rx_csum
&&
2280 (le
->css
& (CSS_ISIPV4
| CSS_ISIPV6
)) &&
2281 (le
->css
& CSS_TCPUDPCSOK
))
2282 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2284 skb
->ip_summed
= CHECKSUM_NONE
;
2287 skb
->protocol
= eth_type_trans(skb
, dev
);
2288 dev
->stats
.rx_packets
++;
2289 dev
->stats
.rx_bytes
+= skb
->len
;
2290 dev
->last_rx
= jiffies
;
2292 #ifdef SKY2_VLAN_TAG_USED
2293 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2294 vlan_hwaccel_receive_skb(skb
,
2296 be16_to_cpu(sky2
->rx_tag
));
2299 netif_receive_skb(skb
);
2301 /* Stop after net poll weight */
2302 if (++work_done
>= to_do
)
2306 #ifdef SKY2_VLAN_TAG_USED
2308 sky2
->rx_tag
= length
;
2312 sky2
->rx_tag
= length
;
2319 /* If this happens then driver assuming wrong format */
2320 if (unlikely(hw
->flags
& SKY2_HW_NEW_LE
)) {
2321 if (net_ratelimit())
2322 printk(KERN_NOTICE
"%s: unexpected"
2323 " checksum status\n",
2328 /* Both checksum counters are programmed to start at
2329 * the same offset, so unless there is a problem they
2330 * should match. This failure is an early indication that
2331 * hardware receive checksumming won't work.
2333 if (likely(status
>> 16 == (status
& 0xffff))) {
2334 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2335 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2336 skb
->csum
= status
& 0xffff;
2338 printk(KERN_NOTICE PFX
"%s: hardware receive "
2339 "checksum problem (status = %#x)\n",
2342 sky2_write32(sky2
->hw
,
2343 Q_ADDR(rxqaddr
[port
], Q_CSR
),
2349 /* TX index reports status for both ports */
2350 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2351 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2353 sky2_tx_done(hw
->dev
[1],
2354 ((status
>> 24) & 0xff)
2355 | (u16
)(length
& 0xf) << 8);
2359 if (net_ratelimit())
2360 printk(KERN_WARNING PFX
2361 "unknown status opcode 0x%x\n", opcode
);
2363 } while (hw
->st_idx
!= idx
);
2365 /* Fully processed status ring so clear irq */
2366 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2370 sky2_rx_update(netdev_priv(hw
->dev
[0]), Q_R1
);
2373 sky2_rx_update(netdev_priv(hw
->dev
[1]), Q_R2
);
2378 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2380 struct net_device
*dev
= hw
->dev
[port
];
2382 if (net_ratelimit())
2383 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2386 if (status
& Y2_IS_PAR_RD1
) {
2387 if (net_ratelimit())
2388 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2391 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2394 if (status
& Y2_IS_PAR_WR1
) {
2395 if (net_ratelimit())
2396 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2399 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2402 if (status
& Y2_IS_PAR_MAC1
) {
2403 if (net_ratelimit())
2404 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2405 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2408 if (status
& Y2_IS_PAR_RX1
) {
2409 if (net_ratelimit())
2410 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2411 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2414 if (status
& Y2_IS_TCP_TXA1
) {
2415 if (net_ratelimit())
2416 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2418 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2422 static void sky2_hw_intr(struct sky2_hw
*hw
)
2424 struct pci_dev
*pdev
= hw
->pdev
;
2425 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2426 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2430 if (status
& Y2_IS_TIST_OV
)
2431 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2433 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2436 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2437 if (net_ratelimit())
2438 dev_err(&pdev
->dev
, "PCI hardware error (0x%x)\n",
2441 sky2_pci_write16(hw
, PCI_STATUS
,
2442 pci_err
| PCI_STATUS_ERROR_BITS
);
2445 if (status
& Y2_IS_PCI_EXP
) {
2446 /* PCI-Express uncorrectable Error occurred */
2449 err
= sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2450 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
2452 if (net_ratelimit())
2453 dev_err(&pdev
->dev
, "PCI Express error (0x%x)\n", err
);
2455 sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2458 if (status
& Y2_HWE_L1_MASK
)
2459 sky2_hw_error(hw
, 0, status
);
2461 if (status
& Y2_HWE_L1_MASK
)
2462 sky2_hw_error(hw
, 1, status
);
2465 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2467 struct net_device
*dev
= hw
->dev
[port
];
2468 struct sky2_port
*sky2
= netdev_priv(dev
);
2469 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2471 if (netif_msg_intr(sky2
))
2472 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2475 if (status
& GM_IS_RX_CO_OV
)
2476 gma_read16(hw
, port
, GM_RX_IRQ_SRC
);
2478 if (status
& GM_IS_TX_CO_OV
)
2479 gma_read16(hw
, port
, GM_TX_IRQ_SRC
);
2481 if (status
& GM_IS_RX_FF_OR
) {
2482 ++dev
->stats
.rx_fifo_errors
;
2483 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2486 if (status
& GM_IS_TX_FF_UR
) {
2487 ++dev
->stats
.tx_fifo_errors
;
2488 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2492 /* This should never happen it is a bug. */
2493 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
,
2494 u16 q
, unsigned ring_size
)
2496 struct net_device
*dev
= hw
->dev
[port
];
2497 struct sky2_port
*sky2
= netdev_priv(dev
);
2499 const u64
*le
= (q
== Q_R1
|| q
== Q_R2
)
2500 ? (u64
*) sky2
->rx_le
: (u64
*) sky2
->tx_le
;
2502 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2503 printk(KERN_ERR PFX
"%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2504 dev
->name
, (unsigned) q
, idx
, (unsigned long long) le
[idx
],
2505 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2507 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2510 static int sky2_rx_hung(struct net_device
*dev
)
2512 struct sky2_port
*sky2
= netdev_priv(dev
);
2513 struct sky2_hw
*hw
= sky2
->hw
;
2514 unsigned port
= sky2
->port
;
2515 unsigned rxq
= rxqaddr
[port
];
2516 u32 mac_rp
= sky2_read32(hw
, SK_REG(port
, RX_GMF_RP
));
2517 u8 mac_lev
= sky2_read8(hw
, SK_REG(port
, RX_GMF_RLEV
));
2518 u8 fifo_rp
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RP
));
2519 u8 fifo_lev
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RL
));
2521 /* If idle and MAC or PCI is stuck */
2522 if (sky2
->check
.last
== dev
->last_rx
&&
2523 ((mac_rp
== sky2
->check
.mac_rp
&&
2524 mac_lev
!= 0 && mac_lev
>= sky2
->check
.mac_lev
) ||
2525 /* Check if the PCI RX hang */
2526 (fifo_rp
== sky2
->check
.fifo_rp
&&
2527 fifo_lev
!= 0 && fifo_lev
>= sky2
->check
.fifo_lev
))) {
2528 printk(KERN_DEBUG PFX
"%s: hung mac %d:%d fifo %d (%d:%d)\n",
2529 dev
->name
, mac_lev
, mac_rp
, fifo_lev
, fifo_rp
,
2530 sky2_read8(hw
, Q_ADDR(rxq
, Q_WP
)));
2533 sky2
->check
.last
= dev
->last_rx
;
2534 sky2
->check
.mac_rp
= mac_rp
;
2535 sky2
->check
.mac_lev
= mac_lev
;
2536 sky2
->check
.fifo_rp
= fifo_rp
;
2537 sky2
->check
.fifo_lev
= fifo_lev
;
2542 static void sky2_watchdog(unsigned long arg
)
2544 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2546 /* Check for lost IRQ once a second */
2547 if (sky2_read32(hw
, B0_ISRC
)) {
2548 napi_schedule(&hw
->napi
);
2552 for (i
= 0; i
< hw
->ports
; i
++) {
2553 struct net_device
*dev
= hw
->dev
[i
];
2554 if (!netif_running(dev
))
2558 /* For chips with Rx FIFO, check if stuck */
2559 if ((hw
->flags
& SKY2_HW_FIFO_HANG_CHECK
) &&
2560 sky2_rx_hung(dev
)) {
2561 pr_info(PFX
"%s: receiver hang detected\n",
2563 schedule_work(&hw
->restart_work
);
2572 mod_timer(&hw
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
2575 /* Hardware/software error handling */
2576 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
2578 if (net_ratelimit())
2579 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
2581 if (status
& Y2_IS_HW_ERR
)
2584 if (status
& Y2_IS_IRQ_MAC1
)
2585 sky2_mac_intr(hw
, 0);
2587 if (status
& Y2_IS_IRQ_MAC2
)
2588 sky2_mac_intr(hw
, 1);
2590 if (status
& Y2_IS_CHK_RX1
)
2591 sky2_le_error(hw
, 0, Q_R1
, RX_LE_SIZE
);
2593 if (status
& Y2_IS_CHK_RX2
)
2594 sky2_le_error(hw
, 1, Q_R2
, RX_LE_SIZE
);
2596 if (status
& Y2_IS_CHK_TXA1
)
2597 sky2_le_error(hw
, 0, Q_XA1
, TX_RING_SIZE
);
2599 if (status
& Y2_IS_CHK_TXA2
)
2600 sky2_le_error(hw
, 1, Q_XA2
, TX_RING_SIZE
);
2603 static int sky2_poll(struct napi_struct
*napi
, int work_limit
)
2605 struct sky2_hw
*hw
= container_of(napi
, struct sky2_hw
, napi
);
2606 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2610 if (unlikely(status
& Y2_IS_ERROR
))
2611 sky2_err_intr(hw
, status
);
2613 if (status
& Y2_IS_IRQ_PHY1
)
2614 sky2_phy_intr(hw
, 0);
2616 if (status
& Y2_IS_IRQ_PHY2
)
2617 sky2_phy_intr(hw
, 1);
2619 while ((idx
= sky2_read16(hw
, STAT_PUT_IDX
)) != hw
->st_idx
) {
2620 work_done
+= sky2_status_intr(hw
, work_limit
- work_done
, idx
);
2622 if (work_done
>= work_limit
)
2626 /* Bug/Errata workaround?
2627 * Need to kick the TX irq moderation timer.
2629 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_START
) {
2630 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2631 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2633 napi_complete(napi
);
2634 sky2_read32(hw
, B0_Y2_SP_LISR
);
2640 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2642 struct sky2_hw
*hw
= dev_id
;
2645 /* Reading this mask interrupts as side effect */
2646 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2647 if (status
== 0 || status
== ~0)
2650 prefetch(&hw
->st_le
[hw
->st_idx
]);
2652 napi_schedule(&hw
->napi
);
2657 #ifdef CONFIG_NET_POLL_CONTROLLER
2658 static void sky2_netpoll(struct net_device
*dev
)
2660 struct sky2_port
*sky2
= netdev_priv(dev
);
2662 napi_schedule(&sky2
->hw
->napi
);
2666 /* Chip internal frequency for clock calculations */
2667 static u32
sky2_mhz(const struct sky2_hw
*hw
)
2669 switch (hw
->chip_id
) {
2670 case CHIP_ID_YUKON_EC
:
2671 case CHIP_ID_YUKON_EC_U
:
2672 case CHIP_ID_YUKON_EX
:
2675 case CHIP_ID_YUKON_FE
:
2678 case CHIP_ID_YUKON_FE_P
:
2681 case CHIP_ID_YUKON_XL
:
2689 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2691 return sky2_mhz(hw
) * us
;
2694 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2696 return clk
/ sky2_mhz(hw
);
2700 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2704 /* Enable all clocks and check for bad PCI access */
2705 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
2707 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2709 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2710 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2712 switch(hw
->chip_id
) {
2713 case CHIP_ID_YUKON_XL
:
2714 hw
->flags
= SKY2_HW_GIGABIT
2715 | SKY2_HW_NEWER_PHY
;
2716 if (hw
->chip_rev
< 3)
2717 hw
->flags
|= SKY2_HW_FIFO_HANG_CHECK
;
2721 case CHIP_ID_YUKON_EC_U
:
2722 hw
->flags
= SKY2_HW_GIGABIT
2724 | SKY2_HW_ADV_POWER_CTL
;
2727 case CHIP_ID_YUKON_EX
:
2728 hw
->flags
= SKY2_HW_GIGABIT
2731 | SKY2_HW_ADV_POWER_CTL
;
2733 /* New transmit checksum */
2734 if (hw
->chip_rev
!= CHIP_REV_YU_EX_B0
)
2735 hw
->flags
|= SKY2_HW_AUTO_TX_SUM
;
2738 case CHIP_ID_YUKON_EC
:
2739 /* This rev is really old, and requires untested workarounds */
2740 if (hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2741 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-EC rev A1\n");
2744 hw
->flags
= SKY2_HW_GIGABIT
| SKY2_HW_FIFO_HANG_CHECK
;
2747 case CHIP_ID_YUKON_FE
:
2750 case CHIP_ID_YUKON_FE_P
:
2751 hw
->flags
= SKY2_HW_NEWER_PHY
2753 | SKY2_HW_AUTO_TX_SUM
2754 | SKY2_HW_ADV_POWER_CTL
;
2757 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
2762 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2763 if (hw
->pmd_type
== 'L' || hw
->pmd_type
== 'S' || hw
->pmd_type
== 'P')
2764 hw
->flags
|= SKY2_HW_FIBRE_PHY
;
2768 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2769 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2770 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2777 static void sky2_reset(struct sky2_hw
*hw
)
2779 struct pci_dev
*pdev
= hw
->pdev
;
2782 u32 hwe_mask
= Y2_HWE_ALL_MASK
;
2785 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
2786 status
= sky2_read16(hw
, HCU_CCSR
);
2787 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
2788 HCU_CCSR_UC_STATE_MSK
);
2789 sky2_write16(hw
, HCU_CCSR
, status
);
2791 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2792 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2795 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2796 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2798 /* allow writes to PCI config */
2799 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2801 /* clear PCI errors, if any */
2802 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2803 status
|= PCI_STATUS_ERROR_BITS
;
2804 sky2_pci_write16(hw
, PCI_STATUS
, status
);
2806 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2808 cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
2810 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
2813 /* If error bit is stuck on ignore it */
2814 if (sky2_read32(hw
, B0_HWE_ISRC
) & Y2_IS_PCI_EXP
)
2815 dev_info(&pdev
->dev
, "ignoring stuck error report bit\n");
2817 hwe_mask
|= Y2_IS_PCI_EXP
;
2822 for (i
= 0; i
< hw
->ports
; i
++) {
2823 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2824 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2826 if (hw
->chip_id
== CHIP_ID_YUKON_EX
)
2827 sky2_write16(hw
, SK_REG(i
, GMAC_CTRL
),
2828 GMC_BYP_MACSECRX_ON
| GMC_BYP_MACSECTX_ON
2832 /* Clear I2C IRQ noise */
2833 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2835 /* turn off hardware timer (unused) */
2836 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2837 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2839 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2841 /* Turn off descriptor polling */
2842 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2844 /* Turn off receive timestamp */
2845 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2846 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2848 /* enable the Tx Arbiters */
2849 for (i
= 0; i
< hw
->ports
; i
++)
2850 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2852 /* Initialize ram interface */
2853 for (i
= 0; i
< hw
->ports
; i
++) {
2854 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2856 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2857 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2858 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2859 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2860 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2861 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2862 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2863 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2864 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2865 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2866 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2867 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2870 sky2_write32(hw
, B0_HWE_IMSK
, hwe_mask
);
2872 for (i
= 0; i
< hw
->ports
; i
++)
2873 sky2_gmac_reset(hw
, i
);
2875 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2878 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2879 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2881 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2882 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2884 /* Set the list last index */
2885 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2887 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2888 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2890 /* set Status-FIFO ISR watermark */
2891 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2892 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2894 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2896 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2897 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2898 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2900 /* enable status unit */
2901 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2903 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2904 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2905 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2908 static void sky2_restart(struct work_struct
*work
)
2910 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
2911 struct net_device
*dev
;
2915 for (i
= 0; i
< hw
->ports
; i
++) {
2917 if (netif_running(dev
))
2921 napi_disable(&hw
->napi
);
2922 sky2_write32(hw
, B0_IMSK
, 0);
2924 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
2925 napi_enable(&hw
->napi
);
2927 for (i
= 0; i
< hw
->ports
; i
++) {
2929 if (netif_running(dev
)) {
2932 printk(KERN_INFO PFX
"%s: could not restart %d\n",
2942 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
2944 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
2947 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2949 const struct sky2_port
*sky2
= netdev_priv(dev
);
2951 wol
->supported
= sky2_wol_supported(sky2
->hw
);
2952 wol
->wolopts
= sky2
->wol
;
2955 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2957 struct sky2_port
*sky2
= netdev_priv(dev
);
2958 struct sky2_hw
*hw
= sky2
->hw
;
2960 if (wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
))
2963 sky2
->wol
= wol
->wolopts
;
2965 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
2966 hw
->chip_id
== CHIP_ID_YUKON_EX
||
2967 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
2968 sky2_write32(hw
, B0_CTST
, sky2
->wol
2969 ? Y2_HW_WOL_ON
: Y2_HW_WOL_OFF
);
2971 if (!netif_running(dev
))
2972 sky2_wol_init(sky2
);
2976 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2978 if (sky2_is_copper(hw
)) {
2979 u32 modes
= SUPPORTED_10baseT_Half
2980 | SUPPORTED_10baseT_Full
2981 | SUPPORTED_100baseT_Half
2982 | SUPPORTED_100baseT_Full
2983 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2985 if (hw
->flags
& SKY2_HW_GIGABIT
)
2986 modes
|= SUPPORTED_1000baseT_Half
2987 | SUPPORTED_1000baseT_Full
;
2990 return SUPPORTED_1000baseT_Half
2991 | SUPPORTED_1000baseT_Full
2996 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2998 struct sky2_port
*sky2
= netdev_priv(dev
);
2999 struct sky2_hw
*hw
= sky2
->hw
;
3001 ecmd
->transceiver
= XCVR_INTERNAL
;
3002 ecmd
->supported
= sky2_supported_modes(hw
);
3003 ecmd
->phy_address
= PHY_ADDR_MARV
;
3004 if (sky2_is_copper(hw
)) {
3005 ecmd
->port
= PORT_TP
;
3006 ecmd
->speed
= sky2
->speed
;
3008 ecmd
->speed
= SPEED_1000
;
3009 ecmd
->port
= PORT_FIBRE
;
3012 ecmd
->advertising
= sky2
->advertising
;
3013 ecmd
->autoneg
= sky2
->autoneg
;
3014 ecmd
->duplex
= sky2
->duplex
;
3018 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3020 struct sky2_port
*sky2
= netdev_priv(dev
);
3021 const struct sky2_hw
*hw
= sky2
->hw
;
3022 u32 supported
= sky2_supported_modes(hw
);
3024 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
3025 ecmd
->advertising
= supported
;
3031 switch (ecmd
->speed
) {
3033 if (ecmd
->duplex
== DUPLEX_FULL
)
3034 setting
= SUPPORTED_1000baseT_Full
;
3035 else if (ecmd
->duplex
== DUPLEX_HALF
)
3036 setting
= SUPPORTED_1000baseT_Half
;
3041 if (ecmd
->duplex
== DUPLEX_FULL
)
3042 setting
= SUPPORTED_100baseT_Full
;
3043 else if (ecmd
->duplex
== DUPLEX_HALF
)
3044 setting
= SUPPORTED_100baseT_Half
;
3050 if (ecmd
->duplex
== DUPLEX_FULL
)
3051 setting
= SUPPORTED_10baseT_Full
;
3052 else if (ecmd
->duplex
== DUPLEX_HALF
)
3053 setting
= SUPPORTED_10baseT_Half
;
3061 if ((setting
& supported
) == 0)
3064 sky2
->speed
= ecmd
->speed
;
3065 sky2
->duplex
= ecmd
->duplex
;
3068 sky2
->autoneg
= ecmd
->autoneg
;
3069 sky2
->advertising
= ecmd
->advertising
;
3071 if (netif_running(dev
)) {
3072 sky2_phy_reinit(sky2
);
3073 sky2_set_multicast(dev
);
3079 static void sky2_get_drvinfo(struct net_device
*dev
,
3080 struct ethtool_drvinfo
*info
)
3082 struct sky2_port
*sky2
= netdev_priv(dev
);
3084 strcpy(info
->driver
, DRV_NAME
);
3085 strcpy(info
->version
, DRV_VERSION
);
3086 strcpy(info
->fw_version
, "N/A");
3087 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
3090 static const struct sky2_stat
{
3091 char name
[ETH_GSTRING_LEN
];
3094 { "tx_bytes", GM_TXO_OK_HI
},
3095 { "rx_bytes", GM_RXO_OK_HI
},
3096 { "tx_broadcast", GM_TXF_BC_OK
},
3097 { "rx_broadcast", GM_RXF_BC_OK
},
3098 { "tx_multicast", GM_TXF_MC_OK
},
3099 { "rx_multicast", GM_RXF_MC_OK
},
3100 { "tx_unicast", GM_TXF_UC_OK
},
3101 { "rx_unicast", GM_RXF_UC_OK
},
3102 { "tx_mac_pause", GM_TXF_MPAUSE
},
3103 { "rx_mac_pause", GM_RXF_MPAUSE
},
3104 { "collisions", GM_TXF_COL
},
3105 { "late_collision",GM_TXF_LAT_COL
},
3106 { "aborted", GM_TXF_ABO_COL
},
3107 { "single_collisions", GM_TXF_SNG_COL
},
3108 { "multi_collisions", GM_TXF_MUL_COL
},
3110 { "rx_short", GM_RXF_SHT
},
3111 { "rx_runt", GM_RXE_FRAG
},
3112 { "rx_64_byte_packets", GM_RXF_64B
},
3113 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
3114 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
3115 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
3116 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
3117 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
3118 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
3119 { "rx_too_long", GM_RXF_LNG_ERR
},
3120 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
3121 { "rx_jabber", GM_RXF_JAB_PKT
},
3122 { "rx_fcs_error", GM_RXF_FCS_ERR
},
3124 { "tx_64_byte_packets", GM_TXF_64B
},
3125 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
3126 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
3127 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
3128 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
3129 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
3130 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
3131 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
3134 static u32
sky2_get_rx_csum(struct net_device
*dev
)
3136 struct sky2_port
*sky2
= netdev_priv(dev
);
3138 return sky2
->rx_csum
;
3141 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
3143 struct sky2_port
*sky2
= netdev_priv(dev
);
3145 sky2
->rx_csum
= data
;
3147 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
3148 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
3153 static u32
sky2_get_msglevel(struct net_device
*netdev
)
3155 struct sky2_port
*sky2
= netdev_priv(netdev
);
3156 return sky2
->msg_enable
;
3159 static int sky2_nway_reset(struct net_device
*dev
)
3161 struct sky2_port
*sky2
= netdev_priv(dev
);
3163 if (!netif_running(dev
) || sky2
->autoneg
!= AUTONEG_ENABLE
)
3166 sky2_phy_reinit(sky2
);
3167 sky2_set_multicast(dev
);
3172 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
3174 struct sky2_hw
*hw
= sky2
->hw
;
3175 unsigned port
= sky2
->port
;
3178 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
3179 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
3180 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
3181 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
3183 for (i
= 2; i
< count
; i
++)
3184 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
3187 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
3189 struct sky2_port
*sky2
= netdev_priv(netdev
);
3190 sky2
->msg_enable
= value
;
3193 static int sky2_get_sset_count(struct net_device
*dev
, int sset
)
3197 return ARRAY_SIZE(sky2_stats
);
3203 static void sky2_get_ethtool_stats(struct net_device
*dev
,
3204 struct ethtool_stats
*stats
, u64
* data
)
3206 struct sky2_port
*sky2
= netdev_priv(dev
);
3208 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
3211 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
3215 switch (stringset
) {
3217 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
3218 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3219 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
3224 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
3226 struct sky2_port
*sky2
= netdev_priv(dev
);
3227 struct sky2_hw
*hw
= sky2
->hw
;
3228 unsigned port
= sky2
->port
;
3229 const struct sockaddr
*addr
= p
;
3231 if (!is_valid_ether_addr(addr
->sa_data
))
3232 return -EADDRNOTAVAIL
;
3234 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3235 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3236 dev
->dev_addr
, ETH_ALEN
);
3237 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3238 dev
->dev_addr
, ETH_ALEN
);
3240 /* virtual address for data */
3241 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3243 /* physical address: used for pause frames */
3244 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3249 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
3253 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3254 filter
[bit
>> 3] |= 1 << (bit
& 7);
3257 static void sky2_set_multicast(struct net_device
*dev
)
3259 struct sky2_port
*sky2
= netdev_priv(dev
);
3260 struct sky2_hw
*hw
= sky2
->hw
;
3261 unsigned port
= sky2
->port
;
3262 struct dev_mc_list
*list
= dev
->mc_list
;
3266 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3268 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3269 memset(filter
, 0, sizeof(filter
));
3271 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3272 reg
|= GM_RXCR_UCF_ENA
;
3274 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3275 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3276 else if (dev
->flags
& IFF_ALLMULTI
)
3277 memset(filter
, 0xff, sizeof(filter
));
3278 else if (dev
->mc_count
== 0 && !rx_pause
)
3279 reg
&= ~GM_RXCR_MCF_ENA
;
3282 reg
|= GM_RXCR_MCF_ENA
;
3285 sky2_add_filter(filter
, pause_mc_addr
);
3287 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
3288 sky2_add_filter(filter
, list
->dmi_addr
);
3291 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3292 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3293 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3294 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3295 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3296 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3297 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3298 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3300 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3303 /* Can have one global because blinking is controlled by
3304 * ethtool and that is always under RTNL mutex
3306 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
3310 switch (hw
->chip_id
) {
3311 case CHIP_ID_YUKON_XL
:
3312 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3313 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3314 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3315 on
? (PHY_M_LEDC_LOS_CTRL(1) |
3316 PHY_M_LEDC_INIT_CTRL(7) |
3317 PHY_M_LEDC_STA1_CTRL(7) |
3318 PHY_M_LEDC_STA0_CTRL(7))
3321 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3325 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
3326 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3327 on
? PHY_M_LED_ALL
: 0);
3331 /* blink LED's for finding board */
3332 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3334 struct sky2_port
*sky2
= netdev_priv(dev
);
3335 struct sky2_hw
*hw
= sky2
->hw
;
3336 unsigned port
= sky2
->port
;
3337 u16 ledctrl
, ledover
= 0;
3342 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
3343 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
3347 /* save initial values */
3348 spin_lock_bh(&sky2
->phy_lock
);
3349 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3350 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3351 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3352 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
3353 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3355 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
3356 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
3360 while (!interrupted
&& ms
> 0) {
3361 sky2_led(hw
, port
, onoff
);
3364 spin_unlock_bh(&sky2
->phy_lock
);
3365 interrupted
= msleep_interruptible(250);
3366 spin_lock_bh(&sky2
->phy_lock
);
3371 /* resume regularly scheduled programming */
3372 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3373 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3374 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3375 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
3376 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3378 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
3379 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
3381 spin_unlock_bh(&sky2
->phy_lock
);
3386 static void sky2_get_pauseparam(struct net_device
*dev
,
3387 struct ethtool_pauseparam
*ecmd
)
3389 struct sky2_port
*sky2
= netdev_priv(dev
);
3391 switch (sky2
->flow_mode
) {
3393 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3396 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3399 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3402 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3405 ecmd
->autoneg
= sky2
->autoneg
;
3408 static int sky2_set_pauseparam(struct net_device
*dev
,
3409 struct ethtool_pauseparam
*ecmd
)
3411 struct sky2_port
*sky2
= netdev_priv(dev
);
3413 sky2
->autoneg
= ecmd
->autoneg
;
3414 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3416 if (netif_running(dev
))
3417 sky2_phy_reinit(sky2
);
3422 static int sky2_get_coalesce(struct net_device
*dev
,
3423 struct ethtool_coalesce
*ecmd
)
3425 struct sky2_port
*sky2
= netdev_priv(dev
);
3426 struct sky2_hw
*hw
= sky2
->hw
;
3428 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3429 ecmd
->tx_coalesce_usecs
= 0;
3431 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3432 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3434 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3436 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3437 ecmd
->rx_coalesce_usecs
= 0;
3439 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3440 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3442 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3444 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3445 ecmd
->rx_coalesce_usecs_irq
= 0;
3447 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3448 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3451 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3456 /* Note: this affect both ports */
3457 static int sky2_set_coalesce(struct net_device
*dev
,
3458 struct ethtool_coalesce
*ecmd
)
3460 struct sky2_port
*sky2
= netdev_priv(dev
);
3461 struct sky2_hw
*hw
= sky2
->hw
;
3462 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3464 if (ecmd
->tx_coalesce_usecs
> tmax
||
3465 ecmd
->rx_coalesce_usecs
> tmax
||
3466 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3469 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
3471 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3473 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3476 if (ecmd
->tx_coalesce_usecs
== 0)
3477 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3479 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3480 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3481 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3483 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3485 if (ecmd
->rx_coalesce_usecs
== 0)
3486 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3488 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3489 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3490 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3492 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3494 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3495 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3497 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3498 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3499 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3501 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3505 static void sky2_get_ringparam(struct net_device
*dev
,
3506 struct ethtool_ringparam
*ering
)
3508 struct sky2_port
*sky2
= netdev_priv(dev
);
3510 ering
->rx_max_pending
= RX_MAX_PENDING
;
3511 ering
->rx_mini_max_pending
= 0;
3512 ering
->rx_jumbo_max_pending
= 0;
3513 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
3515 ering
->rx_pending
= sky2
->rx_pending
;
3516 ering
->rx_mini_pending
= 0;
3517 ering
->rx_jumbo_pending
= 0;
3518 ering
->tx_pending
= sky2
->tx_pending
;
3521 static int sky2_set_ringparam(struct net_device
*dev
,
3522 struct ethtool_ringparam
*ering
)
3524 struct sky2_port
*sky2
= netdev_priv(dev
);
3527 if (ering
->rx_pending
> RX_MAX_PENDING
||
3528 ering
->rx_pending
< 8 ||
3529 ering
->tx_pending
< MAX_SKB_TX_LE
||
3530 ering
->tx_pending
> TX_RING_SIZE
- 1)
3533 if (netif_running(dev
))
3536 sky2
->rx_pending
= ering
->rx_pending
;
3537 sky2
->tx_pending
= ering
->tx_pending
;
3539 if (netif_running(dev
)) {
3544 sky2_set_multicast(dev
);
3550 static int sky2_get_regs_len(struct net_device
*dev
)
3556 * Returns copy of control register region
3557 * Note: ethtool_get_regs always provides full size (16k) buffer
3559 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3562 const struct sky2_port
*sky2
= netdev_priv(dev
);
3563 const void __iomem
*io
= sky2
->hw
->regs
;
3568 for (b
= 0; b
< 128; b
++) {
3569 /* This complicated switch statement is to make sure and
3570 * only access regions that are unreserved.
3571 * Some blocks are only valid on dual port cards.
3572 * and block 3 has some special diagnostic registers that
3577 /* skip diagnostic ram region */
3578 memcpy_fromio(p
+ 0x10, io
+ 0x10, 128 - 0x10);
3581 /* dual port cards only */
3582 case 5: /* Tx Arbiter 2 */
3584 case 14 ... 15: /* TX2 */
3585 case 17: case 19: /* Ram Buffer 2 */
3586 case 22 ... 23: /* Tx Ram Buffer 2 */
3587 case 25: /* Rx MAC Fifo 1 */
3588 case 27: /* Tx MAC Fifo 2 */
3589 case 31: /* GPHY 2 */
3590 case 40 ... 47: /* Pattern Ram 2 */
3591 case 52: case 54: /* TCP Segmentation 2 */
3592 case 112 ... 116: /* GMAC 2 */
3593 if (sky2
->hw
->ports
== 1)
3596 case 0: /* Control */
3597 case 2: /* Mac address */
3598 case 4: /* Tx Arbiter 1 */
3599 case 7: /* PCI express reg */
3601 case 12 ... 13: /* TX1 */
3602 case 16: case 18:/* Rx Ram Buffer 1 */
3603 case 20 ... 21: /* Tx Ram Buffer 1 */
3604 case 24: /* Rx MAC Fifo 1 */
3605 case 26: /* Tx MAC Fifo 1 */
3606 case 28 ... 29: /* Descriptor and status unit */
3607 case 30: /* GPHY 1*/
3608 case 32 ... 39: /* Pattern Ram 1 */
3609 case 48: case 50: /* TCP Segmentation 1 */
3610 case 56 ... 60: /* PCI space */
3611 case 80 ... 84: /* GMAC 1 */
3612 memcpy_fromio(p
, io
, 128);
3624 /* In order to do Jumbo packets on these chips, need to turn off the
3625 * transmit store/forward. Therefore checksum offload won't work.
3627 static int no_tx_offload(struct net_device
*dev
)
3629 const struct sky2_port
*sky2
= netdev_priv(dev
);
3630 const struct sky2_hw
*hw
= sky2
->hw
;
3632 return dev
->mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_EC_U
;
3635 static int sky2_set_tx_csum(struct net_device
*dev
, u32 data
)
3637 if (data
&& no_tx_offload(dev
))
3640 return ethtool_op_set_tx_csum(dev
, data
);
3644 static int sky2_set_tso(struct net_device
*dev
, u32 data
)
3646 if (data
&& no_tx_offload(dev
))
3649 return ethtool_op_set_tso(dev
, data
);
3652 static int sky2_get_eeprom_len(struct net_device
*dev
)
3654 struct sky2_port
*sky2
= netdev_priv(dev
);
3655 struct sky2_hw
*hw
= sky2
->hw
;
3658 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
3659 return 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
3662 static u32
sky2_vpd_read(struct sky2_hw
*hw
, int cap
, u16 offset
)
3666 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
);
3669 offset
= sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
);
3670 } while (!(offset
& PCI_VPD_ADDR_F
));
3672 val
= sky2_pci_read32(hw
, cap
+ PCI_VPD_DATA
);
3676 static void sky2_vpd_write(struct sky2_hw
*hw
, int cap
, u16 offset
, u32 val
)
3678 sky2_pci_write16(hw
, cap
+ PCI_VPD_DATA
, val
);
3679 sky2_pci_write32(hw
, cap
+ PCI_VPD_ADDR
, offset
| PCI_VPD_ADDR_F
);
3681 offset
= sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
);
3682 } while (offset
& PCI_VPD_ADDR_F
);
3685 static int sky2_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3688 struct sky2_port
*sky2
= netdev_priv(dev
);
3689 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3690 int length
= eeprom
->len
;
3691 u16 offset
= eeprom
->offset
;
3696 eeprom
->magic
= SKY2_EEPROM_MAGIC
;
3698 while (length
> 0) {
3699 u32 val
= sky2_vpd_read(sky2
->hw
, cap
, offset
);
3700 int n
= min_t(int, length
, sizeof(val
));
3702 memcpy(data
, &val
, n
);
3710 static int sky2_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3713 struct sky2_port
*sky2
= netdev_priv(dev
);
3714 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3715 int length
= eeprom
->len
;
3716 u16 offset
= eeprom
->offset
;
3721 if (eeprom
->magic
!= SKY2_EEPROM_MAGIC
)
3724 while (length
> 0) {
3726 int n
= min_t(int, length
, sizeof(val
));
3728 if (n
< sizeof(val
))
3729 val
= sky2_vpd_read(sky2
->hw
, cap
, offset
);
3730 memcpy(&val
, data
, n
);
3732 sky2_vpd_write(sky2
->hw
, cap
, offset
, val
);
3742 static const struct ethtool_ops sky2_ethtool_ops
= {
3743 .get_settings
= sky2_get_settings
,
3744 .set_settings
= sky2_set_settings
,
3745 .get_drvinfo
= sky2_get_drvinfo
,
3746 .get_wol
= sky2_get_wol
,
3747 .set_wol
= sky2_set_wol
,
3748 .get_msglevel
= sky2_get_msglevel
,
3749 .set_msglevel
= sky2_set_msglevel
,
3750 .nway_reset
= sky2_nway_reset
,
3751 .get_regs_len
= sky2_get_regs_len
,
3752 .get_regs
= sky2_get_regs
,
3753 .get_link
= ethtool_op_get_link
,
3754 .get_eeprom_len
= sky2_get_eeprom_len
,
3755 .get_eeprom
= sky2_get_eeprom
,
3756 .set_eeprom
= sky2_set_eeprom
,
3757 .set_sg
= ethtool_op_set_sg
,
3758 .set_tx_csum
= sky2_set_tx_csum
,
3759 .set_tso
= sky2_set_tso
,
3760 .get_rx_csum
= sky2_get_rx_csum
,
3761 .set_rx_csum
= sky2_set_rx_csum
,
3762 .get_strings
= sky2_get_strings
,
3763 .get_coalesce
= sky2_get_coalesce
,
3764 .set_coalesce
= sky2_set_coalesce
,
3765 .get_ringparam
= sky2_get_ringparam
,
3766 .set_ringparam
= sky2_set_ringparam
,
3767 .get_pauseparam
= sky2_get_pauseparam
,
3768 .set_pauseparam
= sky2_set_pauseparam
,
3769 .phys_id
= sky2_phys_id
,
3770 .get_sset_count
= sky2_get_sset_count
,
3771 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3774 #ifdef CONFIG_SKY2_DEBUG
3776 static struct dentry
*sky2_debug
;
3778 static int sky2_debug_show(struct seq_file
*seq
, void *v
)
3780 struct net_device
*dev
= seq
->private;
3781 const struct sky2_port
*sky2
= netdev_priv(dev
);
3782 struct sky2_hw
*hw
= sky2
->hw
;
3783 unsigned port
= sky2
->port
;
3787 if (!netif_running(dev
))
3790 seq_printf(seq
, "IRQ src=%x mask=%x control=%x\n",
3791 sky2_read32(hw
, B0_ISRC
),
3792 sky2_read32(hw
, B0_IMSK
),
3793 sky2_read32(hw
, B0_Y2_SP_ICR
));
3795 napi_disable(&hw
->napi
);
3796 last
= sky2_read16(hw
, STAT_PUT_IDX
);
3798 if (hw
->st_idx
== last
)
3799 seq_puts(seq
, "Status ring (empty)\n");
3801 seq_puts(seq
, "Status ring\n");
3802 for (idx
= hw
->st_idx
; idx
!= last
&& idx
< STATUS_RING_SIZE
;
3803 idx
= RING_NEXT(idx
, STATUS_RING_SIZE
)) {
3804 const struct sky2_status_le
*le
= hw
->st_le
+ idx
;
3805 seq_printf(seq
, "[%d] %#x %d %#x\n",
3806 idx
, le
->opcode
, le
->length
, le
->status
);
3808 seq_puts(seq
, "\n");
3811 seq_printf(seq
, "Tx ring pending=%u...%u report=%d done=%d\n",
3812 sky2
->tx_cons
, sky2
->tx_prod
,
3813 sky2_read16(hw
, port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
3814 sky2_read16(hw
, Q_ADDR(txqaddr
[port
], Q_DONE
)));
3816 /* Dump contents of tx ring */
3818 for (idx
= sky2
->tx_next
; idx
!= sky2
->tx_prod
&& idx
< TX_RING_SIZE
;
3819 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
3820 const struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
3821 u32 a
= le32_to_cpu(le
->addr
);
3824 seq_printf(seq
, "%u:", idx
);
3827 switch(le
->opcode
& ~HW_OWNER
) {
3829 seq_printf(seq
, " %#x:", a
);
3832 seq_printf(seq
, " mtu=%d", a
);
3835 seq_printf(seq
, " vlan=%d", be16_to_cpu(le
->length
));
3838 seq_printf(seq
, " csum=%#x", a
);
3841 seq_printf(seq
, " tso=%#x(%d)", a
, le16_to_cpu(le
->length
));
3844 seq_printf(seq
, " %#x(%d)", a
, le16_to_cpu(le
->length
));
3847 seq_printf(seq
, " frag=%#x(%d)", a
, le16_to_cpu(le
->length
));
3850 seq_printf(seq
, " op=%#x,%#x(%d)", le
->opcode
,
3851 a
, le16_to_cpu(le
->length
));
3854 if (le
->ctrl
& EOP
) {
3855 seq_putc(seq
, '\n');
3860 seq_printf(seq
, "\nRx ring hw get=%d put=%d last=%d\n",
3861 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_GET_IDX
)),
3862 last
= sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_PUT_IDX
)),
3863 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_LAST_IDX
)));
3865 sky2_read32(hw
, B0_Y2_SP_LISR
);
3866 napi_enable(&hw
->napi
);
3870 static int sky2_debug_open(struct inode
*inode
, struct file
*file
)
3872 return single_open(file
, sky2_debug_show
, inode
->i_private
);
3875 static const struct file_operations sky2_debug_fops
= {
3876 .owner
= THIS_MODULE
,
3877 .open
= sky2_debug_open
,
3879 .llseek
= seq_lseek
,
3880 .release
= single_release
,
3884 * Use network device events to create/remove/rename
3885 * debugfs file entries
3887 static int sky2_device_event(struct notifier_block
*unused
,
3888 unsigned long event
, void *ptr
)
3890 struct net_device
*dev
= ptr
;
3891 struct sky2_port
*sky2
= netdev_priv(dev
);
3893 if (dev
->open
!= sky2_up
|| !sky2_debug
)
3897 case NETDEV_CHANGENAME
:
3898 if (sky2
->debugfs
) {
3899 sky2
->debugfs
= debugfs_rename(sky2_debug
, sky2
->debugfs
,
3900 sky2_debug
, dev
->name
);
3904 case NETDEV_GOING_DOWN
:
3905 if (sky2
->debugfs
) {
3906 printk(KERN_DEBUG PFX
"%s: remove debugfs\n",
3908 debugfs_remove(sky2
->debugfs
);
3909 sky2
->debugfs
= NULL
;
3914 sky2
->debugfs
= debugfs_create_file(dev
->name
, S_IRUGO
,
3917 if (IS_ERR(sky2
->debugfs
))
3918 sky2
->debugfs
= NULL
;
3924 static struct notifier_block sky2_notifier
= {
3925 .notifier_call
= sky2_device_event
,
3929 static __init
void sky2_debug_init(void)
3933 ent
= debugfs_create_dir("sky2", NULL
);
3934 if (!ent
|| IS_ERR(ent
))
3938 register_netdevice_notifier(&sky2_notifier
);
3941 static __exit
void sky2_debug_cleanup(void)
3944 unregister_netdevice_notifier(&sky2_notifier
);
3945 debugfs_remove(sky2_debug
);
3951 #define sky2_debug_init()
3952 #define sky2_debug_cleanup()
3956 /* Initialize network device */
3957 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3959 int highmem
, int wol
)
3961 struct sky2_port
*sky2
;
3962 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3965 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed\n");
3969 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3970 dev
->irq
= hw
->pdev
->irq
;
3971 dev
->open
= sky2_up
;
3972 dev
->stop
= sky2_down
;
3973 dev
->do_ioctl
= sky2_ioctl
;
3974 dev
->hard_start_xmit
= sky2_xmit_frame
;
3975 dev
->set_multicast_list
= sky2_set_multicast
;
3976 dev
->set_mac_address
= sky2_set_mac_address
;
3977 dev
->change_mtu
= sky2_change_mtu
;
3978 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3979 dev
->tx_timeout
= sky2_tx_timeout
;
3980 dev
->watchdog_timeo
= TX_WATCHDOG
;
3981 #ifdef CONFIG_NET_POLL_CONTROLLER
3983 dev
->poll_controller
= sky2_netpoll
;
3986 sky2
= netdev_priv(dev
);
3989 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3991 /* Auto speed and flow control */
3992 sky2
->autoneg
= AUTONEG_ENABLE
;
3993 sky2
->flow_mode
= FC_BOTH
;
3997 sky2
->advertising
= sky2_supported_modes(hw
);
3998 sky2
->rx_csum
= (hw
->chip_id
!= CHIP_ID_YUKON_XL
);
4001 spin_lock_init(&sky2
->phy_lock
);
4002 sky2
->tx_pending
= TX_DEF_PENDING
;
4003 sky2
->rx_pending
= RX_DEF_PENDING
;
4005 hw
->dev
[port
] = dev
;
4009 dev
->features
|= NETIF_F_TSO
| NETIF_F_IP_CSUM
| NETIF_F_SG
;
4011 dev
->features
|= NETIF_F_HIGHDMA
;
4013 #ifdef SKY2_VLAN_TAG_USED
4014 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4015 if (!(sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
4016 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)) {
4017 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
4018 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
4022 /* read the mac address */
4023 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
4024 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
4029 static void __devinit
sky2_show_addr(struct net_device
*dev
)
4031 const struct sky2_port
*sky2
= netdev_priv(dev
);
4032 DECLARE_MAC_BUF(mac
);
4034 if (netif_msg_probe(sky2
))
4035 printk(KERN_INFO PFX
"%s: addr %s\n",
4036 dev
->name
, print_mac(mac
, dev
->dev_addr
));
4039 /* Handle software interrupt used during MSI test */
4040 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
4042 struct sky2_hw
*hw
= dev_id
;
4043 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
4048 if (status
& Y2_IS_IRQ_SW
) {
4049 hw
->flags
|= SKY2_HW_USE_MSI
;
4050 wake_up(&hw
->msi_wait
);
4051 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4053 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
4058 /* Test interrupt path by forcing a a software IRQ */
4059 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
4061 struct pci_dev
*pdev
= hw
->pdev
;
4064 init_waitqueue_head (&hw
->msi_wait
);
4066 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
4068 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
4070 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4074 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
4075 sky2_read8(hw
, B0_CTST
);
4077 wait_event_timeout(hw
->msi_wait
, (hw
->flags
& SKY2_HW_USE_MSI
), HZ
/10);
4079 if (!(hw
->flags
& SKY2_HW_USE_MSI
)) {
4080 /* MSI test failed, go back to INTx mode */
4081 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
4082 "switching to INTx mode.\n");
4085 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4088 sky2_write32(hw
, B0_IMSK
, 0);
4089 sky2_read32(hw
, B0_IMSK
);
4091 free_irq(pdev
->irq
, hw
);
4096 static int __devinit
pci_wake_enabled(struct pci_dev
*dev
)
4098 int pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
4103 if (pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
))
4105 return value
& PCI_PM_CTRL_PME_ENABLE
;
4108 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
4109 const struct pci_device_id
*ent
)
4111 struct net_device
*dev
;
4113 int err
, using_dac
= 0, wol_default
;
4115 err
= pci_enable_device(pdev
);
4117 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
4121 err
= pci_request_regions(pdev
, DRV_NAME
);
4123 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
4124 goto err_out_disable
;
4127 pci_set_master(pdev
);
4129 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
4130 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
4132 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
4134 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
4135 "for consistent allocations\n");
4136 goto err_out_free_regions
;
4139 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
4141 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
4142 goto err_out_free_regions
;
4146 wol_default
= pci_wake_enabled(pdev
) ? WAKE_MAGIC
: 0;
4149 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
4151 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
4152 goto err_out_free_regions
;
4157 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
4159 dev_err(&pdev
->dev
, "cannot map device registers\n");
4160 goto err_out_free_hw
;
4164 /* The sk98lin vendor driver uses hardware byte swapping but
4165 * this driver uses software swapping.
4169 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
4170 reg
&= ~PCI_REV_DESC
;
4171 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
4175 /* ring for status responses */
4176 hw
->st_le
= pci_alloc_consistent(pdev
, STATUS_LE_BYTES
, &hw
->st_dma
);
4178 goto err_out_iounmap
;
4180 err
= sky2_init(hw
);
4182 goto err_out_iounmap
;
4184 dev_info(&pdev
->dev
, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4185 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
4186 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
4187 hw
->chip_id
, hw
->chip_rev
);
4191 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
4194 goto err_out_free_pci
;
4197 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
4198 err
= sky2_test_msi(hw
);
4199 if (err
== -EOPNOTSUPP
)
4200 pci_disable_msi(pdev
);
4202 goto err_out_free_netdev
;
4205 err
= register_netdev(dev
);
4207 dev_err(&pdev
->dev
, "cannot register net device\n");
4208 goto err_out_free_netdev
;
4211 netif_napi_add(dev
, &hw
->napi
, sky2_poll
, NAPI_WEIGHT
);
4213 err
= request_irq(pdev
->irq
, sky2_intr
,
4214 (hw
->flags
& SKY2_HW_USE_MSI
) ? 0 : IRQF_SHARED
,
4217 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4218 goto err_out_unregister
;
4220 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4221 napi_enable(&hw
->napi
);
4223 sky2_show_addr(dev
);
4225 if (hw
->ports
> 1) {
4226 struct net_device
*dev1
;
4228 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
4230 dev_warn(&pdev
->dev
, "allocation for second device failed\n");
4231 else if ((err
= register_netdev(dev1
))) {
4232 dev_warn(&pdev
->dev
,
4233 "register of second port failed (%d)\n", err
);
4237 sky2_show_addr(dev1
);
4240 setup_timer(&hw
->watchdog_timer
, sky2_watchdog
, (unsigned long) hw
);
4241 INIT_WORK(&hw
->restart_work
, sky2_restart
);
4243 pci_set_drvdata(pdev
, hw
);
4248 if (hw
->flags
& SKY2_HW_USE_MSI
)
4249 pci_disable_msi(pdev
);
4250 unregister_netdev(dev
);
4251 err_out_free_netdev
:
4254 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4255 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4260 err_out_free_regions
:
4261 pci_release_regions(pdev
);
4263 pci_disable_device(pdev
);
4265 pci_set_drvdata(pdev
, NULL
);
4269 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
4271 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4277 del_timer_sync(&hw
->watchdog_timer
);
4278 cancel_work_sync(&hw
->restart_work
);
4280 for (i
= hw
->ports
-1; i
>= 0; --i
)
4281 unregister_netdev(hw
->dev
[i
]);
4283 sky2_write32(hw
, B0_IMSK
, 0);
4287 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
4288 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4289 sky2_read8(hw
, B0_CTST
);
4291 free_irq(pdev
->irq
, hw
);
4292 if (hw
->flags
& SKY2_HW_USE_MSI
)
4293 pci_disable_msi(pdev
);
4294 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4295 pci_release_regions(pdev
);
4296 pci_disable_device(pdev
);
4298 for (i
= hw
->ports
-1; i
>= 0; --i
)
4299 free_netdev(hw
->dev
[i
]);
4304 pci_set_drvdata(pdev
, NULL
);
4308 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4310 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4316 for (i
= 0; i
< hw
->ports
; i
++) {
4317 struct net_device
*dev
= hw
->dev
[i
];
4318 struct sky2_port
*sky2
= netdev_priv(dev
);
4320 if (netif_running(dev
))
4324 sky2_wol_init(sky2
);
4329 sky2_write32(hw
, B0_IMSK
, 0);
4330 napi_disable(&hw
->napi
);
4333 pci_save_state(pdev
);
4334 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
4335 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
4340 static int sky2_resume(struct pci_dev
*pdev
)
4342 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4348 err
= pci_set_power_state(pdev
, PCI_D0
);
4352 err
= pci_restore_state(pdev
);
4356 pci_enable_wake(pdev
, PCI_D0
, 0);
4358 /* Re-enable all clocks */
4359 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
4360 hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
4361 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
4362 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
4365 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4366 napi_enable(&hw
->napi
);
4368 for (i
= 0; i
< hw
->ports
; i
++) {
4369 struct net_device
*dev
= hw
->dev
[i
];
4370 if (netif_running(dev
)) {
4373 printk(KERN_ERR PFX
"%s: could not up: %d\n",
4379 sky2_set_multicast(dev
);
4385 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
4386 pci_disable_device(pdev
);
4391 static void sky2_shutdown(struct pci_dev
*pdev
)
4393 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4399 del_timer_sync(&hw
->watchdog_timer
);
4401 for (i
= 0; i
< hw
->ports
; i
++) {
4402 struct net_device
*dev
= hw
->dev
[i
];
4403 struct sky2_port
*sky2
= netdev_priv(dev
);
4407 sky2_wol_init(sky2
);
4414 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
4415 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
4417 pci_disable_device(pdev
);
4418 pci_set_power_state(pdev
, PCI_D3hot
);
4422 static struct pci_driver sky2_driver
= {
4424 .id_table
= sky2_id_table
,
4425 .probe
= sky2_probe
,
4426 .remove
= __devexit_p(sky2_remove
),
4428 .suspend
= sky2_suspend
,
4429 .resume
= sky2_resume
,
4431 .shutdown
= sky2_shutdown
,
4434 static int __init
sky2_init_module(void)
4437 return pci_register_driver(&sky2_driver
);
4440 static void __exit
sky2_cleanup_module(void)
4442 pci_unregister_driver(&sky2_driver
);
4443 sky2_debug_cleanup();
4446 module_init(sky2_init_module
);
4447 module_exit(sky2_cleanup_module
);
4449 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4450 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4451 MODULE_LICENSE("GPL");
4452 MODULE_VERSION(DRV_VERSION
);