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r8169: identify different registers.
[linux-2.6/libata-dev.git] / drivers / net / r8169.c
blob33c3fbf227f48fb623599fc78e3bf0f6417096e2
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28
29 #include <asm/system.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32
33 #define RTL8169_VERSION "2.3LK-NAPI"
34 #define MODULENAME "r8169"
35 #define PFX MODULENAME ": "
36
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39
40 #ifdef RTL8169_DEBUG
41 #define assert(expr) \
42 if (!(expr)) { \
43 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
44 #expr,__FILE__,__func__,__LINE__); \
45 }
46 #define dprintk(fmt, args...) \
47 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
48 #else
49 #define assert(expr) do {} while (0)
50 #define dprintk(fmt, args...) do {} while (0)
51 #endif /* RTL8169_DEBUG */
52
53 #define R8169_MSG_DEFAULT \
54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
55
56 #define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
61 static const int multicast_filter_limit = 32;
62
63 /* MAC address length */
64 #define MAC_ADDR_LEN 6
65
66 #define MAX_READ_REQUEST_SHIFT 12
67 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
68 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
69 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
83
84 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
86 #define RTL_EEPROM_SIG_ADDR 0x0000
87
88 /* write/read MMIO register */
89 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92 #define RTL_R8(reg) readb (ioaddr + (reg))
93 #define RTL_R16(reg) readw (ioaddr + (reg))
94 #define RTL_R32(reg) readl (ioaddr + (reg))
95
96 enum mac_version {
97 RTL_GIGA_MAC_NONE = 0x00,
98 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
99 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
103 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
104 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
108 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
109 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
117 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
118 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
119 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
120 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
121 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
122 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
123 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
124 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
125 };
126
127 #define _R(NAME,MAC,MASK) \
128 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
129
130 static const struct {
131 const char *name;
132 u8 mac_version;
133 u32 RxConfigMask; /* Clears the bits supported by this chip */
134 } rtl_chip_info[] = {
135 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
136 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
137 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
138 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
139 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
140 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
141 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
142 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
143 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
145 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
147 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
148 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
149 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
150 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
151 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
152 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
155 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
156 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
157 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
158 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
159 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
160 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
161 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
162 };
163 #undef _R
164
165 enum cfg_version {
166 RTL_CFG_0 = 0x00,
167 RTL_CFG_1,
168 RTL_CFG_2
169 };
170
171 static void rtl_hw_start_8169(struct net_device *);
172 static void rtl_hw_start_8168(struct net_device *);
173 static void rtl_hw_start_8101(struct net_device *);
174
175 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
179 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
180 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
181 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
182 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
183 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
184 { PCI_VENDOR_ID_LINKSYS, 0x1032,
185 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
186 { 0x0001, 0x8168,
187 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
188 {0,},
189 };
190
191 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
192
193 static int rx_buf_sz = 16383;
194 static int use_dac;
195 static struct {
196 u32 msg_enable;
197 } debug = { -1 };
198
199 enum rtl_registers {
200 MAC0 = 0, /* Ethernet hardware address. */
201 MAC4 = 4,
202 MAR0 = 8, /* Multicast filter. */
203 CounterAddrLow = 0x10,
204 CounterAddrHigh = 0x14,
205 TxDescStartAddrLow = 0x20,
206 TxDescStartAddrHigh = 0x24,
207 TxHDescStartAddrLow = 0x28,
208 TxHDescStartAddrHigh = 0x2c,
209 FLASH = 0x30,
210 ERSR = 0x36,
211 ChipCmd = 0x37,
212 TxPoll = 0x38,
213 IntrMask = 0x3c,
214 IntrStatus = 0x3e,
215 TxConfig = 0x40,
216 RxConfig = 0x44,
217 RxMissed = 0x4c,
218 Cfg9346 = 0x50,
219 Config0 = 0x51,
220 Config1 = 0x52,
221 Config2 = 0x53,
222 Config3 = 0x54,
223 Config4 = 0x55,
224 Config5 = 0x56,
225 MultiIntr = 0x5c,
226 PHYAR = 0x60,
227 PHYstatus = 0x6c,
228 RxMaxSize = 0xda,
229 CPlusCmd = 0xe0,
230 IntrMitigate = 0xe2,
231 RxDescAddrLow = 0xe4,
232 RxDescAddrHigh = 0xe8,
233 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
234
235 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
236
237 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
238
239 #define TxPacketMax (8064 >> 7)
240
241 FuncEvent = 0xf0,
242 FuncEventMask = 0xf4,
243 FuncPresetState = 0xf8,
244 FuncForceEvent = 0xfc,
245 };
246
247 enum rtl8110_registers {
248 TBICSR = 0x64,
249 TBI_ANAR = 0x68,
250 TBI_LPAR = 0x6a,
251 };
252
253 enum rtl8168_8101_registers {
254 CSIDR = 0x64,
255 CSIAR = 0x68,
256 #define CSIAR_FLAG 0x80000000
257 #define CSIAR_WRITE_CMD 0x80000000
258 #define CSIAR_BYTE_ENABLE 0x0f
259 #define CSIAR_BYTE_ENABLE_SHIFT 12
260 #define CSIAR_ADDR_MASK 0x0fff
261
262 EPHYAR = 0x80,
263 #define EPHYAR_FLAG 0x80000000
264 #define EPHYAR_WRITE_CMD 0x80000000
265 #define EPHYAR_REG_MASK 0x1f
266 #define EPHYAR_REG_SHIFT 16
267 #define EPHYAR_DATA_MASK 0xffff
268 DBG_REG = 0xd1,
269 #define FIX_NAK_1 (1 << 4)
270 #define FIX_NAK_2 (1 << 3)
271 EFUSEAR = 0xdc,
272 #define EFUSEAR_FLAG 0x80000000
273 #define EFUSEAR_WRITE_CMD 0x80000000
274 #define EFUSEAR_READ_CMD 0x00000000
275 #define EFUSEAR_REG_MASK 0x03ff
276 #define EFUSEAR_REG_SHIFT 8
277 #define EFUSEAR_DATA_MASK 0xff
278 };
279
280 enum rtl_register_content {
281 /* InterruptStatusBits */
282 SYSErr = 0x8000,
283 PCSTimeout = 0x4000,
284 SWInt = 0x0100,
285 TxDescUnavail = 0x0080,
286 RxFIFOOver = 0x0040,
287 LinkChg = 0x0020,
288 RxOverflow = 0x0010,
289 TxErr = 0x0008,
290 TxOK = 0x0004,
291 RxErr = 0x0002,
292 RxOK = 0x0001,
293
294 /* RxStatusDesc */
295 RxFOVF = (1 << 23),
296 RxRWT = (1 << 22),
297 RxRES = (1 << 21),
298 RxRUNT = (1 << 20),
299 RxCRC = (1 << 19),
300
301 /* ChipCmdBits */
302 CmdReset = 0x10,
303 CmdRxEnb = 0x08,
304 CmdTxEnb = 0x04,
305 RxBufEmpty = 0x01,
306
307 /* TXPoll register p.5 */
308 HPQ = 0x80, /* Poll cmd on the high prio queue */
309 NPQ = 0x40, /* Poll cmd on the low prio queue */
310 FSWInt = 0x01, /* Forced software interrupt */
311
312 /* Cfg9346Bits */
313 Cfg9346_Lock = 0x00,
314 Cfg9346_Unlock = 0xc0,
315
316 /* rx_mode_bits */
317 AcceptErr = 0x20,
318 AcceptRunt = 0x10,
319 AcceptBroadcast = 0x08,
320 AcceptMulticast = 0x04,
321 AcceptMyPhys = 0x02,
322 AcceptAllPhys = 0x01,
323
324 /* RxConfigBits */
325 RxCfgFIFOShift = 13,
326 RxCfgDMAShift = 8,
327
328 /* TxConfigBits */
329 TxInterFrameGapShift = 24,
330 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
331
332 /* Config1 register p.24 */
333 LEDS1 = (1 << 7),
334 LEDS0 = (1 << 6),
335 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
336 Speed_down = (1 << 4),
337 MEMMAP = (1 << 3),
338 IOMAP = (1 << 2),
339 VPD = (1 << 1),
340 PMEnable = (1 << 0), /* Power Management Enable */
341
342 /* Config2 register p. 25 */
343 PCI_Clock_66MHz = 0x01,
344 PCI_Clock_33MHz = 0x00,
345
346 /* Config3 register p.25 */
347 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
348 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
349 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
350
351 /* Config5 register p.27 */
352 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
353 MWF = (1 << 5), /* Accept Multicast wakeup frame */
354 UWF = (1 << 4), /* Accept Unicast wakeup frame */
355 LanWake = (1 << 1), /* LanWake enable/disable */
356 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
357
358 /* TBICSR p.28 */
359 TBIReset = 0x80000000,
360 TBILoopback = 0x40000000,
361 TBINwEnable = 0x20000000,
362 TBINwRestart = 0x10000000,
363 TBILinkOk = 0x02000000,
364 TBINwComplete = 0x01000000,
365
366 /* CPlusCmd p.31 */
367 EnableBist = (1 << 15), // 8168 8101
368 Mac_dbgo_oe = (1 << 14), // 8168 8101
369 Normal_mode = (1 << 13), // unused
370 Force_half_dup = (1 << 12), // 8168 8101
371 Force_rxflow_en = (1 << 11), // 8168 8101
372 Force_txflow_en = (1 << 10), // 8168 8101
373 Cxpl_dbg_sel = (1 << 9), // 8168 8101
374 ASF = (1 << 8), // 8168 8101
375 PktCntrDisable = (1 << 7), // 8168 8101
376 Mac_dbgo_sel = 0x001c, // 8168
377 RxVlan = (1 << 6),
378 RxChkSum = (1 << 5),
379 PCIDAC = (1 << 4),
380 PCIMulRW = (1 << 3),
381 INTT_0 = 0x0000, // 8168
382 INTT_1 = 0x0001, // 8168
383 INTT_2 = 0x0002, // 8168
384 INTT_3 = 0x0003, // 8168
385
386 /* rtl8169_PHYstatus */
387 TBI_Enable = 0x80,
388 TxFlowCtrl = 0x40,
389 RxFlowCtrl = 0x20,
390 _1000bpsF = 0x10,
391 _100bps = 0x08,
392 _10bps = 0x04,
393 LinkStatus = 0x02,
394 FullDup = 0x01,
395
396 /* _TBICSRBit */
397 TBILinkOK = 0x02000000,
398
399 /* DumpCounterCommand */
400 CounterDump = 0x8,
401 };
402
403 enum desc_status_bit {
404 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
405 RingEnd = (1 << 30), /* End of descriptor ring */
406 FirstFrag = (1 << 29), /* First segment of a packet */
407 LastFrag = (1 << 28), /* Final segment of a packet */
408
409 /* Tx private */
410 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
411 MSSShift = 16, /* MSS value position */
412 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
413 IPCS = (1 << 18), /* Calculate IP checksum */
414 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
415 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
416 TxVlanTag = (1 << 17), /* Add VLAN tag */
417
418 /* Rx private */
419 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
420 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
421
422 #define RxProtoUDP (PID1)
423 #define RxProtoTCP (PID0)
424 #define RxProtoIP (PID1 | PID0)
425 #define RxProtoMask RxProtoIP
426
427 IPFail = (1 << 16), /* IP checksum failed */
428 UDPFail = (1 << 15), /* UDP/IP checksum failed */
429 TCPFail = (1 << 14), /* TCP/IP checksum failed */
430 RxVlanTag = (1 << 16), /* VLAN tag available */
431 };
432
433 #define RsvdMask 0x3fffc000
434
435 struct TxDesc {
436 __le32 opts1;
437 __le32 opts2;
438 __le64 addr;
439 };
440
441 struct RxDesc {
442 __le32 opts1;
443 __le32 opts2;
444 __le64 addr;
445 };
446
447 struct ring_info {
448 struct sk_buff *skb;
449 u32 len;
450 u8 __pad[sizeof(void *) - sizeof(u32)];
451 };
452
453 enum features {
454 RTL_FEATURE_WOL = (1 << 0),
455 RTL_FEATURE_MSI = (1 << 1),
456 RTL_FEATURE_GMII = (1 << 2),
457 };
458
459 struct rtl8169_counters {
460 __le64 tx_packets;
461 __le64 rx_packets;
462 __le64 tx_errors;
463 __le32 rx_errors;
464 __le16 rx_missed;
465 __le16 align_errors;
466 __le32 tx_one_collision;
467 __le32 tx_multi_collision;
468 __le64 rx_unicast;
469 __le64 rx_broadcast;
470 __le32 rx_multicast;
471 __le16 tx_aborted;
472 __le16 tx_underun;
473 };
474
475 struct rtl8169_private {
476 void __iomem *mmio_addr; /* memory map physical address */
477 struct pci_dev *pci_dev; /* Index of PCI device */
478 struct net_device *dev;
479 struct napi_struct napi;
480 spinlock_t lock; /* spin lock flag */
481 u32 msg_enable;
482 int chipset;
483 int mac_version;
484 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
485 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
486 u32 dirty_rx;
487 u32 dirty_tx;
488 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
489 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
490 dma_addr_t TxPhyAddr;
491 dma_addr_t RxPhyAddr;
492 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
493 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
494 struct timer_list timer;
495 u16 cp_cmd;
496 u16 intr_event;
497 u16 napi_event;
498 u16 intr_mask;
499 int phy_1000_ctrl_reg;
500 #ifdef CONFIG_R8169_VLAN
501 struct vlan_group *vlgrp;
502 #endif
503 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
504 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
505 void (*phy_reset_enable)(void __iomem *);
506 void (*hw_start)(struct net_device *);
507 unsigned int (*phy_reset_pending)(void __iomem *);
508 unsigned int (*link_ok)(void __iomem *);
509 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
510 int pcie_cap;
511 struct delayed_work task;
512 unsigned features;
513
514 struct mii_if_info mii;
515 struct rtl8169_counters counters;
516 u32 saved_wolopts;
517 };
518
519 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
520 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
521 module_param(use_dac, int, 0);
522 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
523 module_param_named(debug, debug.msg_enable, int, 0);
524 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
525 MODULE_LICENSE("GPL");
526 MODULE_VERSION(RTL8169_VERSION);
527 MODULE_FIRMWARE(FIRMWARE_8168D_1);
528 MODULE_FIRMWARE(FIRMWARE_8168D_2);
529
530 static int rtl8169_open(struct net_device *dev);
531 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
532 struct net_device *dev);
533 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
534 static int rtl8169_init_ring(struct net_device *dev);
535 static void rtl_hw_start(struct net_device *dev);
536 static int rtl8169_close(struct net_device *dev);
537 static void rtl_set_rx_mode(struct net_device *dev);
538 static void rtl8169_tx_timeout(struct net_device *dev);
539 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
540 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
541 void __iomem *, u32 budget);
542 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
543 static void rtl8169_down(struct net_device *dev);
544 static void rtl8169_rx_clear(struct rtl8169_private *tp);
545 static int rtl8169_poll(struct napi_struct *napi, int budget);
546
547 static const unsigned int rtl8169_rx_config =
548 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
549
550 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
551 {
552 int i;
553
554 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
555
556 for (i = 20; i > 0; i--) {
557 /*
558 * Check if the RTL8169 has completed writing to the specified
559 * MII register.
560 */
561 if (!(RTL_R32(PHYAR) & 0x80000000))
562 break;
563 udelay(25);
564 }
565 /*
566 * According to hardware specs a 20us delay is required after write
567 * complete indication, but before sending next command.
568 */
569 udelay(20);
570 }
571
572 static int mdio_read(void __iomem *ioaddr, int reg_addr)
573 {
574 int i, value = -1;
575
576 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
577
578 for (i = 20; i > 0; i--) {
579 /*
580 * Check if the RTL8169 has completed retrieving data from
581 * the specified MII register.
582 */
583 if (RTL_R32(PHYAR) & 0x80000000) {
584 value = RTL_R32(PHYAR) & 0xffff;
585 break;
586 }
587 udelay(25);
588 }
589 /*
590 * According to hardware specs a 20us delay is required after read
591 * complete indication, but before sending next command.
592 */
593 udelay(20);
594
595 return value;
596 }
597
598 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
599 {
600 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
601 }
602
603 static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
604 {
605 int val;
606
607 val = mdio_read(ioaddr, reg_addr);
608 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
609 }
610
611 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
612 int val)
613 {
614 struct rtl8169_private *tp = netdev_priv(dev);
615 void __iomem *ioaddr = tp->mmio_addr;
616
617 mdio_write(ioaddr, location, val);
618 }
619
620 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
621 {
622 struct rtl8169_private *tp = netdev_priv(dev);
623 void __iomem *ioaddr = tp->mmio_addr;
624
625 return mdio_read(ioaddr, location);
626 }
627
628 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
629 {
630 unsigned int i;
631
632 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
633 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
634
635 for (i = 0; i < 100; i++) {
636 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
637 break;
638 udelay(10);
639 }
640 }
641
642 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
643 {
644 u16 value = 0xffff;
645 unsigned int i;
646
647 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
648
649 for (i = 0; i < 100; i++) {
650 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
651 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
652 break;
653 }
654 udelay(10);
655 }
656
657 return value;
658 }
659
660 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
661 {
662 unsigned int i;
663
664 RTL_W32(CSIDR, value);
665 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
666 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
667
668 for (i = 0; i < 100; i++) {
669 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
670 break;
671 udelay(10);
672 }
673 }
674
675 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
676 {
677 u32 value = ~0x00;
678 unsigned int i;
679
680 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
681 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
682
683 for (i = 0; i < 100; i++) {
684 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
685 value = RTL_R32(CSIDR);
686 break;
687 }
688 udelay(10);
689 }
690
691 return value;
692 }
693
694 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
695 {
696 u8 value = 0xff;
697 unsigned int i;
698
699 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
700
701 for (i = 0; i < 300; i++) {
702 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
703 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
704 break;
705 }
706 udelay(100);
707 }
708
709 return value;
710 }
711
712 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
713 {
714 RTL_W16(IntrMask, 0x0000);
715
716 RTL_W16(IntrStatus, 0xffff);
717 }
718
719 static void rtl8169_asic_down(void __iomem *ioaddr)
720 {
721 RTL_W8(ChipCmd, 0x00);
722 rtl8169_irq_mask_and_ack(ioaddr);
723 RTL_R16(CPlusCmd);
724 }
725
726 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
727 {
728 return RTL_R32(TBICSR) & TBIReset;
729 }
730
731 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
732 {
733 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
734 }
735
736 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
737 {
738 return RTL_R32(TBICSR) & TBILinkOk;
739 }
740
741 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
742 {
743 return RTL_R8(PHYstatus) & LinkStatus;
744 }
745
746 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
747 {
748 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
749 }
750
751 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
752 {
753 unsigned int val;
754
755 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
756 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
757 }
758
759 static void __rtl8169_check_link_status(struct net_device *dev,
760 struct rtl8169_private *tp,
761 void __iomem *ioaddr,
762 bool pm)
763 {
764 unsigned long flags;
765
766 spin_lock_irqsave(&tp->lock, flags);
767 if (tp->link_ok(ioaddr)) {
768 /* This is to cancel a scheduled suspend if there's one. */
769 if (pm)
770 pm_request_resume(&tp->pci_dev->dev);
771 netif_carrier_on(dev);
772 netif_info(tp, ifup, dev, "link up\n");
773 } else {
774 netif_carrier_off(dev);
775 netif_info(tp, ifdown, dev, "link down\n");
776 if (pm)
777 pm_schedule_suspend(&tp->pci_dev->dev, 100);
778 }
779 spin_unlock_irqrestore(&tp->lock, flags);
780 }
781
782 static void rtl8169_check_link_status(struct net_device *dev,
783 struct rtl8169_private *tp,
784 void __iomem *ioaddr)
785 {
786 __rtl8169_check_link_status(dev, tp, ioaddr, false);
787 }
788
789 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
790
791 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
792 {
793 void __iomem *ioaddr = tp->mmio_addr;
794 u8 options;
795 u32 wolopts = 0;
796
797 options = RTL_R8(Config1);
798 if (!(options & PMEnable))
799 return 0;
800
801 options = RTL_R8(Config3);
802 if (options & LinkUp)
803 wolopts |= WAKE_PHY;
804 if (options & MagicPacket)
805 wolopts |= WAKE_MAGIC;
806
807 options = RTL_R8(Config5);
808 if (options & UWF)
809 wolopts |= WAKE_UCAST;
810 if (options & BWF)
811 wolopts |= WAKE_BCAST;
812 if (options & MWF)
813 wolopts |= WAKE_MCAST;
814
815 return wolopts;
816 }
817
818 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
819 {
820 struct rtl8169_private *tp = netdev_priv(dev);
821
822 spin_lock_irq(&tp->lock);
823
824 wol->supported = WAKE_ANY;
825 wol->wolopts = __rtl8169_get_wol(tp);
826
827 spin_unlock_irq(&tp->lock);
828 }
829
830 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
831 {
832 void __iomem *ioaddr = tp->mmio_addr;
833 unsigned int i;
834 static const struct {
835 u32 opt;
836 u16 reg;
837 u8 mask;
838 } cfg[] = {
839 { WAKE_ANY, Config1, PMEnable },
840 { WAKE_PHY, Config3, LinkUp },
841 { WAKE_MAGIC, Config3, MagicPacket },
842 { WAKE_UCAST, Config5, UWF },
843 { WAKE_BCAST, Config5, BWF },
844 { WAKE_MCAST, Config5, MWF },
845 { WAKE_ANY, Config5, LanWake }
846 };
847
848 RTL_W8(Cfg9346, Cfg9346_Unlock);
849
850 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
851 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
852 if (wolopts & cfg[i].opt)
853 options |= cfg[i].mask;
854 RTL_W8(cfg[i].reg, options);
855 }
856
857 RTL_W8(Cfg9346, Cfg9346_Lock);
858 }
859
860 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
861 {
862 struct rtl8169_private *tp = netdev_priv(dev);
863
864 spin_lock_irq(&tp->lock);
865
866 if (wol->wolopts)
867 tp->features |= RTL_FEATURE_WOL;
868 else
869 tp->features &= ~RTL_FEATURE_WOL;
870 __rtl8169_set_wol(tp, wol->wolopts);
871 spin_unlock_irq(&tp->lock);
872
873 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
874
875 return 0;
876 }
877
878 static void rtl8169_get_drvinfo(struct net_device *dev,
879 struct ethtool_drvinfo *info)
880 {
881 struct rtl8169_private *tp = netdev_priv(dev);
882
883 strcpy(info->driver, MODULENAME);
884 strcpy(info->version, RTL8169_VERSION);
885 strcpy(info->bus_info, pci_name(tp->pci_dev));
886 }
887
888 static int rtl8169_get_regs_len(struct net_device *dev)
889 {
890 return R8169_REGS_SIZE;
891 }
892
893 static int rtl8169_set_speed_tbi(struct net_device *dev,
894 u8 autoneg, u16 speed, u8 duplex)
895 {
896 struct rtl8169_private *tp = netdev_priv(dev);
897 void __iomem *ioaddr = tp->mmio_addr;
898 int ret = 0;
899 u32 reg;
900
901 reg = RTL_R32(TBICSR);
902 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
903 (duplex == DUPLEX_FULL)) {
904 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
905 } else if (autoneg == AUTONEG_ENABLE)
906 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
907 else {
908 netif_warn(tp, link, dev,
909 "incorrect speed setting refused in TBI mode\n");
910 ret = -EOPNOTSUPP;
911 }
912
913 return ret;
914 }
915
916 static int rtl8169_set_speed_xmii(struct net_device *dev,
917 u8 autoneg, u16 speed, u8 duplex)
918 {
919 struct rtl8169_private *tp = netdev_priv(dev);
920 void __iomem *ioaddr = tp->mmio_addr;
921 int giga_ctrl, bmcr;
922
923 if (autoneg == AUTONEG_ENABLE) {
924 int auto_nego;
925
926 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
927 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
928 ADVERTISE_100HALF | ADVERTISE_100FULL);
929 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
930
931 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
932 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
933
934 /* The 8100e/8101e/8102e do Fast Ethernet only. */
935 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
936 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
937 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
938 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
939 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
940 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
941 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
942 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
943 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
944 } else {
945 netif_info(tp, link, dev,
946 "PHY does not support 1000Mbps\n");
947 }
948
949 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
950
951 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
952 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
953 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
954 /*
955 * Wake up the PHY.
956 * Vendor specific (0x1f) and reserved (0x0e) MII
957 * registers.
958 */
959 mdio_write(ioaddr, 0x1f, 0x0000);
960 mdio_write(ioaddr, 0x0e, 0x0000);
961 }
962
963 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
964 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
965 } else {
966 giga_ctrl = 0;
967
968 if (speed == SPEED_10)
969 bmcr = 0;
970 else if (speed == SPEED_100)
971 bmcr = BMCR_SPEED100;
972 else
973 return -EINVAL;
974
975 if (duplex == DUPLEX_FULL)
976 bmcr |= BMCR_FULLDPLX;
977
978 mdio_write(ioaddr, 0x1f, 0x0000);
979 }
980
981 tp->phy_1000_ctrl_reg = giga_ctrl;
982
983 mdio_write(ioaddr, MII_BMCR, bmcr);
984
985 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
986 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
987 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
988 mdio_write(ioaddr, 0x17, 0x2138);
989 mdio_write(ioaddr, 0x0e, 0x0260);
990 } else {
991 mdio_write(ioaddr, 0x17, 0x2108);
992 mdio_write(ioaddr, 0x0e, 0x0000);
993 }
994 }
995
996 return 0;
997 }
998
999 static int rtl8169_set_speed(struct net_device *dev,
1000 u8 autoneg, u16 speed, u8 duplex)
1001 {
1002 struct rtl8169_private *tp = netdev_priv(dev);
1003 int ret;
1004
1005 ret = tp->set_speed(dev, autoneg, speed, duplex);
1006
1007 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1008 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1009
1010 return ret;
1011 }
1012
1013 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1014 {
1015 struct rtl8169_private *tp = netdev_priv(dev);
1016 unsigned long flags;
1017 int ret;
1018
1019 spin_lock_irqsave(&tp->lock, flags);
1020 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1021 spin_unlock_irqrestore(&tp->lock, flags);
1022
1023 return ret;
1024 }
1025
1026 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1027 {
1028 struct rtl8169_private *tp = netdev_priv(dev);
1029
1030 return tp->cp_cmd & RxChkSum;
1031 }
1032
1033 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1034 {
1035 struct rtl8169_private *tp = netdev_priv(dev);
1036 void __iomem *ioaddr = tp->mmio_addr;
1037 unsigned long flags;
1038
1039 spin_lock_irqsave(&tp->lock, flags);
1040
1041 if (data)
1042 tp->cp_cmd |= RxChkSum;
1043 else
1044 tp->cp_cmd &= ~RxChkSum;
1045
1046 RTL_W16(CPlusCmd, tp->cp_cmd);
1047 RTL_R16(CPlusCmd);
1048
1049 spin_unlock_irqrestore(&tp->lock, flags);
1050
1051 return 0;
1052 }
1053
1054 #ifdef CONFIG_R8169_VLAN
1055
1056 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1057 struct sk_buff *skb)
1058 {
1059 return (vlan_tx_tag_present(skb)) ?
1060 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1061 }
1062
1063 static void rtl8169_vlan_rx_register(struct net_device *dev,
1064 struct vlan_group *grp)
1065 {
1066 struct rtl8169_private *tp = netdev_priv(dev);
1067 void __iomem *ioaddr = tp->mmio_addr;
1068 unsigned long flags;
1069
1070 spin_lock_irqsave(&tp->lock, flags);
1071 tp->vlgrp = grp;
1072 /*
1073 * Do not disable RxVlan on 8110SCd.
1074 */
1075 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1076 tp->cp_cmd |= RxVlan;
1077 else
1078 tp->cp_cmd &= ~RxVlan;
1079 RTL_W16(CPlusCmd, tp->cp_cmd);
1080 RTL_R16(CPlusCmd);
1081 spin_unlock_irqrestore(&tp->lock, flags);
1082 }
1083
1084 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1085 struct sk_buff *skb, int polling)
1086 {
1087 u32 opts2 = le32_to_cpu(desc->opts2);
1088 struct vlan_group *vlgrp = tp->vlgrp;
1089 int ret;
1090
1091 if (vlgrp && (opts2 & RxVlanTag)) {
1092 u16 vtag = swab16(opts2 & 0xffff);
1093
1094 if (likely(polling))
1095 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1096 else
1097 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1098 ret = 0;
1099 } else
1100 ret = -1;
1101 desc->opts2 = 0;
1102 return ret;
1103 }
1104
1105 #else /* !CONFIG_R8169_VLAN */
1106
1107 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1108 struct sk_buff *skb)
1109 {
1110 return 0;
1111 }
1112
1113 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1114 struct sk_buff *skb, int polling)
1115 {
1116 return -1;
1117 }
1118
1119 #endif
1120
1121 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1122 {
1123 struct rtl8169_private *tp = netdev_priv(dev);
1124 void __iomem *ioaddr = tp->mmio_addr;
1125 u32 status;
1126
1127 cmd->supported =
1128 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1129 cmd->port = PORT_FIBRE;
1130 cmd->transceiver = XCVR_INTERNAL;
1131
1132 status = RTL_R32(TBICSR);
1133 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1134 cmd->autoneg = !!(status & TBINwEnable);
1135
1136 cmd->speed = SPEED_1000;
1137 cmd->duplex = DUPLEX_FULL; /* Always set */
1138
1139 return 0;
1140 }
1141
1142 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1143 {
1144 struct rtl8169_private *tp = netdev_priv(dev);
1145
1146 return mii_ethtool_gset(&tp->mii, cmd);
1147 }
1148
1149 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1150 {
1151 struct rtl8169_private *tp = netdev_priv(dev);
1152 unsigned long flags;
1153 int rc;
1154
1155 spin_lock_irqsave(&tp->lock, flags);
1156
1157 rc = tp->get_settings(dev, cmd);
1158
1159 spin_unlock_irqrestore(&tp->lock, flags);
1160 return rc;
1161 }
1162
1163 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1164 void *p)
1165 {
1166 struct rtl8169_private *tp = netdev_priv(dev);
1167 unsigned long flags;
1168
1169 if (regs->len > R8169_REGS_SIZE)
1170 regs->len = R8169_REGS_SIZE;
1171
1172 spin_lock_irqsave(&tp->lock, flags);
1173 memcpy_fromio(p, tp->mmio_addr, regs->len);
1174 spin_unlock_irqrestore(&tp->lock, flags);
1175 }
1176
1177 static u32 rtl8169_get_msglevel(struct net_device *dev)
1178 {
1179 struct rtl8169_private *tp = netdev_priv(dev);
1180
1181 return tp->msg_enable;
1182 }
1183
1184 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1185 {
1186 struct rtl8169_private *tp = netdev_priv(dev);
1187
1188 tp->msg_enable = value;
1189 }
1190
1191 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1192 "tx_packets",
1193 "rx_packets",
1194 "tx_errors",
1195 "rx_errors",
1196 "rx_missed",
1197 "align_errors",
1198 "tx_single_collisions",
1199 "tx_multi_collisions",
1200 "unicast",
1201 "broadcast",
1202 "multicast",
1203 "tx_aborted",
1204 "tx_underrun",
1205 };
1206
1207 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1208 {
1209 switch (sset) {
1210 case ETH_SS_STATS:
1211 return ARRAY_SIZE(rtl8169_gstrings);
1212 default:
1213 return -EOPNOTSUPP;
1214 }
1215 }
1216
1217 static void rtl8169_update_counters(struct net_device *dev)
1218 {
1219 struct rtl8169_private *tp = netdev_priv(dev);
1220 void __iomem *ioaddr = tp->mmio_addr;
1221 struct rtl8169_counters *counters;
1222 dma_addr_t paddr;
1223 u32 cmd;
1224 int wait = 1000;
1225 struct device *d = &tp->pci_dev->dev;
1226
1227 /*
1228 * Some chips are unable to dump tally counters when the receiver
1229 * is disabled.
1230 */
1231 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1232 return;
1233
1234 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1235 if (!counters)
1236 return;
1237
1238 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1239 cmd = (u64)paddr & DMA_BIT_MASK(32);
1240 RTL_W32(CounterAddrLow, cmd);
1241 RTL_W32(CounterAddrLow, cmd | CounterDump);
1242
1243 while (wait--) {
1244 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1245 /* copy updated counters */
1246 memcpy(&tp->counters, counters, sizeof(*counters));
1247 break;
1248 }
1249 udelay(10);
1250 }
1251
1252 RTL_W32(CounterAddrLow, 0);
1253 RTL_W32(CounterAddrHigh, 0);
1254
1255 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1256 }
1257
1258 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1259 struct ethtool_stats *stats, u64 *data)
1260 {
1261 struct rtl8169_private *tp = netdev_priv(dev);
1262
1263 ASSERT_RTNL();
1264
1265 rtl8169_update_counters(dev);
1266
1267 data[0] = le64_to_cpu(tp->counters.tx_packets);
1268 data[1] = le64_to_cpu(tp->counters.rx_packets);
1269 data[2] = le64_to_cpu(tp->counters.tx_errors);
1270 data[3] = le32_to_cpu(tp->counters.rx_errors);
1271 data[4] = le16_to_cpu(tp->counters.rx_missed);
1272 data[5] = le16_to_cpu(tp->counters.align_errors);
1273 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1274 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1275 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1276 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1277 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1278 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1279 data[12] = le16_to_cpu(tp->counters.tx_underun);
1280 }
1281
1282 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1283 {
1284 switch(stringset) {
1285 case ETH_SS_STATS:
1286 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1287 break;
1288 }
1289 }
1290
1291 static const struct ethtool_ops rtl8169_ethtool_ops = {
1292 .get_drvinfo = rtl8169_get_drvinfo,
1293 .get_regs_len = rtl8169_get_regs_len,
1294 .get_link = ethtool_op_get_link,
1295 .get_settings = rtl8169_get_settings,
1296 .set_settings = rtl8169_set_settings,
1297 .get_msglevel = rtl8169_get_msglevel,
1298 .set_msglevel = rtl8169_set_msglevel,
1299 .get_rx_csum = rtl8169_get_rx_csum,
1300 .set_rx_csum = rtl8169_set_rx_csum,
1301 .set_tx_csum = ethtool_op_set_tx_csum,
1302 .set_sg = ethtool_op_set_sg,
1303 .set_tso = ethtool_op_set_tso,
1304 .get_regs = rtl8169_get_regs,
1305 .get_wol = rtl8169_get_wol,
1306 .set_wol = rtl8169_set_wol,
1307 .get_strings = rtl8169_get_strings,
1308 .get_sset_count = rtl8169_get_sset_count,
1309 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1310 };
1311
1312 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1313 void __iomem *ioaddr)
1314 {
1315 /*
1316 * The driver currently handles the 8168Bf and the 8168Be identically
1317 * but they can be identified more specifically through the test below
1318 * if needed:
1319 *
1320 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1321 *
1322 * Same thing for the 8101Eb and the 8101Ec:
1323 *
1324 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1325 */
1326 static const struct {
1327 u32 mask;
1328 u32 val;
1329 int mac_version;
1330 } mac_info[] = {
1331 /* 8168D family. */
1332 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1333 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1334 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1335 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1336
1337 /* 8168C family. */
1338 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1339 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1340 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1341 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1342 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1343 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1344 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1345 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1346 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1347
1348 /* 8168B family. */
1349 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1350 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1351 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1352 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1353
1354 /* 8101 family. */
1355 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1356 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1357 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1358 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1359 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1360 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1361 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1362 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1363 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1364 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1365 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1366 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1367 /* FIXME: where did these entries come from ? -- FR */
1368 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1369 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1370
1371 /* 8110 family. */
1372 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1373 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1374 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1375 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1376 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1377 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1378
1379 /* Catch-all */
1380 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1381 }, *p = mac_info;
1382 u32 reg;
1383
1384 reg = RTL_R32(TxConfig);
1385 while ((reg & p->mask) != p->val)
1386 p++;
1387 tp->mac_version = p->mac_version;
1388 }
1389
1390 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1391 {
1392 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1393 }
1394
1395 struct phy_reg {
1396 u16 reg;
1397 u16 val;
1398 };
1399
1400 static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
1401 {
1402 while (len-- > 0) {
1403 mdio_write(ioaddr, regs->reg, regs->val);
1404 regs++;
1405 }
1406 }
1407
1408 #define PHY_READ 0x00000000
1409 #define PHY_DATA_OR 0x10000000
1410 #define PHY_DATA_AND 0x20000000
1411 #define PHY_BJMPN 0x30000000
1412 #define PHY_READ_EFUSE 0x40000000
1413 #define PHY_READ_MAC_BYTE 0x50000000
1414 #define PHY_WRITE_MAC_BYTE 0x60000000
1415 #define PHY_CLEAR_READCOUNT 0x70000000
1416 #define PHY_WRITE 0x80000000
1417 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1418 #define PHY_COMP_EQ_SKIPN 0xa0000000
1419 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1420 #define PHY_WRITE_PREVIOUS 0xc0000000
1421 #define PHY_SKIPN 0xd0000000
1422 #define PHY_DELAY_MS 0xe0000000
1423 #define PHY_WRITE_ERI_WORD 0xf0000000
1424
1425 static void
1426 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1427 {
1428 void __iomem *ioaddr = tp->mmio_addr;
1429 __le32 *phytable = (__le32 *)fw->data;
1430 struct net_device *dev = tp->dev;
1431 size_t i;
1432
1433 if (fw->size % sizeof(*phytable)) {
1434 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1435 return;
1436 }
1437
1438 for (i = 0; i < fw->size / sizeof(*phytable); i++) {
1439 u32 action = le32_to_cpu(phytable[i]);
1440
1441 if (!action)
1442 break;
1443
1444 if ((action & 0xf0000000) != PHY_WRITE) {
1445 netif_err(tp, probe, dev,
1446 "unknown action 0x%08x\n", action);
1447 return;
1448 }
1449 }
1450
1451 while (i-- != 0) {
1452 u32 action = le32_to_cpu(*phytable);
1453 u32 data = action & 0x0000ffff;
1454 u32 reg = (action & 0x0fff0000) >> 16;
1455
1456 switch(action & 0xf0000000) {
1457 case PHY_WRITE:
1458 mdio_write(ioaddr, reg, data);
1459 phytable++;
1460 break;
1461 default:
1462 BUG();
1463 }
1464 }
1465 }
1466
1467 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1468 {
1469 static const struct phy_reg phy_reg_init[] = {
1470 { 0x1f, 0x0001 },
1471 { 0x06, 0x006e },
1472 { 0x08, 0x0708 },
1473 { 0x15, 0x4000 },
1474 { 0x18, 0x65c7 },
1475
1476 { 0x1f, 0x0001 },
1477 { 0x03, 0x00a1 },
1478 { 0x02, 0x0008 },
1479 { 0x01, 0x0120 },
1480 { 0x00, 0x1000 },
1481 { 0x04, 0x0800 },
1482 { 0x04, 0x0000 },
1483
1484 { 0x03, 0xff41 },
1485 { 0x02, 0xdf60 },
1486 { 0x01, 0x0140 },
1487 { 0x00, 0x0077 },
1488 { 0x04, 0x7800 },
1489 { 0x04, 0x7000 },
1490
1491 { 0x03, 0x802f },
1492 { 0x02, 0x4f02 },
1493 { 0x01, 0x0409 },
1494 { 0x00, 0xf0f9 },
1495 { 0x04, 0x9800 },
1496 { 0x04, 0x9000 },
1497
1498 { 0x03, 0xdf01 },
1499 { 0x02, 0xdf20 },
1500 { 0x01, 0xff95 },
1501 { 0x00, 0xba00 },
1502 { 0x04, 0xa800 },
1503 { 0x04, 0xa000 },
1504
1505 { 0x03, 0xff41 },
1506 { 0x02, 0xdf20 },
1507 { 0x01, 0x0140 },
1508 { 0x00, 0x00bb },
1509 { 0x04, 0xb800 },
1510 { 0x04, 0xb000 },
1511
1512 { 0x03, 0xdf41 },
1513 { 0x02, 0xdc60 },
1514 { 0x01, 0x6340 },
1515 { 0x00, 0x007d },
1516 { 0x04, 0xd800 },
1517 { 0x04, 0xd000 },
1518
1519 { 0x03, 0xdf01 },
1520 { 0x02, 0xdf20 },
1521 { 0x01, 0x100a },
1522 { 0x00, 0xa0ff },
1523 { 0x04, 0xf800 },
1524 { 0x04, 0xf000 },
1525
1526 { 0x1f, 0x0000 },
1527 { 0x0b, 0x0000 },
1528 { 0x00, 0x9200 }
1529 };
1530
1531 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1532 }
1533
1534 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1535 {
1536 static const struct phy_reg phy_reg_init[] = {
1537 { 0x1f, 0x0002 },
1538 { 0x01, 0x90d0 },
1539 { 0x1f, 0x0000 }
1540 };
1541
1542 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1543 }
1544
1545 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1546 void __iomem *ioaddr)
1547 {
1548 struct pci_dev *pdev = tp->pci_dev;
1549 u16 vendor_id, device_id;
1550
1551 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1552 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1553
1554 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1555 return;
1556
1557 mdio_write(ioaddr, 0x1f, 0x0001);
1558 mdio_write(ioaddr, 0x10, 0xf01b);
1559 mdio_write(ioaddr, 0x1f, 0x0000);
1560 }
1561
1562 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1563 void __iomem *ioaddr)
1564 {
1565 static const struct phy_reg phy_reg_init[] = {
1566 { 0x1f, 0x0001 },
1567 { 0x04, 0x0000 },
1568 { 0x03, 0x00a1 },
1569 { 0x02, 0x0008 },
1570 { 0x01, 0x0120 },
1571 { 0x00, 0x1000 },
1572 { 0x04, 0x0800 },
1573 { 0x04, 0x9000 },
1574 { 0x03, 0x802f },
1575 { 0x02, 0x4f02 },
1576 { 0x01, 0x0409 },
1577 { 0x00, 0xf099 },
1578 { 0x04, 0x9800 },
1579 { 0x04, 0xa000 },
1580 { 0x03, 0xdf01 },
1581 { 0x02, 0xdf20 },
1582 { 0x01, 0xff95 },
1583 { 0x00, 0xba00 },
1584 { 0x04, 0xa800 },
1585 { 0x04, 0xf000 },
1586 { 0x03, 0xdf01 },
1587 { 0x02, 0xdf20 },
1588 { 0x01, 0x101a },
1589 { 0x00, 0xa0ff },
1590 { 0x04, 0xf800 },
1591 { 0x04, 0x0000 },
1592 { 0x1f, 0x0000 },
1593
1594 { 0x1f, 0x0001 },
1595 { 0x10, 0xf41b },
1596 { 0x14, 0xfb54 },
1597 { 0x18, 0xf5c7 },
1598 { 0x1f, 0x0000 },
1599
1600 { 0x1f, 0x0001 },
1601 { 0x17, 0x0cc0 },
1602 { 0x1f, 0x0000 }
1603 };
1604
1605 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1606
1607 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1608 }
1609
1610 static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1611 {
1612 static const struct phy_reg phy_reg_init[] = {
1613 { 0x1f, 0x0001 },
1614 { 0x04, 0x0000 },
1615 { 0x03, 0x00a1 },
1616 { 0x02, 0x0008 },
1617 { 0x01, 0x0120 },
1618 { 0x00, 0x1000 },
1619 { 0x04, 0x0800 },
1620 { 0x04, 0x9000 },
1621 { 0x03, 0x802f },
1622 { 0x02, 0x4f02 },
1623 { 0x01, 0x0409 },
1624 { 0x00, 0xf099 },
1625 { 0x04, 0x9800 },
1626 { 0x04, 0xa000 },
1627 { 0x03, 0xdf01 },
1628 { 0x02, 0xdf20 },
1629 { 0x01, 0xff95 },
1630 { 0x00, 0xba00 },
1631 { 0x04, 0xa800 },
1632 { 0x04, 0xf000 },
1633 { 0x03, 0xdf01 },
1634 { 0x02, 0xdf20 },
1635 { 0x01, 0x101a },
1636 { 0x00, 0xa0ff },
1637 { 0x04, 0xf800 },
1638 { 0x04, 0x0000 },
1639 { 0x1f, 0x0000 },
1640
1641 { 0x1f, 0x0001 },
1642 { 0x0b, 0x8480 },
1643 { 0x1f, 0x0000 },
1644
1645 { 0x1f, 0x0001 },
1646 { 0x18, 0x67c7 },
1647 { 0x04, 0x2000 },
1648 { 0x03, 0x002f },
1649 { 0x02, 0x4360 },
1650 { 0x01, 0x0109 },
1651 { 0x00, 0x3022 },
1652 { 0x04, 0x2800 },
1653 { 0x1f, 0x0000 },
1654
1655 { 0x1f, 0x0001 },
1656 { 0x17, 0x0cc0 },
1657 { 0x1f, 0x0000 }
1658 };
1659
1660 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1661 }
1662
1663 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1664 {
1665 static const struct phy_reg phy_reg_init[] = {
1666 { 0x10, 0xf41b },
1667 { 0x1f, 0x0000 }
1668 };
1669
1670 mdio_write(ioaddr, 0x1f, 0x0001);
1671 mdio_patch(ioaddr, 0x16, 1 << 0);
1672
1673 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1674 }
1675
1676 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1677 {
1678 static const struct phy_reg phy_reg_init[] = {
1679 { 0x1f, 0x0001 },
1680 { 0x10, 0xf41b },
1681 { 0x1f, 0x0000 }
1682 };
1683
1684 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1685 }
1686
1687 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1688 {
1689 static const struct phy_reg phy_reg_init[] = {
1690 { 0x1f, 0x0000 },
1691 { 0x1d, 0x0f00 },
1692 { 0x1f, 0x0002 },
1693 { 0x0c, 0x1ec8 },
1694 { 0x1f, 0x0000 }
1695 };
1696
1697 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1698 }
1699
1700 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1701 {
1702 static const struct phy_reg phy_reg_init[] = {
1703 { 0x1f, 0x0001 },
1704 { 0x1d, 0x3d98 },
1705 { 0x1f, 0x0000 }
1706 };
1707
1708 mdio_write(ioaddr, 0x1f, 0x0000);
1709 mdio_patch(ioaddr, 0x14, 1 << 5);
1710 mdio_patch(ioaddr, 0x0d, 1 << 5);
1711
1712 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1713 }
1714
1715 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1716 {
1717 static const struct phy_reg phy_reg_init[] = {
1718 { 0x1f, 0x0001 },
1719 { 0x12, 0x2300 },
1720 { 0x1f, 0x0002 },
1721 { 0x00, 0x88d4 },
1722 { 0x01, 0x82b1 },
1723 { 0x03, 0x7002 },
1724 { 0x08, 0x9e30 },
1725 { 0x09, 0x01f0 },
1726 { 0x0a, 0x5500 },
1727 { 0x0c, 0x00c8 },
1728 { 0x1f, 0x0003 },
1729 { 0x12, 0xc096 },
1730 { 0x16, 0x000a },
1731 { 0x1f, 0x0000 },
1732 { 0x1f, 0x0000 },
1733 { 0x09, 0x2000 },
1734 { 0x09, 0x0000 }
1735 };
1736
1737 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1738
1739 mdio_patch(ioaddr, 0x14, 1 << 5);
1740 mdio_patch(ioaddr, 0x0d, 1 << 5);
1741 mdio_write(ioaddr, 0x1f, 0x0000);
1742 }
1743
1744 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1745 {
1746 static const struct phy_reg phy_reg_init[] = {
1747 { 0x1f, 0x0001 },
1748 { 0x12, 0x2300 },
1749 { 0x03, 0x802f },
1750 { 0x02, 0x4f02 },
1751 { 0x01, 0x0409 },
1752 { 0x00, 0xf099 },
1753 { 0x04, 0x9800 },
1754 { 0x04, 0x9000 },
1755 { 0x1d, 0x3d98 },
1756 { 0x1f, 0x0002 },
1757 { 0x0c, 0x7eb8 },
1758 { 0x06, 0x0761 },
1759 { 0x1f, 0x0003 },
1760 { 0x16, 0x0f0a },
1761 { 0x1f, 0x0000 }
1762 };
1763
1764 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1765
1766 mdio_patch(ioaddr, 0x16, 1 << 0);
1767 mdio_patch(ioaddr, 0x14, 1 << 5);
1768 mdio_patch(ioaddr, 0x0d, 1 << 5);
1769 mdio_write(ioaddr, 0x1f, 0x0000);
1770 }
1771
1772 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1773 {
1774 static const struct phy_reg phy_reg_init[] = {
1775 { 0x1f, 0x0001 },
1776 { 0x12, 0x2300 },
1777 { 0x1d, 0x3d98 },
1778 { 0x1f, 0x0002 },
1779 { 0x0c, 0x7eb8 },
1780 { 0x06, 0x5461 },
1781 { 0x1f, 0x0003 },
1782 { 0x16, 0x0f0a },
1783 { 0x1f, 0x0000 }
1784 };
1785
1786 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1787
1788 mdio_patch(ioaddr, 0x16, 1 << 0);
1789 mdio_patch(ioaddr, 0x14, 1 << 5);
1790 mdio_patch(ioaddr, 0x0d, 1 << 5);
1791 mdio_write(ioaddr, 0x1f, 0x0000);
1792 }
1793
1794 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1795 {
1796 rtl8168c_3_hw_phy_config(ioaddr);
1797 }
1798
1799 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
1800 {
1801 static const struct phy_reg phy_reg_init_0[] = {
1802 /* Channel Estimation */
1803 { 0x1f, 0x0001 },
1804 { 0x06, 0x4064 },
1805 { 0x07, 0x2863 },
1806 { 0x08, 0x059c },
1807 { 0x09, 0x26b4 },
1808 { 0x0a, 0x6a19 },
1809 { 0x0b, 0xdcc8 },
1810 { 0x10, 0xf06d },
1811 { 0x14, 0x7f68 },
1812 { 0x18, 0x7fd9 },
1813 { 0x1c, 0xf0ff },
1814 { 0x1d, 0x3d9c },
1815 { 0x1f, 0x0003 },
1816 { 0x12, 0xf49f },
1817 { 0x13, 0x070b },
1818 { 0x1a, 0x05ad },
1819 { 0x14, 0x94c0 },
1820
1821 /*
1822 * Tx Error Issue
1823 * enhance line driver power
1824 */
1825 { 0x1f, 0x0002 },
1826 { 0x06, 0x5561 },
1827 { 0x1f, 0x0005 },
1828 { 0x05, 0x8332 },
1829 { 0x06, 0x5561 },
1830
1831 /*
1832 * Can not link to 1Gbps with bad cable
1833 * Decrease SNR threshold form 21.07dB to 19.04dB
1834 */
1835 { 0x1f, 0x0001 },
1836 { 0x17, 0x0cc0 },
1837
1838 { 0x1f, 0x0000 },
1839 { 0x0d, 0xf880 }
1840 };
1841 void __iomem *ioaddr = tp->mmio_addr;
1842 const struct firmware *fw;
1843
1844 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1845
1846 /*
1847 * Rx Error Issue
1848 * Fine Tune Switching regulator parameter
1849 */
1850 mdio_write(ioaddr, 0x1f, 0x0002);
1851 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
1852 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
1853
1854 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
1855 static const struct phy_reg phy_reg_init[] = {
1856 { 0x1f, 0x0002 },
1857 { 0x05, 0x669a },
1858 { 0x1f, 0x0005 },
1859 { 0x05, 0x8330 },
1860 { 0x06, 0x669a },
1861 { 0x1f, 0x0002 }
1862 };
1863 int val;
1864
1865 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1866
1867 val = mdio_read(ioaddr, 0x0d);
1868
1869 if ((val & 0x00ff) != 0x006c) {
1870 static const u32 set[] = {
1871 0x0065, 0x0066, 0x0067, 0x0068,
1872 0x0069, 0x006a, 0x006b, 0x006c
1873 };
1874 int i;
1875
1876 mdio_write(ioaddr, 0x1f, 0x0002);
1877
1878 val &= 0xff00;
1879 for (i = 0; i < ARRAY_SIZE(set); i++)
1880 mdio_write(ioaddr, 0x0d, val | set[i]);
1881 }
1882 } else {
1883 static const struct phy_reg phy_reg_init[] = {
1884 { 0x1f, 0x0002 },
1885 { 0x05, 0x6662 },
1886 { 0x1f, 0x0005 },
1887 { 0x05, 0x8330 },
1888 { 0x06, 0x6662 }
1889 };
1890
1891 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1892 }
1893
1894 /* RSET couple improve */
1895 mdio_write(ioaddr, 0x1f, 0x0002);
1896 mdio_patch(ioaddr, 0x0d, 0x0300);
1897 mdio_patch(ioaddr, 0x0f, 0x0010);
1898
1899 /* Fine tune PLL performance */
1900 mdio_write(ioaddr, 0x1f, 0x0002);
1901 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
1902 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
1903
1904 mdio_write(ioaddr, 0x1f, 0x0005);
1905 mdio_write(ioaddr, 0x05, 0x001b);
1906 if (mdio_read(ioaddr, 0x06) == 0xbf00 &&
1907 request_firmware(&fw, FIRMWARE_8168D_1, &tp->pci_dev->dev) == 0) {
1908 rtl_phy_write_fw(tp, fw);
1909 release_firmware(fw);
1910 } else {
1911 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
1912 }
1913
1914 mdio_write(ioaddr, 0x1f, 0x0000);
1915 }
1916
1917 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
1918 {
1919 static const struct phy_reg phy_reg_init_0[] = {
1920 /* Channel Estimation */
1921 { 0x1f, 0x0001 },
1922 { 0x06, 0x4064 },
1923 { 0x07, 0x2863 },
1924 { 0x08, 0x059c },
1925 { 0x09, 0x26b4 },
1926 { 0x0a, 0x6a19 },
1927 { 0x0b, 0xdcc8 },
1928 { 0x10, 0xf06d },
1929 { 0x14, 0x7f68 },
1930 { 0x18, 0x7fd9 },
1931 { 0x1c, 0xf0ff },
1932 { 0x1d, 0x3d9c },
1933 { 0x1f, 0x0003 },
1934 { 0x12, 0xf49f },
1935 { 0x13, 0x070b },
1936 { 0x1a, 0x05ad },
1937 { 0x14, 0x94c0 },
1938
1939 /*
1940 * Tx Error Issue
1941 * enhance line driver power
1942 */
1943 { 0x1f, 0x0002 },
1944 { 0x06, 0x5561 },
1945 { 0x1f, 0x0005 },
1946 { 0x05, 0x8332 },
1947 { 0x06, 0x5561 },
1948
1949 /*
1950 * Can not link to 1Gbps with bad cable
1951 * Decrease SNR threshold form 21.07dB to 19.04dB
1952 */
1953 { 0x1f, 0x0001 },
1954 { 0x17, 0x0cc0 },
1955
1956 { 0x1f, 0x0000 },
1957 { 0x0d, 0xf880 }
1958 };
1959 void __iomem *ioaddr = tp->mmio_addr;
1960 const struct firmware *fw;
1961
1962 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1963
1964 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
1965 static const struct phy_reg phy_reg_init[] = {
1966 { 0x1f, 0x0002 },
1967 { 0x05, 0x669a },
1968 { 0x1f, 0x0005 },
1969 { 0x05, 0x8330 },
1970 { 0x06, 0x669a },
1971
1972 { 0x1f, 0x0002 }
1973 };
1974 int val;
1975
1976 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1977
1978 val = mdio_read(ioaddr, 0x0d);
1979 if ((val & 0x00ff) != 0x006c) {
1980 static const u32 set[] = {
1981 0x0065, 0x0066, 0x0067, 0x0068,
1982 0x0069, 0x006a, 0x006b, 0x006c
1983 };
1984 int i;
1985
1986 mdio_write(ioaddr, 0x1f, 0x0002);
1987
1988 val &= 0xff00;
1989 for (i = 0; i < ARRAY_SIZE(set); i++)
1990 mdio_write(ioaddr, 0x0d, val | set[i]);
1991 }
1992 } else {
1993 static const struct phy_reg phy_reg_init[] = {
1994 { 0x1f, 0x0002 },
1995 { 0x05, 0x2642 },
1996 { 0x1f, 0x0005 },
1997 { 0x05, 0x8330 },
1998 { 0x06, 0x2642 }
1999 };
2000
2001 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2002 }
2003
2004 /* Fine tune PLL performance */
2005 mdio_write(ioaddr, 0x1f, 0x0002);
2006 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2007 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2008
2009 /* Switching regulator Slew rate */
2010 mdio_write(ioaddr, 0x1f, 0x0002);
2011 mdio_patch(ioaddr, 0x0f, 0x0017);
2012
2013 mdio_write(ioaddr, 0x1f, 0x0005);
2014 mdio_write(ioaddr, 0x05, 0x001b);
2015 if (mdio_read(ioaddr, 0x06) == 0xb300 &&
2016 request_firmware(&fw, FIRMWARE_8168D_2, &tp->pci_dev->dev) == 0) {
2017 rtl_phy_write_fw(tp, fw);
2018 release_firmware(fw);
2019 } else {
2020 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2021 }
2022
2023 mdio_write(ioaddr, 0x1f, 0x0000);
2024 }
2025
2026 static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2027 {
2028 static const struct phy_reg phy_reg_init[] = {
2029 { 0x1f, 0x0002 },
2030 { 0x10, 0x0008 },
2031 { 0x0d, 0x006c },
2032
2033 { 0x1f, 0x0000 },
2034 { 0x0d, 0xf880 },
2035
2036 { 0x1f, 0x0001 },
2037 { 0x17, 0x0cc0 },
2038
2039 { 0x1f, 0x0001 },
2040 { 0x0b, 0xa4d8 },
2041 { 0x09, 0x281c },
2042 { 0x07, 0x2883 },
2043 { 0x0a, 0x6b35 },
2044 { 0x1d, 0x3da4 },
2045 { 0x1c, 0xeffd },
2046 { 0x14, 0x7f52 },
2047 { 0x18, 0x7fc6 },
2048 { 0x08, 0x0601 },
2049 { 0x06, 0x4063 },
2050 { 0x10, 0xf074 },
2051 { 0x1f, 0x0003 },
2052 { 0x13, 0x0789 },
2053 { 0x12, 0xf4bd },
2054 { 0x1a, 0x04fd },
2055 { 0x14, 0x84b0 },
2056 { 0x1f, 0x0000 },
2057 { 0x00, 0x9200 },
2058
2059 { 0x1f, 0x0005 },
2060 { 0x01, 0x0340 },
2061 { 0x1f, 0x0001 },
2062 { 0x04, 0x4000 },
2063 { 0x03, 0x1d21 },
2064 { 0x02, 0x0c32 },
2065 { 0x01, 0x0200 },
2066 { 0x00, 0x5554 },
2067 { 0x04, 0x4800 },
2068 { 0x04, 0x4000 },
2069 { 0x04, 0xf000 },
2070 { 0x03, 0xdf01 },
2071 { 0x02, 0xdf20 },
2072 { 0x01, 0x101a },
2073 { 0x00, 0xa0ff },
2074 { 0x04, 0xf800 },
2075 { 0x04, 0xf000 },
2076 { 0x1f, 0x0000 },
2077
2078 { 0x1f, 0x0007 },
2079 { 0x1e, 0x0023 },
2080 { 0x16, 0x0000 },
2081 { 0x1f, 0x0000 }
2082 };
2083
2084 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2085 }
2086
2087 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2088 {
2089 static const struct phy_reg phy_reg_init[] = {
2090 { 0x1f, 0x0003 },
2091 { 0x08, 0x441d },
2092 { 0x01, 0x9100 },
2093 { 0x1f, 0x0000 }
2094 };
2095
2096 mdio_write(ioaddr, 0x1f, 0x0000);
2097 mdio_patch(ioaddr, 0x11, 1 << 12);
2098 mdio_patch(ioaddr, 0x19, 1 << 13);
2099 mdio_patch(ioaddr, 0x10, 1 << 15);
2100
2101 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2102 }
2103
2104 static void rtl_hw_phy_config(struct net_device *dev)
2105 {
2106 struct rtl8169_private *tp = netdev_priv(dev);
2107 void __iomem *ioaddr = tp->mmio_addr;
2108
2109 rtl8169_print_mac_version(tp);
2110
2111 switch (tp->mac_version) {
2112 case RTL_GIGA_MAC_VER_01:
2113 break;
2114 case RTL_GIGA_MAC_VER_02:
2115 case RTL_GIGA_MAC_VER_03:
2116 rtl8169s_hw_phy_config(ioaddr);
2117 break;
2118 case RTL_GIGA_MAC_VER_04:
2119 rtl8169sb_hw_phy_config(ioaddr);
2120 break;
2121 case RTL_GIGA_MAC_VER_05:
2122 rtl8169scd_hw_phy_config(tp, ioaddr);
2123 break;
2124 case RTL_GIGA_MAC_VER_06:
2125 rtl8169sce_hw_phy_config(ioaddr);
2126 break;
2127 case RTL_GIGA_MAC_VER_07:
2128 case RTL_GIGA_MAC_VER_08:
2129 case RTL_GIGA_MAC_VER_09:
2130 rtl8102e_hw_phy_config(ioaddr);
2131 break;
2132 case RTL_GIGA_MAC_VER_11:
2133 rtl8168bb_hw_phy_config(ioaddr);
2134 break;
2135 case RTL_GIGA_MAC_VER_12:
2136 rtl8168bef_hw_phy_config(ioaddr);
2137 break;
2138 case RTL_GIGA_MAC_VER_17:
2139 rtl8168bef_hw_phy_config(ioaddr);
2140 break;
2141 case RTL_GIGA_MAC_VER_18:
2142 rtl8168cp_1_hw_phy_config(ioaddr);
2143 break;
2144 case RTL_GIGA_MAC_VER_19:
2145 rtl8168c_1_hw_phy_config(ioaddr);
2146 break;
2147 case RTL_GIGA_MAC_VER_20:
2148 rtl8168c_2_hw_phy_config(ioaddr);
2149 break;
2150 case RTL_GIGA_MAC_VER_21:
2151 rtl8168c_3_hw_phy_config(ioaddr);
2152 break;
2153 case RTL_GIGA_MAC_VER_22:
2154 rtl8168c_4_hw_phy_config(ioaddr);
2155 break;
2156 case RTL_GIGA_MAC_VER_23:
2157 case RTL_GIGA_MAC_VER_24:
2158 rtl8168cp_2_hw_phy_config(ioaddr);
2159 break;
2160 case RTL_GIGA_MAC_VER_25:
2161 rtl8168d_1_hw_phy_config(tp);
2162 break;
2163 case RTL_GIGA_MAC_VER_26:
2164 rtl8168d_2_hw_phy_config(tp);
2165 break;
2166 case RTL_GIGA_MAC_VER_27:
2167 rtl8168d_3_hw_phy_config(ioaddr);
2168 break;
2169
2170 default:
2171 break;
2172 }
2173 }
2174
2175 static void rtl8169_phy_timer(unsigned long __opaque)
2176 {
2177 struct net_device *dev = (struct net_device *)__opaque;
2178 struct rtl8169_private *tp = netdev_priv(dev);
2179 struct timer_list *timer = &tp->timer;
2180 void __iomem *ioaddr = tp->mmio_addr;
2181 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2182
2183 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2184
2185 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2186 return;
2187
2188 spin_lock_irq(&tp->lock);
2189
2190 if (tp->phy_reset_pending(ioaddr)) {
2191 /*
2192 * A busy loop could burn quite a few cycles on nowadays CPU.
2193 * Let's delay the execution of the timer for a few ticks.
2194 */
2195 timeout = HZ/10;
2196 goto out_mod_timer;
2197 }
2198
2199 if (tp->link_ok(ioaddr))
2200 goto out_unlock;
2201
2202 netif_warn(tp, link, dev, "PHY reset until link up\n");
2203
2204 tp->phy_reset_enable(ioaddr);
2205
2206 out_mod_timer:
2207 mod_timer(timer, jiffies + timeout);
2208 out_unlock:
2209 spin_unlock_irq(&tp->lock);
2210 }
2211
2212 static inline void rtl8169_delete_timer(struct net_device *dev)
2213 {
2214 struct rtl8169_private *tp = netdev_priv(dev);
2215 struct timer_list *timer = &tp->timer;
2216
2217 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2218 return;
2219
2220 del_timer_sync(timer);
2221 }
2222
2223 static inline void rtl8169_request_timer(struct net_device *dev)
2224 {
2225 struct rtl8169_private *tp = netdev_priv(dev);
2226 struct timer_list *timer = &tp->timer;
2227
2228 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2229 return;
2230
2231 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2232 }
2233
2234 #ifdef CONFIG_NET_POLL_CONTROLLER
2235 /*
2236 * Polling 'interrupt' - used by things like netconsole to send skbs
2237 * without having to re-enable interrupts. It's not called while
2238 * the interrupt routine is executing.
2239 */
2240 static void rtl8169_netpoll(struct net_device *dev)
2241 {
2242 struct rtl8169_private *tp = netdev_priv(dev);
2243 struct pci_dev *pdev = tp->pci_dev;
2244
2245 disable_irq(pdev->irq);
2246 rtl8169_interrupt(pdev->irq, dev);
2247 enable_irq(pdev->irq);
2248 }
2249 #endif
2250
2251 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2252 void __iomem *ioaddr)
2253 {
2254 iounmap(ioaddr);
2255 pci_release_regions(pdev);
2256 pci_clear_mwi(pdev);
2257 pci_disable_device(pdev);
2258 free_netdev(dev);
2259 }
2260
2261 static void rtl8169_phy_reset(struct net_device *dev,
2262 struct rtl8169_private *tp)
2263 {
2264 void __iomem *ioaddr = tp->mmio_addr;
2265 unsigned int i;
2266
2267 tp->phy_reset_enable(ioaddr);
2268 for (i = 0; i < 100; i++) {
2269 if (!tp->phy_reset_pending(ioaddr))
2270 return;
2271 msleep(1);
2272 }
2273 netif_err(tp, link, dev, "PHY reset failed\n");
2274 }
2275
2276 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2277 {
2278 void __iomem *ioaddr = tp->mmio_addr;
2279
2280 rtl_hw_phy_config(dev);
2281
2282 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2283 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2284 RTL_W8(0x82, 0x01);
2285 }
2286
2287 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2288
2289 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2290 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2291
2292 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2293 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2294 RTL_W8(0x82, 0x01);
2295 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2296 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2297 }
2298
2299 rtl8169_phy_reset(dev, tp);
2300
2301 /*
2302 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2303 * only 8101. Don't panic.
2304 */
2305 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2306
2307 if (RTL_R8(PHYstatus) & TBI_Enable)
2308 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2309 }
2310
2311 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2312 {
2313 void __iomem *ioaddr = tp->mmio_addr;
2314 u32 high;
2315 u32 low;
2316
2317 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2318 high = addr[4] | (addr[5] << 8);
2319
2320 spin_lock_irq(&tp->lock);
2321
2322 RTL_W8(Cfg9346, Cfg9346_Unlock);
2323
2324 RTL_W32(MAC4, high);
2325 RTL_R32(MAC4);
2326
2327 RTL_W32(MAC0, low);
2328 RTL_R32(MAC0);
2329
2330 RTL_W8(Cfg9346, Cfg9346_Lock);
2331
2332 spin_unlock_irq(&tp->lock);
2333 }
2334
2335 static int rtl_set_mac_address(struct net_device *dev, void *p)
2336 {
2337 struct rtl8169_private *tp = netdev_priv(dev);
2338 struct sockaddr *addr = p;
2339
2340 if (!is_valid_ether_addr(addr->sa_data))
2341 return -EADDRNOTAVAIL;
2342
2343 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2344
2345 rtl_rar_set(tp, dev->dev_addr);
2346
2347 return 0;
2348 }
2349
2350 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2351 {
2352 struct rtl8169_private *tp = netdev_priv(dev);
2353 struct mii_ioctl_data *data = if_mii(ifr);
2354
2355 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2356 }
2357
2358 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2359 {
2360 switch (cmd) {
2361 case SIOCGMIIPHY:
2362 data->phy_id = 32; /* Internal PHY */
2363 return 0;
2364
2365 case SIOCGMIIREG:
2366 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2367 return 0;
2368
2369 case SIOCSMIIREG:
2370 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2371 return 0;
2372 }
2373 return -EOPNOTSUPP;
2374 }
2375
2376 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2377 {
2378 return -EOPNOTSUPP;
2379 }
2380
2381 static const struct rtl_cfg_info {
2382 void (*hw_start)(struct net_device *);
2383 unsigned int region;
2384 unsigned int align;
2385 u16 intr_event;
2386 u16 napi_event;
2387 unsigned features;
2388 u8 default_ver;
2389 } rtl_cfg_infos [] = {
2390 [RTL_CFG_0] = {
2391 .hw_start = rtl_hw_start_8169,
2392 .region = 1,
2393 .align = 0,
2394 .intr_event = SYSErr | LinkChg | RxOverflow |
2395 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2396 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2397 .features = RTL_FEATURE_GMII,
2398 .default_ver = RTL_GIGA_MAC_VER_01,
2399 },
2400 [RTL_CFG_1] = {
2401 .hw_start = rtl_hw_start_8168,
2402 .region = 2,
2403 .align = 8,
2404 .intr_event = SYSErr | LinkChg | RxOverflow |
2405 TxErr | TxOK | RxOK | RxErr,
2406 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2407 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2408 .default_ver = RTL_GIGA_MAC_VER_11,
2409 },
2410 [RTL_CFG_2] = {
2411 .hw_start = rtl_hw_start_8101,
2412 .region = 2,
2413 .align = 8,
2414 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2415 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2416 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2417 .features = RTL_FEATURE_MSI,
2418 .default_ver = RTL_GIGA_MAC_VER_13,
2419 }
2420 };
2421
2422 /* Cfg9346_Unlock assumed. */
2423 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2424 const struct rtl_cfg_info *cfg)
2425 {
2426 unsigned msi = 0;
2427 u8 cfg2;
2428
2429 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2430 if (cfg->features & RTL_FEATURE_MSI) {
2431 if (pci_enable_msi(pdev)) {
2432 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2433 } else {
2434 cfg2 |= MSIEnable;
2435 msi = RTL_FEATURE_MSI;
2436 }
2437 }
2438 RTL_W8(Config2, cfg2);
2439 return msi;
2440 }
2441
2442 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2443 {
2444 if (tp->features & RTL_FEATURE_MSI) {
2445 pci_disable_msi(pdev);
2446 tp->features &= ~RTL_FEATURE_MSI;
2447 }
2448 }
2449
2450 static const struct net_device_ops rtl8169_netdev_ops = {
2451 .ndo_open = rtl8169_open,
2452 .ndo_stop = rtl8169_close,
2453 .ndo_get_stats = rtl8169_get_stats,
2454 .ndo_start_xmit = rtl8169_start_xmit,
2455 .ndo_tx_timeout = rtl8169_tx_timeout,
2456 .ndo_validate_addr = eth_validate_addr,
2457 .ndo_change_mtu = rtl8169_change_mtu,
2458 .ndo_set_mac_address = rtl_set_mac_address,
2459 .ndo_do_ioctl = rtl8169_ioctl,
2460 .ndo_set_multicast_list = rtl_set_rx_mode,
2461 #ifdef CONFIG_R8169_VLAN
2462 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2463 #endif
2464 #ifdef CONFIG_NET_POLL_CONTROLLER
2465 .ndo_poll_controller = rtl8169_netpoll,
2466 #endif
2467
2468 };
2469
2470 static int __devinit
2471 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2472 {
2473 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2474 const unsigned int region = cfg->region;
2475 struct rtl8169_private *tp;
2476 struct mii_if_info *mii;
2477 struct net_device *dev;
2478 void __iomem *ioaddr;
2479 unsigned int i;
2480 int rc;
2481
2482 if (netif_msg_drv(&debug)) {
2483 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2484 MODULENAME, RTL8169_VERSION);
2485 }
2486
2487 dev = alloc_etherdev(sizeof (*tp));
2488 if (!dev) {
2489 if (netif_msg_drv(&debug))
2490 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
2491 rc = -ENOMEM;
2492 goto out;
2493 }
2494
2495 SET_NETDEV_DEV(dev, &pdev->dev);
2496 dev->netdev_ops = &rtl8169_netdev_ops;
2497 tp = netdev_priv(dev);
2498 tp->dev = dev;
2499 tp->pci_dev = pdev;
2500 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
2501
2502 mii = &tp->mii;
2503 mii->dev = dev;
2504 mii->mdio_read = rtl_mdio_read;
2505 mii->mdio_write = rtl_mdio_write;
2506 mii->phy_id_mask = 0x1f;
2507 mii->reg_num_mask = 0x1f;
2508 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2509
2510 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2511 rc = pci_enable_device(pdev);
2512 if (rc < 0) {
2513 netif_err(tp, probe, dev, "enable failure\n");
2514 goto err_out_free_dev_1;
2515 }
2516
2517 if (pci_set_mwi(pdev) < 0)
2518 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
2519
2520 /* make sure PCI base addr 1 is MMIO */
2521 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
2522 netif_err(tp, probe, dev,
2523 "region #%d not an MMIO resource, aborting\n",
2524 region);
2525 rc = -ENODEV;
2526 goto err_out_mwi_2;
2527 }
2528
2529 /* check for weird/broken PCI region reporting */
2530 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
2531 netif_err(tp, probe, dev,
2532 "Invalid PCI region size(s), aborting\n");
2533 rc = -ENODEV;
2534 goto err_out_mwi_2;
2535 }
2536
2537 rc = pci_request_regions(pdev, MODULENAME);
2538 if (rc < 0) {
2539 netif_err(tp, probe, dev, "could not request regions\n");
2540 goto err_out_mwi_2;
2541 }
2542
2543 tp->cp_cmd = PCIMulRW | RxChkSum;
2544
2545 if ((sizeof(dma_addr_t) > 4) &&
2546 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
2547 tp->cp_cmd |= PCIDAC;
2548 dev->features |= NETIF_F_HIGHDMA;
2549 } else {
2550 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2551 if (rc < 0) {
2552 netif_err(tp, probe, dev, "DMA configuration failed\n");
2553 goto err_out_free_res_3;
2554 }
2555 }
2556
2557 /* ioremap MMIO region */
2558 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2559 if (!ioaddr) {
2560 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
2561 rc = -EIO;
2562 goto err_out_free_res_3;
2563 }
2564
2565 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2566 if (!tp->pcie_cap)
2567 netif_info(tp, probe, dev, "no PCI Express capability\n");
2568
2569 RTL_W16(IntrMask, 0x0000);
2570
2571 /* Soft reset the chip. */
2572 RTL_W8(ChipCmd, CmdReset);
2573
2574 /* Check that the chip has finished the reset. */
2575 for (i = 0; i < 100; i++) {
2576 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2577 break;
2578 msleep_interruptible(1);
2579 }
2580
2581 RTL_W16(IntrStatus, 0xffff);
2582
2583 pci_set_master(pdev);
2584
2585 /* Identify chip attached to board */
2586 rtl8169_get_mac_version(tp, ioaddr);
2587
2588 /* Use appropriate default if unknown */
2589 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2590 netif_notice(tp, probe, dev,
2591 "unknown MAC, using family default\n");
2592 tp->mac_version = cfg->default_ver;
2593 }
2594
2595 rtl8169_print_mac_version(tp);
2596
2597 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2598 if (tp->mac_version == rtl_chip_info[i].mac_version)
2599 break;
2600 }
2601 if (i == ARRAY_SIZE(rtl_chip_info)) {
2602 dev_err(&pdev->dev,
2603 "driver bug, MAC version not found in rtl_chip_info\n");
2604 goto err_out_msi_4;
2605 }
2606 tp->chipset = i;
2607
2608 RTL_W8(Cfg9346, Cfg9346_Unlock);
2609 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2610 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2611 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2612 tp->features |= RTL_FEATURE_WOL;
2613 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2614 tp->features |= RTL_FEATURE_WOL;
2615 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2616 RTL_W8(Cfg9346, Cfg9346_Lock);
2617
2618 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2619 (RTL_R8(PHYstatus) & TBI_Enable)) {
2620 tp->set_speed = rtl8169_set_speed_tbi;
2621 tp->get_settings = rtl8169_gset_tbi;
2622 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2623 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2624 tp->link_ok = rtl8169_tbi_link_ok;
2625 tp->do_ioctl = rtl_tbi_ioctl;
2626
2627 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2628 } else {
2629 tp->set_speed = rtl8169_set_speed_xmii;
2630 tp->get_settings = rtl8169_gset_xmii;
2631 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2632 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2633 tp->link_ok = rtl8169_xmii_link_ok;
2634 tp->do_ioctl = rtl_xmii_ioctl;
2635 }
2636
2637 spin_lock_init(&tp->lock);
2638
2639 tp->mmio_addr = ioaddr;
2640
2641 /* Get MAC address */
2642 for (i = 0; i < MAC_ADDR_LEN; i++)
2643 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2644 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2645
2646 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2647 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2648 dev->irq = pdev->irq;
2649 dev->base_addr = (unsigned long) ioaddr;
2650
2651 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2652
2653 #ifdef CONFIG_R8169_VLAN
2654 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2655 #endif
2656 dev->features |= NETIF_F_GRO;
2657
2658 tp->intr_mask = 0xffff;
2659 tp->hw_start = cfg->hw_start;
2660 tp->intr_event = cfg->intr_event;
2661 tp->napi_event = cfg->napi_event;
2662
2663 init_timer(&tp->timer);
2664 tp->timer.data = (unsigned long) dev;
2665 tp->timer.function = rtl8169_phy_timer;
2666
2667 rc = register_netdev(dev);
2668 if (rc < 0)
2669 goto err_out_msi_4;
2670
2671 pci_set_drvdata(pdev, dev);
2672
2673 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
2674 rtl_chip_info[tp->chipset].name,
2675 dev->base_addr, dev->dev_addr,
2676 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
2677
2678 rtl8169_init_phy(dev, tp);
2679
2680 /*
2681 * Pretend we are using VLANs; This bypasses a nasty bug where
2682 * Interrupts stop flowing on high load on 8110SCd controllers.
2683 */
2684 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2685 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
2686
2687 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2688
2689 if (pci_dev_run_wake(pdev))
2690 pm_runtime_put_noidle(&pdev->dev);
2691
2692 out:
2693 return rc;
2694
2695 err_out_msi_4:
2696 rtl_disable_msi(pdev, tp);
2697 iounmap(ioaddr);
2698 err_out_free_res_3:
2699 pci_release_regions(pdev);
2700 err_out_mwi_2:
2701 pci_clear_mwi(pdev);
2702 pci_disable_device(pdev);
2703 err_out_free_dev_1:
2704 free_netdev(dev);
2705 goto out;
2706 }
2707
2708 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2709 {
2710 struct net_device *dev = pci_get_drvdata(pdev);
2711 struct rtl8169_private *tp = netdev_priv(dev);
2712
2713 cancel_delayed_work_sync(&tp->task);
2714
2715 unregister_netdev(dev);
2716
2717 if (pci_dev_run_wake(pdev))
2718 pm_runtime_get_noresume(&pdev->dev);
2719
2720 /* restore original MAC address */
2721 rtl_rar_set(tp, dev->perm_addr);
2722
2723 rtl_disable_msi(pdev, tp);
2724 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2725 pci_set_drvdata(pdev, NULL);
2726 }
2727
2728 static int rtl8169_open(struct net_device *dev)
2729 {
2730 struct rtl8169_private *tp = netdev_priv(dev);
2731 struct pci_dev *pdev = tp->pci_dev;
2732 int retval = -ENOMEM;
2733
2734 pm_runtime_get_sync(&pdev->dev);
2735
2736 /*
2737 * Rx and Tx desscriptors needs 256 bytes alignment.
2738 * dma_alloc_coherent provides more.
2739 */
2740 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
2741 &tp->TxPhyAddr, GFP_KERNEL);
2742 if (!tp->TxDescArray)
2743 goto err_pm_runtime_put;
2744
2745 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
2746 &tp->RxPhyAddr, GFP_KERNEL);
2747 if (!tp->RxDescArray)
2748 goto err_free_tx_0;
2749
2750 retval = rtl8169_init_ring(dev);
2751 if (retval < 0)
2752 goto err_free_rx_1;
2753
2754 INIT_DELAYED_WORK(&tp->task, NULL);
2755
2756 smp_mb();
2757
2758 retval = request_irq(dev->irq, rtl8169_interrupt,
2759 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2760 dev->name, dev);
2761 if (retval < 0)
2762 goto err_release_ring_2;
2763
2764 napi_enable(&tp->napi);
2765
2766 rtl_hw_start(dev);
2767
2768 rtl8169_request_timer(dev);
2769
2770 tp->saved_wolopts = 0;
2771 pm_runtime_put_noidle(&pdev->dev);
2772
2773 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2774 out:
2775 return retval;
2776
2777 err_release_ring_2:
2778 rtl8169_rx_clear(tp);
2779 err_free_rx_1:
2780 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
2781 tp->RxPhyAddr);
2782 tp->RxDescArray = NULL;
2783 err_free_tx_0:
2784 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
2785 tp->TxPhyAddr);
2786 tp->TxDescArray = NULL;
2787 err_pm_runtime_put:
2788 pm_runtime_put_noidle(&pdev->dev);
2789 goto out;
2790 }
2791
2792 static void rtl8169_hw_reset(void __iomem *ioaddr)
2793 {
2794 /* Disable interrupts */
2795 rtl8169_irq_mask_and_ack(ioaddr);
2796
2797 /* Reset the chipset */
2798 RTL_W8(ChipCmd, CmdReset);
2799
2800 /* PCI commit */
2801 RTL_R8(ChipCmd);
2802 }
2803
2804 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2805 {
2806 void __iomem *ioaddr = tp->mmio_addr;
2807 u32 cfg = rtl8169_rx_config;
2808
2809 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2810 RTL_W32(RxConfig, cfg);
2811
2812 /* Set DMA burst size and Interframe Gap Time */
2813 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2814 (InterFrameGap << TxInterFrameGapShift));
2815 }
2816
2817 static void rtl_hw_start(struct net_device *dev)
2818 {
2819 struct rtl8169_private *tp = netdev_priv(dev);
2820 void __iomem *ioaddr = tp->mmio_addr;
2821 unsigned int i;
2822
2823 /* Soft reset the chip. */
2824 RTL_W8(ChipCmd, CmdReset);
2825
2826 /* Check that the chip has finished the reset. */
2827 for (i = 0; i < 100; i++) {
2828 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2829 break;
2830 msleep_interruptible(1);
2831 }
2832
2833 tp->hw_start(dev);
2834
2835 netif_start_queue(dev);
2836 }
2837
2838
2839 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2840 void __iomem *ioaddr)
2841 {
2842 /*
2843 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2844 * register to be written before TxDescAddrLow to work.
2845 * Switching from MMIO to I/O access fixes the issue as well.
2846 */
2847 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2848 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2849 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2850 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2851 }
2852
2853 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2854 {
2855 u16 cmd;
2856
2857 cmd = RTL_R16(CPlusCmd);
2858 RTL_W16(CPlusCmd, cmd);
2859 return cmd;
2860 }
2861
2862 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
2863 {
2864 /* Low hurts. Let's disable the filtering. */
2865 RTL_W16(RxMaxSize, rx_buf_sz + 1);
2866 }
2867
2868 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2869 {
2870 static const struct {
2871 u32 mac_version;
2872 u32 clk;
2873 u32 val;
2874 } cfg2_info [] = {
2875 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2876 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2877 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2878 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2879 }, *p = cfg2_info;
2880 unsigned int i;
2881 u32 clk;
2882
2883 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2884 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2885 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2886 RTL_W32(0x7c, p->val);
2887 break;
2888 }
2889 }
2890 }
2891
2892 static void rtl_hw_start_8169(struct net_device *dev)
2893 {
2894 struct rtl8169_private *tp = netdev_priv(dev);
2895 void __iomem *ioaddr = tp->mmio_addr;
2896 struct pci_dev *pdev = tp->pci_dev;
2897
2898 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2899 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2900 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2901 }
2902
2903 RTL_W8(Cfg9346, Cfg9346_Unlock);
2904 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2905 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2906 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2907 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2908 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2909
2910 RTL_W8(EarlyTxThres, NoEarlyTx);
2911
2912 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2913
2914 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2915 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2916 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2917 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2918 rtl_set_rx_tx_config_registers(tp);
2919
2920 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2921
2922 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2923 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2924 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2925 "Bit-3 and bit-14 MUST be 1\n");
2926 tp->cp_cmd |= (1 << 14);
2927 }
2928
2929 RTL_W16(CPlusCmd, tp->cp_cmd);
2930
2931 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2932
2933 /*
2934 * Undocumented corner. Supposedly:
2935 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2936 */
2937 RTL_W16(IntrMitigate, 0x0000);
2938
2939 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2940
2941 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2942 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2943 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2944 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2945 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2946 rtl_set_rx_tx_config_registers(tp);
2947 }
2948
2949 RTL_W8(Cfg9346, Cfg9346_Lock);
2950
2951 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2952 RTL_R8(IntrMask);
2953
2954 RTL_W32(RxMissed, 0);
2955
2956 rtl_set_rx_mode(dev);
2957
2958 /* no early-rx interrupts */
2959 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2960
2961 /* Enable all known interrupts by setting the interrupt mask. */
2962 RTL_W16(IntrMask, tp->intr_event);
2963 }
2964
2965 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2966 {
2967 struct net_device *dev = pci_get_drvdata(pdev);
2968 struct rtl8169_private *tp = netdev_priv(dev);
2969 int cap = tp->pcie_cap;
2970
2971 if (cap) {
2972 u16 ctl;
2973
2974 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2975 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2976 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2977 }
2978 }
2979
2980 static void rtl_csi_access_enable(void __iomem *ioaddr)
2981 {
2982 u32 csi;
2983
2984 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2985 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2986 }
2987
2988 struct ephy_info {
2989 unsigned int offset;
2990 u16 mask;
2991 u16 bits;
2992 };
2993
2994 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
2995 {
2996 u16 w;
2997
2998 while (len-- > 0) {
2999 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3000 rtl_ephy_write(ioaddr, e->offset, w);
3001 e++;
3002 }
3003 }
3004
3005 static void rtl_disable_clock_request(struct pci_dev *pdev)
3006 {
3007 struct net_device *dev = pci_get_drvdata(pdev);
3008 struct rtl8169_private *tp = netdev_priv(dev);
3009 int cap = tp->pcie_cap;
3010
3011 if (cap) {
3012 u16 ctl;
3013
3014 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3015 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3016 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3017 }
3018 }
3019
3020 #define R8168_CPCMD_QUIRK_MASK (\
3021 EnableBist | \
3022 Mac_dbgo_oe | \
3023 Force_half_dup | \
3024 Force_rxflow_en | \
3025 Force_txflow_en | \
3026 Cxpl_dbg_sel | \
3027 ASF | \
3028 PktCntrDisable | \
3029 Mac_dbgo_sel)
3030
3031 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3032 {
3033 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3034
3035 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3036
3037 rtl_tx_performance_tweak(pdev,
3038 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3039 }
3040
3041 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3042 {
3043 rtl_hw_start_8168bb(ioaddr, pdev);
3044
3045 RTL_W8(MaxTxPacketSize, TxPacketMax);
3046
3047 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3048 }
3049
3050 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3051 {
3052 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3053
3054 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3055
3056 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3057
3058 rtl_disable_clock_request(pdev);
3059
3060 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3061 }
3062
3063 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3064 {
3065 static const struct ephy_info e_info_8168cp[] = {
3066 { 0x01, 0, 0x0001 },
3067 { 0x02, 0x0800, 0x1000 },
3068 { 0x03, 0, 0x0042 },
3069 { 0x06, 0x0080, 0x0000 },
3070 { 0x07, 0, 0x2000 }
3071 };
3072
3073 rtl_csi_access_enable(ioaddr);
3074
3075 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3076
3077 __rtl_hw_start_8168cp(ioaddr, pdev);
3078 }
3079
3080 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3081 {
3082 rtl_csi_access_enable(ioaddr);
3083
3084 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3085
3086 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3087
3088 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3089 }
3090
3091 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3092 {
3093 rtl_csi_access_enable(ioaddr);
3094
3095 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3096
3097 /* Magic. */
3098 RTL_W8(DBG_REG, 0x20);
3099
3100 RTL_W8(MaxTxPacketSize, TxPacketMax);
3101
3102 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3103
3104 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3105 }
3106
3107 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3108 {
3109 static const struct ephy_info e_info_8168c_1[] = {
3110 { 0x02, 0x0800, 0x1000 },
3111 { 0x03, 0, 0x0002 },
3112 { 0x06, 0x0080, 0x0000 }
3113 };
3114
3115 rtl_csi_access_enable(ioaddr);
3116
3117 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3118
3119 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3120
3121 __rtl_hw_start_8168cp(ioaddr, pdev);
3122 }
3123
3124 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3125 {
3126 static const struct ephy_info e_info_8168c_2[] = {
3127 { 0x01, 0, 0x0001 },
3128 { 0x03, 0x0400, 0x0220 }
3129 };
3130
3131 rtl_csi_access_enable(ioaddr);
3132
3133 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3134
3135 __rtl_hw_start_8168cp(ioaddr, pdev);
3136 }
3137
3138 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3139 {
3140 rtl_hw_start_8168c_2(ioaddr, pdev);
3141 }
3142
3143 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3144 {
3145 rtl_csi_access_enable(ioaddr);
3146
3147 __rtl_hw_start_8168cp(ioaddr, pdev);
3148 }
3149
3150 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3151 {
3152 rtl_csi_access_enable(ioaddr);
3153
3154 rtl_disable_clock_request(pdev);
3155
3156 RTL_W8(MaxTxPacketSize, TxPacketMax);
3157
3158 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3159
3160 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3161 }
3162
3163 static void rtl_hw_start_8168(struct net_device *dev)
3164 {
3165 struct rtl8169_private *tp = netdev_priv(dev);
3166 void __iomem *ioaddr = tp->mmio_addr;
3167 struct pci_dev *pdev = tp->pci_dev;
3168
3169 RTL_W8(Cfg9346, Cfg9346_Unlock);
3170
3171 RTL_W8(MaxTxPacketSize, TxPacketMax);
3172
3173 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3174
3175 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3176
3177 RTL_W16(CPlusCmd, tp->cp_cmd);
3178
3179 RTL_W16(IntrMitigate, 0x5151);
3180
3181 /* Work around for RxFIFO overflow. */
3182 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3183 tp->intr_event |= RxFIFOOver | PCSTimeout;
3184 tp->intr_event &= ~RxOverflow;
3185 }
3186
3187 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3188
3189 rtl_set_rx_mode(dev);
3190
3191 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3192 (InterFrameGap << TxInterFrameGapShift));
3193
3194 RTL_R8(IntrMask);
3195
3196 switch (tp->mac_version) {
3197 case RTL_GIGA_MAC_VER_11:
3198 rtl_hw_start_8168bb(ioaddr, pdev);
3199 break;
3200
3201 case RTL_GIGA_MAC_VER_12:
3202 case RTL_GIGA_MAC_VER_17:
3203 rtl_hw_start_8168bef(ioaddr, pdev);
3204 break;
3205
3206 case RTL_GIGA_MAC_VER_18:
3207 rtl_hw_start_8168cp_1(ioaddr, pdev);
3208 break;
3209
3210 case RTL_GIGA_MAC_VER_19:
3211 rtl_hw_start_8168c_1(ioaddr, pdev);
3212 break;
3213
3214 case RTL_GIGA_MAC_VER_20:
3215 rtl_hw_start_8168c_2(ioaddr, pdev);
3216 break;
3217
3218 case RTL_GIGA_MAC_VER_21:
3219 rtl_hw_start_8168c_3(ioaddr, pdev);
3220 break;
3221
3222 case RTL_GIGA_MAC_VER_22:
3223 rtl_hw_start_8168c_4(ioaddr, pdev);
3224 break;
3225
3226 case RTL_GIGA_MAC_VER_23:
3227 rtl_hw_start_8168cp_2(ioaddr, pdev);
3228 break;
3229
3230 case RTL_GIGA_MAC_VER_24:
3231 rtl_hw_start_8168cp_3(ioaddr, pdev);
3232 break;
3233
3234 case RTL_GIGA_MAC_VER_25:
3235 case RTL_GIGA_MAC_VER_26:
3236 case RTL_GIGA_MAC_VER_27:
3237 rtl_hw_start_8168d(ioaddr, pdev);
3238 break;
3239
3240 default:
3241 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3242 dev->name, tp->mac_version);
3243 break;
3244 }
3245
3246 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3247
3248 RTL_W8(Cfg9346, Cfg9346_Lock);
3249
3250 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3251
3252 RTL_W16(IntrMask, tp->intr_event);
3253 }
3254
3255 #define R810X_CPCMD_QUIRK_MASK (\
3256 EnableBist | \
3257 Mac_dbgo_oe | \
3258 Force_half_dup | \
3259 Force_rxflow_en | \
3260 Force_txflow_en | \
3261 Cxpl_dbg_sel | \
3262 ASF | \
3263 PktCntrDisable | \
3264 PCIDAC | \
3265 PCIMulRW)
3266
3267 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3268 {
3269 static const struct ephy_info e_info_8102e_1[] = {
3270 { 0x01, 0, 0x6e65 },
3271 { 0x02, 0, 0x091f },
3272 { 0x03, 0, 0xc2f9 },
3273 { 0x06, 0, 0xafb5 },
3274 { 0x07, 0, 0x0e00 },
3275 { 0x19, 0, 0xec80 },
3276 { 0x01, 0, 0x2e65 },
3277 { 0x01, 0, 0x6e65 }
3278 };
3279 u8 cfg1;
3280
3281 rtl_csi_access_enable(ioaddr);
3282
3283 RTL_W8(DBG_REG, FIX_NAK_1);
3284
3285 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3286
3287 RTL_W8(Config1,
3288 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3289 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3290
3291 cfg1 = RTL_R8(Config1);
3292 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3293 RTL_W8(Config1, cfg1 & ~LEDS0);
3294
3295 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3296
3297 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3298 }
3299
3300 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3301 {
3302 rtl_csi_access_enable(ioaddr);
3303
3304 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3305
3306 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3307 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3308
3309 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3310 }
3311
3312 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3313 {
3314 rtl_hw_start_8102e_2(ioaddr, pdev);
3315
3316 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3317 }
3318
3319 static void rtl_hw_start_8101(struct net_device *dev)
3320 {
3321 struct rtl8169_private *tp = netdev_priv(dev);
3322 void __iomem *ioaddr = tp->mmio_addr;
3323 struct pci_dev *pdev = tp->pci_dev;
3324
3325 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3326 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3327 int cap = tp->pcie_cap;
3328
3329 if (cap) {
3330 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3331 PCI_EXP_DEVCTL_NOSNOOP_EN);
3332 }
3333 }
3334
3335 switch (tp->mac_version) {
3336 case RTL_GIGA_MAC_VER_07:
3337 rtl_hw_start_8102e_1(ioaddr, pdev);
3338 break;
3339
3340 case RTL_GIGA_MAC_VER_08:
3341 rtl_hw_start_8102e_3(ioaddr, pdev);
3342 break;
3343
3344 case RTL_GIGA_MAC_VER_09:
3345 rtl_hw_start_8102e_2(ioaddr, pdev);
3346 break;
3347 }
3348
3349 RTL_W8(Cfg9346, Cfg9346_Unlock);
3350
3351 RTL_W8(MaxTxPacketSize, TxPacketMax);
3352
3353 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3354
3355 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3356
3357 RTL_W16(CPlusCmd, tp->cp_cmd);
3358
3359 RTL_W16(IntrMitigate, 0x0000);
3360
3361 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3362
3363 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3364 rtl_set_rx_tx_config_registers(tp);
3365
3366 RTL_W8(Cfg9346, Cfg9346_Lock);
3367
3368 RTL_R8(IntrMask);
3369
3370 rtl_set_rx_mode(dev);
3371
3372 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3373
3374 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3375
3376 RTL_W16(IntrMask, tp->intr_event);
3377 }
3378
3379 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3380 {
3381 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3382 return -EINVAL;
3383
3384 dev->mtu = new_mtu;
3385 return 0;
3386 }
3387
3388 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3389 {
3390 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3391 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3392 }
3393
3394 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3395 void **data_buff, struct RxDesc *desc)
3396 {
3397 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
3398 DMA_FROM_DEVICE);
3399
3400 kfree(*data_buff);
3401 *data_buff = NULL;
3402 rtl8169_make_unusable_by_asic(desc);
3403 }
3404
3405 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3406 {
3407 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3408
3409 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3410 }
3411
3412 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3413 u32 rx_buf_sz)
3414 {
3415 desc->addr = cpu_to_le64(mapping);
3416 wmb();
3417 rtl8169_mark_to_asic(desc, rx_buf_sz);
3418 }
3419
3420 static inline void *rtl8169_align(void *data)
3421 {
3422 return (void *)ALIGN((long)data, 16);
3423 }
3424
3425 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3426 struct RxDesc *desc)
3427 {
3428 void *data;
3429 dma_addr_t mapping;
3430 struct device *d = &tp->pci_dev->dev;
3431 struct net_device *dev = tp->dev;
3432 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
3433
3434 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
3435 if (!data)
3436 return NULL;
3437
3438 if (rtl8169_align(data) != data) {
3439 kfree(data);
3440 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
3441 if (!data)
3442 return NULL;
3443 }
3444
3445 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
3446 DMA_FROM_DEVICE);
3447 if (unlikely(dma_mapping_error(d, mapping))) {
3448 if (net_ratelimit())
3449 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3450 goto err_out;
3451 }
3452
3453 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
3454 return data;
3455
3456 err_out:
3457 kfree(data);
3458 return NULL;
3459 }
3460
3461 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3462 {
3463 unsigned int i;
3464
3465 for (i = 0; i < NUM_RX_DESC; i++) {
3466 if (tp->Rx_databuff[i]) {
3467 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
3468 tp->RxDescArray + i);
3469 }
3470 }
3471 }
3472
3473 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3474 {
3475 desc->opts1 |= cpu_to_le32(RingEnd);
3476 }
3477
3478 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3479 {
3480 unsigned int i;
3481
3482 for (i = 0; i < NUM_RX_DESC; i++) {
3483 void *data;
3484
3485 if (tp->Rx_databuff[i])
3486 continue;
3487
3488 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3489 if (!data) {
3490 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
3491 goto err_out;
3492 }
3493 tp->Rx_databuff[i] = data;
3494 }
3495
3496 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3497 return 0;
3498
3499 err_out:
3500 rtl8169_rx_clear(tp);
3501 return -ENOMEM;
3502 }
3503
3504 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3505 {
3506 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3507 }
3508
3509 static int rtl8169_init_ring(struct net_device *dev)
3510 {
3511 struct rtl8169_private *tp = netdev_priv(dev);
3512
3513 rtl8169_init_ring_indexes(tp);
3514
3515 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3516 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
3517
3518 return rtl8169_rx_fill(tp);
3519 }
3520
3521 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
3522 struct TxDesc *desc)
3523 {
3524 unsigned int len = tx_skb->len;
3525
3526 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
3527
3528 desc->opts1 = 0x00;
3529 desc->opts2 = 0x00;
3530 desc->addr = 0x00;
3531 tx_skb->len = 0;
3532 }
3533
3534 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3535 unsigned int n)
3536 {
3537 unsigned int i;
3538
3539 for (i = 0; i < n; i++) {
3540 unsigned int entry = (start + i) % NUM_TX_DESC;
3541 struct ring_info *tx_skb = tp->tx_skb + entry;
3542 unsigned int len = tx_skb->len;
3543
3544 if (len) {
3545 struct sk_buff *skb = tx_skb->skb;
3546
3547 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
3548 tp->TxDescArray + entry);
3549 if (skb) {
3550 tp->dev->stats.tx_dropped++;
3551 dev_kfree_skb(skb);
3552 tx_skb->skb = NULL;
3553 }
3554 }
3555 }
3556 }
3557
3558 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3559 {
3560 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3561 tp->cur_tx = tp->dirty_tx = 0;
3562 }
3563
3564 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3565 {
3566 struct rtl8169_private *tp = netdev_priv(dev);
3567
3568 PREPARE_DELAYED_WORK(&tp->task, task);
3569 schedule_delayed_work(&tp->task, 4);
3570 }
3571
3572 static void rtl8169_wait_for_quiescence(struct net_device *dev)
3573 {
3574 struct rtl8169_private *tp = netdev_priv(dev);
3575 void __iomem *ioaddr = tp->mmio_addr;
3576
3577 synchronize_irq(dev->irq);
3578
3579 /* Wait for any pending NAPI task to complete */
3580 napi_disable(&tp->napi);
3581
3582 rtl8169_irq_mask_and_ack(ioaddr);
3583
3584 tp->intr_mask = 0xffff;
3585 RTL_W16(IntrMask, tp->intr_event);
3586 napi_enable(&tp->napi);
3587 }
3588
3589 static void rtl8169_reinit_task(struct work_struct *work)
3590 {
3591 struct rtl8169_private *tp =
3592 container_of(work, struct rtl8169_private, task.work);
3593 struct net_device *dev = tp->dev;
3594 int ret;
3595
3596 rtnl_lock();
3597
3598 if (!netif_running(dev))
3599 goto out_unlock;
3600
3601 rtl8169_wait_for_quiescence(dev);
3602 rtl8169_close(dev);
3603
3604 ret = rtl8169_open(dev);
3605 if (unlikely(ret < 0)) {
3606 if (net_ratelimit())
3607 netif_err(tp, drv, dev,
3608 "reinit failure (status = %d). Rescheduling\n",
3609 ret);
3610 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3611 }
3612
3613 out_unlock:
3614 rtnl_unlock();
3615 }
3616
3617 static void rtl8169_reset_task(struct work_struct *work)
3618 {
3619 struct rtl8169_private *tp =
3620 container_of(work, struct rtl8169_private, task.work);
3621 struct net_device *dev = tp->dev;
3622
3623 rtnl_lock();
3624
3625 if (!netif_running(dev))
3626 goto out_unlock;
3627
3628 rtl8169_wait_for_quiescence(dev);
3629
3630 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3631 rtl8169_tx_clear(tp);
3632
3633 if (tp->dirty_rx == tp->cur_rx) {
3634 rtl8169_init_ring_indexes(tp);
3635 rtl_hw_start(dev);
3636 netif_wake_queue(dev);
3637 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3638 } else {
3639 if (net_ratelimit())
3640 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
3641 rtl8169_schedule_work(dev, rtl8169_reset_task);
3642 }
3643
3644 out_unlock:
3645 rtnl_unlock();
3646 }
3647
3648 static void rtl8169_tx_timeout(struct net_device *dev)
3649 {
3650 struct rtl8169_private *tp = netdev_priv(dev);
3651
3652 rtl8169_hw_reset(tp->mmio_addr);
3653
3654 /* Let's wait a bit while any (async) irq lands on */
3655 rtl8169_schedule_work(dev, rtl8169_reset_task);
3656 }
3657
3658 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3659 u32 opts1)
3660 {
3661 struct skb_shared_info *info = skb_shinfo(skb);
3662 unsigned int cur_frag, entry;
3663 struct TxDesc * uninitialized_var(txd);
3664 struct device *d = &tp->pci_dev->dev;
3665
3666 entry = tp->cur_tx;
3667 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3668 skb_frag_t *frag = info->frags + cur_frag;
3669 dma_addr_t mapping;
3670 u32 status, len;
3671 void *addr;
3672
3673 entry = (entry + 1) % NUM_TX_DESC;
3674
3675 txd = tp->TxDescArray + entry;
3676 len = frag->size;
3677 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3678 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
3679 if (unlikely(dma_mapping_error(d, mapping))) {
3680 if (net_ratelimit())
3681 netif_err(tp, drv, tp->dev,
3682 "Failed to map TX fragments DMA!\n");
3683 goto err_out;
3684 }
3685
3686 /* anti gcc 2.95.3 bugware (sic) */
3687 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3688
3689 txd->opts1 = cpu_to_le32(status);
3690 txd->addr = cpu_to_le64(mapping);
3691
3692 tp->tx_skb[entry].len = len;
3693 }
3694
3695 if (cur_frag) {
3696 tp->tx_skb[entry].skb = skb;
3697 txd->opts1 |= cpu_to_le32(LastFrag);
3698 }
3699
3700 return cur_frag;
3701
3702 err_out:
3703 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
3704 return -EIO;
3705 }
3706
3707 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3708 {
3709 if (dev->features & NETIF_F_TSO) {
3710 u32 mss = skb_shinfo(skb)->gso_size;
3711
3712 if (mss)
3713 return LargeSend | ((mss & MSSMask) << MSSShift);
3714 }
3715 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3716 const struct iphdr *ip = ip_hdr(skb);
3717
3718 if (ip->protocol == IPPROTO_TCP)
3719 return IPCS | TCPCS;
3720 else if (ip->protocol == IPPROTO_UDP)
3721 return IPCS | UDPCS;
3722 WARN_ON(1); /* we need a WARN() */
3723 }
3724 return 0;
3725 }
3726
3727 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
3728 struct net_device *dev)
3729 {
3730 struct rtl8169_private *tp = netdev_priv(dev);
3731 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
3732 struct TxDesc *txd = tp->TxDescArray + entry;
3733 void __iomem *ioaddr = tp->mmio_addr;
3734 struct device *d = &tp->pci_dev->dev;
3735 dma_addr_t mapping;
3736 u32 status, len;
3737 u32 opts1;
3738 int frags;
3739
3740 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3741 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3742 goto err_stop_0;
3743 }
3744
3745 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3746 goto err_stop_0;
3747
3748 len = skb_headlen(skb);
3749 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
3750 if (unlikely(dma_mapping_error(d, mapping))) {
3751 if (net_ratelimit())
3752 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3753 goto err_dma_0;
3754 }
3755
3756 tp->tx_skb[entry].len = len;
3757 txd->addr = cpu_to_le64(mapping);
3758 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3759
3760 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3761
3762 frags = rtl8169_xmit_frags(tp, skb, opts1);
3763 if (frags < 0)
3764 goto err_dma_1;
3765 else if (frags)
3766 opts1 |= FirstFrag;
3767 else {
3768 opts1 |= FirstFrag | LastFrag;
3769 tp->tx_skb[entry].skb = skb;
3770 }
3771
3772 wmb();
3773
3774 /* anti gcc 2.95.3 bugware (sic) */
3775 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3776 txd->opts1 = cpu_to_le32(status);
3777
3778 tp->cur_tx += frags + 1;
3779
3780 wmb();
3781
3782 RTL_W8(TxPoll, NPQ); /* set polling bit */
3783
3784 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3785 netif_stop_queue(dev);
3786 smp_rmb();
3787 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3788 netif_wake_queue(dev);
3789 }
3790
3791 return NETDEV_TX_OK;
3792
3793 err_dma_1:
3794 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3795 err_dma_0:
3796 dev_kfree_skb(skb);
3797 dev->stats.tx_dropped++;
3798 return NETDEV_TX_OK;
3799
3800 err_stop_0:
3801 netif_stop_queue(dev);
3802 dev->stats.tx_dropped++;
3803 return NETDEV_TX_BUSY;
3804 }
3805
3806 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3807 {
3808 struct rtl8169_private *tp = netdev_priv(dev);
3809 struct pci_dev *pdev = tp->pci_dev;
3810 void __iomem *ioaddr = tp->mmio_addr;
3811 u16 pci_status, pci_cmd;
3812
3813 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3814 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3815
3816 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
3817 pci_cmd, pci_status);
3818
3819 /*
3820 * The recovery sequence below admits a very elaborated explanation:
3821 * - it seems to work;
3822 * - I did not see what else could be done;
3823 * - it makes iop3xx happy.
3824 *
3825 * Feel free to adjust to your needs.
3826 */
3827 if (pdev->broken_parity_status)
3828 pci_cmd &= ~PCI_COMMAND_PARITY;
3829 else
3830 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3831
3832 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3833
3834 pci_write_config_word(pdev, PCI_STATUS,
3835 pci_status & (PCI_STATUS_DETECTED_PARITY |
3836 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3837 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3838
3839 /* The infamous DAC f*ckup only happens at boot time */
3840 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3841 netif_info(tp, intr, dev, "disabling PCI DAC\n");
3842 tp->cp_cmd &= ~PCIDAC;
3843 RTL_W16(CPlusCmd, tp->cp_cmd);
3844 dev->features &= ~NETIF_F_HIGHDMA;
3845 }
3846
3847 rtl8169_hw_reset(ioaddr);
3848
3849 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3850 }
3851
3852 static void rtl8169_tx_interrupt(struct net_device *dev,
3853 struct rtl8169_private *tp,
3854 void __iomem *ioaddr)
3855 {
3856 unsigned int dirty_tx, tx_left;
3857
3858 dirty_tx = tp->dirty_tx;
3859 smp_rmb();
3860 tx_left = tp->cur_tx - dirty_tx;
3861
3862 while (tx_left > 0) {
3863 unsigned int entry = dirty_tx % NUM_TX_DESC;
3864 struct ring_info *tx_skb = tp->tx_skb + entry;
3865 u32 status;
3866
3867 rmb();
3868 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3869 if (status & DescOwn)
3870 break;
3871
3872 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
3873 tp->TxDescArray + entry);
3874 if (status & LastFrag) {
3875 dev->stats.tx_packets++;
3876 dev->stats.tx_bytes += tx_skb->skb->len;
3877 dev_kfree_skb(tx_skb->skb);
3878 tx_skb->skb = NULL;
3879 }
3880 dirty_tx++;
3881 tx_left--;
3882 }
3883
3884 if (tp->dirty_tx != dirty_tx) {
3885 tp->dirty_tx = dirty_tx;
3886 smp_wmb();
3887 if (netif_queue_stopped(dev) &&
3888 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3889 netif_wake_queue(dev);
3890 }
3891 /*
3892 * 8168 hack: TxPoll requests are lost when the Tx packets are
3893 * too close. Let's kick an extra TxPoll request when a burst
3894 * of start_xmit activity is detected (if it is not detected,
3895 * it is slow enough). -- FR
3896 */
3897 smp_rmb();
3898 if (tp->cur_tx != dirty_tx)
3899 RTL_W8(TxPoll, NPQ);
3900 }
3901 }
3902
3903 static inline int rtl8169_fragmented_frame(u32 status)
3904 {
3905 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3906 }
3907
3908 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
3909 {
3910 u32 status = opts1 & RxProtoMask;
3911
3912 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3913 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
3914 skb->ip_summed = CHECKSUM_UNNECESSARY;
3915 else
3916 skb_checksum_none_assert(skb);
3917 }
3918
3919 static struct sk_buff *rtl8169_try_rx_copy(void *data,
3920 struct rtl8169_private *tp,
3921 int pkt_size,
3922 dma_addr_t addr)
3923 {
3924 struct sk_buff *skb;
3925 struct device *d = &tp->pci_dev->dev;
3926
3927 data = rtl8169_align(data);
3928 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
3929 prefetch(data);
3930 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
3931 if (skb)
3932 memcpy(skb->data, data, pkt_size);
3933 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
3934
3935 return skb;
3936 }
3937
3938 /*
3939 * Warning : rtl8169_rx_interrupt() might be called :
3940 * 1) from NAPI (softirq) context
3941 * (polling = 1 : we should call netif_receive_skb())
3942 * 2) from process context (rtl8169_reset_task())
3943 * (polling = 0 : we must call netif_rx() instead)
3944 */
3945 static int rtl8169_rx_interrupt(struct net_device *dev,
3946 struct rtl8169_private *tp,
3947 void __iomem *ioaddr, u32 budget)
3948 {
3949 unsigned int cur_rx, rx_left;
3950 unsigned int count;
3951 int polling = (budget != ~(u32)0) ? 1 : 0;
3952
3953 cur_rx = tp->cur_rx;
3954 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3955 rx_left = min(rx_left, budget);
3956
3957 for (; rx_left > 0; rx_left--, cur_rx++) {
3958 unsigned int entry = cur_rx % NUM_RX_DESC;
3959 struct RxDesc *desc = tp->RxDescArray + entry;
3960 u32 status;
3961
3962 rmb();
3963 status = le32_to_cpu(desc->opts1);
3964
3965 if (status & DescOwn)
3966 break;
3967 if (unlikely(status & RxRES)) {
3968 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
3969 status);
3970 dev->stats.rx_errors++;
3971 if (status & (RxRWT | RxRUNT))
3972 dev->stats.rx_length_errors++;
3973 if (status & RxCRC)
3974 dev->stats.rx_crc_errors++;
3975 if (status & RxFOVF) {
3976 rtl8169_schedule_work(dev, rtl8169_reset_task);
3977 dev->stats.rx_fifo_errors++;
3978 }
3979 rtl8169_mark_to_asic(desc, rx_buf_sz);
3980 } else {
3981 struct sk_buff *skb;
3982 dma_addr_t addr = le64_to_cpu(desc->addr);
3983 int pkt_size = (status & 0x00001FFF) - 4;
3984
3985 /*
3986 * The driver does not support incoming fragmented
3987 * frames. They are seen as a symptom of over-mtu
3988 * sized frames.
3989 */
3990 if (unlikely(rtl8169_fragmented_frame(status))) {
3991 dev->stats.rx_dropped++;
3992 dev->stats.rx_length_errors++;
3993 rtl8169_mark_to_asic(desc, rx_buf_sz);
3994 continue;
3995 }
3996
3997 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
3998 tp, pkt_size, addr);
3999 rtl8169_mark_to_asic(desc, rx_buf_sz);
4000 if (!skb) {
4001 dev->stats.rx_dropped++;
4002 continue;
4003 }
4004
4005 rtl8169_rx_csum(skb, status);
4006 skb_put(skb, pkt_size);
4007 skb->protocol = eth_type_trans(skb, dev);
4008
4009 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4010 if (likely(polling))
4011 napi_gro_receive(&tp->napi, skb);
4012 else
4013 netif_rx(skb);
4014 }
4015
4016 dev->stats.rx_bytes += pkt_size;
4017 dev->stats.rx_packets++;
4018 }
4019
4020 /* Work around for AMD plateform. */
4021 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4022 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4023 desc->opts2 = 0;
4024 cur_rx++;
4025 }
4026 }
4027
4028 count = cur_rx - tp->cur_rx;
4029 tp->cur_rx = cur_rx;
4030
4031 tp->dirty_rx += count;
4032
4033 return count;
4034 }
4035
4036 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4037 {
4038 struct net_device *dev = dev_instance;
4039 struct rtl8169_private *tp = netdev_priv(dev);
4040 void __iomem *ioaddr = tp->mmio_addr;
4041 int handled = 0;
4042 int status;
4043
4044 /* loop handling interrupts until we have no new ones or
4045 * we hit a invalid/hotplug case.
4046 */
4047 status = RTL_R16(IntrStatus);
4048 while (status && status != 0xffff) {
4049 handled = 1;
4050
4051 /* Handle all of the error cases first. These will reset
4052 * the chip, so just exit the loop.
4053 */
4054 if (unlikely(!netif_running(dev))) {
4055 rtl8169_asic_down(ioaddr);
4056 break;
4057 }
4058
4059 /* Work around for rx fifo overflow */
4060 if (unlikely(status & RxFIFOOver) &&
4061 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4062 netif_stop_queue(dev);
4063 rtl8169_tx_timeout(dev);
4064 break;
4065 }
4066
4067 if (unlikely(status & SYSErr)) {
4068 rtl8169_pcierr_interrupt(dev);
4069 break;
4070 }
4071
4072 if (status & LinkChg)
4073 __rtl8169_check_link_status(dev, tp, ioaddr, true);
4074
4075 /* We need to see the lastest version of tp->intr_mask to
4076 * avoid ignoring an MSI interrupt and having to wait for
4077 * another event which may never come.
4078 */
4079 smp_rmb();
4080 if (status & tp->intr_mask & tp->napi_event) {
4081 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4082 tp->intr_mask = ~tp->napi_event;
4083
4084 if (likely(napi_schedule_prep(&tp->napi)))
4085 __napi_schedule(&tp->napi);
4086 else
4087 netif_info(tp, intr, dev,
4088 "interrupt %04x in poll\n", status);
4089 }
4090
4091 /* We only get a new MSI interrupt when all active irq
4092 * sources on the chip have been acknowledged. So, ack
4093 * everything we've seen and check if new sources have become
4094 * active to avoid blocking all interrupts from the chip.
4095 */
4096 RTL_W16(IntrStatus,
4097 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4098 status = RTL_R16(IntrStatus);
4099 }
4100
4101 return IRQ_RETVAL(handled);
4102 }
4103
4104 static int rtl8169_poll(struct napi_struct *napi, int budget)
4105 {
4106 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4107 struct net_device *dev = tp->dev;
4108 void __iomem *ioaddr = tp->mmio_addr;
4109 int work_done;
4110
4111 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4112 rtl8169_tx_interrupt(dev, tp, ioaddr);
4113
4114 if (work_done < budget) {
4115 napi_complete(napi);
4116
4117 /* We need for force the visibility of tp->intr_mask
4118 * for other CPUs, as we can loose an MSI interrupt
4119 * and potentially wait for a retransmit timeout if we don't.
4120 * The posted write to IntrMask is safe, as it will
4121 * eventually make it to the chip and we won't loose anything
4122 * until it does.
4123 */
4124 tp->intr_mask = 0xffff;
4125 wmb();
4126 RTL_W16(IntrMask, tp->intr_event);
4127 }
4128
4129 return work_done;
4130 }
4131
4132 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4133 {
4134 struct rtl8169_private *tp = netdev_priv(dev);
4135
4136 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4137 return;
4138
4139 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4140 RTL_W32(RxMissed, 0);
4141 }
4142
4143 static void rtl8169_down(struct net_device *dev)
4144 {
4145 struct rtl8169_private *tp = netdev_priv(dev);
4146 void __iomem *ioaddr = tp->mmio_addr;
4147
4148 rtl8169_delete_timer(dev);
4149
4150 netif_stop_queue(dev);
4151
4152 napi_disable(&tp->napi);
4153
4154 spin_lock_irq(&tp->lock);
4155
4156 rtl8169_asic_down(ioaddr);
4157 /*
4158 * At this point device interrupts can not be enabled in any function,
4159 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4160 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4161 */
4162 rtl8169_rx_missed(dev, ioaddr);
4163
4164 spin_unlock_irq(&tp->lock);
4165
4166 synchronize_irq(dev->irq);
4167
4168 /* Give a racing hard_start_xmit a few cycles to complete. */
4169 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4170
4171 rtl8169_tx_clear(tp);
4172
4173 rtl8169_rx_clear(tp);
4174 }
4175
4176 static int rtl8169_close(struct net_device *dev)
4177 {
4178 struct rtl8169_private *tp = netdev_priv(dev);
4179 struct pci_dev *pdev = tp->pci_dev;
4180
4181 pm_runtime_get_sync(&pdev->dev);
4182
4183 /* update counters before going down */
4184 rtl8169_update_counters(dev);
4185
4186 rtl8169_down(dev);
4187
4188 free_irq(dev->irq, dev);
4189
4190 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4191 tp->RxPhyAddr);
4192 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4193 tp->TxPhyAddr);
4194 tp->TxDescArray = NULL;
4195 tp->RxDescArray = NULL;
4196
4197 pm_runtime_put_sync(&pdev->dev);
4198
4199 return 0;
4200 }
4201
4202 static void rtl_set_rx_mode(struct net_device *dev)
4203 {
4204 struct rtl8169_private *tp = netdev_priv(dev);
4205 void __iomem *ioaddr = tp->mmio_addr;
4206 unsigned long flags;
4207 u32 mc_filter[2]; /* Multicast hash filter */
4208 int rx_mode;
4209 u32 tmp = 0;
4210
4211 if (dev->flags & IFF_PROMISC) {
4212 /* Unconditionally log net taps. */
4213 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4214 rx_mode =
4215 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4216 AcceptAllPhys;
4217 mc_filter[1] = mc_filter[0] = 0xffffffff;
4218 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4219 (dev->flags & IFF_ALLMULTI)) {
4220 /* Too many to filter perfectly -- accept all multicasts. */
4221 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4222 mc_filter[1] = mc_filter[0] = 0xffffffff;
4223 } else {
4224 struct netdev_hw_addr *ha;
4225
4226 rx_mode = AcceptBroadcast | AcceptMyPhys;
4227 mc_filter[1] = mc_filter[0] = 0;
4228 netdev_for_each_mc_addr(ha, dev) {
4229 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4230 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4231 rx_mode |= AcceptMulticast;
4232 }
4233 }
4234
4235 spin_lock_irqsave(&tp->lock, flags);
4236
4237 tmp = rtl8169_rx_config | rx_mode |
4238 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4239
4240 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4241 u32 data = mc_filter[0];
4242
4243 mc_filter[0] = swab32(mc_filter[1]);
4244 mc_filter[1] = swab32(data);
4245 }
4246
4247 RTL_W32(MAR0 + 4, mc_filter[1]);
4248 RTL_W32(MAR0 + 0, mc_filter[0]);
4249
4250 RTL_W32(RxConfig, tmp);
4251
4252 spin_unlock_irqrestore(&tp->lock, flags);
4253 }
4254
4255 /**
4256 * rtl8169_get_stats - Get rtl8169 read/write statistics
4257 * @dev: The Ethernet Device to get statistics for
4258 *
4259 * Get TX/RX statistics for rtl8169
4260 */
4261 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4262 {
4263 struct rtl8169_private *tp = netdev_priv(dev);
4264 void __iomem *ioaddr = tp->mmio_addr;
4265 unsigned long flags;
4266
4267 if (netif_running(dev)) {
4268 spin_lock_irqsave(&tp->lock, flags);
4269 rtl8169_rx_missed(dev, ioaddr);
4270 spin_unlock_irqrestore(&tp->lock, flags);
4271 }
4272
4273 return &dev->stats;
4274 }
4275
4276 static void rtl8169_net_suspend(struct net_device *dev)
4277 {
4278 if (!netif_running(dev))
4279 return;
4280
4281 netif_device_detach(dev);
4282 netif_stop_queue(dev);
4283 }
4284
4285 #ifdef CONFIG_PM
4286
4287 static int rtl8169_suspend(struct device *device)
4288 {
4289 struct pci_dev *pdev = to_pci_dev(device);
4290 struct net_device *dev = pci_get_drvdata(pdev);
4291
4292 rtl8169_net_suspend(dev);
4293
4294 return 0;
4295 }
4296
4297 static void __rtl8169_resume(struct net_device *dev)
4298 {
4299 netif_device_attach(dev);
4300 rtl8169_schedule_work(dev, rtl8169_reset_task);
4301 }
4302
4303 static int rtl8169_resume(struct device *device)
4304 {
4305 struct pci_dev *pdev = to_pci_dev(device);
4306 struct net_device *dev = pci_get_drvdata(pdev);
4307 struct rtl8169_private *tp = netdev_priv(dev);
4308
4309 rtl8169_init_phy(dev, tp);
4310
4311 if (netif_running(dev))
4312 __rtl8169_resume(dev);
4313
4314 return 0;
4315 }
4316
4317 static int rtl8169_runtime_suspend(struct device *device)
4318 {
4319 struct pci_dev *pdev = to_pci_dev(device);
4320 struct net_device *dev = pci_get_drvdata(pdev);
4321 struct rtl8169_private *tp = netdev_priv(dev);
4322
4323 if (!tp->TxDescArray)
4324 return 0;
4325
4326 spin_lock_irq(&tp->lock);
4327 tp->saved_wolopts = __rtl8169_get_wol(tp);
4328 __rtl8169_set_wol(tp, WAKE_ANY);
4329 spin_unlock_irq(&tp->lock);
4330
4331 rtl8169_net_suspend(dev);
4332
4333 return 0;
4334 }
4335
4336 static int rtl8169_runtime_resume(struct device *device)
4337 {
4338 struct pci_dev *pdev = to_pci_dev(device);
4339 struct net_device *dev = pci_get_drvdata(pdev);
4340 struct rtl8169_private *tp = netdev_priv(dev);
4341
4342 if (!tp->TxDescArray)
4343 return 0;
4344
4345 spin_lock_irq(&tp->lock);
4346 __rtl8169_set_wol(tp, tp->saved_wolopts);
4347 tp->saved_wolopts = 0;
4348 spin_unlock_irq(&tp->lock);
4349
4350 rtl8169_init_phy(dev, tp);
4351
4352 __rtl8169_resume(dev);
4353
4354 return 0;
4355 }
4356
4357 static int rtl8169_runtime_idle(struct device *device)
4358 {
4359 struct pci_dev *pdev = to_pci_dev(device);
4360 struct net_device *dev = pci_get_drvdata(pdev);
4361 struct rtl8169_private *tp = netdev_priv(dev);
4362
4363 return tp->TxDescArray ? -EBUSY : 0;
4364 }
4365
4366 static const struct dev_pm_ops rtl8169_pm_ops = {
4367 .suspend = rtl8169_suspend,
4368 .resume = rtl8169_resume,
4369 .freeze = rtl8169_suspend,
4370 .thaw = rtl8169_resume,
4371 .poweroff = rtl8169_suspend,
4372 .restore = rtl8169_resume,
4373 .runtime_suspend = rtl8169_runtime_suspend,
4374 .runtime_resume = rtl8169_runtime_resume,
4375 .runtime_idle = rtl8169_runtime_idle,
4376 };
4377
4378 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4379
4380 #else /* !CONFIG_PM */
4381
4382 #define RTL8169_PM_OPS NULL
4383
4384 #endif /* !CONFIG_PM */
4385
4386 static void rtl_shutdown(struct pci_dev *pdev)
4387 {
4388 struct net_device *dev = pci_get_drvdata(pdev);
4389 struct rtl8169_private *tp = netdev_priv(dev);
4390 void __iomem *ioaddr = tp->mmio_addr;
4391
4392 rtl8169_net_suspend(dev);
4393
4394 /* restore original MAC address */
4395 rtl_rar_set(tp, dev->perm_addr);
4396
4397 spin_lock_irq(&tp->lock);
4398
4399 rtl8169_asic_down(ioaddr);
4400
4401 spin_unlock_irq(&tp->lock);
4402
4403 if (system_state == SYSTEM_POWER_OFF) {
4404 /* WoL fails with some 8168 when the receiver is disabled. */
4405 if (tp->features & RTL_FEATURE_WOL) {
4406 pci_clear_master(pdev);
4407
4408 RTL_W8(ChipCmd, CmdRxEnb);
4409 /* PCI commit */
4410 RTL_R8(ChipCmd);
4411 }
4412
4413 pci_wake_from_d3(pdev, true);
4414 pci_set_power_state(pdev, PCI_D3hot);
4415 }
4416 }
4417
4418 static struct pci_driver rtl8169_pci_driver = {
4419 .name = MODULENAME,
4420 .id_table = rtl8169_pci_tbl,
4421 .probe = rtl8169_init_one,
4422 .remove = __devexit_p(rtl8169_remove_one),
4423 .shutdown = rtl_shutdown,
4424 .driver.pm = RTL8169_PM_OPS,
4425 };
4426
4427 static int __init rtl8169_init_module(void)
4428 {
4429 return pci_register_driver(&rtl8169_pci_driver);
4430 }
4431
4432 static void __exit rtl8169_cleanup_module(void)
4433 {
4434 pci_unregister_driver(&rtl8169_pci_driver);
4435 }
4436
4437 module_init(rtl8169_init_module);
4438 module_exit(rtl8169_cleanup_module);
Linux 2.6 libata-dev (mirror)