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ALSA: hda - Add probe_mask quirk for Medion MD96630
[linux-2.6/libata-dev.git] / sound / pci / hda / hda_intel.c
blob6462d758e641817c4e27abb95bb74fbcc390f2ea
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int single_cmd;
62 static int enable_msi;
63
64 module_param_array(index, int, NULL, 0444);
65 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
66 module_param_array(id, charp, NULL, 0444);
67 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
68 module_param_array(enable, bool, NULL, 0444);
69 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
70 module_param_array(model, charp, NULL, 0444);
71 MODULE_PARM_DESC(model, "Use the given board model.");
72 module_param_array(position_fix, int, NULL, 0444);
73 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
74 "(0 = auto, 1 = none, 2 = POSBUF).");
75 module_param_array(bdl_pos_adj, int, NULL, 0644);
76 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
77 module_param_array(probe_mask, int, NULL, 0444);
78 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
79 module_param(single_cmd, bool, 0444);
80 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
81 "(for debugging only).");
82 module_param(enable_msi, int, 0444);
83 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
84
85 #ifdef CONFIG_SND_HDA_POWER_SAVE
86 /* power_save option is defined in hda_codec.c */
87
88 /* reset the HD-audio controller in power save mode.
89 * this may give more power-saving, but will take longer time to
90 * wake up.
91 */
92 static int power_save_controller = 1;
93 module_param(power_save_controller, bool, 0644);
94 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
95 #endif
96
97 MODULE_LICENSE("GPL");
98 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
99 "{Intel, ICH6M},"
100 "{Intel, ICH7},"
101 "{Intel, ESB2},"
102 "{Intel, ICH8},"
103 "{Intel, ICH9},"
104 "{Intel, ICH10},"
105 "{Intel, PCH},"
106 "{Intel, SCH},"
107 "{ATI, SB450},"
108 "{ATI, SB600},"
109 "{ATI, RS600},"
110 "{ATI, RS690},"
111 "{ATI, RS780},"
112 "{ATI, R600},"
113 "{ATI, RV630},"
114 "{ATI, RV610},"
115 "{ATI, RV670},"
116 "{ATI, RV635},"
117 "{ATI, RV620},"
118 "{ATI, RV770},"
119 "{VIA, VT8251},"
120 "{VIA, VT8237A},"
121 "{SiS, SIS966},"
122 "{ULI, M5461}}");
123 MODULE_DESCRIPTION("Intel HDA driver");
124
125 #define SFX "hda-intel: "
126
127
128 /*
129 * registers
130 */
131 #define ICH6_REG_GCAP 0x00
132 #define ICH6_REG_VMIN 0x02
133 #define ICH6_REG_VMAJ 0x03
134 #define ICH6_REG_OUTPAY 0x04
135 #define ICH6_REG_INPAY 0x06
136 #define ICH6_REG_GCTL 0x08
137 #define ICH6_REG_WAKEEN 0x0c
138 #define ICH6_REG_STATESTS 0x0e
139 #define ICH6_REG_GSTS 0x10
140 #define ICH6_REG_INTCTL 0x20
141 #define ICH6_REG_INTSTS 0x24
142 #define ICH6_REG_WALCLK 0x30
143 #define ICH6_REG_SYNC 0x34
144 #define ICH6_REG_CORBLBASE 0x40
145 #define ICH6_REG_CORBUBASE 0x44
146 #define ICH6_REG_CORBWP 0x48
147 #define ICH6_REG_CORBRP 0x4A
148 #define ICH6_REG_CORBCTL 0x4c
149 #define ICH6_REG_CORBSTS 0x4d
150 #define ICH6_REG_CORBSIZE 0x4e
151
152 #define ICH6_REG_RIRBLBASE 0x50
153 #define ICH6_REG_RIRBUBASE 0x54
154 #define ICH6_REG_RIRBWP 0x58
155 #define ICH6_REG_RINTCNT 0x5a
156 #define ICH6_REG_RIRBCTL 0x5c
157 #define ICH6_REG_RIRBSTS 0x5d
158 #define ICH6_REG_RIRBSIZE 0x5e
159
160 #define ICH6_REG_IC 0x60
161 #define ICH6_REG_IR 0x64
162 #define ICH6_REG_IRS 0x68
163 #define ICH6_IRS_VALID (1<<1)
164 #define ICH6_IRS_BUSY (1<<0)
165
166 #define ICH6_REG_DPLBASE 0x70
167 #define ICH6_REG_DPUBASE 0x74
168 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
169
170 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
171 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
172
173 /* stream register offsets from stream base */
174 #define ICH6_REG_SD_CTL 0x00
175 #define ICH6_REG_SD_STS 0x03
176 #define ICH6_REG_SD_LPIB 0x04
177 #define ICH6_REG_SD_CBL 0x08
178 #define ICH6_REG_SD_LVI 0x0c
179 #define ICH6_REG_SD_FIFOW 0x0e
180 #define ICH6_REG_SD_FIFOSIZE 0x10
181 #define ICH6_REG_SD_FORMAT 0x12
182 #define ICH6_REG_SD_BDLPL 0x18
183 #define ICH6_REG_SD_BDLPU 0x1c
184
185 /* PCI space */
186 #define ICH6_PCIREG_TCSEL 0x44
187
188 /*
189 * other constants
190 */
191
192 /* max number of SDs */
193 /* ICH, ATI and VIA have 4 playback and 4 capture */
194 #define ICH6_NUM_CAPTURE 4
195 #define ICH6_NUM_PLAYBACK 4
196
197 /* ULI has 6 playback and 5 capture */
198 #define ULI_NUM_CAPTURE 5
199 #define ULI_NUM_PLAYBACK 6
200
201 /* ATI HDMI has 1 playback and 0 capture */
202 #define ATIHDMI_NUM_CAPTURE 0
203 #define ATIHDMI_NUM_PLAYBACK 1
204
205 /* TERA has 4 playback and 3 capture */
206 #define TERA_NUM_CAPTURE 3
207 #define TERA_NUM_PLAYBACK 4
208
209 /* this number is statically defined for simplicity */
210 #define MAX_AZX_DEV 16
211
212 /* max number of fragments - we may use more if allocating more pages for BDL */
213 #define BDL_SIZE 4096
214 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
215 #define AZX_MAX_FRAG 32
216 /* max buffer size - no h/w limit, you can increase as you like */
217 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
218 /* max number of PCM devics per card */
219 #define AZX_MAX_PCMS 8
220
221 /* RIRB int mask: overrun[2], response[0] */
222 #define RIRB_INT_RESPONSE 0x01
223 #define RIRB_INT_OVERRUN 0x04
224 #define RIRB_INT_MASK 0x05
225
226 /* STATESTS int mask: S3,SD2,SD1,SD0 */
227 #define AZX_MAX_CODECS 4
228 #define STATESTS_INT_MASK 0x0f
229
230 /* SD_CTL bits */
231 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
232 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
233 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
234 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
235 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
236 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
237 #define SD_CTL_STREAM_TAG_SHIFT 20
238
239 /* SD_CTL and SD_STS */
240 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
241 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
242 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
243 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
244 SD_INT_COMPLETE)
245
246 /* SD_STS */
247 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
248
249 /* INTCTL and INTSTS */
250 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
251 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
252 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
253
254 /* GCTL unsolicited response enable bit */
255 #define ICH6_GCTL_UREN (1<<8)
256
257 /* GCTL reset bit */
258 #define ICH6_GCTL_RESET (1<<0)
259
260 /* CORB/RIRB control, read/write pointer */
261 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
262 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
263 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
264 /* below are so far hardcoded - should read registers in future */
265 #define ICH6_MAX_CORB_ENTRIES 256
266 #define ICH6_MAX_RIRB_ENTRIES 256
267
268 /* position fix mode */
269 enum {
270 POS_FIX_AUTO,
271 POS_FIX_LPIB,
272 POS_FIX_POSBUF,
273 };
274
275 /* Defines for ATI HD Audio support in SB450 south bridge */
276 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
277 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
278
279 /* Defines for Nvidia HDA support */
280 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
281 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
282 #define NVIDIA_HDA_ISTRM_COH 0x4d
283 #define NVIDIA_HDA_OSTRM_COH 0x4c
284 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
285
286 /* Defines for Intel SCH HDA snoop control */
287 #define INTEL_SCH_HDA_DEVC 0x78
288 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
289
290 /* Define IN stream 0 FIFO size offset in VIA controller */
291 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
292 /* Define VIA HD Audio Device ID*/
293 #define VIA_HDAC_DEVICE_ID 0x3288
294
295 /* HD Audio class code */
296 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
297
298 /*
299 */
300
301 struct azx_dev {
302 struct snd_dma_buffer bdl; /* BDL buffer */
303 u32 *posbuf; /* position buffer pointer */
304
305 unsigned int bufsize; /* size of the play buffer in bytes */
306 unsigned int period_bytes; /* size of the period in bytes */
307 unsigned int frags; /* number for period in the play buffer */
308 unsigned int fifo_size; /* FIFO size */
309
310 void __iomem *sd_addr; /* stream descriptor pointer */
311
312 u32 sd_int_sta_mask; /* stream int status mask */
313
314 /* pcm support */
315 struct snd_pcm_substream *substream; /* assigned substream,
316 * set in PCM open
317 */
318 unsigned int format_val; /* format value to be set in the
319 * controller and the codec
320 */
321 unsigned char stream_tag; /* assigned stream */
322 unsigned char index; /* stream index */
323
324 unsigned int opened :1;
325 unsigned int running :1;
326 unsigned int irq_pending :1;
327 unsigned int irq_ignore :1;
328 /*
329 * For VIA:
330 * A flag to ensure DMA position is 0
331 * when link position is not greater than FIFO size
332 */
333 unsigned int insufficient :1;
334 };
335
336 /* CORB/RIRB */
337 struct azx_rb {
338 u32 *buf; /* CORB/RIRB buffer
339 * Each CORB entry is 4byte, RIRB is 8byte
340 */
341 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
342 /* for RIRB */
343 unsigned short rp, wp; /* read/write pointers */
344 int cmds; /* number of pending requests */
345 u32 res; /* last read value */
346 };
347
348 struct azx {
349 struct snd_card *card;
350 struct pci_dev *pci;
351 int dev_index;
352
353 /* chip type specific */
354 int driver_type;
355 int playback_streams;
356 int playback_index_offset;
357 int capture_streams;
358 int capture_index_offset;
359 int num_streams;
360
361 /* pci resources */
362 unsigned long addr;
363 void __iomem *remap_addr;
364 int irq;
365
366 /* locks */
367 spinlock_t reg_lock;
368 struct mutex open_mutex;
369
370 /* streams (x num_streams) */
371 struct azx_dev *azx_dev;
372
373 /* PCM */
374 struct snd_pcm *pcm[AZX_MAX_PCMS];
375
376 /* HD codec */
377 unsigned short codec_mask;
378 struct hda_bus *bus;
379
380 /* CORB/RIRB */
381 struct azx_rb corb;
382 struct azx_rb rirb;
383
384 /* CORB/RIRB and position buffers */
385 struct snd_dma_buffer rb;
386 struct snd_dma_buffer posbuf;
387
388 /* flags */
389 int position_fix;
390 unsigned int running :1;
391 unsigned int initialized :1;
392 unsigned int single_cmd :1;
393 unsigned int polling_mode :1;
394 unsigned int msi :1;
395 unsigned int irq_pending_warned :1;
396 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
397 unsigned int probing :1; /* codec probing phase */
398
399 /* for debugging */
400 unsigned int last_cmd; /* last issued command (to sync) */
401
402 /* for pending irqs */
403 struct work_struct irq_pending_work;
404
405 /* reboot notifier (for mysterious hangup problem at power-down) */
406 struct notifier_block reboot_notifier;
407 };
408
409 /* driver types */
410 enum {
411 AZX_DRIVER_ICH,
412 AZX_DRIVER_SCH,
413 AZX_DRIVER_ATI,
414 AZX_DRIVER_ATIHDMI,
415 AZX_DRIVER_VIA,
416 AZX_DRIVER_SIS,
417 AZX_DRIVER_ULI,
418 AZX_DRIVER_NVIDIA,
419 AZX_DRIVER_TERA,
420 AZX_DRIVER_GENERIC,
421 AZX_NUM_DRIVERS, /* keep this as last entry */
422 };
423
424 static char *driver_short_names[] __devinitdata = {
425 [AZX_DRIVER_ICH] = "HDA Intel",
426 [AZX_DRIVER_SCH] = "HDA Intel MID",
427 [AZX_DRIVER_ATI] = "HDA ATI SB",
428 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
429 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
430 [AZX_DRIVER_SIS] = "HDA SIS966",
431 [AZX_DRIVER_ULI] = "HDA ULI M5461",
432 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
433 [AZX_DRIVER_TERA] = "HDA Teradici",
434 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
435 };
436
437 /*
438 * macros for easy use
439 */
440 #define azx_writel(chip,reg,value) \
441 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
442 #define azx_readl(chip,reg) \
443 readl((chip)->remap_addr + ICH6_REG_##reg)
444 #define azx_writew(chip,reg,value) \
445 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
446 #define azx_readw(chip,reg) \
447 readw((chip)->remap_addr + ICH6_REG_##reg)
448 #define azx_writeb(chip,reg,value) \
449 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
450 #define azx_readb(chip,reg) \
451 readb((chip)->remap_addr + ICH6_REG_##reg)
452
453 #define azx_sd_writel(dev,reg,value) \
454 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
455 #define azx_sd_readl(dev,reg) \
456 readl((dev)->sd_addr + ICH6_REG_##reg)
457 #define azx_sd_writew(dev,reg,value) \
458 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
459 #define azx_sd_readw(dev,reg) \
460 readw((dev)->sd_addr + ICH6_REG_##reg)
461 #define azx_sd_writeb(dev,reg,value) \
462 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
463 #define azx_sd_readb(dev,reg) \
464 readb((dev)->sd_addr + ICH6_REG_##reg)
465
466 /* for pcm support */
467 #define get_azx_dev(substream) (substream->runtime->private_data)
468
469 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
470
471 /*
472 * Interface for HD codec
473 */
474
475 /*
476 * CORB / RIRB interface
477 */
478 static int azx_alloc_cmd_io(struct azx *chip)
479 {
480 int err;
481
482 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
483 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
484 snd_dma_pci_data(chip->pci),
485 PAGE_SIZE, &chip->rb);
486 if (err < 0) {
487 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
488 return err;
489 }
490 return 0;
491 }
492
493 static void azx_init_cmd_io(struct azx *chip)
494 {
495 /* CORB set up */
496 chip->corb.addr = chip->rb.addr;
497 chip->corb.buf = (u32 *)chip->rb.area;
498 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
499 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
500
501 /* set the corb size to 256 entries (ULI requires explicitly) */
502 azx_writeb(chip, CORBSIZE, 0x02);
503 /* set the corb write pointer to 0 */
504 azx_writew(chip, CORBWP, 0);
505 /* reset the corb hw read pointer */
506 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
507 /* enable corb dma */
508 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
509
510 /* RIRB set up */
511 chip->rirb.addr = chip->rb.addr + 2048;
512 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
513 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
514 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
515
516 /* set the rirb size to 256 entries (ULI requires explicitly) */
517 azx_writeb(chip, RIRBSIZE, 0x02);
518 /* reset the rirb hw write pointer */
519 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
520 /* set N=1, get RIRB response interrupt for new entry */
521 azx_writew(chip, RINTCNT, 1);
522 /* enable rirb dma and response irq */
523 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
524 chip->rirb.rp = chip->rirb.cmds = 0;
525 }
526
527 static void azx_free_cmd_io(struct azx *chip)
528 {
529 /* disable ringbuffer DMAs */
530 azx_writeb(chip, RIRBCTL, 0);
531 azx_writeb(chip, CORBCTL, 0);
532 }
533
534 /* send a command */
535 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
536 {
537 struct azx *chip = bus->private_data;
538 unsigned int wp;
539
540 /* add command to corb */
541 wp = azx_readb(chip, CORBWP);
542 wp++;
543 wp %= ICH6_MAX_CORB_ENTRIES;
544
545 spin_lock_irq(&chip->reg_lock);
546 chip->rirb.cmds++;
547 chip->corb.buf[wp] = cpu_to_le32(val);
548 azx_writel(chip, CORBWP, wp);
549 spin_unlock_irq(&chip->reg_lock);
550
551 return 0;
552 }
553
554 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
555
556 /* retrieve RIRB entry - called from interrupt handler */
557 static void azx_update_rirb(struct azx *chip)
558 {
559 unsigned int rp, wp;
560 u32 res, res_ex;
561
562 wp = azx_readb(chip, RIRBWP);
563 if (wp == chip->rirb.wp)
564 return;
565 chip->rirb.wp = wp;
566
567 while (chip->rirb.rp != wp) {
568 chip->rirb.rp++;
569 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
570
571 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
572 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
573 res = le32_to_cpu(chip->rirb.buf[rp]);
574 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
575 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
576 else if (chip->rirb.cmds) {
577 chip->rirb.res = res;
578 smp_wmb();
579 chip->rirb.cmds--;
580 }
581 }
582 }
583
584 /* receive a response */
585 static unsigned int azx_rirb_get_response(struct hda_bus *bus)
586 {
587 struct azx *chip = bus->private_data;
588 unsigned long timeout;
589
590 again:
591 timeout = jiffies + msecs_to_jiffies(1000);
592 for (;;) {
593 if (chip->polling_mode) {
594 spin_lock_irq(&chip->reg_lock);
595 azx_update_rirb(chip);
596 spin_unlock_irq(&chip->reg_lock);
597 }
598 if (!chip->rirb.cmds) {
599 smp_rmb();
600 return chip->rirb.res; /* the last value */
601 }
602 if (time_after(jiffies, timeout))
603 break;
604 if (bus->needs_damn_long_delay)
605 msleep(2); /* temporary workaround */
606 else {
607 udelay(10);
608 cond_resched();
609 }
610 }
611
612 if (chip->msi) {
613 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
614 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
615 free_irq(chip->irq, chip);
616 chip->irq = -1;
617 pci_disable_msi(chip->pci);
618 chip->msi = 0;
619 if (azx_acquire_irq(chip, 1) < 0)
620 return -1;
621 goto again;
622 }
623
624 if (!chip->polling_mode) {
625 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
626 "switching to polling mode: last cmd=0x%08x\n",
627 chip->last_cmd);
628 chip->polling_mode = 1;
629 goto again;
630 }
631
632 if (chip->probing) {
633 /* If this critical timeout happens during the codec probing
634 * phase, this is likely an access to a non-existing codec
635 * slot. Better to return an error and reset the system.
636 */
637 return -1;
638 }
639
640 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
641 "switching to single_cmd mode: last cmd=0x%08x\n",
642 chip->last_cmd);
643 chip->rirb.rp = azx_readb(chip, RIRBWP);
644 chip->rirb.cmds = 0;
645 /* switch to single_cmd mode */
646 chip->single_cmd = 1;
647 azx_free_cmd_io(chip);
648 return -1;
649 }
650
651 /*
652 * Use the single immediate command instead of CORB/RIRB for simplicity
653 *
654 * Note: according to Intel, this is not preferred use. The command was
655 * intended for the BIOS only, and may get confused with unsolicited
656 * responses. So, we shouldn't use it for normal operation from the
657 * driver.
658 * I left the codes, however, for debugging/testing purposes.
659 */
660
661 /* send a command */
662 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
663 {
664 struct azx *chip = bus->private_data;
665 int timeout = 50;
666
667 while (timeout--) {
668 /* check ICB busy bit */
669 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
670 /* Clear IRV valid bit */
671 azx_writew(chip, IRS, azx_readw(chip, IRS) |
672 ICH6_IRS_VALID);
673 azx_writel(chip, IC, val);
674 azx_writew(chip, IRS, azx_readw(chip, IRS) |
675 ICH6_IRS_BUSY);
676 return 0;
677 }
678 udelay(1);
679 }
680 if (printk_ratelimit())
681 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
682 azx_readw(chip, IRS), val);
683 return -EIO;
684 }
685
686 /* receive a response */
687 static unsigned int azx_single_get_response(struct hda_bus *bus)
688 {
689 struct azx *chip = bus->private_data;
690 int timeout = 50;
691
692 while (timeout--) {
693 /* check IRV busy bit */
694 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
695 return azx_readl(chip, IR);
696 udelay(1);
697 }
698 if (printk_ratelimit())
699 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
700 azx_readw(chip, IRS));
701 return (unsigned int)-1;
702 }
703
704 /*
705 * The below are the main callbacks from hda_codec.
706 *
707 * They are just the skeleton to call sub-callbacks according to the
708 * current setting of chip->single_cmd.
709 */
710
711 /* send a command */
712 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
713 {
714 struct azx *chip = bus->private_data;
715
716 chip->last_cmd = val;
717 if (chip->single_cmd)
718 return azx_single_send_cmd(bus, val);
719 else
720 return azx_corb_send_cmd(bus, val);
721 }
722
723 /* get a response */
724 static unsigned int azx_get_response(struct hda_bus *bus)
725 {
726 struct azx *chip = bus->private_data;
727 if (chip->single_cmd)
728 return azx_single_get_response(bus);
729 else
730 return azx_rirb_get_response(bus);
731 }
732
733 #ifdef CONFIG_SND_HDA_POWER_SAVE
734 static void azx_power_notify(struct hda_bus *bus);
735 #endif
736
737 /* reset codec link */
738 static int azx_reset(struct azx *chip)
739 {
740 int count;
741
742 /* clear STATESTS */
743 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
744
745 /* reset controller */
746 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
747
748 count = 50;
749 while (azx_readb(chip, GCTL) && --count)
750 msleep(1);
751
752 /* delay for >= 100us for codec PLL to settle per spec
753 * Rev 0.9 section 5.5.1
754 */
755 msleep(1);
756
757 /* Bring controller out of reset */
758 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
759
760 count = 50;
761 while (!azx_readb(chip, GCTL) && --count)
762 msleep(1);
763
764 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
765 msleep(1);
766
767 /* check to see if controller is ready */
768 if (!azx_readb(chip, GCTL)) {
769 snd_printd("azx_reset: controller not ready!\n");
770 return -EBUSY;
771 }
772
773 /* Accept unsolicited responses */
774 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
775
776 /* detect codecs */
777 if (!chip->codec_mask) {
778 chip->codec_mask = azx_readw(chip, STATESTS);
779 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
780 }
781
782 return 0;
783 }
784
785
786 /*
787 * Lowlevel interface
788 */
789
790 /* enable interrupts */
791 static void azx_int_enable(struct azx *chip)
792 {
793 /* enable controller CIE and GIE */
794 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
795 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
796 }
797
798 /* disable interrupts */
799 static void azx_int_disable(struct azx *chip)
800 {
801 int i;
802
803 /* disable interrupts in stream descriptor */
804 for (i = 0; i < chip->num_streams; i++) {
805 struct azx_dev *azx_dev = &chip->azx_dev[i];
806 azx_sd_writeb(azx_dev, SD_CTL,
807 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
808 }
809
810 /* disable SIE for all streams */
811 azx_writeb(chip, INTCTL, 0);
812
813 /* disable controller CIE and GIE */
814 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
815 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
816 }
817
818 /* clear interrupts */
819 static void azx_int_clear(struct azx *chip)
820 {
821 int i;
822
823 /* clear stream status */
824 for (i = 0; i < chip->num_streams; i++) {
825 struct azx_dev *azx_dev = &chip->azx_dev[i];
826 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
827 }
828
829 /* clear STATESTS */
830 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
831
832 /* clear rirb status */
833 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
834
835 /* clear int status */
836 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
837 }
838
839 /* start a stream */
840 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
841 {
842 /*
843 * Before stream start, initialize parameter
844 */
845 azx_dev->insufficient = 1;
846
847 /* enable SIE */
848 azx_writeb(chip, INTCTL,
849 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
850 /* set DMA start and interrupt mask */
851 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
852 SD_CTL_DMA_START | SD_INT_MASK);
853 }
854
855 /* stop a stream */
856 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
857 {
858 /* stop DMA */
859 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
860 ~(SD_CTL_DMA_START | SD_INT_MASK));
861 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
862 /* disable SIE */
863 azx_writeb(chip, INTCTL,
864 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
865 }
866
867
868 /*
869 * reset and start the controller registers
870 */
871 static void azx_init_chip(struct azx *chip)
872 {
873 if (chip->initialized)
874 return;
875
876 /* reset controller */
877 azx_reset(chip);
878
879 /* initialize interrupts */
880 azx_int_clear(chip);
881 azx_int_enable(chip);
882
883 /* initialize the codec command I/O */
884 if (!chip->single_cmd)
885 azx_init_cmd_io(chip);
886
887 /* program the position buffer */
888 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
889 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
890
891 chip->initialized = 1;
892 }
893
894 /*
895 * initialize the PCI registers
896 */
897 /* update bits in a PCI register byte */
898 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
899 unsigned char mask, unsigned char val)
900 {
901 unsigned char data;
902
903 pci_read_config_byte(pci, reg, &data);
904 data &= ~mask;
905 data |= (val & mask);
906 pci_write_config_byte(pci, reg, data);
907 }
908
909 static void azx_init_pci(struct azx *chip)
910 {
911 unsigned short snoop;
912
913 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
914 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
915 * Ensuring these bits are 0 clears playback static on some HD Audio
916 * codecs
917 */
918 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
919
920 switch (chip->driver_type) {
921 case AZX_DRIVER_ATI:
922 /* For ATI SB450 azalia HD audio, we need to enable snoop */
923 update_pci_byte(chip->pci,
924 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
925 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
926 break;
927 case AZX_DRIVER_NVIDIA:
928 /* For NVIDIA HDA, enable snoop */
929 update_pci_byte(chip->pci,
930 NVIDIA_HDA_TRANSREG_ADDR,
931 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
932 update_pci_byte(chip->pci,
933 NVIDIA_HDA_ISTRM_COH,
934 0x01, NVIDIA_HDA_ENABLE_COHBIT);
935 update_pci_byte(chip->pci,
936 NVIDIA_HDA_OSTRM_COH,
937 0x01, NVIDIA_HDA_ENABLE_COHBIT);
938 break;
939 case AZX_DRIVER_SCH:
940 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
941 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
942 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
943 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
944 pci_read_config_word(chip->pci,
945 INTEL_SCH_HDA_DEVC, &snoop);
946 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
947 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
948 ? "Failed" : "OK");
949 }
950 break;
951
952 }
953 }
954
955
956 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
957
958 /*
959 * interrupt handler
960 */
961 static irqreturn_t azx_interrupt(int irq, void *dev_id)
962 {
963 struct azx *chip = dev_id;
964 struct azx_dev *azx_dev;
965 u32 status;
966 int i;
967
968 spin_lock(&chip->reg_lock);
969
970 status = azx_readl(chip, INTSTS);
971 if (status == 0) {
972 spin_unlock(&chip->reg_lock);
973 return IRQ_NONE;
974 }
975
976 for (i = 0; i < chip->num_streams; i++) {
977 azx_dev = &chip->azx_dev[i];
978 if (status & azx_dev->sd_int_sta_mask) {
979 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
980 if (!azx_dev->substream || !azx_dev->running)
981 continue;
982 /* ignore the first dummy IRQ (due to pos_adj) */
983 if (azx_dev->irq_ignore) {
984 azx_dev->irq_ignore = 0;
985 continue;
986 }
987 /* check whether this IRQ is really acceptable */
988 if (azx_position_ok(chip, azx_dev)) {
989 azx_dev->irq_pending = 0;
990 spin_unlock(&chip->reg_lock);
991 snd_pcm_period_elapsed(azx_dev->substream);
992 spin_lock(&chip->reg_lock);
993 } else {
994 /* bogus IRQ, process it later */
995 azx_dev->irq_pending = 1;
996 schedule_work(&chip->irq_pending_work);
997 }
998 }
999 }
1000
1001 /* clear rirb int */
1002 status = azx_readb(chip, RIRBSTS);
1003 if (status & RIRB_INT_MASK) {
1004 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
1005 azx_update_rirb(chip);
1006 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1007 }
1008
1009 #if 0
1010 /* clear state status int */
1011 if (azx_readb(chip, STATESTS) & 0x04)
1012 azx_writeb(chip, STATESTS, 0x04);
1013 #endif
1014 spin_unlock(&chip->reg_lock);
1015
1016 return IRQ_HANDLED;
1017 }
1018
1019
1020 /*
1021 * set up a BDL entry
1022 */
1023 static int setup_bdle(struct snd_pcm_substream *substream,
1024 struct azx_dev *azx_dev, u32 **bdlp,
1025 int ofs, int size, int with_ioc)
1026 {
1027 u32 *bdl = *bdlp;
1028
1029 while (size > 0) {
1030 dma_addr_t addr;
1031 int chunk;
1032
1033 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1034 return -EINVAL;
1035
1036 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1037 /* program the address field of the BDL entry */
1038 bdl[0] = cpu_to_le32((u32)addr);
1039 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1040 /* program the size field of the BDL entry */
1041 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1042 bdl[2] = cpu_to_le32(chunk);
1043 /* program the IOC to enable interrupt
1044 * only when the whole fragment is processed
1045 */
1046 size -= chunk;
1047 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1048 bdl += 4;
1049 azx_dev->frags++;
1050 ofs += chunk;
1051 }
1052 *bdlp = bdl;
1053 return ofs;
1054 }
1055
1056 /*
1057 * set up BDL entries
1058 */
1059 static int azx_setup_periods(struct azx *chip,
1060 struct snd_pcm_substream *substream,
1061 struct azx_dev *azx_dev)
1062 {
1063 u32 *bdl;
1064 int i, ofs, periods, period_bytes;
1065 int pos_adj;
1066
1067 /* reset BDL address */
1068 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1069 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1070
1071 period_bytes = snd_pcm_lib_period_bytes(substream);
1072 azx_dev->period_bytes = period_bytes;
1073 periods = azx_dev->bufsize / period_bytes;
1074
1075 /* program the initial BDL entries */
1076 bdl = (u32 *)azx_dev->bdl.area;
1077 ofs = 0;
1078 azx_dev->frags = 0;
1079 azx_dev->irq_ignore = 0;
1080 pos_adj = bdl_pos_adj[chip->dev_index];
1081 if (pos_adj > 0) {
1082 struct snd_pcm_runtime *runtime = substream->runtime;
1083 int pos_align = pos_adj;
1084 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1085 if (!pos_adj)
1086 pos_adj = pos_align;
1087 else
1088 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1089 pos_align;
1090 pos_adj = frames_to_bytes(runtime, pos_adj);
1091 if (pos_adj >= period_bytes) {
1092 snd_printk(KERN_WARNING "Too big adjustment %d\n",
1093 bdl_pos_adj[chip->dev_index]);
1094 pos_adj = 0;
1095 } else {
1096 ofs = setup_bdle(substream, azx_dev,
1097 &bdl, ofs, pos_adj, 1);
1098 if (ofs < 0)
1099 goto error;
1100 azx_dev->irq_ignore = 1;
1101 }
1102 } else
1103 pos_adj = 0;
1104 for (i = 0; i < periods; i++) {
1105 if (i == periods - 1 && pos_adj)
1106 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1107 period_bytes - pos_adj, 0);
1108 else
1109 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1110 period_bytes, 1);
1111 if (ofs < 0)
1112 goto error;
1113 }
1114 return 0;
1115
1116 error:
1117 snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1118 azx_dev->bufsize, period_bytes);
1119 /* reset */
1120 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1121 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1122 return -EINVAL;
1123 }
1124
1125 /*
1126 * set up the SD for streaming
1127 */
1128 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1129 {
1130 unsigned char val;
1131 int timeout;
1132
1133 /* make sure the run bit is zero for SD */
1134 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1135 ~SD_CTL_DMA_START);
1136 /* reset stream */
1137 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1138 SD_CTL_STREAM_RESET);
1139 udelay(3);
1140 timeout = 300;
1141 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1142 --timeout)
1143 ;
1144 val &= ~SD_CTL_STREAM_RESET;
1145 azx_sd_writeb(azx_dev, SD_CTL, val);
1146 udelay(3);
1147
1148 timeout = 300;
1149 /* waiting for hardware to report that the stream is out of reset */
1150 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1151 --timeout)
1152 ;
1153
1154 /* program the stream_tag */
1155 azx_sd_writel(azx_dev, SD_CTL,
1156 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1157 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1158
1159 /* program the length of samples in cyclic buffer */
1160 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1161
1162 /* program the stream format */
1163 /* this value needs to be the same as the one programmed */
1164 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1165
1166 /* program the stream LVI (last valid index) of the BDL */
1167 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1168
1169 /* program the BDL address */
1170 /* lower BDL address */
1171 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1172 /* upper BDL address */
1173 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1174
1175 /* enable the position buffer */
1176 if (chip->position_fix == POS_FIX_POSBUF ||
1177 chip->position_fix == POS_FIX_AUTO ||
1178 chip->via_dmapos_patch) {
1179 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1180 azx_writel(chip, DPLBASE,
1181 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1182 }
1183
1184 /* set the interrupt enable bits in the descriptor control register */
1185 azx_sd_writel(azx_dev, SD_CTL,
1186 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1187
1188 return 0;
1189 }
1190
1191 /*
1192 * Probe the given codec address
1193 */
1194 static int probe_codec(struct azx *chip, int addr)
1195 {
1196 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1197 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1198 unsigned int res;
1199
1200 chip->probing = 1;
1201 azx_send_cmd(chip->bus, cmd);
1202 res = azx_get_response(chip->bus);
1203 chip->probing = 0;
1204 if (res == -1)
1205 return -EIO;
1206 snd_printdd("hda_intel: codec #%d probed OK\n", addr);
1207 return 0;
1208 }
1209
1210 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1211 struct hda_pcm *cpcm);
1212 static void azx_stop_chip(struct azx *chip);
1213
1214 /*
1215 * Codec initialization
1216 */
1217
1218 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1219 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1220 [AZX_DRIVER_TERA] = 1,
1221 };
1222
1223 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1224 unsigned int codec_probe_mask)
1225 {
1226 struct hda_bus_template bus_temp;
1227 int c, codecs, err;
1228 int max_slots;
1229
1230 memset(&bus_temp, 0, sizeof(bus_temp));
1231 bus_temp.private_data = chip;
1232 bus_temp.modelname = model;
1233 bus_temp.pci = chip->pci;
1234 bus_temp.ops.command = azx_send_cmd;
1235 bus_temp.ops.get_response = azx_get_response;
1236 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1237 #ifdef CONFIG_SND_HDA_POWER_SAVE
1238 bus_temp.ops.pm_notify = azx_power_notify;
1239 #endif
1240
1241 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1242 if (err < 0)
1243 return err;
1244
1245 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1246 chip->bus->needs_damn_long_delay = 1;
1247
1248 codecs = 0;
1249 max_slots = azx_max_codecs[chip->driver_type];
1250 if (!max_slots)
1251 max_slots = AZX_MAX_CODECS;
1252
1253 /* First try to probe all given codec slots */
1254 for (c = 0; c < max_slots; c++) {
1255 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1256 if (probe_codec(chip, c) < 0) {
1257 /* Some BIOSen give you wrong codec addresses
1258 * that don't exist
1259 */
1260 snd_printk(KERN_WARNING
1261 "hda_intel: Codec #%d probe error; "
1262 "disabling it...\n", c);
1263 chip->codec_mask &= ~(1 << c);
1264 /* More badly, accessing to a non-existing
1265 * codec often screws up the controller chip,
1266 * and distrubs the further communications.
1267 * Thus if an error occurs during probing,
1268 * better to reset the controller chip to
1269 * get back to the sanity state.
1270 */
1271 azx_stop_chip(chip);
1272 azx_init_chip(chip);
1273 }
1274 }
1275 }
1276
1277 /* Then create codec instances */
1278 for (c = 0; c < max_slots; c++) {
1279 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1280 struct hda_codec *codec;
1281 err = snd_hda_codec_new(chip->bus, c, &codec);
1282 if (err < 0)
1283 continue;
1284 codecs++;
1285 }
1286 }
1287 if (!codecs) {
1288 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1289 return -ENXIO;
1290 }
1291
1292 return 0;
1293 }
1294
1295
1296 /*
1297 * PCM support
1298 */
1299
1300 /* assign a stream for the PCM */
1301 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1302 {
1303 int dev, i, nums;
1304 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1305 dev = chip->playback_index_offset;
1306 nums = chip->playback_streams;
1307 } else {
1308 dev = chip->capture_index_offset;
1309 nums = chip->capture_streams;
1310 }
1311 for (i = 0; i < nums; i++, dev++)
1312 if (!chip->azx_dev[dev].opened) {
1313 chip->azx_dev[dev].opened = 1;
1314 return &chip->azx_dev[dev];
1315 }
1316 return NULL;
1317 }
1318
1319 /* release the assigned stream */
1320 static inline void azx_release_device(struct azx_dev *azx_dev)
1321 {
1322 azx_dev->opened = 0;
1323 }
1324
1325 static struct snd_pcm_hardware azx_pcm_hw = {
1326 .info = (SNDRV_PCM_INFO_MMAP |
1327 SNDRV_PCM_INFO_INTERLEAVED |
1328 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1329 SNDRV_PCM_INFO_MMAP_VALID |
1330 /* No full-resume yet implemented */
1331 /* SNDRV_PCM_INFO_RESUME |*/
1332 SNDRV_PCM_INFO_PAUSE |
1333 SNDRV_PCM_INFO_SYNC_START),
1334 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1335 .rates = SNDRV_PCM_RATE_48000,
1336 .rate_min = 48000,
1337 .rate_max = 48000,
1338 .channels_min = 2,
1339 .channels_max = 2,
1340 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1341 .period_bytes_min = 128,
1342 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1343 .periods_min = 2,
1344 .periods_max = AZX_MAX_FRAG,
1345 .fifo_size = 0,
1346 };
1347
1348 struct azx_pcm {
1349 struct azx *chip;
1350 struct hda_codec *codec;
1351 struct hda_pcm_stream *hinfo[2];
1352 };
1353
1354 static int azx_pcm_open(struct snd_pcm_substream *substream)
1355 {
1356 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1357 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1358 struct azx *chip = apcm->chip;
1359 struct azx_dev *azx_dev;
1360 struct snd_pcm_runtime *runtime = substream->runtime;
1361 unsigned long flags;
1362 int err;
1363
1364 mutex_lock(&chip->open_mutex);
1365 azx_dev = azx_assign_device(chip, substream->stream);
1366 if (azx_dev == NULL) {
1367 mutex_unlock(&chip->open_mutex);
1368 return -EBUSY;
1369 }
1370 runtime->hw = azx_pcm_hw;
1371 runtime->hw.channels_min = hinfo->channels_min;
1372 runtime->hw.channels_max = hinfo->channels_max;
1373 runtime->hw.formats = hinfo->formats;
1374 runtime->hw.rates = hinfo->rates;
1375 snd_pcm_limit_hw_rates(runtime);
1376 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1377 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1378 128);
1379 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1380 128);
1381 snd_hda_power_up(apcm->codec);
1382 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1383 if (err < 0) {
1384 azx_release_device(azx_dev);
1385 snd_hda_power_down(apcm->codec);
1386 mutex_unlock(&chip->open_mutex);
1387 return err;
1388 }
1389 spin_lock_irqsave(&chip->reg_lock, flags);
1390 azx_dev->substream = substream;
1391 azx_dev->running = 0;
1392 spin_unlock_irqrestore(&chip->reg_lock, flags);
1393
1394 runtime->private_data = azx_dev;
1395 snd_pcm_set_sync(substream);
1396 mutex_unlock(&chip->open_mutex);
1397 return 0;
1398 }
1399
1400 static int azx_pcm_close(struct snd_pcm_substream *substream)
1401 {
1402 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1403 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1404 struct azx *chip = apcm->chip;
1405 struct azx_dev *azx_dev = get_azx_dev(substream);
1406 unsigned long flags;
1407
1408 mutex_lock(&chip->open_mutex);
1409 spin_lock_irqsave(&chip->reg_lock, flags);
1410 azx_dev->substream = NULL;
1411 azx_dev->running = 0;
1412 spin_unlock_irqrestore(&chip->reg_lock, flags);
1413 azx_release_device(azx_dev);
1414 hinfo->ops.close(hinfo, apcm->codec, substream);
1415 snd_hda_power_down(apcm->codec);
1416 mutex_unlock(&chip->open_mutex);
1417 return 0;
1418 }
1419
1420 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1421 struct snd_pcm_hw_params *hw_params)
1422 {
1423 return snd_pcm_lib_malloc_pages(substream,
1424 params_buffer_bytes(hw_params));
1425 }
1426
1427 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1428 {
1429 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1430 struct azx_dev *azx_dev = get_azx_dev(substream);
1431 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1432
1433 /* reset BDL address */
1434 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1435 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1436 azx_sd_writel(azx_dev, SD_CTL, 0);
1437
1438 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1439
1440 return snd_pcm_lib_free_pages(substream);
1441 }
1442
1443 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1444 {
1445 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1446 struct azx *chip = apcm->chip;
1447 struct azx_dev *azx_dev = get_azx_dev(substream);
1448 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1449 struct snd_pcm_runtime *runtime = substream->runtime;
1450
1451 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1452 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1453 runtime->channels,
1454 runtime->format,
1455 hinfo->maxbps);
1456 if (!azx_dev->format_val) {
1457 snd_printk(KERN_ERR SFX
1458 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1459 runtime->rate, runtime->channels, runtime->format);
1460 return -EINVAL;
1461 }
1462
1463 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1464 azx_dev->bufsize, azx_dev->format_val);
1465 if (azx_setup_periods(chip, substream, azx_dev) < 0)
1466 return -EINVAL;
1467 azx_setup_controller(chip, azx_dev);
1468 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1469 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1470 else
1471 azx_dev->fifo_size = 0;
1472
1473 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1474 azx_dev->format_val, substream);
1475 }
1476
1477 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1478 {
1479 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1480 struct azx *chip = apcm->chip;
1481 struct azx_dev *azx_dev;
1482 struct snd_pcm_substream *s;
1483 int start, nsync = 0, sbits = 0;
1484 int nwait, timeout;
1485
1486 switch (cmd) {
1487 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1488 case SNDRV_PCM_TRIGGER_RESUME:
1489 case SNDRV_PCM_TRIGGER_START:
1490 start = 1;
1491 break;
1492 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1493 case SNDRV_PCM_TRIGGER_SUSPEND:
1494 case SNDRV_PCM_TRIGGER_STOP:
1495 start = 0;
1496 break;
1497 default:
1498 return -EINVAL;
1499 }
1500
1501 snd_pcm_group_for_each_entry(s, substream) {
1502 if (s->pcm->card != substream->pcm->card)
1503 continue;
1504 azx_dev = get_azx_dev(s);
1505 sbits |= 1 << azx_dev->index;
1506 nsync++;
1507 snd_pcm_trigger_done(s, substream);
1508 }
1509
1510 spin_lock(&chip->reg_lock);
1511 if (nsync > 1) {
1512 /* first, set SYNC bits of corresponding streams */
1513 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1514 }
1515 snd_pcm_group_for_each_entry(s, substream) {
1516 if (s->pcm->card != substream->pcm->card)
1517 continue;
1518 azx_dev = get_azx_dev(s);
1519 if (start)
1520 azx_stream_start(chip, azx_dev);
1521 else
1522 azx_stream_stop(chip, azx_dev);
1523 azx_dev->running = start;
1524 }
1525 spin_unlock(&chip->reg_lock);
1526 if (start) {
1527 if (nsync == 1)
1528 return 0;
1529 /* wait until all FIFOs get ready */
1530 for (timeout = 5000; timeout; timeout--) {
1531 nwait = 0;
1532 snd_pcm_group_for_each_entry(s, substream) {
1533 if (s->pcm->card != substream->pcm->card)
1534 continue;
1535 azx_dev = get_azx_dev(s);
1536 if (!(azx_sd_readb(azx_dev, SD_STS) &
1537 SD_STS_FIFO_READY))
1538 nwait++;
1539 }
1540 if (!nwait)
1541 break;
1542 cpu_relax();
1543 }
1544 } else {
1545 /* wait until all RUN bits are cleared */
1546 for (timeout = 5000; timeout; timeout--) {
1547 nwait = 0;
1548 snd_pcm_group_for_each_entry(s, substream) {
1549 if (s->pcm->card != substream->pcm->card)
1550 continue;
1551 azx_dev = get_azx_dev(s);
1552 if (azx_sd_readb(azx_dev, SD_CTL) &
1553 SD_CTL_DMA_START)
1554 nwait++;
1555 }
1556 if (!nwait)
1557 break;
1558 cpu_relax();
1559 }
1560 }
1561 if (nsync > 1) {
1562 spin_lock(&chip->reg_lock);
1563 /* reset SYNC bits */
1564 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1565 spin_unlock(&chip->reg_lock);
1566 }
1567 return 0;
1568 }
1569
1570 /* get the current DMA position with correction on VIA chips */
1571 static unsigned int azx_via_get_position(struct azx *chip,
1572 struct azx_dev *azx_dev)
1573 {
1574 unsigned int link_pos, mini_pos, bound_pos;
1575 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1576 unsigned int fifo_size;
1577
1578 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1579 if (azx_dev->index >= 4) {
1580 /* Playback, no problem using link position */
1581 return link_pos;
1582 }
1583
1584 /* Capture */
1585 /* For new chipset,
1586 * use mod to get the DMA position just like old chipset
1587 */
1588 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1589 mod_dma_pos %= azx_dev->period_bytes;
1590
1591 /* azx_dev->fifo_size can't get FIFO size of in stream.
1592 * Get from base address + offset.
1593 */
1594 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1595
1596 if (azx_dev->insufficient) {
1597 /* Link position never gather than FIFO size */
1598 if (link_pos <= fifo_size)
1599 return 0;
1600
1601 azx_dev->insufficient = 0;
1602 }
1603
1604 if (link_pos <= fifo_size)
1605 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1606 else
1607 mini_pos = link_pos - fifo_size;
1608
1609 /* Find nearest previous boudary */
1610 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1611 mod_link_pos = link_pos % azx_dev->period_bytes;
1612 if (mod_link_pos >= fifo_size)
1613 bound_pos = link_pos - mod_link_pos;
1614 else if (mod_dma_pos >= mod_mini_pos)
1615 bound_pos = mini_pos - mod_mini_pos;
1616 else {
1617 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1618 if (bound_pos >= azx_dev->bufsize)
1619 bound_pos = 0;
1620 }
1621
1622 /* Calculate real DMA position we want */
1623 return bound_pos + mod_dma_pos;
1624 }
1625
1626 static unsigned int azx_get_position(struct azx *chip,
1627 struct azx_dev *azx_dev)
1628 {
1629 unsigned int pos;
1630
1631 if (chip->via_dmapos_patch)
1632 pos = azx_via_get_position(chip, azx_dev);
1633 else if (chip->position_fix == POS_FIX_POSBUF ||
1634 chip->position_fix == POS_FIX_AUTO) {
1635 /* use the position buffer */
1636 pos = le32_to_cpu(*azx_dev->posbuf);
1637 } else {
1638 /* read LPIB */
1639 pos = azx_sd_readl(azx_dev, SD_LPIB);
1640 }
1641 if (pos >= azx_dev->bufsize)
1642 pos = 0;
1643 return pos;
1644 }
1645
1646 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1647 {
1648 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1649 struct azx *chip = apcm->chip;
1650 struct azx_dev *azx_dev = get_azx_dev(substream);
1651 return bytes_to_frames(substream->runtime,
1652 azx_get_position(chip, azx_dev));
1653 }
1654
1655 /*
1656 * Check whether the current DMA position is acceptable for updating
1657 * periods. Returns non-zero if it's OK.
1658 *
1659 * Many HD-audio controllers appear pretty inaccurate about
1660 * the update-IRQ timing. The IRQ is issued before actually the
1661 * data is processed. So, we need to process it afterwords in a
1662 * workqueue.
1663 */
1664 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1665 {
1666 unsigned int pos;
1667
1668 pos = azx_get_position(chip, azx_dev);
1669 if (chip->position_fix == POS_FIX_AUTO) {
1670 if (!pos) {
1671 printk(KERN_WARNING
1672 "hda-intel: Invalid position buffer, "
1673 "using LPIB read method instead.\n");
1674 chip->position_fix = POS_FIX_LPIB;
1675 pos = azx_get_position(chip, azx_dev);
1676 } else
1677 chip->position_fix = POS_FIX_POSBUF;
1678 }
1679
1680 if (!bdl_pos_adj[chip->dev_index])
1681 return 1; /* no delayed ack */
1682 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1683 return 0; /* NG - it's below the period boundary */
1684 return 1; /* OK, it's fine */
1685 }
1686
1687 /*
1688 * The work for pending PCM period updates.
1689 */
1690 static void azx_irq_pending_work(struct work_struct *work)
1691 {
1692 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1693 int i, pending;
1694
1695 if (!chip->irq_pending_warned) {
1696 printk(KERN_WARNING
1697 "hda-intel: IRQ timing workaround is activated "
1698 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1699 chip->card->number);
1700 chip->irq_pending_warned = 1;
1701 }
1702
1703 for (;;) {
1704 pending = 0;
1705 spin_lock_irq(&chip->reg_lock);
1706 for (i = 0; i < chip->num_streams; i++) {
1707 struct azx_dev *azx_dev = &chip->azx_dev[i];
1708 if (!azx_dev->irq_pending ||
1709 !azx_dev->substream ||
1710 !azx_dev->running)
1711 continue;
1712 if (azx_position_ok(chip, azx_dev)) {
1713 azx_dev->irq_pending = 0;
1714 spin_unlock(&chip->reg_lock);
1715 snd_pcm_period_elapsed(azx_dev->substream);
1716 spin_lock(&chip->reg_lock);
1717 } else
1718 pending++;
1719 }
1720 spin_unlock_irq(&chip->reg_lock);
1721 if (!pending)
1722 return;
1723 cond_resched();
1724 }
1725 }
1726
1727 /* clear irq_pending flags and assure no on-going workq */
1728 static void azx_clear_irq_pending(struct azx *chip)
1729 {
1730 int i;
1731
1732 spin_lock_irq(&chip->reg_lock);
1733 for (i = 0; i < chip->num_streams; i++)
1734 chip->azx_dev[i].irq_pending = 0;
1735 spin_unlock_irq(&chip->reg_lock);
1736 flush_scheduled_work();
1737 }
1738
1739 static struct snd_pcm_ops azx_pcm_ops = {
1740 .open = azx_pcm_open,
1741 .close = azx_pcm_close,
1742 .ioctl = snd_pcm_lib_ioctl,
1743 .hw_params = azx_pcm_hw_params,
1744 .hw_free = azx_pcm_hw_free,
1745 .prepare = azx_pcm_prepare,
1746 .trigger = azx_pcm_trigger,
1747 .pointer = azx_pcm_pointer,
1748 .page = snd_pcm_sgbuf_ops_page,
1749 };
1750
1751 static void azx_pcm_free(struct snd_pcm *pcm)
1752 {
1753 struct azx_pcm *apcm = pcm->private_data;
1754 if (apcm) {
1755 apcm->chip->pcm[pcm->device] = NULL;
1756 kfree(apcm);
1757 }
1758 }
1759
1760 static int
1761 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1762 struct hda_pcm *cpcm)
1763 {
1764 struct azx *chip = bus->private_data;
1765 struct snd_pcm *pcm;
1766 struct azx_pcm *apcm;
1767 int pcm_dev = cpcm->device;
1768 int s, err;
1769
1770 if (pcm_dev >= AZX_MAX_PCMS) {
1771 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1772 pcm_dev);
1773 return -EINVAL;
1774 }
1775 if (chip->pcm[pcm_dev]) {
1776 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1777 return -EBUSY;
1778 }
1779 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1780 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1781 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1782 &pcm);
1783 if (err < 0)
1784 return err;
1785 strcpy(pcm->name, cpcm->name);
1786 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1787 if (apcm == NULL)
1788 return -ENOMEM;
1789 apcm->chip = chip;
1790 apcm->codec = codec;
1791 pcm->private_data = apcm;
1792 pcm->private_free = azx_pcm_free;
1793 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1794 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1795 chip->pcm[pcm_dev] = pcm;
1796 cpcm->pcm = pcm;
1797 for (s = 0; s < 2; s++) {
1798 apcm->hinfo[s] = &cpcm->stream[s];
1799 if (cpcm->stream[s].substreams)
1800 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1801 }
1802 /* buffer pre-allocation */
1803 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1804 snd_dma_pci_data(chip->pci),
1805 1024 * 64, 32 * 1024 * 1024);
1806 return 0;
1807 }
1808
1809 /*
1810 * mixer creation - all stuff is implemented in hda module
1811 */
1812 static int __devinit azx_mixer_create(struct azx *chip)
1813 {
1814 return snd_hda_build_controls(chip->bus);
1815 }
1816
1817
1818 /*
1819 * initialize SD streams
1820 */
1821 static int __devinit azx_init_stream(struct azx *chip)
1822 {
1823 int i;
1824
1825 /* initialize each stream (aka device)
1826 * assign the starting bdl address to each stream (device)
1827 * and initialize
1828 */
1829 for (i = 0; i < chip->num_streams; i++) {
1830 struct azx_dev *azx_dev = &chip->azx_dev[i];
1831 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1832 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1833 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1834 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1835 azx_dev->sd_int_sta_mask = 1 << i;
1836 /* stream tag: must be non-zero and unique */
1837 azx_dev->index = i;
1838 azx_dev->stream_tag = i + 1;
1839 }
1840
1841 return 0;
1842 }
1843
1844 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1845 {
1846 if (request_irq(chip->pci->irq, azx_interrupt,
1847 chip->msi ? 0 : IRQF_SHARED,
1848 "HDA Intel", chip)) {
1849 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1850 "disabling device\n", chip->pci->irq);
1851 if (do_disconnect)
1852 snd_card_disconnect(chip->card);
1853 return -1;
1854 }
1855 chip->irq = chip->pci->irq;
1856 pci_intx(chip->pci, !chip->msi);
1857 return 0;
1858 }
1859
1860
1861 static void azx_stop_chip(struct azx *chip)
1862 {
1863 if (!chip->initialized)
1864 return;
1865
1866 /* disable interrupts */
1867 azx_int_disable(chip);
1868 azx_int_clear(chip);
1869
1870 /* disable CORB/RIRB */
1871 azx_free_cmd_io(chip);
1872
1873 /* disable position buffer */
1874 azx_writel(chip, DPLBASE, 0);
1875 azx_writel(chip, DPUBASE, 0);
1876
1877 chip->initialized = 0;
1878 }
1879
1880 #ifdef CONFIG_SND_HDA_POWER_SAVE
1881 /* power-up/down the controller */
1882 static void azx_power_notify(struct hda_bus *bus)
1883 {
1884 struct azx *chip = bus->private_data;
1885 struct hda_codec *c;
1886 int power_on = 0;
1887
1888 list_for_each_entry(c, &bus->codec_list, list) {
1889 if (c->power_on) {
1890 power_on = 1;
1891 break;
1892 }
1893 }
1894 if (power_on)
1895 azx_init_chip(chip);
1896 else if (chip->running && power_save_controller)
1897 azx_stop_chip(chip);
1898 }
1899 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1900
1901 #ifdef CONFIG_PM
1902 /*
1903 * power management
1904 */
1905 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1906 {
1907 struct snd_card *card = pci_get_drvdata(pci);
1908 struct azx *chip = card->private_data;
1909 int i;
1910
1911 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1912 azx_clear_irq_pending(chip);
1913 for (i = 0; i < AZX_MAX_PCMS; i++)
1914 snd_pcm_suspend_all(chip->pcm[i]);
1915 if (chip->initialized)
1916 snd_hda_suspend(chip->bus, state);
1917 azx_stop_chip(chip);
1918 if (chip->irq >= 0) {
1919 free_irq(chip->irq, chip);
1920 chip->irq = -1;
1921 }
1922 if (chip->msi)
1923 pci_disable_msi(chip->pci);
1924 pci_disable_device(pci);
1925 pci_save_state(pci);
1926 pci_set_power_state(pci, pci_choose_state(pci, state));
1927 return 0;
1928 }
1929
1930 static int azx_resume(struct pci_dev *pci)
1931 {
1932 struct snd_card *card = pci_get_drvdata(pci);
1933 struct azx *chip = card->private_data;
1934
1935 pci_set_power_state(pci, PCI_D0);
1936 pci_restore_state(pci);
1937 if (pci_enable_device(pci) < 0) {
1938 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1939 "disabling device\n");
1940 snd_card_disconnect(card);
1941 return -EIO;
1942 }
1943 pci_set_master(pci);
1944 if (chip->msi)
1945 if (pci_enable_msi(pci) < 0)
1946 chip->msi = 0;
1947 if (azx_acquire_irq(chip, 1) < 0)
1948 return -EIO;
1949 azx_init_pci(chip);
1950
1951 if (snd_hda_codecs_inuse(chip->bus))
1952 azx_init_chip(chip);
1953
1954 snd_hda_resume(chip->bus);
1955 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1956 return 0;
1957 }
1958 #endif /* CONFIG_PM */
1959
1960
1961 /*
1962 * reboot notifier for hang-up problem at power-down
1963 */
1964 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
1965 {
1966 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
1967 azx_stop_chip(chip);
1968 return NOTIFY_OK;
1969 }
1970
1971 static void azx_notifier_register(struct azx *chip)
1972 {
1973 chip->reboot_notifier.notifier_call = azx_halt;
1974 register_reboot_notifier(&chip->reboot_notifier);
1975 }
1976
1977 static void azx_notifier_unregister(struct azx *chip)
1978 {
1979 if (chip->reboot_notifier.notifier_call)
1980 unregister_reboot_notifier(&chip->reboot_notifier);
1981 }
1982
1983 /*
1984 * destructor
1985 */
1986 static int azx_free(struct azx *chip)
1987 {
1988 int i;
1989
1990 azx_notifier_unregister(chip);
1991
1992 if (chip->initialized) {
1993 azx_clear_irq_pending(chip);
1994 for (i = 0; i < chip->num_streams; i++)
1995 azx_stream_stop(chip, &chip->azx_dev[i]);
1996 azx_stop_chip(chip);
1997 }
1998
1999 if (chip->irq >= 0)
2000 free_irq(chip->irq, (void*)chip);
2001 if (chip->msi)
2002 pci_disable_msi(chip->pci);
2003 if (chip->remap_addr)
2004 iounmap(chip->remap_addr);
2005
2006 if (chip->azx_dev) {
2007 for (i = 0; i < chip->num_streams; i++)
2008 if (chip->azx_dev[i].bdl.area)
2009 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2010 }
2011 if (chip->rb.area)
2012 snd_dma_free_pages(&chip->rb);
2013 if (chip->posbuf.area)
2014 snd_dma_free_pages(&chip->posbuf);
2015 pci_release_regions(chip->pci);
2016 pci_disable_device(chip->pci);
2017 kfree(chip->azx_dev);
2018 kfree(chip);
2019
2020 return 0;
2021 }
2022
2023 static int azx_dev_free(struct snd_device *device)
2024 {
2025 return azx_free(device->device_data);
2026 }
2027
2028 /*
2029 * white/black-listing for position_fix
2030 */
2031 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2032 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2033 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2034 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2035 {}
2036 };
2037
2038 static int __devinit check_position_fix(struct azx *chip, int fix)
2039 {
2040 const struct snd_pci_quirk *q;
2041
2042 /* Check VIA HD Audio Controller exist */
2043 if (chip->pci->vendor == PCI_VENDOR_ID_VIA &&
2044 chip->pci->device == VIA_HDAC_DEVICE_ID) {
2045 chip->via_dmapos_patch = 1;
2046 /* Use link position directly, avoid any transfer problem. */
2047 return POS_FIX_LPIB;
2048 }
2049 chip->via_dmapos_patch = 0;
2050
2051 if (fix == POS_FIX_AUTO) {
2052 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2053 if (q) {
2054 printk(KERN_INFO
2055 "hda_intel: position_fix set to %d "
2056 "for device %04x:%04x\n",
2057 q->value, q->subvendor, q->subdevice);
2058 return q->value;
2059 }
2060 }
2061 return fix;
2062 }
2063
2064 /*
2065 * black-lists for probe_mask
2066 */
2067 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2068 /* Thinkpad often breaks the controller communication when accessing
2069 * to the non-working (or non-existing) modem codec slot.
2070 */
2071 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2072 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2073 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2074 /* broken BIOS */
2075 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2076 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2077 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2078 {}
2079 };
2080
2081 static void __devinit check_probe_mask(struct azx *chip, int dev)
2082 {
2083 const struct snd_pci_quirk *q;
2084
2085 if (probe_mask[dev] == -1) {
2086 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2087 if (q) {
2088 printk(KERN_INFO
2089 "hda_intel: probe_mask set to 0x%x "
2090 "for device %04x:%04x\n",
2091 q->value, q->subvendor, q->subdevice);
2092 probe_mask[dev] = q->value;
2093 }
2094 }
2095 }
2096
2097
2098 /*
2099 * constructor
2100 */
2101 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2102 int dev, int driver_type,
2103 struct azx **rchip)
2104 {
2105 struct azx *chip;
2106 int i, err;
2107 unsigned short gcap;
2108 static struct snd_device_ops ops = {
2109 .dev_free = azx_dev_free,
2110 };
2111
2112 *rchip = NULL;
2113
2114 err = pci_enable_device(pci);
2115 if (err < 0)
2116 return err;
2117
2118 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2119 if (!chip) {
2120 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2121 pci_disable_device(pci);
2122 return -ENOMEM;
2123 }
2124
2125 spin_lock_init(&chip->reg_lock);
2126 mutex_init(&chip->open_mutex);
2127 chip->card = card;
2128 chip->pci = pci;
2129 chip->irq = -1;
2130 chip->driver_type = driver_type;
2131 chip->msi = enable_msi;
2132 chip->dev_index = dev;
2133 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2134
2135 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2136 check_probe_mask(chip, dev);
2137
2138 chip->single_cmd = single_cmd;
2139
2140 if (bdl_pos_adj[dev] < 0) {
2141 switch (chip->driver_type) {
2142 case AZX_DRIVER_ICH:
2143 bdl_pos_adj[dev] = 1;
2144 break;
2145 default:
2146 bdl_pos_adj[dev] = 32;
2147 break;
2148 }
2149 }
2150
2151 #if BITS_PER_LONG != 64
2152 /* Fix up base address on ULI M5461 */
2153 if (chip->driver_type == AZX_DRIVER_ULI) {
2154 u16 tmp3;
2155 pci_read_config_word(pci, 0x40, &tmp3);
2156 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2157 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2158 }
2159 #endif
2160
2161 err = pci_request_regions(pci, "ICH HD audio");
2162 if (err < 0) {
2163 kfree(chip);
2164 pci_disable_device(pci);
2165 return err;
2166 }
2167
2168 chip->addr = pci_resource_start(pci, 0);
2169 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
2170 if (chip->remap_addr == NULL) {
2171 snd_printk(KERN_ERR SFX "ioremap error\n");
2172 err = -ENXIO;
2173 goto errout;
2174 }
2175
2176 if (chip->msi)
2177 if (pci_enable_msi(pci) < 0)
2178 chip->msi = 0;
2179
2180 if (azx_acquire_irq(chip, 0) < 0) {
2181 err = -EBUSY;
2182 goto errout;
2183 }
2184
2185 pci_set_master(pci);
2186 synchronize_irq(chip->irq);
2187
2188 gcap = azx_readw(chip, GCAP);
2189 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2190
2191 /* allow 64bit DMA address if supported by H/W */
2192 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2193 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2194
2195 /* read number of streams from GCAP register instead of using
2196 * hardcoded value
2197 */
2198 chip->capture_streams = (gcap >> 8) & 0x0f;
2199 chip->playback_streams = (gcap >> 12) & 0x0f;
2200 if (!chip->playback_streams && !chip->capture_streams) {
2201 /* gcap didn't give any info, switching to old method */
2202
2203 switch (chip->driver_type) {
2204 case AZX_DRIVER_ULI:
2205 chip->playback_streams = ULI_NUM_PLAYBACK;
2206 chip->capture_streams = ULI_NUM_CAPTURE;
2207 break;
2208 case AZX_DRIVER_ATIHDMI:
2209 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2210 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2211 break;
2212 case AZX_DRIVER_GENERIC:
2213 default:
2214 chip->playback_streams = ICH6_NUM_PLAYBACK;
2215 chip->capture_streams = ICH6_NUM_CAPTURE;
2216 break;
2217 }
2218 }
2219 chip->capture_index_offset = 0;
2220 chip->playback_index_offset = chip->capture_streams;
2221 chip->num_streams = chip->playback_streams + chip->capture_streams;
2222 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2223 GFP_KERNEL);
2224 if (!chip->azx_dev) {
2225 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2226 goto errout;
2227 }
2228
2229 for (i = 0; i < chip->num_streams; i++) {
2230 /* allocate memory for the BDL for each stream */
2231 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2232 snd_dma_pci_data(chip->pci),
2233 BDL_SIZE, &chip->azx_dev[i].bdl);
2234 if (err < 0) {
2235 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2236 goto errout;
2237 }
2238 }
2239 /* allocate memory for the position buffer */
2240 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2241 snd_dma_pci_data(chip->pci),
2242 chip->num_streams * 8, &chip->posbuf);
2243 if (err < 0) {
2244 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2245 goto errout;
2246 }
2247 /* allocate CORB/RIRB */
2248 if (!chip->single_cmd) {
2249 err = azx_alloc_cmd_io(chip);
2250 if (err < 0)
2251 goto errout;
2252 }
2253
2254 /* initialize streams */
2255 azx_init_stream(chip);
2256
2257 /* initialize chip */
2258 azx_init_pci(chip);
2259 azx_init_chip(chip);
2260
2261 /* codec detection */
2262 if (!chip->codec_mask) {
2263 snd_printk(KERN_ERR SFX "no codecs found!\n");
2264 err = -ENODEV;
2265 goto errout;
2266 }
2267
2268 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2269 if (err <0) {
2270 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2271 goto errout;
2272 }
2273
2274 strcpy(card->driver, "HDA-Intel");
2275 strcpy(card->shortname, driver_short_names[chip->driver_type]);
2276 sprintf(card->longname, "%s at 0x%lx irq %i",
2277 card->shortname, chip->addr, chip->irq);
2278
2279 *rchip = chip;
2280 return 0;
2281
2282 errout:
2283 azx_free(chip);
2284 return err;
2285 }
2286
2287 static void power_down_all_codecs(struct azx *chip)
2288 {
2289 #ifdef CONFIG_SND_HDA_POWER_SAVE
2290 /* The codecs were powered up in snd_hda_codec_new().
2291 * Now all initialization done, so turn them down if possible
2292 */
2293 struct hda_codec *codec;
2294 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2295 snd_hda_power_down(codec);
2296 }
2297 #endif
2298 }
2299
2300 static int __devinit azx_probe(struct pci_dev *pci,
2301 const struct pci_device_id *pci_id)
2302 {
2303 static int dev;
2304 struct snd_card *card;
2305 struct azx *chip;
2306 int err;
2307
2308 if (dev >= SNDRV_CARDS)
2309 return -ENODEV;
2310 if (!enable[dev]) {
2311 dev++;
2312 return -ENOENT;
2313 }
2314
2315 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2316 if (!card) {
2317 snd_printk(KERN_ERR SFX "Error creating card!\n");
2318 return -ENOMEM;
2319 }
2320
2321 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2322 if (err < 0)
2323 goto out_free;
2324 card->private_data = chip;
2325
2326 /* create codec instances */
2327 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2328 if (err < 0)
2329 goto out_free;
2330
2331 /* create PCM streams */
2332 err = snd_hda_build_pcms(chip->bus);
2333 if (err < 0)
2334 goto out_free;
2335
2336 /* create mixer controls */
2337 err = azx_mixer_create(chip);
2338 if (err < 0)
2339 goto out_free;
2340
2341 snd_card_set_dev(card, &pci->dev);
2342
2343 err = snd_card_register(card);
2344 if (err < 0)
2345 goto out_free;
2346
2347 pci_set_drvdata(pci, card);
2348 chip->running = 1;
2349 power_down_all_codecs(chip);
2350 azx_notifier_register(chip);
2351
2352 dev++;
2353 return err;
2354 out_free:
2355 snd_card_free(card);
2356 return err;
2357 }
2358
2359 static void __devexit azx_remove(struct pci_dev *pci)
2360 {
2361 snd_card_free(pci_get_drvdata(pci));
2362 pci_set_drvdata(pci, NULL);
2363 }
2364
2365 /* PCI IDs */
2366 static struct pci_device_id azx_ids[] = {
2367 /* ICH 6..10 */
2368 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2369 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2370 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2371 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2372 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2373 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2374 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2375 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2376 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2377 /* PCH */
2378 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2379 /* SCH */
2380 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2381 /* ATI SB 450/600 */
2382 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2383 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2384 /* ATI HDMI */
2385 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2386 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2387 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2388 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2389 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2390 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2391 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2392 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2393 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2394 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2395 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2396 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2397 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2398 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2399 /* VIA VT8251/VT8237A */
2400 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2401 /* SIS966 */
2402 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2403 /* ULI M5461 */
2404 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2405 /* NVIDIA MCP */
2406 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2407 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2408 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2409 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2410 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2411 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2412 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2413 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2414 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2415 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2416 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2417 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2418 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2419 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2420 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2421 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2422 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2423 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2424 { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2425 { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2426 { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2427 { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2428 /* Teradici */
2429 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2430 /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2431 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2432 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2433 .class_mask = 0xffffff,
2434 .driver_data = AZX_DRIVER_GENERIC },
2435 { 0, }
2436 };
2437 MODULE_DEVICE_TABLE(pci, azx_ids);
2438
2439 /* pci_driver definition */
2440 static struct pci_driver driver = {
2441 .name = "HDA Intel",
2442 .id_table = azx_ids,
2443 .probe = azx_probe,
2444 .remove = __devexit_p(azx_remove),
2445 #ifdef CONFIG_PM
2446 .suspend = azx_suspend,
2447 .resume = azx_resume,
2448 #endif
2449 };
2450
2451 static int __init alsa_card_azx_init(void)
2452 {
2453 return pci_register_driver(&driver);
2454 }
2455
2456 static void __exit alsa_card_azx_exit(void)
2457 {
2458 pci_unregister_driver(&driver);
2459 }
2460
2461 module_init(alsa_card_azx_init)
2462 module_exit(alsa_card_azx_exit)
Linux 2.6 libata-dev (mirror)