1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31 #include <linux/netdevice.h>
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
37 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
);
38 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
);
39 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
);
40 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
);
41 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
);
42 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
44 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
);
45 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
46 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
47 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
);
49 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
);
50 static s32
ixgbe_fc_autoneg_fiber(struct ixgbe_hw
*hw
);
51 static s32
ixgbe_fc_autoneg_backplane(struct ixgbe_hw
*hw
);
52 static s32
ixgbe_fc_autoneg_copper(struct ixgbe_hw
*hw
);
53 static s32
ixgbe_device_supports_autoneg_fc(struct ixgbe_hw
*hw
);
54 static s32
ixgbe_negotiate_fc(struct ixgbe_hw
*hw
, u32 adv_reg
, u32 lp_reg
,
55 u32 adv_sym
, u32 adv_asm
, u32 lp_sym
, u32 lp_asm
);
56 static s32
ixgbe_setup_fc(struct ixgbe_hw
*hw
, s32 packetbuf_num
);
57 static s32
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw
*hw
, u32 ee_reg
);
60 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
61 * @hw: pointer to hardware structure
63 * Starts the hardware by filling the bus info structure and media type, clears
64 * all on chip counters, initializes receive address registers, multicast
65 * table, VLAN filter table, calls routine to set up link and flow control
66 * settings, and leaves transmit and receive units disabled and uninitialized
68 s32
ixgbe_start_hw_generic(struct ixgbe_hw
*hw
)
72 /* Set the media type */
73 hw
->phy
.media_type
= hw
->mac
.ops
.get_media_type(hw
);
75 /* Identify the PHY */
76 hw
->phy
.ops
.identify(hw
);
78 /* Clear the VLAN filter table */
79 hw
->mac
.ops
.clear_vfta(hw
);
81 /* Clear statistics registers */
82 hw
->mac
.ops
.clear_hw_cntrs(hw
);
84 /* Set No Snoop Disable */
85 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
86 ctrl_ext
|= IXGBE_CTRL_EXT_NS_DIS
;
87 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
88 IXGBE_WRITE_FLUSH(hw
);
90 /* Setup flow control */
91 ixgbe_setup_fc(hw
, 0);
93 /* Clear adapter stopped flag */
94 hw
->adapter_stopped
= false;
100 * ixgbe_start_hw_gen2 - Init sequence for common device family
101 * @hw: pointer to hw structure
103 * Performs the init sequence common to the second generation
105 * Devices in the second generation:
109 s32
ixgbe_start_hw_gen2(struct ixgbe_hw
*hw
)
114 /* Clear the rate limiters */
115 for (i
= 0; i
< hw
->mac
.max_tx_queues
; i
++) {
116 IXGBE_WRITE_REG(hw
, IXGBE_RTTDQSEL
, i
);
117 IXGBE_WRITE_REG(hw
, IXGBE_RTTBCNRC
, 0);
119 IXGBE_WRITE_FLUSH(hw
);
121 /* Disable relaxed ordering */
122 for (i
= 0; i
< hw
->mac
.max_tx_queues
; i
++) {
123 regval
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(i
));
124 regval
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
125 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(i
), regval
);
128 for (i
= 0; i
< hw
->mac
.max_rx_queues
; i
++) {
129 regval
= IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
130 regval
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
131 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
132 IXGBE_WRITE_REG(hw
, IXGBE_DCA_RXCTRL(i
), regval
);
139 * ixgbe_init_hw_generic - Generic hardware initialization
140 * @hw: pointer to hardware structure
142 * Initialize the hardware by resetting the hardware, filling the bus info
143 * structure and media type, clears all on chip counters, initializes receive
144 * address registers, multicast table, VLAN filter table, calls routine to set
145 * up link and flow control settings, and leaves transmit and receive units
146 * disabled and uninitialized
148 s32
ixgbe_init_hw_generic(struct ixgbe_hw
*hw
)
152 /* Reset the hardware */
153 status
= hw
->mac
.ops
.reset_hw(hw
);
157 status
= hw
->mac
.ops
.start_hw(hw
);
164 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
165 * @hw: pointer to hardware structure
167 * Clears all hardware statistics counters by reading them from the hardware
168 * Statistics counters are clear on read.
170 s32
ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw
*hw
)
174 IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
175 IXGBE_READ_REG(hw
, IXGBE_ILLERRC
);
176 IXGBE_READ_REG(hw
, IXGBE_ERRBC
);
177 IXGBE_READ_REG(hw
, IXGBE_MSPDC
);
178 for (i
= 0; i
< 8; i
++)
179 IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
181 IXGBE_READ_REG(hw
, IXGBE_MLFC
);
182 IXGBE_READ_REG(hw
, IXGBE_MRFC
);
183 IXGBE_READ_REG(hw
, IXGBE_RLEC
);
184 IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
185 IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
186 if (hw
->mac
.type
>= ixgbe_mac_82599EB
) {
187 IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
188 IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
190 IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
191 IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
194 for (i
= 0; i
< 8; i
++) {
195 IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
196 IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
197 if (hw
->mac
.type
>= ixgbe_mac_82599EB
) {
198 IXGBE_READ_REG(hw
, IXGBE_PXONRXCNT(i
));
199 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXCNT(i
));
201 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
202 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
205 if (hw
->mac
.type
>= ixgbe_mac_82599EB
)
206 for (i
= 0; i
< 8; i
++)
207 IXGBE_READ_REG(hw
, IXGBE_PXON2OFFCNT(i
));
208 IXGBE_READ_REG(hw
, IXGBE_PRC64
);
209 IXGBE_READ_REG(hw
, IXGBE_PRC127
);
210 IXGBE_READ_REG(hw
, IXGBE_PRC255
);
211 IXGBE_READ_REG(hw
, IXGBE_PRC511
);
212 IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
213 IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
214 IXGBE_READ_REG(hw
, IXGBE_GPRC
);
215 IXGBE_READ_REG(hw
, IXGBE_BPRC
);
216 IXGBE_READ_REG(hw
, IXGBE_MPRC
);
217 IXGBE_READ_REG(hw
, IXGBE_GPTC
);
218 IXGBE_READ_REG(hw
, IXGBE_GORCL
);
219 IXGBE_READ_REG(hw
, IXGBE_GORCH
);
220 IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
221 IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
222 for (i
= 0; i
< 8; i
++)
223 IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
224 IXGBE_READ_REG(hw
, IXGBE_RUC
);
225 IXGBE_READ_REG(hw
, IXGBE_RFC
);
226 IXGBE_READ_REG(hw
, IXGBE_ROC
);
227 IXGBE_READ_REG(hw
, IXGBE_RJC
);
228 IXGBE_READ_REG(hw
, IXGBE_MNGPRC
);
229 IXGBE_READ_REG(hw
, IXGBE_MNGPDC
);
230 IXGBE_READ_REG(hw
, IXGBE_MNGPTC
);
231 IXGBE_READ_REG(hw
, IXGBE_TORL
);
232 IXGBE_READ_REG(hw
, IXGBE_TORH
);
233 IXGBE_READ_REG(hw
, IXGBE_TPR
);
234 IXGBE_READ_REG(hw
, IXGBE_TPT
);
235 IXGBE_READ_REG(hw
, IXGBE_PTC64
);
236 IXGBE_READ_REG(hw
, IXGBE_PTC127
);
237 IXGBE_READ_REG(hw
, IXGBE_PTC255
);
238 IXGBE_READ_REG(hw
, IXGBE_PTC511
);
239 IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
240 IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
241 IXGBE_READ_REG(hw
, IXGBE_MPTC
);
242 IXGBE_READ_REG(hw
, IXGBE_BPTC
);
243 for (i
= 0; i
< 16; i
++) {
244 IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
245 IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
246 if (hw
->mac
.type
>= ixgbe_mac_82599EB
) {
247 IXGBE_READ_REG(hw
, IXGBE_QBRC_L(i
));
248 IXGBE_READ_REG(hw
, IXGBE_QBRC_H(i
));
249 IXGBE_READ_REG(hw
, IXGBE_QBTC_L(i
));
250 IXGBE_READ_REG(hw
, IXGBE_QBTC_H(i
));
251 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
253 IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
254 IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
258 if (hw
->mac
.type
== ixgbe_mac_X540
) {
260 hw
->phy
.ops
.identify(hw
);
261 hw
->phy
.ops
.read_reg(hw
, 0x3, IXGBE_PCRC8ECL
, &i
);
262 hw
->phy
.ops
.read_reg(hw
, 0x3, IXGBE_PCRC8ECH
, &i
);
263 hw
->phy
.ops
.read_reg(hw
, 0x3, IXGBE_LDPCECL
, &i
);
264 hw
->phy
.ops
.read_reg(hw
, 0x3, IXGBE_LDPCECH
, &i
);
271 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
272 * @hw: pointer to hardware structure
273 * @pba_num: stores the part number string from the EEPROM
274 * @pba_num_size: part number string buffer length
276 * Reads the part number string from the EEPROM.
278 s32
ixgbe_read_pba_string_generic(struct ixgbe_hw
*hw
, u8
*pba_num
,
287 if (pba_num
== NULL
) {
288 hw_dbg(hw
, "PBA string buffer was null\n");
289 return IXGBE_ERR_INVALID_ARGUMENT
;
292 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM0_PTR
, &data
);
294 hw_dbg(hw
, "NVM Read Error\n");
298 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM1_PTR
, &pba_ptr
);
300 hw_dbg(hw
, "NVM Read Error\n");
305 * if data is not ptr guard the PBA must be in legacy format which
306 * means pba_ptr is actually our second data word for the PBA number
307 * and we can decode it into an ascii string
309 if (data
!= IXGBE_PBANUM_PTR_GUARD
) {
310 hw_dbg(hw
, "NVM PBA number is not stored as string\n");
312 /* we will need 11 characters to store the PBA */
313 if (pba_num_size
< 11) {
314 hw_dbg(hw
, "PBA string buffer too small\n");
315 return IXGBE_ERR_NO_SPACE
;
318 /* extract hex string from data and pba_ptr */
319 pba_num
[0] = (data
>> 12) & 0xF;
320 pba_num
[1] = (data
>> 8) & 0xF;
321 pba_num
[2] = (data
>> 4) & 0xF;
322 pba_num
[3] = data
& 0xF;
323 pba_num
[4] = (pba_ptr
>> 12) & 0xF;
324 pba_num
[5] = (pba_ptr
>> 8) & 0xF;
327 pba_num
[8] = (pba_ptr
>> 4) & 0xF;
328 pba_num
[9] = pba_ptr
& 0xF;
330 /* put a null character on the end of our string */
333 /* switch all the data but the '-' to hex char */
334 for (offset
= 0; offset
< 10; offset
++) {
335 if (pba_num
[offset
] < 0xA)
336 pba_num
[offset
] += '0';
337 else if (pba_num
[offset
] < 0x10)
338 pba_num
[offset
] += 'A' - 0xA;
344 ret_val
= hw
->eeprom
.ops
.read(hw
, pba_ptr
, &length
);
346 hw_dbg(hw
, "NVM Read Error\n");
350 if (length
== 0xFFFF || length
== 0) {
351 hw_dbg(hw
, "NVM PBA number section invalid length\n");
352 return IXGBE_ERR_PBA_SECTION
;
355 /* check if pba_num buffer is big enough */
356 if (pba_num_size
< (((u32
)length
* 2) - 1)) {
357 hw_dbg(hw
, "PBA string buffer too small\n");
358 return IXGBE_ERR_NO_SPACE
;
361 /* trim pba length from start of string */
365 for (offset
= 0; offset
< length
; offset
++) {
366 ret_val
= hw
->eeprom
.ops
.read(hw
, pba_ptr
+ offset
, &data
);
368 hw_dbg(hw
, "NVM Read Error\n");
371 pba_num
[offset
* 2] = (u8
)(data
>> 8);
372 pba_num
[(offset
* 2) + 1] = (u8
)(data
& 0xFF);
374 pba_num
[offset
* 2] = '\0';
380 * ixgbe_get_mac_addr_generic - Generic get MAC address
381 * @hw: pointer to hardware structure
382 * @mac_addr: Adapter MAC address
384 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
385 * A reset of the adapter must be performed prior to calling this function
386 * in order for the MAC address to have been loaded from the EEPROM into RAR0
388 s32
ixgbe_get_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*mac_addr
)
394 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(0));
395 rar_low
= IXGBE_READ_REG(hw
, IXGBE_RAL(0));
397 for (i
= 0; i
< 4; i
++)
398 mac_addr
[i
] = (u8
)(rar_low
>> (i
*8));
400 for (i
= 0; i
< 2; i
++)
401 mac_addr
[i
+4] = (u8
)(rar_high
>> (i
*8));
407 * ixgbe_get_bus_info_generic - Generic set PCI bus info
408 * @hw: pointer to hardware structure
410 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
412 s32
ixgbe_get_bus_info_generic(struct ixgbe_hw
*hw
)
414 struct ixgbe_adapter
*adapter
= hw
->back
;
415 struct ixgbe_mac_info
*mac
= &hw
->mac
;
418 hw
->bus
.type
= ixgbe_bus_type_pci_express
;
420 /* Get the negotiated link width and speed from PCI config space */
421 pci_read_config_word(adapter
->pdev
, IXGBE_PCI_LINK_STATUS
,
424 switch (link_status
& IXGBE_PCI_LINK_WIDTH
) {
425 case IXGBE_PCI_LINK_WIDTH_1
:
426 hw
->bus
.width
= ixgbe_bus_width_pcie_x1
;
428 case IXGBE_PCI_LINK_WIDTH_2
:
429 hw
->bus
.width
= ixgbe_bus_width_pcie_x2
;
431 case IXGBE_PCI_LINK_WIDTH_4
:
432 hw
->bus
.width
= ixgbe_bus_width_pcie_x4
;
434 case IXGBE_PCI_LINK_WIDTH_8
:
435 hw
->bus
.width
= ixgbe_bus_width_pcie_x8
;
438 hw
->bus
.width
= ixgbe_bus_width_unknown
;
442 switch (link_status
& IXGBE_PCI_LINK_SPEED
) {
443 case IXGBE_PCI_LINK_SPEED_2500
:
444 hw
->bus
.speed
= ixgbe_bus_speed_2500
;
446 case IXGBE_PCI_LINK_SPEED_5000
:
447 hw
->bus
.speed
= ixgbe_bus_speed_5000
;
450 hw
->bus
.speed
= ixgbe_bus_speed_unknown
;
454 mac
->ops
.set_lan_id(hw
);
460 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
461 * @hw: pointer to the HW structure
463 * Determines the LAN function id by reading memory-mapped registers
464 * and swaps the port value if requested.
466 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw
*hw
)
468 struct ixgbe_bus_info
*bus
= &hw
->bus
;
471 reg
= IXGBE_READ_REG(hw
, IXGBE_STATUS
);
472 bus
->func
= (reg
& IXGBE_STATUS_LAN_ID
) >> IXGBE_STATUS_LAN_ID_SHIFT
;
473 bus
->lan_id
= bus
->func
;
475 /* check for a port swap */
476 reg
= IXGBE_READ_REG(hw
, IXGBE_FACTPS
);
477 if (reg
& IXGBE_FACTPS_LFS
)
482 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
483 * @hw: pointer to hardware structure
485 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
486 * disables transmit and receive units. The adapter_stopped flag is used by
487 * the shared code and drivers to determine if the adapter is in a stopped
488 * state and should not touch the hardware.
490 s32
ixgbe_stop_adapter_generic(struct ixgbe_hw
*hw
)
492 u32 number_of_queues
;
497 * Set the adapter_stopped flag so other driver functions stop touching
500 hw
->adapter_stopped
= true;
502 /* Disable the receive unit */
503 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
504 reg_val
&= ~(IXGBE_RXCTRL_RXEN
);
505 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, reg_val
);
506 IXGBE_WRITE_FLUSH(hw
);
507 usleep_range(2000, 4000);
509 /* Clear interrupt mask to stop from interrupts being generated */
510 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
512 /* Clear any pending interrupts */
513 IXGBE_READ_REG(hw
, IXGBE_EICR
);
515 /* Disable the transmit unit. Each queue must be disabled. */
516 number_of_queues
= hw
->mac
.max_tx_queues
;
517 for (i
= 0; i
< number_of_queues
; i
++) {
518 reg_val
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
519 if (reg_val
& IXGBE_TXDCTL_ENABLE
) {
520 reg_val
&= ~IXGBE_TXDCTL_ENABLE
;
521 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(i
), reg_val
);
526 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
527 * access and verify no pending requests
529 ixgbe_disable_pcie_master(hw
);
535 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
536 * @hw: pointer to hardware structure
537 * @index: led number to turn on
539 s32
ixgbe_led_on_generic(struct ixgbe_hw
*hw
, u32 index
)
541 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
543 /* To turn on the LED, set mode to ON. */
544 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
545 led_reg
|= IXGBE_LED_ON
<< IXGBE_LED_MODE_SHIFT(index
);
546 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
547 IXGBE_WRITE_FLUSH(hw
);
553 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
554 * @hw: pointer to hardware structure
555 * @index: led number to turn off
557 s32
ixgbe_led_off_generic(struct ixgbe_hw
*hw
, u32 index
)
559 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
561 /* To turn off the LED, set mode to OFF. */
562 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
563 led_reg
|= IXGBE_LED_OFF
<< IXGBE_LED_MODE_SHIFT(index
);
564 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
565 IXGBE_WRITE_FLUSH(hw
);
571 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
572 * @hw: pointer to hardware structure
574 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
575 * ixgbe_hw struct in order to set up EEPROM access.
577 s32
ixgbe_init_eeprom_params_generic(struct ixgbe_hw
*hw
)
579 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
583 if (eeprom
->type
== ixgbe_eeprom_uninitialized
) {
584 eeprom
->type
= ixgbe_eeprom_none
;
585 /* Set default semaphore delay to 10ms which is a well
587 eeprom
->semaphore_delay
= 10;
590 * Check for EEPROM present first.
591 * If not present leave as none
593 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
594 if (eec
& IXGBE_EEC_PRES
) {
595 eeprom
->type
= ixgbe_eeprom_spi
;
598 * SPI EEPROM is assumed here. This code would need to
599 * change if a future EEPROM is not SPI.
601 eeprom_size
= (u16
)((eec
& IXGBE_EEC_SIZE
) >>
602 IXGBE_EEC_SIZE_SHIFT
);
603 eeprom
->word_size
= 1 << (eeprom_size
+
604 IXGBE_EEPROM_WORD_SIZE_SHIFT
);
607 if (eec
& IXGBE_EEC_ADDR_SIZE
)
608 eeprom
->address_bits
= 16;
610 eeprom
->address_bits
= 8;
611 hw_dbg(hw
, "Eeprom params: type = %d, size = %d, address bits: "
612 "%d\n", eeprom
->type
, eeprom
->word_size
,
613 eeprom
->address_bits
);
620 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
621 * @hw: pointer to hardware structure
622 * @offset: offset within the EEPROM to be written to
623 * @data: 16 bit word to be written to the EEPROM
625 * If ixgbe_eeprom_update_checksum is not called after this function, the
626 * EEPROM will most likely contain an invalid checksum.
628 s32
ixgbe_write_eeprom_generic(struct ixgbe_hw
*hw
, u16 offset
, u16 data
)
631 u8 write_opcode
= IXGBE_EEPROM_WRITE_OPCODE_SPI
;
633 hw
->eeprom
.ops
.init_params(hw
);
635 if (offset
>= hw
->eeprom
.word_size
) {
636 status
= IXGBE_ERR_EEPROM
;
640 /* Prepare the EEPROM for writing */
641 status
= ixgbe_acquire_eeprom(hw
);
644 if (ixgbe_ready_eeprom(hw
) != 0) {
645 ixgbe_release_eeprom(hw
);
646 status
= IXGBE_ERR_EEPROM
;
651 ixgbe_standby_eeprom(hw
);
653 /* Send the WRITE ENABLE command (8 bit opcode ) */
654 ixgbe_shift_out_eeprom_bits(hw
, IXGBE_EEPROM_WREN_OPCODE_SPI
,
655 IXGBE_EEPROM_OPCODE_BITS
);
657 ixgbe_standby_eeprom(hw
);
660 * Some SPI eeproms use the 8th address bit embedded in the
663 if ((hw
->eeprom
.address_bits
== 8) && (offset
>= 128))
664 write_opcode
|= IXGBE_EEPROM_A8_OPCODE_SPI
;
666 /* Send the Write command (8-bit opcode + addr) */
667 ixgbe_shift_out_eeprom_bits(hw
, write_opcode
,
668 IXGBE_EEPROM_OPCODE_BITS
);
669 ixgbe_shift_out_eeprom_bits(hw
, (u16
)(offset
*2),
670 hw
->eeprom
.address_bits
);
673 data
= (data
>> 8) | (data
<< 8);
674 ixgbe_shift_out_eeprom_bits(hw
, data
, 16);
675 ixgbe_standby_eeprom(hw
);
677 /* Done with writing - release the EEPROM */
678 ixgbe_release_eeprom(hw
);
686 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
687 * @hw: pointer to hardware structure
688 * @offset: offset within the EEPROM to be read
689 * @data: read 16 bit value from EEPROM
691 * Reads 16 bit value from EEPROM through bit-bang method
693 s32
ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
698 u8 read_opcode
= IXGBE_EEPROM_READ_OPCODE_SPI
;
700 hw
->eeprom
.ops
.init_params(hw
);
702 if (offset
>= hw
->eeprom
.word_size
) {
703 status
= IXGBE_ERR_EEPROM
;
707 /* Prepare the EEPROM for reading */
708 status
= ixgbe_acquire_eeprom(hw
);
711 if (ixgbe_ready_eeprom(hw
) != 0) {
712 ixgbe_release_eeprom(hw
);
713 status
= IXGBE_ERR_EEPROM
;
718 ixgbe_standby_eeprom(hw
);
721 * Some SPI eeproms use the 8th address bit embedded in the
724 if ((hw
->eeprom
.address_bits
== 8) && (offset
>= 128))
725 read_opcode
|= IXGBE_EEPROM_A8_OPCODE_SPI
;
727 /* Send the READ command (opcode + addr) */
728 ixgbe_shift_out_eeprom_bits(hw
, read_opcode
,
729 IXGBE_EEPROM_OPCODE_BITS
);
730 ixgbe_shift_out_eeprom_bits(hw
, (u16
)(offset
*2),
731 hw
->eeprom
.address_bits
);
734 word_in
= ixgbe_shift_in_eeprom_bits(hw
, 16);
735 *data
= (word_in
>> 8) | (word_in
<< 8);
737 /* End this read operation */
738 ixgbe_release_eeprom(hw
);
746 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
747 * @hw: pointer to hardware structure
748 * @offset: offset of word in the EEPROM to read
749 * @data: word read from the EEPROM
751 * Reads a 16 bit word from the EEPROM using the EERD register.
753 s32
ixgbe_read_eerd_generic(struct ixgbe_hw
*hw
, u16 offset
, u16
*data
)
758 hw
->eeprom
.ops
.init_params(hw
);
760 if (offset
>= hw
->eeprom
.word_size
) {
761 status
= IXGBE_ERR_EEPROM
;
765 eerd
= (offset
<< IXGBE_EEPROM_RW_ADDR_SHIFT
) +
766 IXGBE_EEPROM_RW_REG_START
;
768 IXGBE_WRITE_REG(hw
, IXGBE_EERD
, eerd
);
769 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_READ
);
772 *data
= (IXGBE_READ_REG(hw
, IXGBE_EERD
) >>
773 IXGBE_EEPROM_RW_REG_DATA
);
775 hw_dbg(hw
, "Eeprom read timed out\n");
782 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
783 * @hw: pointer to hardware structure
784 * @offset: offset of word in the EEPROM to write
785 * @data: word write to the EEPROM
787 * Write a 16 bit word to the EEPROM using the EEWR register.
789 s32
ixgbe_write_eewr_generic(struct ixgbe_hw
*hw
, u16 offset
, u16 data
)
794 hw
->eeprom
.ops
.init_params(hw
);
796 if (offset
>= hw
->eeprom
.word_size
) {
797 status
= IXGBE_ERR_EEPROM
;
801 eewr
= (offset
<< IXGBE_EEPROM_RW_ADDR_SHIFT
) |
802 (data
<< IXGBE_EEPROM_RW_REG_DATA
) | IXGBE_EEPROM_RW_REG_START
;
804 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_WRITE
);
806 hw_dbg(hw
, "Eeprom write EEWR timed out\n");
810 IXGBE_WRITE_REG(hw
, IXGBE_EEWR
, eewr
);
812 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_WRITE
);
814 hw_dbg(hw
, "Eeprom write EEWR timed out\n");
823 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
824 * @hw: pointer to hardware structure
825 * @ee_reg: EEPROM flag for polling
827 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
828 * read or write is done respectively.
830 static s32
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw
*hw
, u32 ee_reg
)
834 s32 status
= IXGBE_ERR_EEPROM
;
836 for (i
= 0; i
< IXGBE_EERD_EEWR_ATTEMPTS
; i
++) {
837 if (ee_reg
== IXGBE_NVM_POLL_READ
)
838 reg
= IXGBE_READ_REG(hw
, IXGBE_EERD
);
840 reg
= IXGBE_READ_REG(hw
, IXGBE_EEWR
);
842 if (reg
& IXGBE_EEPROM_RW_REG_DONE
) {
852 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
853 * @hw: pointer to hardware structure
855 * Prepares EEPROM for access using bit-bang method. This function should
856 * be called before issuing a command to the EEPROM.
858 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
)
864 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) != 0)
865 status
= IXGBE_ERR_SWFW_SYNC
;
868 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
870 /* Request EEPROM Access */
871 eec
|= IXGBE_EEC_REQ
;
872 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
874 for (i
= 0; i
< IXGBE_EEPROM_GRANT_ATTEMPTS
; i
++) {
875 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
876 if (eec
& IXGBE_EEC_GNT
)
881 /* Release if grant not acquired */
882 if (!(eec
& IXGBE_EEC_GNT
)) {
883 eec
&= ~IXGBE_EEC_REQ
;
884 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
885 hw_dbg(hw
, "Could not acquire EEPROM grant\n");
887 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
888 status
= IXGBE_ERR_EEPROM
;
891 /* Setup EEPROM for Read/Write */
893 /* Clear CS and SK */
894 eec
&= ~(IXGBE_EEC_CS
| IXGBE_EEC_SK
);
895 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
896 IXGBE_WRITE_FLUSH(hw
);
904 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
905 * @hw: pointer to hardware structure
907 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
909 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
)
911 s32 status
= IXGBE_ERR_EEPROM
;
916 /* Get SMBI software semaphore between device drivers first */
917 for (i
= 0; i
< timeout
; i
++) {
919 * If the SMBI bit is 0 when we read it, then the bit will be
920 * set and we have the semaphore
922 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
923 if (!(swsm
& IXGBE_SWSM_SMBI
)) {
930 /* Now get the semaphore between SW/FW through the SWESMBI bit */
932 for (i
= 0; i
< timeout
; i
++) {
933 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
935 /* Set the SW EEPROM semaphore bit to request access */
936 swsm
|= IXGBE_SWSM_SWESMBI
;
937 IXGBE_WRITE_REG(hw
, IXGBE_SWSM
, swsm
);
940 * If we set the bit successfully then we got the
943 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
944 if (swsm
& IXGBE_SWSM_SWESMBI
)
951 * Release semaphores and return error if SW EEPROM semaphore
952 * was not granted because we don't have access to the EEPROM
955 hw_dbg(hw
, "SWESMBI Software EEPROM semaphore "
957 ixgbe_release_eeprom_semaphore(hw
);
958 status
= IXGBE_ERR_EEPROM
;
961 hw_dbg(hw
, "Software semaphore SMBI between device drivers "
969 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
970 * @hw: pointer to hardware structure
972 * This function clears hardware semaphore bits.
974 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
)
978 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
980 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
981 swsm
&= ~(IXGBE_SWSM_SWESMBI
| IXGBE_SWSM_SMBI
);
982 IXGBE_WRITE_REG(hw
, IXGBE_SWSM
, swsm
);
983 IXGBE_WRITE_FLUSH(hw
);
987 * ixgbe_ready_eeprom - Polls for EEPROM ready
988 * @hw: pointer to hardware structure
990 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
)
997 * Read "Status Register" repeatedly until the LSB is cleared. The
998 * EEPROM will signal that the command has been completed by clearing
999 * bit 0 of the internal status register. If it's not cleared within
1000 * 5 milliseconds, then error out.
1002 for (i
= 0; i
< IXGBE_EEPROM_MAX_RETRY_SPI
; i
+= 5) {
1003 ixgbe_shift_out_eeprom_bits(hw
, IXGBE_EEPROM_RDSR_OPCODE_SPI
,
1004 IXGBE_EEPROM_OPCODE_BITS
);
1005 spi_stat_reg
= (u8
)ixgbe_shift_in_eeprom_bits(hw
, 8);
1006 if (!(spi_stat_reg
& IXGBE_EEPROM_STATUS_RDY_SPI
))
1010 ixgbe_standby_eeprom(hw
);
1014 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1015 * devices (and only 0-5mSec on 5V devices)
1017 if (i
>= IXGBE_EEPROM_MAX_RETRY_SPI
) {
1018 hw_dbg(hw
, "SPI EEPROM Status error\n");
1019 status
= IXGBE_ERR_EEPROM
;
1026 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1027 * @hw: pointer to hardware structure
1029 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
)
1033 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1035 /* Toggle CS to flush commands */
1036 eec
|= IXGBE_EEC_CS
;
1037 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1038 IXGBE_WRITE_FLUSH(hw
);
1040 eec
&= ~IXGBE_EEC_CS
;
1041 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1042 IXGBE_WRITE_FLUSH(hw
);
1047 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1048 * @hw: pointer to hardware structure
1049 * @data: data to send to the EEPROM
1050 * @count: number of bits to shift out
1052 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
1059 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1062 * Mask is used to shift "count" bits of "data" out to the EEPROM
1063 * one bit at a time. Determine the starting bit based on count
1065 mask
= 0x01 << (count
- 1);
1067 for (i
= 0; i
< count
; i
++) {
1069 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1070 * "1", and then raising and then lowering the clock (the SK
1071 * bit controls the clock input to the EEPROM). A "0" is
1072 * shifted out to the EEPROM by setting "DI" to "0" and then
1073 * raising and then lowering the clock.
1076 eec
|= IXGBE_EEC_DI
;
1078 eec
&= ~IXGBE_EEC_DI
;
1080 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1081 IXGBE_WRITE_FLUSH(hw
);
1085 ixgbe_raise_eeprom_clk(hw
, &eec
);
1086 ixgbe_lower_eeprom_clk(hw
, &eec
);
1089 * Shift mask to signify next bit of data to shift in to the
1095 /* We leave the "DI" bit set to "0" when we leave this routine. */
1096 eec
&= ~IXGBE_EEC_DI
;
1097 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1098 IXGBE_WRITE_FLUSH(hw
);
1102 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1103 * @hw: pointer to hardware structure
1105 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
)
1112 * In order to read a register from the EEPROM, we need to shift
1113 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1114 * the clock input to the EEPROM (setting the SK bit), and then reading
1115 * the value of the "DO" bit. During this "shifting in" process the
1116 * "DI" bit should always be clear.
1118 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1120 eec
&= ~(IXGBE_EEC_DO
| IXGBE_EEC_DI
);
1122 for (i
= 0; i
< count
; i
++) {
1124 ixgbe_raise_eeprom_clk(hw
, &eec
);
1126 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1128 eec
&= ~(IXGBE_EEC_DI
);
1129 if (eec
& IXGBE_EEC_DO
)
1132 ixgbe_lower_eeprom_clk(hw
, &eec
);
1139 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1140 * @hw: pointer to hardware structure
1141 * @eec: EEC register's current value
1143 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
1146 * Raise the clock input to the EEPROM
1147 * (setting the SK bit), then delay
1149 *eec
= *eec
| IXGBE_EEC_SK
;
1150 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, *eec
);
1151 IXGBE_WRITE_FLUSH(hw
);
1156 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1157 * @hw: pointer to hardware structure
1158 * @eecd: EECD's current value
1160 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
1163 * Lower the clock input to the EEPROM (clearing the SK bit), then
1166 *eec
= *eec
& ~IXGBE_EEC_SK
;
1167 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, *eec
);
1168 IXGBE_WRITE_FLUSH(hw
);
1173 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1174 * @hw: pointer to hardware structure
1176 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
)
1180 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1182 eec
|= IXGBE_EEC_CS
; /* Pull CS high */
1183 eec
&= ~IXGBE_EEC_SK
; /* Lower SCK */
1185 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1186 IXGBE_WRITE_FLUSH(hw
);
1190 /* Stop requesting EEPROM access */
1191 eec
&= ~IXGBE_EEC_REQ
;
1192 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1194 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
1197 * Delay before attempt to obtain semaphore again to allow FW
1198 * access. semaphore_delay is in ms we need us for usleep_range
1200 usleep_range(hw
->eeprom
.semaphore_delay
* 1000,
1201 hw
->eeprom
.semaphore_delay
* 2000);
1205 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1206 * @hw: pointer to hardware structure
1208 u16
ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw
*hw
)
1217 /* Include 0x0-0x3F in the checksum */
1218 for (i
= 0; i
< IXGBE_EEPROM_CHECKSUM
; i
++) {
1219 if (hw
->eeprom
.ops
.read(hw
, i
, &word
) != 0) {
1220 hw_dbg(hw
, "EEPROM read failed\n");
1226 /* Include all data from pointers except for the fw pointer */
1227 for (i
= IXGBE_PCIE_ANALOG_PTR
; i
< IXGBE_FW_PTR
; i
++) {
1228 hw
->eeprom
.ops
.read(hw
, i
, &pointer
);
1230 /* Make sure the pointer seems valid */
1231 if (pointer
!= 0xFFFF && pointer
!= 0) {
1232 hw
->eeprom
.ops
.read(hw
, pointer
, &length
);
1234 if (length
!= 0xFFFF && length
!= 0) {
1235 for (j
= pointer
+1; j
<= pointer
+length
; j
++) {
1236 hw
->eeprom
.ops
.read(hw
, j
, &word
);
1243 checksum
= (u16
)IXGBE_EEPROM_SUM
- checksum
;
1249 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1250 * @hw: pointer to hardware structure
1251 * @checksum_val: calculated checksum
1253 * Performs checksum calculation and validates the EEPROM checksum. If the
1254 * caller does not need checksum_val, the value can be NULL.
1256 s32
ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw
*hw
,
1261 u16 read_checksum
= 0;
1264 * Read the first word from the EEPROM. If this times out or fails, do
1265 * not continue or we could be in for a very long wait while every
1268 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
1271 checksum
= hw
->eeprom
.ops
.calc_checksum(hw
);
1273 hw
->eeprom
.ops
.read(hw
, IXGBE_EEPROM_CHECKSUM
, &read_checksum
);
1276 * Verify read checksum from EEPROM is the same as
1277 * calculated checksum
1279 if (read_checksum
!= checksum
)
1280 status
= IXGBE_ERR_EEPROM_CHECKSUM
;
1282 /* If the user cares, return the calculated checksum */
1284 *checksum_val
= checksum
;
1286 hw_dbg(hw
, "EEPROM read failed\n");
1293 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1294 * @hw: pointer to hardware structure
1296 s32
ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw
*hw
)
1302 * Read the first word from the EEPROM. If this times out or fails, do
1303 * not continue or we could be in for a very long wait while every
1306 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
1309 checksum
= hw
->eeprom
.ops
.calc_checksum(hw
);
1310 status
= hw
->eeprom
.ops
.write(hw
, IXGBE_EEPROM_CHECKSUM
,
1313 hw_dbg(hw
, "EEPROM read failed\n");
1320 * ixgbe_validate_mac_addr - Validate MAC address
1321 * @mac_addr: pointer to MAC address.
1323 * Tests a MAC address to ensure it is a valid Individual Address
1325 s32
ixgbe_validate_mac_addr(u8
*mac_addr
)
1329 /* Make sure it is not a multicast address */
1330 if (IXGBE_IS_MULTICAST(mac_addr
))
1331 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1332 /* Not a broadcast address */
1333 else if (IXGBE_IS_BROADCAST(mac_addr
))
1334 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1335 /* Reject the zero address */
1336 else if (mac_addr
[0] == 0 && mac_addr
[1] == 0 && mac_addr
[2] == 0 &&
1337 mac_addr
[3] == 0 && mac_addr
[4] == 0 && mac_addr
[5] == 0)
1338 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1344 * ixgbe_set_rar_generic - Set Rx address register
1345 * @hw: pointer to hardware structure
1346 * @index: Receive address register to write
1347 * @addr: Address to put into receive address register
1348 * @vmdq: VMDq "set" or "pool" index
1349 * @enable_addr: set flag that address is active
1351 * Puts an ethernet address into a receive address register.
1353 s32
ixgbe_set_rar_generic(struct ixgbe_hw
*hw
, u32 index
, u8
*addr
, u32 vmdq
,
1356 u32 rar_low
, rar_high
;
1357 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1359 /* Make sure we are using a valid rar index range */
1360 if (index
>= rar_entries
) {
1361 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1362 return IXGBE_ERR_INVALID_ARGUMENT
;
1365 /* setup VMDq pool selection before this RAR gets enabled */
1366 hw
->mac
.ops
.set_vmdq(hw
, index
, vmdq
);
1369 * HW expects these in little endian so we reverse the byte
1370 * order from network order (big endian) to little endian
1372 rar_low
= ((u32
)addr
[0] |
1373 ((u32
)addr
[1] << 8) |
1374 ((u32
)addr
[2] << 16) |
1375 ((u32
)addr
[3] << 24));
1377 * Some parts put the VMDq setting in the extra RAH bits,
1378 * so save everything except the lower 16 bits that hold part
1379 * of the address and the address valid bit.
1381 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1382 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1383 rar_high
|= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1385 if (enable_addr
!= 0)
1386 rar_high
|= IXGBE_RAH_AV
;
1388 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), rar_low
);
1389 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1395 * ixgbe_clear_rar_generic - Remove Rx address register
1396 * @hw: pointer to hardware structure
1397 * @index: Receive address register to write
1399 * Clears an ethernet address from a receive address register.
1401 s32
ixgbe_clear_rar_generic(struct ixgbe_hw
*hw
, u32 index
)
1404 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1406 /* Make sure we are using a valid rar index range */
1407 if (index
>= rar_entries
) {
1408 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1409 return IXGBE_ERR_INVALID_ARGUMENT
;
1413 * Some parts put the VMDq setting in the extra RAH bits,
1414 * so save everything except the lower 16 bits that hold part
1415 * of the address and the address valid bit.
1417 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1418 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1420 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), 0);
1421 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1423 /* clear VMDq pool/queue selection for this RAR */
1424 hw
->mac
.ops
.clear_vmdq(hw
, index
, IXGBE_CLEAR_VMDQ_ALL
);
1430 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1431 * @hw: pointer to hardware structure
1433 * Places the MAC address in receive address register 0 and clears the rest
1434 * of the receive address registers. Clears the multicast table. Assumes
1435 * the receiver is in reset when the routine is called.
1437 s32
ixgbe_init_rx_addrs_generic(struct ixgbe_hw
*hw
)
1440 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1443 * If the current mac address is valid, assume it is a software override
1444 * to the permanent address.
1445 * Otherwise, use the permanent address from the eeprom.
1447 if (ixgbe_validate_mac_addr(hw
->mac
.addr
) ==
1448 IXGBE_ERR_INVALID_MAC_ADDR
) {
1449 /* Get the MAC address from the RAR0 for later reference */
1450 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.addr
);
1452 hw_dbg(hw
, " Keeping Current RAR0 Addr =%pM\n", hw
->mac
.addr
);
1454 /* Setup the receive address. */
1455 hw_dbg(hw
, "Overriding MAC Address in RAR[0]\n");
1456 hw_dbg(hw
, " New MAC Addr =%pM\n", hw
->mac
.addr
);
1458 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, 0, IXGBE_RAH_AV
);
1460 /* clear VMDq pool/queue selection for RAR 0 */
1461 hw
->mac
.ops
.clear_vmdq(hw
, 0, IXGBE_CLEAR_VMDQ_ALL
);
1463 hw
->addr_ctrl
.overflow_promisc
= 0;
1465 hw
->addr_ctrl
.rar_used_count
= 1;
1467 /* Zero out the other receive addresses. */
1468 hw_dbg(hw
, "Clearing RAR[1-%d]\n", rar_entries
- 1);
1469 for (i
= 1; i
< rar_entries
; i
++) {
1470 IXGBE_WRITE_REG(hw
, IXGBE_RAL(i
), 0);
1471 IXGBE_WRITE_REG(hw
, IXGBE_RAH(i
), 0);
1475 hw
->addr_ctrl
.mta_in_use
= 0;
1476 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
1478 hw_dbg(hw
, " Clearing MTA\n");
1479 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
1480 IXGBE_WRITE_REG(hw
, IXGBE_MTA(i
), 0);
1482 if (hw
->mac
.ops
.init_uta_tables
)
1483 hw
->mac
.ops
.init_uta_tables(hw
);
1489 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1490 * @hw: pointer to hardware structure
1491 * @mc_addr: the multicast address
1493 * Extracts the 12 bits, from a multicast address, to determine which
1494 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1495 * incoming rx multicast addresses, to determine the bit-vector to check in
1496 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1497 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1498 * to mc_filter_type.
1500 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1504 switch (hw
->mac
.mc_filter_type
) {
1505 case 0: /* use bits [47:36] of the address */
1506 vector
= ((mc_addr
[4] >> 4) | (((u16
)mc_addr
[5]) << 4));
1508 case 1: /* use bits [46:35] of the address */
1509 vector
= ((mc_addr
[4] >> 3) | (((u16
)mc_addr
[5]) << 5));
1511 case 2: /* use bits [45:34] of the address */
1512 vector
= ((mc_addr
[4] >> 2) | (((u16
)mc_addr
[5]) << 6));
1514 case 3: /* use bits [43:32] of the address */
1515 vector
= ((mc_addr
[4]) | (((u16
)mc_addr
[5]) << 8));
1517 default: /* Invalid mc_filter_type */
1518 hw_dbg(hw
, "MC filter type param set incorrectly\n");
1522 /* vector can only be 12-bits or boundary will be exceeded */
1528 * ixgbe_set_mta - Set bit-vector in multicast table
1529 * @hw: pointer to hardware structure
1530 * @hash_value: Multicast address hash value
1532 * Sets the bit-vector in the multicast table.
1534 static void ixgbe_set_mta(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1540 hw
->addr_ctrl
.mta_in_use
++;
1542 vector
= ixgbe_mta_vector(hw
, mc_addr
);
1543 hw_dbg(hw
, " bit-vector = 0x%03X\n", vector
);
1546 * The MTA is a register array of 128 32-bit registers. It is treated
1547 * like an array of 4096 bits. We want to set bit
1548 * BitArray[vector_value]. So we figure out what register the bit is
1549 * in, read it, OR in the new bit, then write back the new value. The
1550 * register is determined by the upper 7 bits of the vector value and
1551 * the bit within that register are determined by the lower 5 bits of
1554 vector_reg
= (vector
>> 5) & 0x7F;
1555 vector_bit
= vector
& 0x1F;
1556 hw
->mac
.mta_shadow
[vector_reg
] |= (1 << vector_bit
);
1560 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1561 * @hw: pointer to hardware structure
1562 * @netdev: pointer to net device structure
1564 * The given list replaces any existing list. Clears the MC addrs from receive
1565 * address registers and the multicast table. Uses unused receive address
1566 * registers for the first multicast addresses, and hashes the rest into the
1569 s32
ixgbe_update_mc_addr_list_generic(struct ixgbe_hw
*hw
,
1570 struct net_device
*netdev
)
1572 struct netdev_hw_addr
*ha
;
1576 * Set the new number of MC addresses that we are being requested to
1579 hw
->addr_ctrl
.num_mc_addrs
= netdev_mc_count(netdev
);
1580 hw
->addr_ctrl
.mta_in_use
= 0;
1582 /* Clear mta_shadow */
1583 hw_dbg(hw
, " Clearing MTA\n");
1584 memset(&hw
->mac
.mta_shadow
, 0, sizeof(hw
->mac
.mta_shadow
));
1586 /* Update mta shadow */
1587 netdev_for_each_mc_addr(ha
, netdev
) {
1588 hw_dbg(hw
, " Adding the multicast addresses:\n");
1589 ixgbe_set_mta(hw
, ha
->addr
);
1593 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
1594 IXGBE_WRITE_REG_ARRAY(hw
, IXGBE_MTA(0), i
,
1595 hw
->mac
.mta_shadow
[i
]);
1597 if (hw
->addr_ctrl
.mta_in_use
> 0)
1598 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
,
1599 IXGBE_MCSTCTRL_MFE
| hw
->mac
.mc_filter_type
);
1601 hw_dbg(hw
, "ixgbe_update_mc_addr_list_generic Complete\n");
1606 * ixgbe_enable_mc_generic - Enable multicast address in RAR
1607 * @hw: pointer to hardware structure
1609 * Enables multicast address in RAR and the use of the multicast hash table.
1611 s32
ixgbe_enable_mc_generic(struct ixgbe_hw
*hw
)
1613 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
1615 if (a
->mta_in_use
> 0)
1616 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, IXGBE_MCSTCTRL_MFE
|
1617 hw
->mac
.mc_filter_type
);
1623 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1624 * @hw: pointer to hardware structure
1626 * Disables multicast address in RAR and the use of the multicast hash table.
1628 s32
ixgbe_disable_mc_generic(struct ixgbe_hw
*hw
)
1630 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
1632 if (a
->mta_in_use
> 0)
1633 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
1639 * ixgbe_fc_enable_generic - Enable flow control
1640 * @hw: pointer to hardware structure
1641 * @packetbuf_num: packet buffer number (0-7)
1643 * Enable flow control according to the current settings.
1645 s32
ixgbe_fc_enable_generic(struct ixgbe_hw
*hw
, s32 packetbuf_num
)
1648 u32 mflcn_reg
, fccfg_reg
;
1654 if (hw
->fc
.requested_mode
== ixgbe_fc_pfc
)
1657 #endif /* CONFIG_DCB */
1658 /* Negotiate the fc mode to use */
1659 ret_val
= ixgbe_fc_autoneg(hw
);
1660 if (ret_val
== IXGBE_ERR_FLOW_CONTROL
)
1663 /* Disable any previous flow control settings */
1664 mflcn_reg
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
1665 mflcn_reg
&= ~(IXGBE_MFLCN_RFCE
| IXGBE_MFLCN_RPFCE
);
1667 fccfg_reg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
1668 fccfg_reg
&= ~(IXGBE_FCCFG_TFCE_802_3X
| IXGBE_FCCFG_TFCE_PRIORITY
);
1671 * The possible values of fc.current_mode are:
1672 * 0: Flow control is completely disabled
1673 * 1: Rx flow control is enabled (we can receive pause frames,
1674 * but not send pause frames).
1675 * 2: Tx flow control is enabled (we can send pause frames but
1676 * we do not support receiving pause frames).
1677 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1679 * 4: Priority Flow Control is enabled.
1683 switch (hw
->fc
.current_mode
) {
1686 * Flow control is disabled by software override or autoneg.
1687 * The code below will actually disable it in the HW.
1690 case ixgbe_fc_rx_pause
:
1692 * Rx Flow control is enabled and Tx Flow control is
1693 * disabled by software override. Since there really
1694 * isn't a way to advertise that we are capable of RX
1695 * Pause ONLY, we will advertise that we support both
1696 * symmetric and asymmetric Rx PAUSE. Later, we will
1697 * disable the adapter's ability to send PAUSE frames.
1699 mflcn_reg
|= IXGBE_MFLCN_RFCE
;
1701 case ixgbe_fc_tx_pause
:
1703 * Tx Flow control is enabled, and Rx Flow control is
1704 * disabled by software override.
1706 fccfg_reg
|= IXGBE_FCCFG_TFCE_802_3X
;
1709 /* Flow control (both Rx and Tx) is enabled by SW override. */
1710 mflcn_reg
|= IXGBE_MFLCN_RFCE
;
1711 fccfg_reg
|= IXGBE_FCCFG_TFCE_802_3X
;
1717 #endif /* CONFIG_DCB */
1719 hw_dbg(hw
, "Flow control param set incorrectly\n");
1720 ret_val
= IXGBE_ERR_CONFIG
;
1725 /* Set 802.3x based flow control settings. */
1726 mflcn_reg
|= IXGBE_MFLCN_DPF
;
1727 IXGBE_WRITE_REG(hw
, IXGBE_MFLCN
, mflcn_reg
);
1728 IXGBE_WRITE_REG(hw
, IXGBE_FCCFG
, fccfg_reg
);
1730 rx_pba_size
= IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(packetbuf_num
));
1731 rx_pba_size
>>= IXGBE_RXPBSIZE_SHIFT
;
1733 fcrth
= (rx_pba_size
- hw
->fc
.high_water
) << 10;
1734 fcrtl
= (rx_pba_size
- hw
->fc
.low_water
) << 10;
1736 if (hw
->fc
.current_mode
& ixgbe_fc_tx_pause
) {
1737 fcrth
|= IXGBE_FCRTH_FCEN
;
1738 if (hw
->fc
.send_xon
)
1739 fcrtl
|= IXGBE_FCRTL_XONE
;
1742 IXGBE_WRITE_REG(hw
, IXGBE_FCRTH_82599(packetbuf_num
), fcrth
);
1743 IXGBE_WRITE_REG(hw
, IXGBE_FCRTL_82599(packetbuf_num
), fcrtl
);
1745 /* Configure pause time (2 TCs per register) */
1746 reg
= IXGBE_READ_REG(hw
, IXGBE_FCTTV(packetbuf_num
/ 2));
1747 if ((packetbuf_num
& 1) == 0)
1748 reg
= (reg
& 0xFFFF0000) | hw
->fc
.pause_time
;
1750 reg
= (reg
& 0x0000FFFF) | (hw
->fc
.pause_time
<< 16);
1751 IXGBE_WRITE_REG(hw
, IXGBE_FCTTV(packetbuf_num
/ 2), reg
);
1753 IXGBE_WRITE_REG(hw
, IXGBE_FCRTV
, (hw
->fc
.pause_time
>> 1));
1760 * ixgbe_fc_autoneg - Configure flow control
1761 * @hw: pointer to hardware structure
1763 * Compares our advertised flow control capabilities to those advertised by
1764 * our link partner, and determines the proper flow control mode to use.
1766 s32
ixgbe_fc_autoneg(struct ixgbe_hw
*hw
)
1768 s32 ret_val
= IXGBE_ERR_FC_NOT_NEGOTIATED
;
1769 ixgbe_link_speed speed
;
1772 if (hw
->fc
.disable_fc_autoneg
)
1776 * AN should have completed when the cable was plugged in.
1777 * Look for reasons to bail out. Bail out if:
1778 * - FC autoneg is disabled, or if
1781 * Since we're being called from an LSC, link is already known to be up.
1782 * So use link_up_wait_to_complete=false.
1784 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
1786 ret_val
= IXGBE_ERR_FLOW_CONTROL
;
1790 switch (hw
->phy
.media_type
) {
1791 /* Autoneg flow control on fiber adapters */
1792 case ixgbe_media_type_fiber
:
1793 if (speed
== IXGBE_LINK_SPEED_1GB_FULL
)
1794 ret_val
= ixgbe_fc_autoneg_fiber(hw
);
1797 /* Autoneg flow control on backplane adapters */
1798 case ixgbe_media_type_backplane
:
1799 ret_val
= ixgbe_fc_autoneg_backplane(hw
);
1802 /* Autoneg flow control on copper adapters */
1803 case ixgbe_media_type_copper
:
1804 if (ixgbe_device_supports_autoneg_fc(hw
) == 0)
1805 ret_val
= ixgbe_fc_autoneg_copper(hw
);
1814 hw
->fc
.fc_was_autonegged
= true;
1816 hw
->fc
.fc_was_autonegged
= false;
1817 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1823 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
1824 * @hw: pointer to hardware structure
1826 * Enable flow control according on 1 gig fiber.
1828 static s32
ixgbe_fc_autoneg_fiber(struct ixgbe_hw
*hw
)
1830 u32 pcs_anadv_reg
, pcs_lpab_reg
, linkstat
;
1834 * On multispeed fiber at 1g, bail out if
1835 * - link is up but AN did not complete, or if
1836 * - link is up and AN completed but timed out
1839 linkstat
= IXGBE_READ_REG(hw
, IXGBE_PCS1GLSTA
);
1840 if (((linkstat
& IXGBE_PCS1GLSTA_AN_COMPLETE
) == 0) ||
1841 ((linkstat
& IXGBE_PCS1GLSTA_AN_TIMED_OUT
) == 1)) {
1842 ret_val
= IXGBE_ERR_FC_NOT_NEGOTIATED
;
1846 pcs_anadv_reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANA
);
1847 pcs_lpab_reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANLP
);
1849 ret_val
= ixgbe_negotiate_fc(hw
, pcs_anadv_reg
,
1850 pcs_lpab_reg
, IXGBE_PCS1GANA_SYM_PAUSE
,
1851 IXGBE_PCS1GANA_ASM_PAUSE
,
1852 IXGBE_PCS1GANA_SYM_PAUSE
,
1853 IXGBE_PCS1GANA_ASM_PAUSE
);
1860 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
1861 * @hw: pointer to hardware structure
1863 * Enable flow control according to IEEE clause 37.
1865 static s32
ixgbe_fc_autoneg_backplane(struct ixgbe_hw
*hw
)
1867 u32 links2
, anlp1_reg
, autoc_reg
, links
;
1871 * On backplane, bail out if
1872 * - backplane autoneg was not completed, or if
1873 * - we are 82599 and link partner is not AN enabled
1875 links
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
1876 if ((links
& IXGBE_LINKS_KX_AN_COMP
) == 0) {
1877 hw
->fc
.fc_was_autonegged
= false;
1878 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1879 ret_val
= IXGBE_ERR_FC_NOT_NEGOTIATED
;
1883 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1884 links2
= IXGBE_READ_REG(hw
, IXGBE_LINKS2
);
1885 if ((links2
& IXGBE_LINKS2_AN_SUPPORTED
) == 0) {
1886 hw
->fc
.fc_was_autonegged
= false;
1887 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1888 ret_val
= IXGBE_ERR_FC_NOT_NEGOTIATED
;
1893 * Read the 10g AN autoc and LP ability registers and resolve
1894 * local flow control settings accordingly
1896 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
1897 anlp1_reg
= IXGBE_READ_REG(hw
, IXGBE_ANLP1
);
1899 ret_val
= ixgbe_negotiate_fc(hw
, autoc_reg
,
1900 anlp1_reg
, IXGBE_AUTOC_SYM_PAUSE
, IXGBE_AUTOC_ASM_PAUSE
,
1901 IXGBE_ANLP1_SYM_PAUSE
, IXGBE_ANLP1_ASM_PAUSE
);
1908 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
1909 * @hw: pointer to hardware structure
1911 * Enable flow control according to IEEE clause 37.
1913 static s32
ixgbe_fc_autoneg_copper(struct ixgbe_hw
*hw
)
1915 u16 technology_ability_reg
= 0;
1916 u16 lp_technology_ability_reg
= 0;
1918 hw
->phy
.ops
.read_reg(hw
, MDIO_AN_ADVERTISE
,
1920 &technology_ability_reg
);
1921 hw
->phy
.ops
.read_reg(hw
, MDIO_AN_LPA
,
1923 &lp_technology_ability_reg
);
1925 return ixgbe_negotiate_fc(hw
, (u32
)technology_ability_reg
,
1926 (u32
)lp_technology_ability_reg
,
1927 IXGBE_TAF_SYM_PAUSE
, IXGBE_TAF_ASM_PAUSE
,
1928 IXGBE_TAF_SYM_PAUSE
, IXGBE_TAF_ASM_PAUSE
);
1932 * ixgbe_negotiate_fc - Negotiate flow control
1933 * @hw: pointer to hardware structure
1934 * @adv_reg: flow control advertised settings
1935 * @lp_reg: link partner's flow control settings
1936 * @adv_sym: symmetric pause bit in advertisement
1937 * @adv_asm: asymmetric pause bit in advertisement
1938 * @lp_sym: symmetric pause bit in link partner advertisement
1939 * @lp_asm: asymmetric pause bit in link partner advertisement
1941 * Find the intersection between advertised settings and link partner's
1942 * advertised settings
1944 static s32
ixgbe_negotiate_fc(struct ixgbe_hw
*hw
, u32 adv_reg
, u32 lp_reg
,
1945 u32 adv_sym
, u32 adv_asm
, u32 lp_sym
, u32 lp_asm
)
1947 if ((!(adv_reg
)) || (!(lp_reg
)))
1948 return IXGBE_ERR_FC_NOT_NEGOTIATED
;
1950 if ((adv_reg
& adv_sym
) && (lp_reg
& lp_sym
)) {
1952 * Now we need to check if the user selected Rx ONLY
1953 * of pause frames. In this case, we had to advertise
1954 * FULL flow control because we could not advertise RX
1955 * ONLY. Hence, we must now check to see if we need to
1956 * turn OFF the TRANSMISSION of PAUSE frames.
1958 if (hw
->fc
.requested_mode
== ixgbe_fc_full
) {
1959 hw
->fc
.current_mode
= ixgbe_fc_full
;
1960 hw_dbg(hw
, "Flow Control = FULL.\n");
1962 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
1963 hw_dbg(hw
, "Flow Control=RX PAUSE frames only\n");
1965 } else if (!(adv_reg
& adv_sym
) && (adv_reg
& adv_asm
) &&
1966 (lp_reg
& lp_sym
) && (lp_reg
& lp_asm
)) {
1967 hw
->fc
.current_mode
= ixgbe_fc_tx_pause
;
1968 hw_dbg(hw
, "Flow Control = TX PAUSE frames only.\n");
1969 } else if ((adv_reg
& adv_sym
) && (adv_reg
& adv_asm
) &&
1970 !(lp_reg
& lp_sym
) && (lp_reg
& lp_asm
)) {
1971 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
1972 hw_dbg(hw
, "Flow Control = RX PAUSE frames only.\n");
1974 hw
->fc
.current_mode
= ixgbe_fc_none
;
1975 hw_dbg(hw
, "Flow Control = NONE.\n");
1981 * ixgbe_setup_fc - Set up flow control
1982 * @hw: pointer to hardware structure
1984 * Called at init time to set up flow control.
1986 static s32
ixgbe_setup_fc(struct ixgbe_hw
*hw
, s32 packetbuf_num
)
1989 u32 reg
= 0, reg_bp
= 0;
1993 if (hw
->fc
.requested_mode
== ixgbe_fc_pfc
) {
1994 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1998 #endif /* CONFIG_DCB */
1999 /* Validate the packetbuf configuration */
2000 if (packetbuf_num
< 0 || packetbuf_num
> 7) {
2001 hw_dbg(hw
, "Invalid packet buffer number [%d], expected range "
2002 "is 0-7\n", packetbuf_num
);
2003 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
2008 * Validate the water mark configuration. Zero water marks are invalid
2009 * because it causes the controller to just blast out fc packets.
2011 if (!hw
->fc
.low_water
|| !hw
->fc
.high_water
|| !hw
->fc
.pause_time
) {
2012 hw_dbg(hw
, "Invalid water mark configuration\n");
2013 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
2018 * Validate the requested mode. Strict IEEE mode does not allow
2019 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
2021 if (hw
->fc
.strict_ieee
&& hw
->fc
.requested_mode
== ixgbe_fc_rx_pause
) {
2022 hw_dbg(hw
, "ixgbe_fc_rx_pause not valid in strict "
2024 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
2029 * 10gig parts do not have a word in the EEPROM to determine the
2030 * default flow control setting, so we explicitly set it to full.
2032 if (hw
->fc
.requested_mode
== ixgbe_fc_default
)
2033 hw
->fc
.requested_mode
= ixgbe_fc_full
;
2036 * Set up the 1G and 10G flow control advertisement registers so the
2037 * HW will be able to do fc autoneg once the cable is plugged in. If
2038 * we link at 10G, the 1G advertisement is harmless and vice versa.
2041 switch (hw
->phy
.media_type
) {
2042 case ixgbe_media_type_fiber
:
2043 case ixgbe_media_type_backplane
:
2044 reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANA
);
2045 reg_bp
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2048 case ixgbe_media_type_copper
:
2049 hw
->phy
.ops
.read_reg(hw
, MDIO_AN_ADVERTISE
,
2050 MDIO_MMD_AN
, ®_cu
);
2058 * The possible values of fc.requested_mode are:
2059 * 0: Flow control is completely disabled
2060 * 1: Rx flow control is enabled (we can receive pause frames,
2061 * but not send pause frames).
2062 * 2: Tx flow control is enabled (we can send pause frames but
2063 * we do not support receiving pause frames).
2064 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2066 * 4: Priority Flow Control is enabled.
2070 switch (hw
->fc
.requested_mode
) {
2072 /* Flow control completely disabled by software override. */
2073 reg
&= ~(IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
);
2074 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
)
2075 reg_bp
&= ~(IXGBE_AUTOC_SYM_PAUSE
|
2076 IXGBE_AUTOC_ASM_PAUSE
);
2077 else if (hw
->phy
.media_type
== ixgbe_media_type_copper
)
2078 reg_cu
&= ~(IXGBE_TAF_SYM_PAUSE
| IXGBE_TAF_ASM_PAUSE
);
2080 case ixgbe_fc_rx_pause
:
2082 * Rx Flow control is enabled and Tx Flow control is
2083 * disabled by software override. Since there really
2084 * isn't a way to advertise that we are capable of RX
2085 * Pause ONLY, we will advertise that we support both
2086 * symmetric and asymmetric Rx PAUSE. Later, we will
2087 * disable the adapter's ability to send PAUSE frames.
2089 reg
|= (IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
);
2090 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
)
2091 reg_bp
|= (IXGBE_AUTOC_SYM_PAUSE
|
2092 IXGBE_AUTOC_ASM_PAUSE
);
2093 else if (hw
->phy
.media_type
== ixgbe_media_type_copper
)
2094 reg_cu
|= (IXGBE_TAF_SYM_PAUSE
| IXGBE_TAF_ASM_PAUSE
);
2096 case ixgbe_fc_tx_pause
:
2098 * Tx Flow control is enabled, and Rx Flow control is
2099 * disabled by software override.
2101 reg
|= (IXGBE_PCS1GANA_ASM_PAUSE
);
2102 reg
&= ~(IXGBE_PCS1GANA_SYM_PAUSE
);
2103 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
) {
2104 reg_bp
|= (IXGBE_AUTOC_ASM_PAUSE
);
2105 reg_bp
&= ~(IXGBE_AUTOC_SYM_PAUSE
);
2106 } else if (hw
->phy
.media_type
== ixgbe_media_type_copper
) {
2107 reg_cu
|= (IXGBE_TAF_ASM_PAUSE
);
2108 reg_cu
&= ~(IXGBE_TAF_SYM_PAUSE
);
2112 /* Flow control (both Rx and Tx) is enabled by SW override. */
2113 reg
|= (IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
);
2114 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
)
2115 reg_bp
|= (IXGBE_AUTOC_SYM_PAUSE
|
2116 IXGBE_AUTOC_ASM_PAUSE
);
2117 else if (hw
->phy
.media_type
== ixgbe_media_type_copper
)
2118 reg_cu
|= (IXGBE_TAF_SYM_PAUSE
| IXGBE_TAF_ASM_PAUSE
);
2124 #endif /* CONFIG_DCB */
2126 hw_dbg(hw
, "Flow control param set incorrectly\n");
2127 ret_val
= IXGBE_ERR_CONFIG
;
2132 if (hw
->mac
.type
!= ixgbe_mac_X540
) {
2134 * Enable auto-negotiation between the MAC & PHY;
2135 * the MAC will advertise clause 37 flow control.
2137 IXGBE_WRITE_REG(hw
, IXGBE_PCS1GANA
, reg
);
2138 reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GLCTL
);
2140 /* Disable AN timeout */
2141 if (hw
->fc
.strict_ieee
)
2142 reg
&= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN
;
2144 IXGBE_WRITE_REG(hw
, IXGBE_PCS1GLCTL
, reg
);
2145 hw_dbg(hw
, "Set up FC; PCS1GLCTL = 0x%08X\n", reg
);
2149 * AUTOC restart handles negotiation of 1G and 10G on backplane
2150 * and copper. There is no need to set the PCS1GCTL register.
2153 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
) {
2154 reg_bp
|= IXGBE_AUTOC_AN_RESTART
;
2155 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, reg_bp
);
2156 } else if ((hw
->phy
.media_type
== ixgbe_media_type_copper
) &&
2157 (ixgbe_device_supports_autoneg_fc(hw
) == 0)) {
2158 hw
->phy
.ops
.write_reg(hw
, MDIO_AN_ADVERTISE
,
2159 MDIO_MMD_AN
, reg_cu
);
2162 hw_dbg(hw
, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg
);
2168 * ixgbe_disable_pcie_master - Disable PCI-express master access
2169 * @hw: pointer to hardware structure
2171 * Disables PCI-Express master access and verifies there are no pending
2172 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2173 * bit hasn't caused the master requests to be disabled, else 0
2174 * is returned signifying master requests disabled.
2176 s32
ixgbe_disable_pcie_master(struct ixgbe_hw
*hw
)
2178 struct ixgbe_adapter
*adapter
= hw
->back
;
2181 u32 number_of_queues
;
2185 /* Just jump out if bus mastering is already disabled */
2186 if (!(IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_GIO
))
2189 /* Disable the receive unit by stopping each queue */
2190 number_of_queues
= hw
->mac
.max_rx_queues
;
2191 for (i
= 0; i
< number_of_queues
; i
++) {
2192 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
2193 if (reg_val
& IXGBE_RXDCTL_ENABLE
) {
2194 reg_val
&= ~IXGBE_RXDCTL_ENABLE
;
2195 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(i
), reg_val
);
2199 reg_val
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
2200 reg_val
|= IXGBE_CTRL_GIO_DIS
;
2201 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, reg_val
);
2203 for (i
= 0; i
< IXGBE_PCI_MASTER_DISABLE_TIMEOUT
; i
++) {
2204 if (!(IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_GIO
))
2205 goto check_device_status
;
2209 hw_dbg(hw
, "GIO Master Disable bit didn't clear - requesting resets\n");
2210 status
= IXGBE_ERR_MASTER_REQUESTS_PENDING
;
2213 * Before proceeding, make sure that the PCIe block does not have
2214 * transactions pending.
2216 check_device_status
:
2217 for (i
= 0; i
< IXGBE_PCI_MASTER_DISABLE_TIMEOUT
; i
++) {
2218 pci_read_config_word(adapter
->pdev
, IXGBE_PCI_DEVICE_STATUS
,
2220 if (!(dev_status
& IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING
))
2225 if (i
== IXGBE_PCI_MASTER_DISABLE_TIMEOUT
)
2226 hw_dbg(hw
, "PCIe transaction pending bit also did not clear.\n");
2231 * Two consecutive resets are required via CTRL.RST per datasheet
2232 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2233 * of this need. The first reset prevents new master requests from
2234 * being issued by our device. We then must wait 1usec for any
2235 * remaining completions from the PCIe bus to trickle in, and then reset
2236 * again to clear out any effects they may have had on our device.
2238 hw
->mac
.flags
|= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
2246 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2247 * @hw: pointer to hardware structure
2248 * @mask: Mask to specify which semaphore to acquire
2250 * Acquires the SWFW semaphore through the GSSR register for the specified
2251 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2253 s32
ixgbe_acquire_swfw_sync(struct ixgbe_hw
*hw
, u16 mask
)
2257 u32 fwmask
= mask
<< 5;
2262 * SW EEPROM semaphore bit is used for access to all
2263 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2265 if (ixgbe_get_eeprom_semaphore(hw
))
2266 return IXGBE_ERR_SWFW_SYNC
;
2268 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
2269 if (!(gssr
& (fwmask
| swmask
)))
2273 * Firmware currently using resource (fwmask) or other software
2274 * thread currently using resource (swmask)
2276 ixgbe_release_eeprom_semaphore(hw
);
2277 usleep_range(5000, 10000);
2282 hw_dbg(hw
, "Driver can't access resource, SW_FW_SYNC timeout.\n");
2283 return IXGBE_ERR_SWFW_SYNC
;
2287 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
2289 ixgbe_release_eeprom_semaphore(hw
);
2294 * ixgbe_release_swfw_sync - Release SWFW semaphore
2295 * @hw: pointer to hardware structure
2296 * @mask: Mask to specify which semaphore to release
2298 * Releases the SWFW semaphore through the GSSR register for the specified
2299 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2301 void ixgbe_release_swfw_sync(struct ixgbe_hw
*hw
, u16 mask
)
2306 ixgbe_get_eeprom_semaphore(hw
);
2308 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
2310 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
2312 ixgbe_release_eeprom_semaphore(hw
);
2316 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2317 * @hw: pointer to hardware structure
2318 * @regval: register value to write to RXCTRL
2320 * Enables the Rx DMA unit
2322 s32
ixgbe_enable_rx_dma_generic(struct ixgbe_hw
*hw
, u32 regval
)
2324 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, regval
);
2330 * ixgbe_blink_led_start_generic - Blink LED based on index.
2331 * @hw: pointer to hardware structure
2332 * @index: led number to blink
2334 s32
ixgbe_blink_led_start_generic(struct ixgbe_hw
*hw
, u32 index
)
2336 ixgbe_link_speed speed
= 0;
2338 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2339 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
2342 * Link must be up to auto-blink the LEDs;
2343 * Force it if link is down.
2345 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
2348 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
2349 autoc_reg
|= IXGBE_AUTOC_FLU
;
2350 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
2351 usleep_range(10000, 20000);
2354 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
2355 led_reg
|= IXGBE_LED_BLINK(index
);
2356 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
2357 IXGBE_WRITE_FLUSH(hw
);
2363 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2364 * @hw: pointer to hardware structure
2365 * @index: led number to stop blinking
2367 s32
ixgbe_blink_led_stop_generic(struct ixgbe_hw
*hw
, u32 index
)
2369 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2370 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
2372 autoc_reg
&= ~IXGBE_AUTOC_FLU
;
2373 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
2374 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
2376 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
2377 led_reg
&= ~IXGBE_LED_BLINK(index
);
2378 led_reg
|= IXGBE_LED_LINK_ACTIVE
<< IXGBE_LED_MODE_SHIFT(index
);
2379 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
2380 IXGBE_WRITE_FLUSH(hw
);
2386 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2387 * @hw: pointer to hardware structure
2388 * @san_mac_offset: SAN MAC address offset
2390 * This function will read the EEPROM location for the SAN MAC address
2391 * pointer, and returns the value at that location. This is used in both
2392 * get and set mac_addr routines.
2394 static s32
ixgbe_get_san_mac_addr_offset(struct ixgbe_hw
*hw
,
2395 u16
*san_mac_offset
)
2398 * First read the EEPROM pointer to see if the MAC addresses are
2401 hw
->eeprom
.ops
.read(hw
, IXGBE_SAN_MAC_ADDR_PTR
, san_mac_offset
);
2407 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2408 * @hw: pointer to hardware structure
2409 * @san_mac_addr: SAN MAC address
2411 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2412 * per-port, so set_lan_id() must be called before reading the addresses.
2413 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2414 * upon for non-SFP connections, so we must call it here.
2416 s32
ixgbe_get_san_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*san_mac_addr
)
2418 u16 san_mac_data
, san_mac_offset
;
2422 * First read the EEPROM pointer to see if the MAC addresses are
2423 * available. If they're not, no point in calling set_lan_id() here.
2425 ixgbe_get_san_mac_addr_offset(hw
, &san_mac_offset
);
2427 if ((san_mac_offset
== 0) || (san_mac_offset
== 0xFFFF)) {
2429 * No addresses available in this EEPROM. It's not an
2430 * error though, so just wipe the local address and return.
2432 for (i
= 0; i
< 6; i
++)
2433 san_mac_addr
[i
] = 0xFF;
2435 goto san_mac_addr_out
;
2438 /* make sure we know which port we need to program */
2439 hw
->mac
.ops
.set_lan_id(hw
);
2440 /* apply the port offset to the address offset */
2441 (hw
->bus
.func
) ? (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT1_OFFSET
) :
2442 (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT0_OFFSET
);
2443 for (i
= 0; i
< 3; i
++) {
2444 hw
->eeprom
.ops
.read(hw
, san_mac_offset
, &san_mac_data
);
2445 san_mac_addr
[i
* 2] = (u8
)(san_mac_data
);
2446 san_mac_addr
[i
* 2 + 1] = (u8
)(san_mac_data
>> 8);
2455 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2456 * @hw: pointer to hardware structure
2458 * Read PCIe configuration space, and get the MSI-X vector count from
2459 * the capabilities table.
2461 u32
ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw
*hw
)
2463 struct ixgbe_adapter
*adapter
= hw
->back
;
2465 pci_read_config_word(adapter
->pdev
, IXGBE_PCIE_MSIX_82599_CAPS
,
2467 msix_count
&= IXGBE_PCIE_MSIX_TBL_SZ_MASK
;
2469 /* MSI-X count is zero-based in HW, so increment to give proper value */
2476 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2477 * @hw: pointer to hardware struct
2478 * @rar: receive address register index to disassociate
2479 * @vmdq: VMDq pool index to remove from the rar
2481 s32
ixgbe_clear_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
2483 u32 mpsar_lo
, mpsar_hi
;
2484 u32 rar_entries
= hw
->mac
.num_rar_entries
;
2486 /* Make sure we are using a valid rar index range */
2487 if (rar
>= rar_entries
) {
2488 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
2489 return IXGBE_ERR_INVALID_ARGUMENT
;
2492 mpsar_lo
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
2493 mpsar_hi
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
2495 if (!mpsar_lo
&& !mpsar_hi
)
2498 if (vmdq
== IXGBE_CLEAR_VMDQ_ALL
) {
2500 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), 0);
2504 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), 0);
2507 } else if (vmdq
< 32) {
2508 mpsar_lo
&= ~(1 << vmdq
);
2509 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar_lo
);
2511 mpsar_hi
&= ~(1 << (vmdq
- 32));
2512 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar_hi
);
2515 /* was that the last pool using this rar? */
2516 if (mpsar_lo
== 0 && mpsar_hi
== 0 && rar
!= 0)
2517 hw
->mac
.ops
.clear_rar(hw
, rar
);
2523 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2524 * @hw: pointer to hardware struct
2525 * @rar: receive address register index to associate with a VMDq index
2526 * @vmdq: VMDq pool index
2528 s32
ixgbe_set_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
2531 u32 rar_entries
= hw
->mac
.num_rar_entries
;
2533 /* Make sure we are using a valid rar index range */
2534 if (rar
>= rar_entries
) {
2535 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
2536 return IXGBE_ERR_INVALID_ARGUMENT
;
2540 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
2542 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar
);
2544 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
2545 mpsar
|= 1 << (vmdq
- 32);
2546 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar
);
2552 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2553 * @hw: pointer to hardware structure
2555 s32
ixgbe_init_uta_tables_generic(struct ixgbe_hw
*hw
)
2559 for (i
= 0; i
< 128; i
++)
2560 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), 0);
2566 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2567 * @hw: pointer to hardware structure
2568 * @vlan: VLAN id to write to VLAN filter
2570 * return the VLVF index where this VLAN id should be placed
2573 static s32
ixgbe_find_vlvf_slot(struct ixgbe_hw
*hw
, u32 vlan
)
2576 u32 first_empty_slot
= 0;
2579 /* short cut the special case */
2584 * Search for the vlan id in the VLVF entries. Save off the first empty
2585 * slot found along the way
2587 for (regindex
= 1; regindex
< IXGBE_VLVF_ENTRIES
; regindex
++) {
2588 bits
= IXGBE_READ_REG(hw
, IXGBE_VLVF(regindex
));
2589 if (!bits
&& !(first_empty_slot
))
2590 first_empty_slot
= regindex
;
2591 else if ((bits
& 0x0FFF) == vlan
)
2596 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2597 * in the VLVF. Else use the first empty VLVF register for this
2600 if (regindex
>= IXGBE_VLVF_ENTRIES
) {
2601 if (first_empty_slot
)
2602 regindex
= first_empty_slot
;
2604 hw_dbg(hw
, "No space in VLVF.\n");
2605 regindex
= IXGBE_ERR_NO_SPACE
;
2613 * ixgbe_set_vfta_generic - Set VLAN filter table
2614 * @hw: pointer to hardware structure
2615 * @vlan: VLAN id to write to VLAN filter
2616 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2617 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2619 * Turn on/off specified VLAN in the VLAN filter table.
2621 s32
ixgbe_set_vfta_generic(struct ixgbe_hw
*hw
, u32 vlan
, u32 vind
,
2630 bool vfta_changed
= false;
2633 return IXGBE_ERR_PARAM
;
2636 * this is a 2 part operation - first the VFTA, then the
2637 * VLVF and VLVFB if VT Mode is set
2638 * We don't write the VFTA until we know the VLVF part succeeded.
2642 * The VFTA is a bitstring made up of 128 32-bit registers
2643 * that enable the particular VLAN id, much like the MTA:
2644 * bits[11-5]: which register
2645 * bits[4-0]: which bit in the register
2647 regindex
= (vlan
>> 5) & 0x7F;
2648 bitindex
= vlan
& 0x1F;
2649 targetbit
= (1 << bitindex
);
2650 vfta
= IXGBE_READ_REG(hw
, IXGBE_VFTA(regindex
));
2653 if (!(vfta
& targetbit
)) {
2655 vfta_changed
= true;
2658 if ((vfta
& targetbit
)) {
2660 vfta_changed
= true;
2667 * make sure the vlan is in VLVF
2668 * set the vind bit in the matching VLVFB
2670 * clear the pool bit and possibly the vind
2672 vt
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2673 if (vt
& IXGBE_VT_CTL_VT_ENABLE
) {
2676 vlvf_index
= ixgbe_find_vlvf_slot(hw
, vlan
);
2681 /* set the pool bit */
2683 bits
= IXGBE_READ_REG(hw
,
2684 IXGBE_VLVFB(vlvf_index
*2));
2685 bits
|= (1 << vind
);
2687 IXGBE_VLVFB(vlvf_index
*2),
2690 bits
= IXGBE_READ_REG(hw
,
2691 IXGBE_VLVFB((vlvf_index
*2)+1));
2692 bits
|= (1 << (vind
-32));
2694 IXGBE_VLVFB((vlvf_index
*2)+1),
2698 /* clear the pool bit */
2700 bits
= IXGBE_READ_REG(hw
,
2701 IXGBE_VLVFB(vlvf_index
*2));
2702 bits
&= ~(1 << vind
);
2704 IXGBE_VLVFB(vlvf_index
*2),
2706 bits
|= IXGBE_READ_REG(hw
,
2707 IXGBE_VLVFB((vlvf_index
*2)+1));
2709 bits
= IXGBE_READ_REG(hw
,
2710 IXGBE_VLVFB((vlvf_index
*2)+1));
2711 bits
&= ~(1 << (vind
-32));
2713 IXGBE_VLVFB((vlvf_index
*2)+1),
2715 bits
|= IXGBE_READ_REG(hw
,
2716 IXGBE_VLVFB(vlvf_index
*2));
2721 * If there are still bits set in the VLVFB registers
2722 * for the VLAN ID indicated we need to see if the
2723 * caller is requesting that we clear the VFTA entry bit.
2724 * If the caller has requested that we clear the VFTA
2725 * entry bit but there are still pools/VFs using this VLAN
2726 * ID entry then ignore the request. We're not worried
2727 * about the case where we're turning the VFTA VLAN ID
2728 * entry bit on, only when requested to turn it off as
2729 * there may be multiple pools and/or VFs using the
2730 * VLAN ID entry. In that case we cannot clear the
2731 * VFTA bit until all pools/VFs using that VLAN ID have also
2732 * been cleared. This will be indicated by "bits" being
2736 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(vlvf_index
),
2737 (IXGBE_VLVF_VIEN
| vlan
));
2739 /* someone wants to clear the vfta entry
2740 * but some pools/VFs are still using it.
2742 vfta_changed
= false;
2746 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(vlvf_index
), 0);
2750 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(regindex
), vfta
);
2756 * ixgbe_clear_vfta_generic - Clear VLAN filter table
2757 * @hw: pointer to hardware structure
2759 * Clears the VLAN filer table, and the VMDq index associated with the filter
2761 s32
ixgbe_clear_vfta_generic(struct ixgbe_hw
*hw
)
2765 for (offset
= 0; offset
< hw
->mac
.vft_size
; offset
++)
2766 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(offset
), 0);
2768 for (offset
= 0; offset
< IXGBE_VLVF_ENTRIES
; offset
++) {
2769 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(offset
), 0);
2770 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB(offset
*2), 0);
2771 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB((offset
*2)+1), 0);
2778 * ixgbe_check_mac_link_generic - Determine link and speed status
2779 * @hw: pointer to hardware structure
2780 * @speed: pointer to link speed
2781 * @link_up: true when link is up
2782 * @link_up_wait_to_complete: bool used to wait for link up or not
2784 * Reads the links register to determine if link is up and the current speed
2786 s32
ixgbe_check_mac_link_generic(struct ixgbe_hw
*hw
, ixgbe_link_speed
*speed
,
2787 bool *link_up
, bool link_up_wait_to_complete
)
2789 u32 links_reg
, links_orig
;
2792 /* clear the old state */
2793 links_orig
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
2795 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
2797 if (links_orig
!= links_reg
) {
2798 hw_dbg(hw
, "LINKS changed from %08X to %08X\n",
2799 links_orig
, links_reg
);
2802 if (link_up_wait_to_complete
) {
2803 for (i
= 0; i
< IXGBE_LINK_UP_TIME
; i
++) {
2804 if (links_reg
& IXGBE_LINKS_UP
) {
2811 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
2814 if (links_reg
& IXGBE_LINKS_UP
)
2820 if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
2821 IXGBE_LINKS_SPEED_10G_82599
)
2822 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
2823 else if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
2824 IXGBE_LINKS_SPEED_1G_82599
)
2825 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
2826 else if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
2827 IXGBE_LINKS_SPEED_100_82599
)
2828 *speed
= IXGBE_LINK_SPEED_100_FULL
;
2830 *speed
= IXGBE_LINK_SPEED_UNKNOWN
;
2832 /* if link is down, zero out the current_mode */
2833 if (*link_up
== false) {
2834 hw
->fc
.current_mode
= ixgbe_fc_none
;
2835 hw
->fc
.fc_was_autonegged
= false;
2842 * ixgbe_get_wwn_prefix_generic Get alternative WWNN/WWPN prefix from
2844 * @hw: pointer to hardware structure
2845 * @wwnn_prefix: the alternative WWNN prefix
2846 * @wwpn_prefix: the alternative WWPN prefix
2848 * This function will read the EEPROM from the alternative SAN MAC address
2849 * block to check the support for the alternative WWNN/WWPN prefix support.
2851 s32
ixgbe_get_wwn_prefix_generic(struct ixgbe_hw
*hw
, u16
*wwnn_prefix
,
2855 u16 alt_san_mac_blk_offset
;
2857 /* clear output first */
2858 *wwnn_prefix
= 0xFFFF;
2859 *wwpn_prefix
= 0xFFFF;
2861 /* check if alternative SAN MAC is supported */
2862 hw
->eeprom
.ops
.read(hw
, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR
,
2863 &alt_san_mac_blk_offset
);
2865 if ((alt_san_mac_blk_offset
== 0) ||
2866 (alt_san_mac_blk_offset
== 0xFFFF))
2867 goto wwn_prefix_out
;
2869 /* check capability in alternative san mac address block */
2870 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET
;
2871 hw
->eeprom
.ops
.read(hw
, offset
, &caps
);
2872 if (!(caps
& IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN
))
2873 goto wwn_prefix_out
;
2875 /* get the corresponding prefix for WWNN/WWPN */
2876 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET
;
2877 hw
->eeprom
.ops
.read(hw
, offset
, wwnn_prefix
);
2879 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET
;
2880 hw
->eeprom
.ops
.read(hw
, offset
, wwpn_prefix
);
2887 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
2889 * @hw: pointer to hardware structure
2891 * There are several phys that do not support autoneg flow control. This
2892 * function check the device id to see if the associated phy supports
2893 * autoneg flow control.
2895 static s32
ixgbe_device_supports_autoneg_fc(struct ixgbe_hw
*hw
)
2898 switch (hw
->device_id
) {
2899 case IXGBE_DEV_ID_X540T
:
2901 case IXGBE_DEV_ID_82599_T3_LOM
:
2904 return IXGBE_ERR_FC_NOT_SUPPORTED
;
2909 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
2910 * @hw: pointer to hardware structure
2911 * @enable: enable or disable switch for anti-spoofing
2912 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
2915 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw
*hw
, bool enable
, int pf
)
2918 int pf_target_reg
= pf
>> 3;
2919 int pf_target_shift
= pf
% 8;
2922 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2926 pfvfspoof
= IXGBE_SPOOF_MACAS_MASK
;
2929 * PFVFSPOOF register array is size 8 with 8 bits assigned to
2930 * MAC anti-spoof enables in each register array element.
2932 for (j
= 0; j
< IXGBE_PFVFSPOOF_REG_COUNT
; j
++)
2933 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(j
), pfvfspoof
);
2935 /* If not enabling anti-spoofing then done */
2940 * The PF should be allowed to spoof so that it can support
2941 * emulation mode NICs. Reset the bit assigned to the PF
2943 pfvfspoof
= IXGBE_READ_REG(hw
, IXGBE_PFVFSPOOF(pf_target_reg
));
2944 pfvfspoof
^= (1 << pf_target_shift
);
2945 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(pf_target_reg
), pfvfspoof
);
2949 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
2950 * @hw: pointer to hardware structure
2951 * @enable: enable or disable switch for VLAN anti-spoofing
2952 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
2955 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw
*hw
, bool enable
, int vf
)
2957 int vf_target_reg
= vf
>> 3;
2958 int vf_target_shift
= vf
% 8 + IXGBE_SPOOF_VLANAS_SHIFT
;
2961 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2964 pfvfspoof
= IXGBE_READ_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
));
2966 pfvfspoof
|= (1 << vf_target_shift
);
2968 pfvfspoof
&= ~(1 << vf_target_shift
);
2969 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
), pfvfspoof
);