| blob | 14849350101136818bd8d2990c88057eb0dbfddc |
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
21 /*
22 Module: rt73usb
23 Abstract: Data structures and registers for the rt73usb module.
24 Supported chipsets: rt2571W & rt2671.
25 */
27 #ifndef RT73USB_H
28 #define RT73USB_H
30 /*
31 * RF chip defines.
32 */
33 #define RF5226 0x0001
34 #define RF2528 0x0002
35 #define RF5225 0x0003
36 #define RF2527 0x0004
38 /*
39 * Signal information.
40 * Defaul offset is required for RSSI <-> dBm conversion.
41 */
42 #define DEFAULT_RSSI_OFFSET 120
44 /*
45 * Register layout information.
46 */
47 #define CSR_REG_BASE 0x3000
48 #define CSR_REG_SIZE 0x04b0
49 #define EEPROM_BASE 0x0000
50 #define EEPROM_SIZE 0x0100
51 #define BBP_SIZE 0x0080
52 #define RF_SIZE 0x0014
54 /*
55 * Number of TX queues.
56 */
57 #define NUM_TX_QUEUES 4
59 /*
60 * USB registers.
61 */
63 /*
64 * MCU_LEDCS: LED control for MCU Mailbox.
65 */
66 #define MCU_LEDCS_LED_MODE FIELD16(0x001f)
67 #define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
68 #define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
69 #define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
70 #define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
71 #define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
72 #define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
73 #define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
74 #define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
75 #define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
76 #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
77 #define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
79 /*
80 * 8051 firmware image.
81 */
83 #define FIRMWARE_IMAGE_BASE 0x0800
85 /*
86 * Security key table memory.
87 * 16 entries 32-byte for shared key table
88 * 64 entries 32-byte for pairwise key table
89 * 64 entries 8-byte for pairwise ta key table
90 */
91 #define SHARED_KEY_TABLE_BASE 0x1000
92 #define PAIRWISE_KEY_TABLE_BASE 0x1200
93 #define PAIRWISE_TA_TABLE_BASE 0x1a00
106 /*
107 * Since NULL frame won't be that long (256 byte),
108 * We steal 16 tail bytes to save debugging settings.
109 */
110 #define HW_DEBUG_SETTING_BASE 0x2bf0
112 /*
113 * On-chip BEACON frame space.
114 */
115 #define HW_BEACON_BASE0 0x2400
116 #define HW_BEACON_BASE1 0x2500
117 #define HW_BEACON_BASE2 0x2600
118 #define HW_BEACON_BASE3 0x2700
120 #define HW_BEACON_OFFSET(__index) \
121 ( HW_BEACON_BASE0 + (__index * 0x0100) )
123 /*
124 * MAC Control/Status Registers(CSR).
125 * Some values are set in TU, whereas 1 TU == 1024 us.
126 */
128 /*
129 * MAC_CSR0: ASIC revision number.
130 */
131 #define MAC_CSR0 0x3000
133 /*
134 * MAC_CSR1: System control register.
135 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
136 * BBP_RESET: Hardware reset BBP.
137 * HOST_READY: Host is ready after initialization, 1: ready.
138 */
139 #define MAC_CSR1 0x3004
140 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
141 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
142 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
144 /*
145 * MAC_CSR2: STA MAC register 0.
146 */
147 #define MAC_CSR2 0x3008
148 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
149 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
150 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
151 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
153 /*
154 * MAC_CSR3: STA MAC register 1.
155 * UNICAST_TO_ME_MASK:
156 * Used to mask off bits from byte 5 of the MAC address
157 * to determine the UNICAST_TO_ME bit for RX frames.
158 * The full mask is complemented by BSS_ID_MASK:
159 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
160 */
161 #define MAC_CSR3 0x300c
162 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
163 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
164 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
166 /*
167 * MAC_CSR4: BSSID register 0.
168 */
169 #define MAC_CSR4 0x3010
170 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
171 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
172 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
173 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
175 /*
176 * MAC_CSR5: BSSID register 1.
177 * BSS_ID_MASK:
178 * This mask is used to mask off bits 0 and 1 of byte 5 of the
179 * BSSID. This will make sure that those bits will be ignored
180 * when determining the MY_BSS of RX frames.
181 * 0: 1-BSSID mode (BSS index = 0)
182 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
183 * 2: 2-BSSID mode (BSS index: byte5, bit 1)
184 * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
185 */
186 #define MAC_CSR5 0x3014
187 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
188 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
189 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
191 /*
192 * MAC_CSR6: Maximum frame length register.
193 */
194 #define MAC_CSR6 0x3018
195 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
197 /*
198 * MAC_CSR7: Reserved
199 */
200 #define MAC_CSR7 0x301c
202 /*
203 * MAC_CSR8: SIFS/EIFS register.
204 * All units are in US.
205 */
206 #define MAC_CSR8 0x3020
207 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
208 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
209 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
211 /*
212 * MAC_CSR9: Back-Off control register.
213 * SLOT_TIME: Slot time, default is 20us for 802.11BG.
214 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
215 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
216 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
217 */
218 #define MAC_CSR9 0x3024
219 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
220 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
221 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
222 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
224 /*
225 * MAC_CSR10: Power state configuration.
226 */
227 #define MAC_CSR10 0x3028
229 /*
230 * MAC_CSR11: Power saving transition time register.
231 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
232 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
233 * WAKEUP_LATENCY: In unit of TU.
234 */
235 #define MAC_CSR11 0x302c
236 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
237 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
238 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
239 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
241 /*
242 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
243 * CURRENT_STATE: 0:sleep, 1:awake.
244 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
245 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
246 */
247 #define MAC_CSR12 0x3030
248 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
249 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
250 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
251 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
253 /*
254 * MAC_CSR13: GPIO.
255 */
256 #define MAC_CSR13 0x3034
258 /*
259 * MAC_CSR14: LED control register.
260 * ON_PERIOD: On period, default 70ms.
261 * OFF_PERIOD: Off period, default 30ms.
262 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
263 * SW_LED: s/w LED, 1: ON, 0: OFF.
264 * HW_LED_POLARITY: 0: active low, 1: active high.
265 */
266 #define MAC_CSR14 0x3038
267 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
268 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
269 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
270 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
271 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
272 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
274 /*
275 * MAC_CSR15: NAV control.
276 */
277 #define MAC_CSR15 0x303c
279 /*
280 * TXRX control registers.
281 * Some values are set in TU, whereas 1 TU == 1024 us.
282 */
284 /*
285 * TXRX_CSR0: TX/RX configuration register.
286 * TSF_OFFSET: Default is 24.
287 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
288 * DISABLE_RX: Disable Rx engine.
289 * DROP_CRC: Drop CRC error.
290 * DROP_PHYSICAL: Drop physical error.
291 * DROP_CONTROL: Drop control frame.
292 * DROP_NOT_TO_ME: Drop not to me unicast frame.
293 * DROP_TO_DS: Drop fram ToDs bit is true.
294 * DROP_VERSION_ERROR: Drop version error frame.
295 * DROP_MULTICAST: Drop multicast frames.
296 * DROP_BORADCAST: Drop broadcast frames.
297 * ROP_ACK_CTS: Drop received ACK and CTS.
298 */
299 #define TXRX_CSR0 0x3040
300 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
301 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
302 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
303 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
304 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
305 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
306 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
307 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
308 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
309 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
310 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
311 #define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
312 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
313 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
315 /*
316 * TXRX_CSR1
317 */
318 #define TXRX_CSR1 0x3044
319 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
320 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
321 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
322 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
323 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
324 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
325 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
326 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
328 /*
329 * TXRX_CSR2
330 */
331 #define TXRX_CSR2 0x3048
332 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
333 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
334 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
335 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
336 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
337 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
338 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
339 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
341 /*
342 * TXRX_CSR3
343 */
344 #define TXRX_CSR3 0x304c
345 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
346 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
347 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
348 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
349 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
350 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
351 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
352 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
354 /*
355 * TXRX_CSR4: Auto-Responder/Tx-retry register.
356 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
357 * OFDM_TX_RATE_DOWN: 1:enable.
358 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
359 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
360 */
361 #define TXRX_CSR4 0x3050
362 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
363 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
364 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
365 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
366 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
367 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
368 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
369 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
370 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
371 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
373 /*
374 * TXRX_CSR5
375 */
376 #define TXRX_CSR5 0x3054
378 /*
379 * TXRX_CSR6: ACK/CTS payload consumed time
380 */
381 #define TXRX_CSR6 0x3058
383 /*
384 * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
385 */
386 #define TXRX_CSR7 0x305c
387 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
388 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
389 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
390 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
392 /*
393 * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
394 */
395 #define TXRX_CSR8 0x3060
396 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
397 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
398 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
399 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
401 /*
402 * TXRX_CSR9: Synchronization control register.
403 * BEACON_INTERVAL: In unit of 1/16 TU.
404 * TSF_TICKING: Enable TSF auto counting.
405 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
406 * BEACON_GEN: Enable beacon generator.
407 */
408 #define TXRX_CSR9 0x3064
409 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
410 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
411 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
412 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
413 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
414 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
416 /*
417 * TXRX_CSR10: BEACON alignment.
418 */
419 #define TXRX_CSR10 0x3068
421 /*
422 * TXRX_CSR11: AES mask.
423 */
424 #define TXRX_CSR11 0x306c
426 /*
427 * TXRX_CSR12: TSF low 32.
428 */
429 #define TXRX_CSR12 0x3070
430 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
432 /*
433 * TXRX_CSR13: TSF high 32.
434 */
435 #define TXRX_CSR13 0x3074
436 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
438 /*
439 * TXRX_CSR14: TBTT timer.
440 */
441 #define TXRX_CSR14 0x3078
443 /*
444 * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
445 */
446 #define TXRX_CSR15 0x307c
448 /*
449 * PHY control registers.
450 * Some values are set in TU, whereas 1 TU == 1024 us.
451 */
453 /*
454 * PHY_CSR0: RF/PS control.
455 */
456 #define PHY_CSR0 0x3080
457 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
458 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
460 /*
461 * PHY_CSR1
462 */
463 #define PHY_CSR1 0x3084
464 #define PHY_CSR1_RF_RPI FIELD32(0x00010000)
466 /*
467 * PHY_CSR2: Pre-TX BBP control.
468 */
469 #define PHY_CSR2 0x3088
471 /*
472 * PHY_CSR3: BBP serial control register.
473 * VALUE: Register value to program into BBP.
474 * REG_NUM: Selected BBP register.
475 * READ_CONTROL: 0: Write BBP, 1: Read BBP.
476 * BUSY: 1: ASIC is busy execute BBP programming.
477 */
478 #define PHY_CSR3 0x308c
479 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
480 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
481 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
482 #define PHY_CSR3_BUSY FIELD32(0x00010000)
484 /*
485 * PHY_CSR4: RF serial control register
486 * VALUE: Register value (include register id) serial out to RF/IF chip.
487 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
488 * IF_SELECT: 1: select IF to program, 0: select RF to program.
489 * PLL_LD: RF PLL_LD status.
490 * BUSY: 1: ASIC is busy execute RF programming.
491 */
492 #define PHY_CSR4 0x3090
493 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
494 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
495 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
496 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
497 #define PHY_CSR4_BUSY FIELD32(0x80000000)
499 /*
500 * PHY_CSR5: RX to TX signal switch timing control.
501 */
502 #define PHY_CSR5 0x3094
503 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
505 /*
506 * PHY_CSR6: TX to RX signal timing control.
507 */
508 #define PHY_CSR6 0x3098
509 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
511 /*
512 * PHY_CSR7: TX DAC switching timing control.
513 */
514 #define PHY_CSR7 0x309c
516 /*
517 * Security control register.
518 */
520 /*
521 * SEC_CSR0: Shared key table control.
522 */
523 #define SEC_CSR0 0x30a0
524 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
525 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
526 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
527 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
528 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
529 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
530 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
531 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
532 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
533 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
534 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
535 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
536 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
537 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
538 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
539 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
541 /*
542 * SEC_CSR1: Shared key table security mode register.
543 */
544 #define SEC_CSR1 0x30a4
545 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
546 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
547 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
548 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
549 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
550 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
551 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
552 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
554 /*
555 * Pairwise key table valid bitmap registers.
556 * SEC_CSR2: pairwise key table valid bitmap 0.
557 * SEC_CSR3: pairwise key table valid bitmap 1.
558 */
559 #define SEC_CSR2 0x30a8
560 #define SEC_CSR3 0x30ac
562 /*
563 * SEC_CSR4: Pairwise key table lookup control.
564 */
565 #define SEC_CSR4 0x30b0
567 /*
568 * SEC_CSR5: shared key table security mode register.
569 */
570 #define SEC_CSR5 0x30b4
571 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
572 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
573 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
574 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
575 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
576 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
577 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
578 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
580 /*
581 * STA control registers.
582 */
584 /*
585 * STA_CSR0: RX PLCP error count & RX FCS error count.
586 */
587 #define STA_CSR0 0x30c0
588 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
589 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
591 /*
592 * STA_CSR1: RX False CCA count & RX LONG frame count.
593 */
594 #define STA_CSR1 0x30c4
595 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
596 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
598 /*
599 * STA_CSR2: TX Beacon count and RX FIFO overflow count.
600 */
601 #define STA_CSR2 0x30c8
602 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
603 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
605 /*
606 * STA_CSR3: TX Beacon count.
607 */
608 #define STA_CSR3 0x30cc
609 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
611 /*
612 * STA_CSR4: TX Retry count.
613 */
614 #define STA_CSR4 0x30d0
615 #define STA_CSR4_TX_NO_RETRY_COUNT FIELD32(0x0000ffff)
616 #define STA_CSR4_TX_ONE_RETRY_COUNT FIELD32(0xffff0000)
618 /*
619 * STA_CSR5: TX Retry count.
620 */
621 #define STA_CSR5 0x30d4
622 #define STA_CSR4_TX_MULTI_RETRY_COUNT FIELD32(0x0000ffff)
623 #define STA_CSR4_TX_RETRY_FAIL_COUNT FIELD32(0xffff0000)
625 /*
626 * QOS control registers.
627 */
629 /*
630 * QOS_CSR1: TXOP holder MAC address register.
631 */
632 #define QOS_CSR1 0x30e4
633 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
634 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
636 /*
637 * QOS_CSR2: TXOP holder timeout register.
638 */
639 #define QOS_CSR2 0x30e8
641 /*
642 * RX QOS-CFPOLL MAC address register.
643 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
644 * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
645 */
646 #define QOS_CSR3 0x30ec
647 #define QOS_CSR4 0x30f0
649 /*
650 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
651 */
652 #define QOS_CSR5 0x30f4
654 /*
655 * WMM Scheduler Register
656 */
658 /*
659 * AIFSN_CSR: AIFSN for each EDCA AC.
660 * AIFSN0: For AC_BK.
661 * AIFSN1: For AC_BE.
662 * AIFSN2: For AC_VI.
663 * AIFSN3: For AC_VO.
664 */
665 #define AIFSN_CSR 0x0400
666 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
667 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
668 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
669 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
671 /*
672 * CWMIN_CSR: CWmin for each EDCA AC.
673 * CWMIN0: For AC_BK.
674 * CWMIN1: For AC_BE.
675 * CWMIN2: For AC_VI.
676 * CWMIN3: For AC_VO.
677 */
678 #define CWMIN_CSR 0x0404
679 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
680 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
681 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
682 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
684 /*
685 * CWMAX_CSR: CWmax for each EDCA AC.
686 * CWMAX0: For AC_BK.
687 * CWMAX1: For AC_BE.
688 * CWMAX2: For AC_VI.
689 * CWMAX3: For AC_VO.
690 */
691 #define CWMAX_CSR 0x0408
692 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
693 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
694 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
695 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
697 /*
698 * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
699 * AC0_TX_OP: For AC_BK, in unit of 32us.
700 * AC1_TX_OP: For AC_BE, in unit of 32us.
701 */
702 #define AC_TXOP_CSR0 0x040c
703 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
704 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
706 /*
707 * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
708 * AC2_TX_OP: For AC_VI, in unit of 32us.
709 * AC3_TX_OP: For AC_VO, in unit of 32us.
710 */
711 #define AC_TXOP_CSR1 0x0410
712 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
713 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
715 /*
716 * BBP registers.
717 * The wordsize of the BBP is 8 bits.
718 */
720 /*
721 * R2
722 */
723 #define BBP_R2_BG_MODE FIELD8(0x20)
725 /*
726 * R3
727 */
728 #define BBP_R3_SMART_MODE FIELD8(0x01)
730 /*
731 * R4: RX antenna control
732 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
733 */
735 /*
736 * ANTENNA_CONTROL semantics (guessed):
737 * 0x1: Software controlled antenna switching (fixed or SW diversity)
738 * 0x2: Hardware diversity.
739 */
740 #define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03)
741 #define BBP_R4_RX_FRAME_END FIELD8(0x20)
743 /*
744 * R77
745 */
746 #define BBP_R77_RX_ANTENNA FIELD8(0x03)
748 /*
749 * RF registers
750 */
752 /*
753 * RF 3
754 */
755 #define RF3_TXPOWER FIELD32(0x00003e00)
757 /*
758 * RF 4
759 */
760 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
762 /*
763 * EEPROM content.
764 * The wordsize of the EEPROM is 16 bits.
765 */
767 /*
768 * HW MAC address.
769 */
770 #define EEPROM_MAC_ADDR_0 0x0002
771 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
772 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
773 #define EEPROM_MAC_ADDR1 0x0003
774 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
775 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
776 #define EEPROM_MAC_ADDR_2 0x0004
777 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
778 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
780 /*
781 * EEPROM antenna.
782 * ANTENNA_NUM: Number of antenna's.
783 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
784 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
785 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
786 * DYN_TXAGC: Dynamic TX AGC control.
787 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
788 * RF_TYPE: Rf_type of this adapter.
789 */
790 #define EEPROM_ANTENNA 0x0010
791 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
792 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
793 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
794 #define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
795 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
796 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
797 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
799 /*
800 * EEPROM NIC config.
801 * EXTERNAL_LNA: External LNA.
802 */
803 #define EEPROM_NIC 0x0011
804 #define EEPROM_NIC_EXTERNAL_LNA FIELD16(0x0010)
806 /*
807 * EEPROM geography.
808 * GEO_A: Default geographical setting for 5GHz band
809 * GEO: Default geographical setting.
810 */
811 #define EEPROM_GEOGRAPHY 0x0012
812 #define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
813 #define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
815 /*
816 * EEPROM BBP.
817 */
818 #define EEPROM_BBP_START 0x0013
819 #define EEPROM_BBP_SIZE 16
820 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
821 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
823 /*
824 * EEPROM TXPOWER 802.11G
825 */
826 #define EEPROM_TXPOWER_G_START 0x0023
827 #define EEPROM_TXPOWER_G_SIZE 7
828 #define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
829 #define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
831 /*
832 * EEPROM Frequency
833 */
834 #define EEPROM_FREQ 0x002f
835 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
836 #define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
837 #define EEPROM_FREQ_SEQ FIELD16(0x0300)
839 /*
840 * EEPROM LED.
841 * POLARITY_RDY_G: Polarity RDY_G setting.
842 * POLARITY_RDY_A: Polarity RDY_A setting.
843 * POLARITY_ACT: Polarity ACT setting.
844 * POLARITY_GPIO_0: Polarity GPIO0 setting.
845 * POLARITY_GPIO_1: Polarity GPIO1 setting.
846 * POLARITY_GPIO_2: Polarity GPIO2 setting.
847 * POLARITY_GPIO_3: Polarity GPIO3 setting.
848 * POLARITY_GPIO_4: Polarity GPIO4 setting.
849 * LED_MODE: Led mode.
850 */
851 #define EEPROM_LED 0x0030
852 #define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
853 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
854 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
855 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
856 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
857 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
858 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
859 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
860 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
862 /*
863 * EEPROM TXPOWER 802.11A
864 */
865 #define EEPROM_TXPOWER_A_START 0x0031
866 #define EEPROM_TXPOWER_A_SIZE 12
867 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
868 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
870 /*
871 * EEPROM RSSI offset 802.11BG
872 */
873 #define EEPROM_RSSI_OFFSET_BG 0x004d
874 #define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
875 #define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
877 /*
878 * EEPROM RSSI offset 802.11A
879 */
880 #define EEPROM_RSSI_OFFSET_A 0x004e
881 #define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
882 #define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
884 /*
885 * DMA descriptor defines.
886 */
887 #define TXD_DESC_SIZE ( 6 * sizeof(__le32) )
888 #define TXINFO_SIZE ( 6 * sizeof(__le32) )
889 #define RXD_DESC_SIZE ( 6 * sizeof(__le32) )
891 /*
892 * TX descriptor format for TX, PRIO and Beacon Ring.
893 */
895 /*
896 * Word0
897 * BURST: Next frame belongs to same "burst" event.
898 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
899 * KEY_TABLE: Use per-client pairwise KEY table.
900 * KEY_INDEX:
901 * Key index (0~31) to the pairwise KEY table.
902 * 0~3 to shared KEY table 0 (BSS0).
903 * 4~7 to shared KEY table 1 (BSS1).
904 * 8~11 to shared KEY table 2 (BSS2).
905 * 12~15 to shared KEY table 3 (BSS3).
906 * BURST2: For backward compatibility, set to same value as BURST.
907 */
908 #define TXD_W0_BURST FIELD32(0x00000001)
909 #define TXD_W0_VALID FIELD32(0x00000002)
910 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
911 #define TXD_W0_ACK FIELD32(0x00000008)
912 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
913 #define TXD_W0_OFDM FIELD32(0x00000020)
914 #define TXD_W0_IFS FIELD32(0x00000040)
915 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
916 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
917 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
918 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
919 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
920 #define TXD_W0_BURST2 FIELD32(0x10000000)
921 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
923 /*
924 * Word1
925 * HOST_Q_ID: EDCA/HCCA queue ID.
926 * HW_SEQUENCE: MAC overwrites the frame sequence number.
927 * BUFFER_COUNT: Number of buffers in this TXD.
928 */
929 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
930 #define TXD_W1_AIFSN FIELD32(0x000000f0)
931 #define TXD_W1_CWMIN FIELD32(0x00000f00)
932 #define TXD_W1_CWMAX FIELD32(0x0000f000)
933 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
934 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
935 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
937 /*
938 * Word2: PLCP information
939 */
940 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
941 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
942 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
943 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
945 /*
946 * Word3
947 */
948 #define TXD_W3_IV FIELD32(0xffffffff)
950 /*
951 * Word4
952 */
953 #define TXD_W4_EIV FIELD32(0xffffffff)
955 /*
956 * Word5
957 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
958 * PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt.
959 * WAITING_DMA_DONE_INT: TXD been filled with data
960 * and waiting for TxDoneISR housekeeping.
961 */
962 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
963 #define TXD_W5_PACKET_ID FIELD32(0x0000ff00)
964 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
965 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
967 /*
968 * RX descriptor format for RX Ring.
969 */
971 /*
972 * Word0
973 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
974 * KEY_INDEX: Decryption key actually used.
975 */
976 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
977 #define RXD_W0_DROP FIELD32(0x00000002)
978 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
979 #define RXD_W0_MULTICAST FIELD32(0x00000008)
980 #define RXD_W0_BROADCAST FIELD32(0x00000010)
981 #define RXD_W0_MY_BSS FIELD32(0x00000020)
982 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
983 #define RXD_W0_OFDM FIELD32(0x00000080)
984 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
985 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
986 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
987 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
989 /*
990 * WORD1
991 * SIGNAL: RX raw data rate reported by BBP.
992 * RSSI: RSSI reported by BBP.
993 */
994 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
995 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
996 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
997 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
999 /*
1000 * Word2
1001 * IV: Received IV of originally encrypted.
1002 */
1003 #define RXD_W2_IV FIELD32(0xffffffff)
1005 /*
1006 * Word3
1007 * EIV: Received EIV of originally encrypted.
1008 */
1009 #define RXD_W3_EIV FIELD32(0xffffffff)
1011 /*
1012 * Word4
1013 */
1014 #define RXD_W4_RESERVED FIELD32(0xffffffff)
1016 /*
1017 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1018 * and passed to the HOST driver.
1019 * The following fields are for DMA block and HOST usage only.
1020 * Can't be touched by ASIC MAC block.
1021 */
1023 /*
1024 * Word5
1025 */
1026 #define RXD_W5_RESERVED FIELD32(0xffffffff)
1028 /*
1029 * Macro's for converting txpower from EEPROM to mac80211 value
1030 * and from mac80211 value to register value.
1031 */
1032 #define MIN_TXPOWER 0
1033 #define MAX_TXPOWER 31
1034 #define DEFAULT_TXPOWER 24
1036 #define TXPOWER_FROM_DEV(__txpower) \
1037 ({ \
1038 ((__txpower) > MAX_TXPOWER) ? \
1039 DEFAULT_TXPOWER : (__txpower); \
1040 })
1042 #define TXPOWER_TO_DEV(__txpower) \
1043 ({ \
1044 ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
1045 (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
1046 (__txpower)); \
1047 })