| blob | bc5564258228be1ef0218fe3863c91c3f3b731f5 |
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
21 /*
22 Module: rt2400pci
23 Abstract: Data structures and registers for the rt2400pci module.
24 Supported chipsets: RT2460.
25 */
27 #ifndef RT2400PCI_H
28 #define RT2400PCI_H
30 /*
31 * RF chip defines.
32 */
33 #define RF2420 0x0000
34 #define RF2421 0x0001
36 /*
37 * Signal information.
38 * Defaul offset is required for RSSI <-> dBm conversion.
39 */
40 #define DEFAULT_RSSI_OFFSET 100
42 /*
43 * Register layout information.
44 */
45 #define CSR_REG_BASE 0x0000
46 #define CSR_REG_SIZE 0x014c
47 #define EEPROM_BASE 0x0000
48 #define EEPROM_SIZE 0x0100
49 #define BBP_SIZE 0x0020
50 #define RF_SIZE 0x0010
52 /*
53 * Number of TX queues.
54 */
55 #define NUM_TX_QUEUES 2
57 /*
58 * Control/Status Registers(CSR).
59 * Some values are set in TU, whereas 1 TU == 1024 us.
60 */
62 /*
63 * CSR0: ASIC revision number.
64 */
65 #define CSR0 0x0000
67 /*
68 * CSR1: System control register.
69 * SOFT_RESET: Software reset, 1: reset, 0: normal.
70 * BBP_RESET: Hardware reset, 1: reset, 0, release.
71 * HOST_READY: Host ready after initialization.
72 */
73 #define CSR1 0x0004
74 #define CSR1_SOFT_RESET FIELD32(0x00000001)
75 #define CSR1_BBP_RESET FIELD32(0x00000002)
76 #define CSR1_HOST_READY FIELD32(0x00000004)
78 /*
79 * CSR2: System admin status register (invalid).
80 */
81 #define CSR2 0x0008
83 /*
84 * CSR3: STA MAC address register 0.
85 */
86 #define CSR3 0x000c
87 #define CSR3_BYTE0 FIELD32(0x000000ff)
88 #define CSR3_BYTE1 FIELD32(0x0000ff00)
89 #define CSR3_BYTE2 FIELD32(0x00ff0000)
90 #define CSR3_BYTE3 FIELD32(0xff000000)
92 /*
93 * CSR4: STA MAC address register 1.
94 */
95 #define CSR4 0x0010
96 #define CSR4_BYTE4 FIELD32(0x000000ff)
97 #define CSR4_BYTE5 FIELD32(0x0000ff00)
99 /*
100 * CSR5: BSSID register 0.
101 */
102 #define CSR5 0x0014
103 #define CSR5_BYTE0 FIELD32(0x000000ff)
104 #define CSR5_BYTE1 FIELD32(0x0000ff00)
105 #define CSR5_BYTE2 FIELD32(0x00ff0000)
106 #define CSR5_BYTE3 FIELD32(0xff000000)
108 /*
109 * CSR6: BSSID register 1.
110 */
111 #define CSR6 0x0018
112 #define CSR6_BYTE4 FIELD32(0x000000ff)
113 #define CSR6_BYTE5 FIELD32(0x0000ff00)
115 /*
116 * CSR7: Interrupt source register.
117 * Write 1 to clear interrupt.
118 * TBCN_EXPIRE: Beacon timer expired interrupt.
119 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
120 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
121 * TXDONE_TXRING: Tx ring transmit done interrupt.
122 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
123 * TXDONE_PRIORING: Priority ring transmit done interrupt.
124 * RXDONE: Receive done interrupt.
125 */
126 #define CSR7 0x001c
127 #define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
128 #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
129 #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
130 #define CSR7_TXDONE_TXRING FIELD32(0x00000008)
131 #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
132 #define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
133 #define CSR7_RXDONE FIELD32(0x00000040)
135 /*
136 * CSR8: Interrupt mask register.
137 * Write 1 to mask interrupt.
138 * TBCN_EXPIRE: Beacon timer expired interrupt.
139 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
140 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
141 * TXDONE_TXRING: Tx ring transmit done interrupt.
142 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
143 * TXDONE_PRIORING: Priority ring transmit done interrupt.
144 * RXDONE: Receive done interrupt.
145 */
146 #define CSR8 0x0020
147 #define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
148 #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
149 #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
150 #define CSR8_TXDONE_TXRING FIELD32(0x00000008)
151 #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
152 #define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
153 #define CSR8_RXDONE FIELD32(0x00000040)
155 /*
156 * CSR9: Maximum frame length register.
157 * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
158 */
159 #define CSR9 0x0024
160 #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
162 /*
163 * CSR11: Back-off control register.
164 * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
165 * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
166 * SLOT_TIME: Slot time, default is 20us for 802.11b.
167 * LONG_RETRY: Long retry count.
168 * SHORT_RETRY: Short retry count.
169 */
170 #define CSR11 0x002c
171 #define CSR11_CWMIN FIELD32(0x0000000f)
172 #define CSR11_CWMAX FIELD32(0x000000f0)
173 #define CSR11_SLOT_TIME FIELD32(0x00001f00)
174 #define CSR11_LONG_RETRY FIELD32(0x00ff0000)
175 #define CSR11_SHORT_RETRY FIELD32(0xff000000)
177 /*
178 * CSR12: Synchronization configuration register 0.
179 * All units in 1/16 TU.
180 * BEACON_INTERVAL: Beacon interval, default is 100 TU.
181 * CFPMAX_DURATION: Cfp maximum duration, default is 100 TU.
182 */
183 #define CSR12 0x0030
184 #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
185 #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
187 /*
188 * CSR13: Synchronization configuration register 1.
189 * All units in 1/16 TU.
190 * ATIMW_DURATION: Atim window duration.
191 * CFP_PERIOD: Cfp period, default is 0 TU.
192 */
193 #define CSR13 0x0034
194 #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
195 #define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
197 /*
198 * CSR14: Synchronization control register.
199 * TSF_COUNT: Enable tsf auto counting.
200 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
201 * TBCN: Enable tbcn with reload value.
202 * TCFP: Enable tcfp & cfp / cp switching.
203 * TATIMW: Enable tatimw & atim window switching.
204 * BEACON_GEN: Enable beacon generator.
205 * CFP_COUNT_PRELOAD: Cfp count preload value.
206 * TBCM_PRELOAD: Tbcn preload value in units of 64us.
207 */
208 #define CSR14 0x0038
209 #define CSR14_TSF_COUNT FIELD32(0x00000001)
210 #define CSR14_TSF_SYNC FIELD32(0x00000006)
211 #define CSR14_TBCN FIELD32(0x00000008)
212 #define CSR14_TCFP FIELD32(0x00000010)
213 #define CSR14_TATIMW FIELD32(0x00000020)
214 #define CSR14_BEACON_GEN FIELD32(0x00000040)
215 #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
216 #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
218 /*
219 * CSR15: Synchronization status register.
220 * CFP: ASIC is in contention-free period.
221 * ATIMW: ASIC is in ATIM window.
222 * BEACON_SENT: Beacon is send.
223 */
224 #define CSR15 0x003c
225 #define CSR15_CFP FIELD32(0x00000001)
226 #define CSR15_ATIMW FIELD32(0x00000002)
227 #define CSR15_BEACON_SENT FIELD32(0x00000004)
229 /*
230 * CSR16: TSF timer register 0.
231 */
232 #define CSR16 0x0040
233 #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
235 /*
236 * CSR17: TSF timer register 1.
237 */
238 #define CSR17 0x0044
239 #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
241 /*
242 * CSR18: IFS timer register 0.
243 * SIFS: Sifs, default is 10 us.
244 * PIFS: Pifs, default is 30 us.
245 */
246 #define CSR18 0x0048
247 #define CSR18_SIFS FIELD32(0x0000ffff)
248 #define CSR18_PIFS FIELD32(0xffff0000)
250 /*
251 * CSR19: IFS timer register 1.
252 * DIFS: Difs, default is 50 us.
253 * EIFS: Eifs, default is 364 us.
254 */
255 #define CSR19 0x004c
256 #define CSR19_DIFS FIELD32(0x0000ffff)
257 #define CSR19_EIFS FIELD32(0xffff0000)
259 /*
260 * CSR20: Wakeup timer register.
261 * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
262 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
263 * AUTOWAKE: Enable auto wakeup / sleep mechanism.
264 */
265 #define CSR20 0x0050
266 #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
267 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
268 #define CSR20_AUTOWAKE FIELD32(0x01000000)
270 /*
271 * CSR21: EEPROM control register.
272 * RELOAD: Write 1 to reload eeprom content.
273 * TYPE_93C46: 1: 93c46, 0:93c66.
274 */
275 #define CSR21 0x0054
276 #define CSR21_RELOAD FIELD32(0x00000001)
277 #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
278 #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
279 #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
280 #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
281 #define CSR21_TYPE_93C46 FIELD32(0x00000020)
283 /*
284 * CSR22: CFP control register.
285 * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
286 * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
287 */
288 #define CSR22 0x0058
289 #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
290 #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
292 /*
293 * Transmit related CSRs.
294 * Some values are set in TU, whereas 1 TU == 1024 us.
295 */
297 /*
298 * TXCSR0: TX Control Register.
299 * KICK_TX: Kick tx ring.
300 * KICK_ATIM: Kick atim ring.
301 * KICK_PRIO: Kick priority ring.
302 * ABORT: Abort all transmit related ring operation.
303 */
304 #define TXCSR0 0x0060
305 #define TXCSR0_KICK_TX FIELD32(0x00000001)
306 #define TXCSR0_KICK_ATIM FIELD32(0x00000002)
307 #define TXCSR0_KICK_PRIO FIELD32(0x00000004)
308 #define TXCSR0_ABORT FIELD32(0x00000008)
310 /*
311 * TXCSR1: TX Configuration Register.
312 * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
313 * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
314 * TSF_OFFSET: Insert tsf offset.
315 * AUTORESPONDER: Enable auto responder which include ack & cts.
316 */
317 #define TXCSR1 0x0064
318 #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
319 #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
320 #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
321 #define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
323 /*
324 * TXCSR2: Tx descriptor configuration register.
325 * TXD_SIZE: Tx descriptor size, default is 48.
326 * NUM_TXD: Number of tx entries in ring.
327 * NUM_ATIM: Number of atim entries in ring.
328 * NUM_PRIO: Number of priority entries in ring.
329 */
330 #define TXCSR2 0x0068
331 #define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
332 #define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
333 #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
334 #define TXCSR2_NUM_PRIO FIELD32(0xff000000)
336 /*
337 * TXCSR3: TX Ring Base address register.
338 */
339 #define TXCSR3 0x006c
340 #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
342 /*
343 * TXCSR4: TX Atim Ring Base address register.
344 */
345 #define TXCSR4 0x0070
346 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
348 /*
349 * TXCSR5: TX Prio Ring Base address register.
350 */
351 #define TXCSR5 0x0074
352 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
354 /*
355 * TXCSR6: Beacon Base address register.
356 */
357 #define TXCSR6 0x0078
358 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
360 /*
361 * TXCSR7: Auto responder control register.
362 * AR_POWERMANAGEMENT: Auto responder power management bit.
363 */
364 #define TXCSR7 0x007c
365 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
367 /*
368 * Receive related CSRs.
369 * Some values are set in TU, whereas 1 TU == 1024 us.
370 */
372 /*
373 * RXCSR0: RX Control Register.
374 * DISABLE_RX: Disable rx engine.
375 * DROP_CRC: Drop crc error.
376 * DROP_PHYSICAL: Drop physical error.
377 * DROP_CONTROL: Drop control frame.
378 * DROP_NOT_TO_ME: Drop not to me unicast frame.
379 * DROP_TODS: Drop frame tods bit is true.
380 * DROP_VERSION_ERROR: Drop version error frame.
381 * PASS_CRC: Pass all packets with crc attached.
382 */
383 #define RXCSR0 0x0080
384 #define RXCSR0_DISABLE_RX FIELD32(0x00000001)
385 #define RXCSR0_DROP_CRC FIELD32(0x00000002)
386 #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
387 #define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
388 #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
389 #define RXCSR0_DROP_TODS FIELD32(0x00000020)
390 #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
391 #define RXCSR0_PASS_CRC FIELD32(0x00000080)
393 /*
394 * RXCSR1: RX descriptor configuration register.
395 * RXD_SIZE: Rx descriptor size, default is 32b.
396 * NUM_RXD: Number of rx entries in ring.
397 */
398 #define RXCSR1 0x0084
399 #define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
400 #define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
402 /*
403 * RXCSR2: RX Ring base address register.
404 */
405 #define RXCSR2 0x0088
406 #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
408 /*
409 * RXCSR3: BBP ID register for Rx operation.
410 * BBP_ID#: BBP register # id.
411 * BBP_ID#_VALID: BBP register # id is valid or not.
412 */
413 #define RXCSR3 0x0090
414 #define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
415 #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
416 #define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
417 #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
418 #define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
419 #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
420 #define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
421 #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
423 /*
424 * RXCSR4: BBP ID register for Rx operation.
425 * BBP_ID#: BBP register # id.
426 * BBP_ID#_VALID: BBP register # id is valid or not.
427 */
428 #define RXCSR4 0x0094
429 #define RXCSR4_BBP_ID4 FIELD32(0x0000007f)
430 #define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080)
431 #define RXCSR4_BBP_ID5 FIELD32(0x00007f00)
432 #define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000)
434 /*
435 * ARCSR0: Auto Responder PLCP config register 0.
436 * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
437 * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
438 */
439 #define ARCSR0 0x0098
440 #define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff)
441 #define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00)
442 #define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000)
443 #define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000)
445 /*
446 * ARCSR1: Auto Responder PLCP config register 1.
447 * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
448 * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
449 */
450 #define ARCSR1 0x009c
451 #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
452 #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
453 #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
454 #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
456 /*
457 * Miscellaneous Registers.
458 * Some values are set in TU, whereas 1 TU == 1024 us.
459 */
461 /*
462 * PCICSR: PCI control register.
463 * BIG_ENDIAN: 1: big endian, 0: little endian.
464 * RX_TRESHOLD: Rx threshold in dw to start pci access
465 * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
466 * TX_TRESHOLD: Tx threshold in dw to start pci access
467 * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
468 * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
469 * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
470 */
471 #define PCICSR 0x008c
472 #define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
473 #define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
474 #define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
475 #define PCICSR_BURST_LENTH FIELD32(0x00000060)
476 #define PCICSR_ENABLE_CLK FIELD32(0x00000080)
478 /*
479 * CNT0: FCS error count.
480 * FCS_ERROR: FCS error count, cleared when read.
481 */
482 #define CNT0 0x00a0
483 #define CNT0_FCS_ERROR FIELD32(0x0000ffff)
485 /*
486 * Statistic Register.
487 * CNT1: PLCP error count.
488 * CNT2: Long error count.
489 * CNT3: CCA false alarm count.
490 * CNT4: Rx FIFO overflow count.
491 * CNT5: Tx FIFO underrun count.
492 */
493 #define TIMECSR2 0x00a8
494 #define CNT1 0x00ac
495 #define CNT2 0x00b0
496 #define TIMECSR3 0x00b4
497 #define CNT3 0x00b8
498 #define CNT4 0x00bc
499 #define CNT5 0x00c0
501 /*
502 * Baseband Control Register.
503 */
505 /*
506 * PWRCSR0: Power mode configuration register.
507 */
508 #define PWRCSR0 0x00c4
510 /*
511 * Power state transition time registers.
512 */
513 #define PSCSR0 0x00c8
514 #define PSCSR1 0x00cc
515 #define PSCSR2 0x00d0
516 #define PSCSR3 0x00d4
518 /*
519 * PWRCSR1: Manual power control / status register.
520 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
521 * SET_STATE: Set state. Write 1 to trigger, self cleared.
522 * BBP_DESIRE_STATE: BBP desired state.
523 * RF_DESIRE_STATE: RF desired state.
524 * BBP_CURR_STATE: BBP current state.
525 * RF_CURR_STATE: RF current state.
526 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
527 */
528 #define PWRCSR1 0x00d8
529 #define PWRCSR1_SET_STATE FIELD32(0x00000001)
530 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
531 #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
532 #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
533 #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
534 #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
536 /*
537 * TIMECSR: Timer control register.
538 * US_COUNT: 1 us timer count in units of clock cycles.
539 * US_64_COUNT: 64 us timer count in units of 1 us timer.
540 * BEACON_EXPECT: Beacon expect window.
541 */
542 #define TIMECSR 0x00dc
543 #define TIMECSR_US_COUNT FIELD32(0x000000ff)
544 #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
545 #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
547 /*
548 * MACCSR0: MAC configuration register 0.
549 */
550 #define MACCSR0 0x00e0
552 /*
553 * MACCSR1: MAC configuration register 1.
554 * KICK_RX: Kick one-shot rx in one-shot rx mode.
555 * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
556 * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
557 * AUTO_TXBBP: Auto tx logic access bbp control register.
558 * AUTO_RXBBP: Auto rx logic access bbp control register.
559 * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
560 * INTERSIL_IF: Intersil if calibration pin.
561 */
562 #define MACCSR1 0x00e4
563 #define MACCSR1_KICK_RX FIELD32(0x00000001)
564 #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
565 #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
566 #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
567 #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
568 #define MACCSR1_LOOPBACK FIELD32(0x00000060)
569 #define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
571 /*
572 * RALINKCSR: Ralink Rx auto-reset BBCR.
573 * AR_BBP_DATA#: Auto reset BBP register # data.
574 * AR_BBP_ID#: Auto reset BBP register # id.
575 */
576 #define RALINKCSR 0x00e8
577 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
578 #define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00)
579 #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
580 #define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000)
582 /*
583 * BCNCSR: Beacon interval control register.
584 * CHANGE: Write one to change beacon interval.
585 * DELTATIME: The delta time value.
586 * NUM_BEACON: Number of beacon according to mode.
587 * MODE: Please refer to asic specs.
588 * PLUS: Plus or minus delta time value.
589 */
590 #define BCNCSR 0x00ec
591 #define BCNCSR_CHANGE FIELD32(0x00000001)
592 #define BCNCSR_DELTATIME FIELD32(0x0000001e)
593 #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
594 #define BCNCSR_MODE FIELD32(0x00006000)
595 #define BCNCSR_PLUS FIELD32(0x00008000)
597 /*
598 * BBP / RF / IF Control Register.
599 */
601 /*
602 * BBPCSR: BBP serial control register.
603 * VALUE: Register value to program into BBP.
604 * REGNUM: Selected BBP register.
605 * BUSY: 1: asic is busy execute BBP programming.
606 * WRITE_CONTROL: 1: write BBP, 0: read BBP.
607 */
608 #define BBPCSR 0x00f0
609 #define BBPCSR_VALUE FIELD32(0x000000ff)
610 #define BBPCSR_REGNUM FIELD32(0x00007f00)
611 #define BBPCSR_BUSY FIELD32(0x00008000)
612 #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
614 /*
615 * RFCSR: RF serial control register.
616 * VALUE: Register value + id to program into rf/if.
617 * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
618 * IF_SELECT: Chip to program: 0: rf, 1: if.
619 * PLL_LD: Rf pll_ld status.
620 * BUSY: 1: asic is busy execute rf programming.
621 */
622 #define RFCSR 0x00f4
623 #define RFCSR_VALUE FIELD32(0x00ffffff)
624 #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
625 #define RFCSR_IF_SELECT FIELD32(0x20000000)
626 #define RFCSR_PLL_LD FIELD32(0x40000000)
627 #define RFCSR_BUSY FIELD32(0x80000000)
629 /*
630 * LEDCSR: LED control register.
631 * ON_PERIOD: On period, default 70ms.
632 * OFF_PERIOD: Off period, default 30ms.
633 * LINK: 0: linkoff, 1: linkup.
634 * ACTIVITY: 0: idle, 1: active.
635 */
636 #define LEDCSR 0x00f8
637 #define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
638 #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
639 #define LEDCSR_LINK FIELD32(0x00010000)
640 #define LEDCSR_ACTIVITY FIELD32(0x00020000)
642 /*
643 * ASIC pointer information.
644 * RXPTR: Current RX ring address.
645 * TXPTR: Current Tx ring address.
646 * PRIPTR: Current Priority ring address.
647 * ATIMPTR: Current ATIM ring address.
648 */
649 #define RXPTR 0x0100
650 #define TXPTR 0x0104
651 #define PRIPTR 0x0108
652 #define ATIMPTR 0x010c
654 /*
655 * GPIO and others.
656 */
658 /*
659 * GPIOCSR: GPIO control register.
660 */
661 #define GPIOCSR 0x0120
662 #define GPIOCSR_BIT0 FIELD32(0x00000001)
663 #define GPIOCSR_BIT1 FIELD32(0x00000002)
664 #define GPIOCSR_BIT2 FIELD32(0x00000004)
665 #define GPIOCSR_BIT3 FIELD32(0x00000008)
666 #define GPIOCSR_BIT4 FIELD32(0x00000010)
667 #define GPIOCSR_BIT5 FIELD32(0x00000020)
668 #define GPIOCSR_BIT6 FIELD32(0x00000040)
669 #define GPIOCSR_BIT7 FIELD32(0x00000080)
671 /*
672 * BBPPCSR: BBP Pin control register.
673 */
674 #define BBPPCSR 0x0124
676 /*
677 * BCNCSR1: Tx BEACON offset time control register.
678 * PRELOAD: Beacon timer offset in units of usec.
679 */
680 #define BCNCSR1 0x0130
681 #define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
683 /*
684 * MACCSR2: TX_PE to RX_PE turn-around time control register
685 * DELAY: RX_PE low width, in units of pci clock cycle.
686 */
687 #define MACCSR2 0x0134
688 #define MACCSR2_DELAY FIELD32(0x000000ff)
690 /*
691 * ARCSR2: 1 Mbps ACK/CTS PLCP.
692 */
693 #define ARCSR2 0x013c
694 #define ARCSR2_SIGNAL FIELD32(0x000000ff)
695 #define ARCSR2_SERVICE FIELD32(0x0000ff00)
696 #define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000)
697 #define ARCSR2_LENGTH FIELD32(0xffff0000)
699 /*
700 * ARCSR3: 2 Mbps ACK/CTS PLCP.
701 */
702 #define ARCSR3 0x0140
703 #define ARCSR3_SIGNAL FIELD32(0x000000ff)
704 #define ARCSR3_SERVICE FIELD32(0x0000ff00)
705 #define ARCSR3_LENGTH FIELD32(0xffff0000)
707 /*
708 * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
709 */
710 #define ARCSR4 0x0144
711 #define ARCSR4_SIGNAL FIELD32(0x000000ff)
712 #define ARCSR4_SERVICE FIELD32(0x0000ff00)
713 #define ARCSR4_LENGTH FIELD32(0xffff0000)
715 /*
716 * ARCSR5: 11 Mbps ACK/CTS PLCP.
717 */
718 #define ARCSR5 0x0148
719 #define ARCSR5_SIGNAL FIELD32(0x000000ff)
720 #define ARCSR5_SERVICE FIELD32(0x0000ff00)
721 #define ARCSR5_LENGTH FIELD32(0xffff0000)
723 /*
724 * BBP registers.
725 * The wordsize of the BBP is 8 bits.
726 */
728 /*
729 * R1: TX antenna control
730 */
731 #define BBP_R1_TX_ANTENNA FIELD8(0x03)
733 /*
734 * R4: RX antenna control
735 */
736 #define BBP_R4_RX_ANTENNA FIELD8(0x06)
738 /*
739 * RF registers
740 */
742 /*
743 * RF 1
744 */
745 #define RF1_TUNER FIELD32(0x00020000)
747 /*
748 * RF 3
749 */
750 #define RF3_TUNER FIELD32(0x00000100)
751 #define RF3_TXPOWER FIELD32(0x00003e00)
753 /*
754 * EEPROM content.
755 * The wordsize of the EEPROM is 16 bits.
756 */
758 /*
759 * HW MAC address.
760 */
761 #define EEPROM_MAC_ADDR_0 0x0002
762 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
763 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
764 #define EEPROM_MAC_ADDR1 0x0003
765 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
766 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
767 #define EEPROM_MAC_ADDR_2 0x0004
768 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
769 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
771 /*
772 * EEPROM antenna.
773 * ANTENNA_NUM: Number of antenna's.
774 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
775 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
776 * RF_TYPE: Rf_type of this adapter.
777 * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
778 * RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning.
779 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
780 */
781 #define EEPROM_ANTENNA 0x0b
782 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
783 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
784 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
785 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0040)
786 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x0180)
787 #define EEPROM_ANTENNA_RX_AGCVGC_TUNING FIELD16(0x0200)
788 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
790 /*
791 * EEPROM BBP.
792 */
793 #define EEPROM_BBP_START 0x0c
794 #define EEPROM_BBP_SIZE 7
795 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
796 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
798 /*
799 * EEPROM TXPOWER
800 */
801 #define EEPROM_TXPOWER_START 0x13
802 #define EEPROM_TXPOWER_SIZE 7
803 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
804 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
806 /*
807 * DMA descriptor defines.
808 */
809 #define TXD_DESC_SIZE ( 8 * sizeof(__le32) )
810 #define RXD_DESC_SIZE ( 8 * sizeof(__le32) )
812 /*
813 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
814 */
816 /*
817 * Word0
818 */
819 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
820 #define TXD_W0_VALID FIELD32(0x00000002)
821 #define TXD_W0_RESULT FIELD32(0x0000001c)
822 #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
823 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
824 #define TXD_W0_ACK FIELD32(0x00000200)
825 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
826 #define TXD_W0_RTS FIELD32(0x00000800)
827 #define TXD_W0_IFS FIELD32(0x00006000)
828 #define TXD_W0_RETRY_MODE FIELD32(0x00008000)
829 #define TXD_W0_AGC FIELD32(0x00ff0000)
830 #define TXD_W0_R2 FIELD32(0xff000000)
832 /*
833 * Word1
834 */
835 #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
837 /*
838 * Word2
839 */
840 #define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
841 #define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000)
843 /*
844 * Word3 & 4: PLCP information
845 * The PLCP values should be treated as if they were BBP values.
846 */
847 #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
848 #define TXD_W3_PLCP_SIGNAL_REGNUM FIELD32(0x00007f00)
849 #define TXD_W3_PLCP_SIGNAL_BUSY FIELD32(0x00008000)
850 #define TXD_W3_PLCP_SERVICE FIELD32(0x00ff0000)
851 #define TXD_W3_PLCP_SERVICE_REGNUM FIELD32(0x7f000000)
852 #define TXD_W3_PLCP_SERVICE_BUSY FIELD32(0x80000000)
854 #define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x000000ff)
855 #define TXD_W3_PLCP_LENGTH_LOW_REGNUM FIELD32(0x00007f00)
856 #define TXD_W3_PLCP_LENGTH_LOW_BUSY FIELD32(0x00008000)
857 #define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0x00ff0000)
858 #define TXD_W3_PLCP_LENGTH_HIGH_REGNUM FIELD32(0x7f000000)
859 #define TXD_W3_PLCP_LENGTH_HIGH_BUSY FIELD32(0x80000000)
861 /*
862 * Word5
863 */
864 #define TXD_W5_BBCR4 FIELD32(0x0000ffff)
865 #define TXD_W5_AGC_REG FIELD32(0x007f0000)
866 #define TXD_W5_AGC_REG_VALID FIELD32(0x00800000)
867 #define TXD_W5_XXX_REG FIELD32(0x7f000000)
868 #define TXD_W5_XXX_REG_VALID FIELD32(0x80000000)
870 /*
871 * Word6
872 */
873 #define TXD_W6_SK_BUFF FIELD32(0xffffffff)
875 /*
876 * Word7
877 */
878 #define TXD_W7_RESERVED FIELD32(0xffffffff)
880 /*
881 * RX descriptor format for RX Ring.
882 */
884 /*
885 * Word0
886 */
887 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
888 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
889 #define RXD_W0_MULTICAST FIELD32(0x00000004)
890 #define RXD_W0_BROADCAST FIELD32(0x00000008)
891 #define RXD_W0_MY_BSS FIELD32(0x00000010)
892 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
893 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
894 #define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000)
896 /*
897 * Word1
898 */
899 #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
901 /*
902 * Word2
903 */
904 #define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
905 #define RXD_W2_BBR0 FIELD32(0x00ff0000)
906 #define RXD_W2_SIGNAL FIELD32(0xff000000)
908 /*
909 * Word3
910 */
911 #define RXD_W3_RSSI FIELD32(0x000000ff)
912 #define RXD_W3_BBR3 FIELD32(0x0000ff00)
913 #define RXD_W3_BBR4 FIELD32(0x00ff0000)
914 #define RXD_W3_BBR5 FIELD32(0xff000000)
916 /*
917 * Word4
918 */
919 #define RXD_W4_RX_END_TIME FIELD32(0xffffffff)
921 /*
922 * Word5 & 6 & 7: Reserved
923 */
924 #define RXD_W5_RESERVED FIELD32(0xffffffff)
925 #define RXD_W6_RESERVED FIELD32(0xffffffff)
926 #define RXD_W7_RESERVED FIELD32(0xffffffff)
928 /*
929 * Macro's for converting txpower from EEPROM to mac80211 value
930 * and from mac80211 value to register value.
931 * NOTE: Logics in rt2400pci for txpower are reversed
932 * compared to the other rt2x00 drivers. A higher txpower
933 * value means that the txpower must be lowered. This is
934 * important when converting the value coming from the
935 * mac80211 stack to the rt2400 acceptable value.
936 */
937 #define MIN_TXPOWER 31
938 #define MAX_TXPOWER 62
939 #define DEFAULT_TXPOWER 39
941 #define TXPOWER_FROM_DEV(__txpower) \
942 ({ \
943 ((__txpower) > MAX_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER : \
944 ((__txpower) < MIN_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER : \
945 (((__txpower) - MAX_TXPOWER) + MIN_TXPOWER); \
946 })
948 #define TXPOWER_TO_DEV(__txpower) \
949 ({ \
950 (__txpower) += MIN_TXPOWER; \
951 ((__txpower) <= MIN_TXPOWER) ? MAX_TXPOWER : \
952 (((__txpower) >= MAX_TXPOWER) ? MIN_TXPOWER : \
953 (MAX_TXPOWER - ((__txpower) - MIN_TXPOWER))); \
954 })