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ath5k: Misc hw_attach fixes
[linux-2.6/libata-dev.git] / drivers / net / wireless / ath5k / hw.c
blob8cd8659e9128b608fcfb2fbb0a16dd0577ccf5c2
1 /*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23 /*
24 * HW related functions for Atheros Wireless LAN devices.
25 */
26
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29
30 #include "reg.h"
31 #include "base.h"
32 #include "debug.h"
33
34 /* Rate tables */
35 static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A;
36 static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B;
37 static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G;
38 static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO;
39 static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR;
40
41 /* Prototypes */
42 static int ath5k_hw_nic_reset(struct ath5k_hw *, u32);
43 static int ath5k_hw_nic_wakeup(struct ath5k_hw *, int, bool);
44 static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
45 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
46 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
47 unsigned int, unsigned int);
48 static int ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
49 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
50 unsigned int);
51 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc *,
52 struct ath5k_tx_status *);
53 static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
54 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
55 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
56 unsigned int, unsigned int);
57 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *, struct ath5k_desc *,
58 struct ath5k_tx_status *);
59 static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *, struct ath5k_desc *,
60 struct ath5k_rx_status *);
61 static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *, struct ath5k_desc *,
62 struct ath5k_rx_status *);
63 static int ath5k_hw_get_capabilities(struct ath5k_hw *);
64
65 static int ath5k_eeprom_init(struct ath5k_hw *);
66 static int ath5k_eeprom_read_mac(struct ath5k_hw *, u8 *);
67
68 static int ath5k_hw_enable_pspoll(struct ath5k_hw *, u8 *, u16);
69 static int ath5k_hw_disable_pspoll(struct ath5k_hw *);
70
71 /*
72 * Enable to overwrite the country code (use "00" for debug)
73 */
74 #if 0
75 #define COUNTRYCODE "00"
76 #endif
77
78 /*******************\
79 General Functions
80 \*******************/
81
82 /*
83 * Functions used internaly
84 */
85
86 static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
87 {
88 return turbo ? (usec * 80) : (usec * 40);
89 }
90
91 static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
92 {
93 return turbo ? (clock / 80) : (clock / 40);
94 }
95
96 /*
97 * Check if a register write has been completed
98 */
99 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
100 bool is_set)
101 {
102 int i;
103 u32 data;
104
105 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
106 data = ath5k_hw_reg_read(ah, reg);
107 if (is_set && (data & flag))
108 break;
109 else if ((data & flag) == val)
110 break;
111 udelay(15);
112 }
113
114 return (i <= 0) ? -EAGAIN : 0;
115 }
116
117
118 /***************************************\
119 Attach/Detach Functions
120 \***************************************/
121
122 /*
123 * Power On Self Test helper function
124 */
125 static int ath5k_hw_post(struct ath5k_hw *ah)
126 {
127
128 int i, c;
129 u16 cur_reg;
130 u16 regs[2] = {AR5K_STA_ID0, AR5K_PHY(8)};
131 u32 var_pattern;
132 u32 static_pattern[4] = {
133 0x55555555, 0xaaaaaaaa,
134 0x66666666, 0x99999999
135 };
136 u32 init_val;
137 u32 cur_val;
138
139 for (c = 0; c < 2; c++) {
140
141 cur_reg = regs[c];
142
143 /* Save previous value */
144 init_val = ath5k_hw_reg_read(ah, cur_reg);
145
146 for (i = 0; i < 256; i++) {
147 var_pattern = i << 16 | i;
148 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
149 cur_val = ath5k_hw_reg_read(ah, cur_reg);
150
151 if (cur_val != var_pattern) {
152 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
153 return -EAGAIN;
154 }
155
156 /* Found on ndiswrapper dumps */
157 var_pattern = 0x0039080f;
158 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
159 }
160
161 for (i = 0; i < 4; i++) {
162 var_pattern = static_pattern[i];
163 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
164 cur_val = ath5k_hw_reg_read(ah, cur_reg);
165
166 if (cur_val != var_pattern) {
167 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
168 return -EAGAIN;
169 }
170
171 /* Found on ndiswrapper dumps */
172 var_pattern = 0x003b080f;
173 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
174 }
175
176 /* Restore previous value */
177 ath5k_hw_reg_write(ah, init_val, cur_reg);
178
179 }
180
181 return 0;
182
183 }
184
185 /*
186 * Check if the device is supported and initialize the needed structs
187 */
188 struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
189 {
190 struct ath5k_hw *ah;
191 struct pci_dev *pdev = sc->pdev;
192 u8 mac[ETH_ALEN];
193 int ret;
194 u32 srev;
195
196 /*If we passed the test malloc a ath5k_hw struct*/
197 ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
198 if (ah == NULL) {
199 ret = -ENOMEM;
200 ATH5K_ERR(sc, "out of memory\n");
201 goto err;
202 }
203
204 ah->ah_sc = sc;
205 ah->ah_iobase = sc->iobase;
206
207 /*
208 * HW information
209 */
210
211 ah->ah_op_mode = IEEE80211_IF_TYPE_STA;
212 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
213 ah->ah_turbo = false;
214 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
215 ah->ah_imr = 0;
216 ah->ah_atim_window = 0;
217 ah->ah_aifs = AR5K_TUNE_AIFS;
218 ah->ah_cw_min = AR5K_TUNE_CWMIN;
219 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
220 ah->ah_software_retry = false;
221 ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
222
223 /*
224 * Set the mac revision based on the pci id
225 */
226 ah->ah_version = mac_version;
227
228 /*Fill the ath5k_hw struct with the needed functions*/
229 if (ah->ah_version == AR5K_AR5212)
230 ah->ah_magic = AR5K_EEPROM_MAGIC_5212;
231 else if (ah->ah_version == AR5K_AR5211)
232 ah->ah_magic = AR5K_EEPROM_MAGIC_5211;
233
234 if (ah->ah_version == AR5K_AR5212) {
235 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
236 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
237 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
238 } else {
239 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
240 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
241 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
242 }
243
244 if (ah->ah_version == AR5K_AR5212)
245 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
246 else if (ah->ah_version <= AR5K_AR5211)
247 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
248
249 /* Bring device out of sleep and reset it's units */
250 ret = ath5k_hw_nic_wakeup(ah, AR5K_INIT_MODE, true);
251 if (ret)
252 goto err_free;
253
254 /* Get MAC, PHY and RADIO revisions */
255 srev = ath5k_hw_reg_read(ah, AR5K_SREV);
256 ah->ah_mac_srev = srev;
257 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
258 ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
259 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
260 0xffffffff;
261 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
262 CHANNEL_5GHZ);
263
264 if (ah->ah_version == AR5K_AR5210)
265 ah->ah_radio_2ghz_revision = 0;
266 else
267 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
268 CHANNEL_2GHZ);
269
270 /* Return on unsuported chips (unsupported eeprom etc) */
271 if ((srev >= AR5K_SREV_VER_AR5416) &&
272 (srev < AR5K_SREV_VER_AR2425)) {
273 ATH5K_ERR(sc, "Device not yet supported.\n");
274 ret = -ENODEV;
275 goto err_free;
276 } else if (srev == AR5K_SREV_VER_AR2425) {
277 ATH5K_WARN(sc, "Support for RF2425 is under development.\n");
278 }
279
280 /* Identify single chip solutions */
281 if (((srev <= AR5K_SREV_VER_AR5414) &&
282 (srev >= AR5K_SREV_VER_AR2413)) ||
283 (srev == AR5K_SREV_VER_AR2425)) {
284 ah->ah_single_chip = true;
285 } else {
286 ah->ah_single_chip = false;
287 }
288
289 /* Single chip radio */
290 if (ah->ah_radio_2ghz_revision == ah->ah_radio_5ghz_revision)
291 ah->ah_radio_2ghz_revision = 0;
292
293 /* Identify the radio chip*/
294 if (ah->ah_version == AR5K_AR5210) {
295 ah->ah_radio = AR5K_RF5110;
296 /*
297 * Register returns 0x0/0x04 for radio revision
298 * so ath5k_hw_radio_revision doesn't parse the value
299 * correctly. For now we are based on mac's srev to
300 * identify RF2425 radio.
301 */
302 } else if (srev == AR5K_SREV_VER_AR2425) {
303 ah->ah_radio = AR5K_RF2425;
304 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
305 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
306 ah->ah_radio = AR5K_RF5111;
307 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
308 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC0) {
309 ah->ah_radio = AR5K_RF5112;
310 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
311 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) {
312 ah->ah_radio = AR5K_RF2413;
313 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
314 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC2) {
315 ah->ah_radio = AR5K_RF5413;
316 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
317 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) {
318 /* AR5424 */
319 if (srev >= AR5K_SREV_VER_AR5424) {
320 ah->ah_radio = AR5K_RF5413;
321 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
322 /* AR2424 */
323 } else {
324 ah->ah_radio = AR5K_RF2413; /* For testing */
325 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
326 }
327 }
328 ah->ah_phy = AR5K_PHY(0);
329
330 /*
331 * Write PCI-E power save settings
332 */
333 if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
334 ath5k_hw_reg_write(ah, 0x9248fc00, 0x4080);
335 ath5k_hw_reg_write(ah, 0x24924924, 0x4080);
336 ath5k_hw_reg_write(ah, 0x28000039, 0x4080);
337 ath5k_hw_reg_write(ah, 0x53160824, 0x4080);
338 ath5k_hw_reg_write(ah, 0xe5980579, 0x4080);
339 ath5k_hw_reg_write(ah, 0x001defff, 0x4080);
340 ath5k_hw_reg_write(ah, 0x1aaabe40, 0x4080);
341 ath5k_hw_reg_write(ah, 0xbe105554, 0x4080);
342 ath5k_hw_reg_write(ah, 0x000e3007, 0x4080);
343 ath5k_hw_reg_write(ah, 0x00000000, 0x4084);
344 }
345
346 /*
347 * POST
348 */
349 ret = ath5k_hw_post(ah);
350 if (ret)
351 goto err_free;
352
353 /* Write AR5K_PCICFG_UNK on 2112B and later chips */
354 if (ah->ah_radio_5ghz_revision > AR5K_SREV_RAD_2112B ||
355 srev > AR5K_SREV_VER_AR2413) {
356 ath5k_hw_reg_write(ah, AR5K_PCICFG_UNK, AR5K_PCICFG);
357 }
358
359 /*
360 * Get card capabilities, values, ...
361 */
362 ret = ath5k_eeprom_init(ah);
363 if (ret) {
364 ATH5K_ERR(sc, "unable to init EEPROM\n");
365 goto err_free;
366 }
367
368 /* Get misc capabilities */
369 ret = ath5k_hw_get_capabilities(ah);
370 if (ret) {
371 ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
372 sc->pdev->device);
373 goto err_free;
374 }
375
376 /* Get MAC address */
377 ret = ath5k_eeprom_read_mac(ah, mac);
378 if (ret) {
379 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
380 sc->pdev->device);
381 goto err_free;
382 }
383
384 ath5k_hw_set_lladdr(ah, mac);
385 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
386 memset(ah->ah_bssid, 0xff, ETH_ALEN);
387 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
388 ath5k_hw_set_opmode(ah);
389
390 ath5k_hw_set_rfgain_opt(ah);
391
392 return ah;
393 err_free:
394 kfree(ah);
395 err:
396 return ERR_PTR(ret);
397 }
398
399 /*
400 * Bring up MAC + PHY Chips
401 */
402 static int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
403 {
404 struct pci_dev *pdev = ah->ah_sc->pdev;
405 u32 turbo, mode, clock, bus_flags;
406 int ret;
407
408 turbo = 0;
409 mode = 0;
410 clock = 0;
411
412 ATH5K_TRACE(ah->ah_sc);
413
414 /* Wakeup the device */
415 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
416 if (ret) {
417 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
418 return ret;
419 }
420
421 if (ah->ah_version != AR5K_AR5210) {
422 /*
423 * Get channel mode flags
424 */
425
426 if (ah->ah_radio >= AR5K_RF5112) {
427 mode = AR5K_PHY_MODE_RAD_RF5112;
428 clock = AR5K_PHY_PLL_RF5112;
429 } else {
430 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
431 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
432 }
433
434 if (flags & CHANNEL_2GHZ) {
435 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
436 clock |= AR5K_PHY_PLL_44MHZ;
437
438 if (flags & CHANNEL_CCK) {
439 mode |= AR5K_PHY_MODE_MOD_CCK;
440 } else if (flags & CHANNEL_OFDM) {
441 /* XXX Dynamic OFDM/CCK is not supported by the
442 * AR5211 so we set MOD_OFDM for plain g (no
443 * CCK headers) operation. We need to test
444 * this, 5211 might support ofdm-only g after
445 * all, there are also initial register values
446 * in the code for g mode (see initvals.c). */
447 if (ah->ah_version == AR5K_AR5211)
448 mode |= AR5K_PHY_MODE_MOD_OFDM;
449 else
450 mode |= AR5K_PHY_MODE_MOD_DYN;
451 } else {
452 ATH5K_ERR(ah->ah_sc,
453 "invalid radio modulation mode\n");
454 return -EINVAL;
455 }
456 } else if (flags & CHANNEL_5GHZ) {
457 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
458 clock |= AR5K_PHY_PLL_40MHZ;
459
460 if (flags & CHANNEL_OFDM)
461 mode |= AR5K_PHY_MODE_MOD_OFDM;
462 else {
463 ATH5K_ERR(ah->ah_sc,
464 "invalid radio modulation mode\n");
465 return -EINVAL;
466 }
467 } else {
468 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
469 return -EINVAL;
470 }
471
472 if (flags & CHANNEL_TURBO)
473 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
474 } else { /* Reset the device */
475
476 /* ...enable Atheros turbo mode if requested */
477 if (flags & CHANNEL_TURBO)
478 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
479 AR5K_PHY_TURBO);
480 }
481
482 /* reseting PCI on PCI-E cards results card to hang
483 * and always return 0xffff... so we ingore that flag
484 * for PCI-E cards */
485 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
486
487 /* Reset chipset */
488 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
489 AR5K_RESET_CTL_BASEBAND | bus_flags);
490 if (ret) {
491 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
492 return -EIO;
493 }
494
495 if (ah->ah_version == AR5K_AR5210)
496 udelay(2300);
497
498 /* ...wakeup again!*/
499 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
500 if (ret) {
501 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
502 return ret;
503 }
504
505 /* ...final warm reset */
506 if (ath5k_hw_nic_reset(ah, 0)) {
507 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
508 return -EIO;
509 }
510
511 if (ah->ah_version != AR5K_AR5210) {
512 /* ...set the PHY operating mode */
513 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
514 udelay(300);
515
516 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
517 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
518 }
519
520 return 0;
521 }
522
523 /*
524 * Get the rate table for a specific operation mode
525 */
526 const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah,
527 unsigned int mode)
528 {
529 ATH5K_TRACE(ah->ah_sc);
530
531 if (!test_bit(mode, ah->ah_capabilities.cap_mode))
532 return NULL;
533
534 /* Get rate tables */
535 switch (mode) {
536 case AR5K_MODE_11A:
537 return &ath5k_rt_11a;
538 case AR5K_MODE_11A_TURBO:
539 return &ath5k_rt_turbo;
540 case AR5K_MODE_11B:
541 return &ath5k_rt_11b;
542 case AR5K_MODE_11G:
543 return &ath5k_rt_11g;
544 case AR5K_MODE_11G_TURBO:
545 return &ath5k_rt_xr;
546 }
547
548 return NULL;
549 }
550
551 /*
552 * Free the ath5k_hw struct
553 */
554 void ath5k_hw_detach(struct ath5k_hw *ah)
555 {
556 ATH5K_TRACE(ah->ah_sc);
557
558 __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
559
560 if (ah->ah_rf_banks != NULL)
561 kfree(ah->ah_rf_banks);
562
563 /* assume interrupts are down */
564 kfree(ah);
565 }
566
567 /****************************\
568 Reset function and helpers
569 \****************************/
570
571 /**
572 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
573 *
574 * @ah: the &struct ath5k_hw
575 * @channel: the currently set channel upon reset
576 *
577 * Write the OFDM timings for the AR5212 upon reset. This is a helper for
578 * ath5k_hw_reset(). This seems to tune the PLL a specified frequency
579 * depending on the bandwidth of the channel.
580 *
581 */
582 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
583 struct ieee80211_channel *channel)
584 {
585 /* Get exponent and mantissa and set it */
586 u32 coef_scaled, coef_exp, coef_man,
587 ds_coef_exp, ds_coef_man, clock;
588
589 if (!(ah->ah_version == AR5K_AR5212) ||
590 !(channel->hw_value & CHANNEL_OFDM))
591 BUG();
592
593 /* Seems there are two PLLs, one for baseband sampling and one
594 * for tuning. Tuning basebands are 40 MHz or 80MHz when in
595 * turbo. */
596 clock = channel->hw_value & CHANNEL_TURBO ? 80 : 40;
597 coef_scaled = ((5 * (clock << 24)) / 2) /
598 channel->center_freq;
599
600 for (coef_exp = 31; coef_exp > 0; coef_exp--)
601 if ((coef_scaled >> coef_exp) & 0x1)
602 break;
603
604 if (!coef_exp)
605 return -EINVAL;
606
607 coef_exp = 14 - (coef_exp - 24);
608 coef_man = coef_scaled +
609 (1 << (24 - coef_exp - 1));
610 ds_coef_man = coef_man >> (24 - coef_exp);
611 ds_coef_exp = coef_exp - 16;
612
613 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
614 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
615 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
616 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
617
618 return 0;
619 }
620
621 /**
622 * ath5k_hw_write_rate_duration - set rate duration during hw resets
623 *
624 * @ah: the &struct ath5k_hw
625 * @mode: one of enum ath5k_driver_mode
626 *
627 * Write the rate duration table for the current mode upon hw reset. This
628 * is a helper for ath5k_hw_reset(). It seems all this is doing is setting
629 * an ACK timeout for the hardware for the current mode for each rate. The
630 * rates which are capable of short preamble (802.11b rates 2Mbps, 5.5Mbps,
631 * and 11Mbps) have another register for the short preamble ACK timeout
632 * calculation.
633 *
634 */
635 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
636 unsigned int mode)
637 {
638 struct ath5k_softc *sc = ah->ah_sc;
639 const struct ath5k_rate_table *rt;
640 struct ieee80211_rate srate = {};
641 unsigned int i;
642
643 /* Get rate table for the current operating mode */
644 rt = ath5k_hw_get_rate_table(ah, mode);
645
646 /* Write rate duration table */
647 for (i = 0; i < rt->rate_count; i++) {
648 const struct ath5k_rate *rate, *control_rate;
649
650 u32 reg;
651 u16 tx_time;
652
653 rate = &rt->rates[i];
654 control_rate = &rt->rates[rate->control_rate];
655
656 /* Set ACK timeout */
657 reg = AR5K_RATE_DUR(rate->rate_code);
658
659 srate.bitrate = control_rate->rate_kbps/100;
660
661 /* An ACK frame consists of 10 bytes. If you add the FCS,
662 * which ieee80211_generic_frame_duration() adds,
663 * its 14 bytes. Note we use the control rate and not the
664 * actual rate for this rate. See mac80211 tx.c
665 * ieee80211_duration() for a brief description of
666 * what rate we should choose to TX ACKs. */
667 tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw,
668 sc->vif, 10, &srate));
669
670 ath5k_hw_reg_write(ah, tx_time, reg);
671
672 if (!HAS_SHPREAMBLE(i))
673 continue;
674
675 /*
676 * We're not distinguishing short preamble here,
677 * This is true, all we'll get is a longer value here
678 * which is not necessarilly bad. We could use
679 * export ieee80211_frame_duration() but that needs to be
680 * fixed first to be properly used by mac802111 drivers:
681 *
682 * - remove erp stuff and let the routine figure ofdm
683 * erp rates
684 * - remove passing argument ieee80211_local as
685 * drivers don't have access to it
686 * - move drivers using ieee80211_generic_frame_duration()
687 * to this
688 */
689 ath5k_hw_reg_write(ah, tx_time,
690 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
691 }
692 }
693
694 /*
695 * Main reset function
696 */
697 int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
698 struct ieee80211_channel *channel, bool change_channel)
699 {
700 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
701 struct pci_dev *pdev = ah->ah_sc->pdev;
702 u32 data, s_seq, s_ant, s_led[3], dma_size;
703 unsigned int i, mode, freq, ee_mode, ant[2];
704 int ret;
705
706 ATH5K_TRACE(ah->ah_sc);
707
708 s_seq = 0;
709 s_ant = 0;
710 ee_mode = 0;
711 freq = 0;
712 mode = 0;
713
714 /*
715 * Save some registers before a reset
716 */
717 /*DCU/Antenna selection not available on 5210*/
718 if (ah->ah_version != AR5K_AR5210) {
719 if (change_channel) {
720 /* Seq number for queue 0 -do this for all queues ? */
721 s_seq = ath5k_hw_reg_read(ah,
722 AR5K_QUEUE_DFS_SEQNUM(0));
723 /*Default antenna*/
724 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
725 }
726 }
727
728 /*GPIOs*/
729 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE;
730 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
731 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
732
733 if (change_channel && ah->ah_rf_banks != NULL)
734 ath5k_hw_get_rf_gain(ah);
735
736
737 /*Wakeup the device*/
738 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
739 if (ret)
740 return ret;
741
742 /*
743 * Initialize operating mode
744 */
745 ah->ah_op_mode = op_mode;
746
747 /*
748 * 5111/5112 Settings
749 * 5210 only comes with RF5110
750 */
751 if (ah->ah_version != AR5K_AR5210) {
752 if (ah->ah_radio != AR5K_RF5111 &&
753 ah->ah_radio != AR5K_RF5112 &&
754 ah->ah_radio != AR5K_RF5413 &&
755 ah->ah_radio != AR5K_RF2413 &&
756 ah->ah_radio != AR5K_RF2425) {
757 ATH5K_ERR(ah->ah_sc,
758 "invalid phy radio: %u\n", ah->ah_radio);
759 return -EINVAL;
760 }
761
762 switch (channel->hw_value & CHANNEL_MODES) {
763 case CHANNEL_A:
764 mode = AR5K_MODE_11A;
765 freq = AR5K_INI_RFGAIN_5GHZ;
766 ee_mode = AR5K_EEPROM_MODE_11A;
767 break;
768 case CHANNEL_G:
769 mode = AR5K_MODE_11G;
770 freq = AR5K_INI_RFGAIN_2GHZ;
771 ee_mode = AR5K_EEPROM_MODE_11G;
772 break;
773 case CHANNEL_B:
774 mode = AR5K_MODE_11B;
775 freq = AR5K_INI_RFGAIN_2GHZ;
776 ee_mode = AR5K_EEPROM_MODE_11B;
777 break;
778 case CHANNEL_T:
779 mode = AR5K_MODE_11A_TURBO;
780 freq = AR5K_INI_RFGAIN_5GHZ;
781 ee_mode = AR5K_EEPROM_MODE_11A;
782 break;
783 /*Is this ok on 5211 too ?*/
784 case CHANNEL_TG:
785 mode = AR5K_MODE_11G_TURBO;
786 freq = AR5K_INI_RFGAIN_2GHZ;
787 ee_mode = AR5K_EEPROM_MODE_11G;
788 break;
789 case CHANNEL_XR:
790 if (ah->ah_version == AR5K_AR5211) {
791 ATH5K_ERR(ah->ah_sc,
792 "XR mode not available on 5211");
793 return -EINVAL;
794 }
795 mode = AR5K_MODE_XR;
796 freq = AR5K_INI_RFGAIN_5GHZ;
797 ee_mode = AR5K_EEPROM_MODE_11A;
798 break;
799 default:
800 ATH5K_ERR(ah->ah_sc,
801 "invalid channel: %d\n", channel->center_freq);
802 return -EINVAL;
803 }
804
805 /* PHY access enable */
806 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
807
808 }
809
810 ret = ath5k_hw_write_initvals(ah, mode, change_channel);
811 if (ret)
812 return ret;
813
814 /*
815 * 5211/5212 Specific
816 */
817 if (ah->ah_version != AR5K_AR5210) {
818 /*
819 * Write initial RF gain settings
820 * This should work for both 5111/5112
821 */
822 ret = ath5k_hw_rfgain(ah, freq);
823 if (ret)
824 return ret;
825
826 mdelay(1);
827
828 /*
829 * Write some more initial register settings
830 */
831 if (ah->ah_version == AR5K_AR5212) {
832 ath5k_hw_reg_write(ah, 0x0002a002, 0x982c);
833
834 if (channel->hw_value == CHANNEL_G)
835 if (ah->ah_mac_srev < AR5K_SREV_VER_AR2413)
836 ath5k_hw_reg_write(ah, 0x00f80d80,
837 0x994c);
838 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2424)
839 ath5k_hw_reg_write(ah, 0x00380140,
840 0x994c);
841 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2425)
842 ath5k_hw_reg_write(ah, 0x00fc0ec0,
843 0x994c);
844 else /* 2425 */
845 ath5k_hw_reg_write(ah, 0x00fc0fc0,
846 0x994c);
847 else
848 ath5k_hw_reg_write(ah, 0x00000000, 0x994c);
849
850 ath5k_hw_reg_write(ah, 0x000009b5, 0xa228);
851 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
852 ath5k_hw_reg_write(ah, 0x00000000, 0xa254);
853 ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL);
854 }
855
856 /* Fix for first revision of the RF5112 RF chipset */
857 if (ah->ah_radio >= AR5K_RF5112 &&
858 ah->ah_radio_5ghz_revision <
859 AR5K_SREV_RAD_5112A) {
860 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
861 AR5K_PHY_CCKTXCTL);
862 if (channel->hw_value & CHANNEL_5GHZ)
863 data = 0xffb81020;
864 else
865 data = 0xffb80d20;
866 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
867 }
868
869 /*
870 * Set TX power (FIXME)
871 */
872 ret = ath5k_hw_txpower(ah, channel, AR5K_TUNE_DEFAULT_TXPOWER);
873 if (ret)
874 return ret;
875
876 /* Write rate duration table only on AR5212 and if
877 * virtual interface has already been brought up
878 * XXX: rethink this after new mode changes to
879 * mac80211 are integrated */
880 if (ah->ah_version == AR5K_AR5212 &&
881 ah->ah_sc->vif != NULL)
882 ath5k_hw_write_rate_duration(ah, mode);
883
884 /*
885 * Write RF registers
886 * TODO:Does this work on 5211 (5111) ?
887 */
888 ret = ath5k_hw_rfregs(ah, channel, mode);
889 if (ret)
890 return ret;
891
892 /*
893 * Configure additional registers
894 */
895
896 /* Write OFDM timings on 5212*/
897 if (ah->ah_version == AR5K_AR5212 &&
898 channel->hw_value & CHANNEL_OFDM) {
899 ret = ath5k_hw_write_ofdm_timings(ah, channel);
900 if (ret)
901 return ret;
902 }
903
904 /*Enable/disable 802.11b mode on 5111
905 (enable 2111 frequency converter + CCK)*/
906 if (ah->ah_radio == AR5K_RF5111) {
907 if (mode == AR5K_MODE_11B)
908 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
909 AR5K_TXCFG_B_MODE);
910 else
911 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
912 AR5K_TXCFG_B_MODE);
913 }
914
915 /*
916 * Set channel and calibrate the PHY
917 */
918 ret = ath5k_hw_channel(ah, channel);
919 if (ret)
920 return ret;
921
922 /* Set antenna mode */
923 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_ANT_CTL,
924 ah->ah_antenna[ee_mode][0], 0xfffffc06);
925
926 /*
927 * In case a fixed antenna was set as default
928 * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE
929 * registers.
930 */
931 if (s_ant != 0){
932 if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */
933 ant[0] = ant[1] = AR5K_ANT_FIXED_A;
934 else /* 2 - Aux */
935 ant[0] = ant[1] = AR5K_ANT_FIXED_B;
936 } else {
937 ant[0] = AR5K_ANT_FIXED_A;
938 ant[1] = AR5K_ANT_FIXED_B;
939 }
940
941 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[0]],
942 AR5K_PHY_ANT_SWITCH_TABLE_0);
943 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[1]],
944 AR5K_PHY_ANT_SWITCH_TABLE_1);
945
946 /* Commit values from EEPROM */
947 if (ah->ah_radio == AR5K_RF5111)
948 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
949 AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip);
950
951 ath5k_hw_reg_write(ah,
952 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
953 AR5K_PHY_NFTHRES);
954
955 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_SETTLING,
956 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80,
957 0xffffc07f);
958 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_GAIN,
959 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000,
960 0xfffc0fff);
961 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_DESIRED_SIZE,
962 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
963 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00),
964 0xffff0000);
965
966 ath5k_hw_reg_write(ah,
967 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
968 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
969 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
970 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
971
972 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_RF_CTL3,
973 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
974 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_NF,
975 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
976 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 4, 0xffffff01);
977
978 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
979 AR5K_PHY_IQ_CORR_ENABLE |
980 (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
981 ee->ee_q_cal[ee_mode]);
982
983 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
984 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
985 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
986 ee->ee_margin_tx_rx[ee_mode]);
987
988 } else {
989 mdelay(1);
990 /* Disable phy and wait */
991 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
992 mdelay(1);
993 }
994
995 /*
996 * Restore saved values
997 */
998 /*DCU/Antenna selection not available on 5210*/
999 if (ah->ah_version != AR5K_AR5210) {
1000 ath5k_hw_reg_write(ah, s_seq, AR5K_QUEUE_DFS_SEQNUM(0));
1001 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
1002 }
1003 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1004 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1005 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1006
1007 /*
1008 * Misc
1009 */
1010 /* XXX: add ah->aid once mac80211 gives this to us */
1011 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
1012
1013 ath5k_hw_set_opmode(ah);
1014 /*PISR/SISR Not available on 5210*/
1015 if (ah->ah_version != AR5K_AR5210) {
1016 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
1017 /* If we later allow tuning for this, store into sc structure */
1018 data = AR5K_TUNE_RSSI_THRES |
1019 AR5K_TUNE_BMISS_THRES << AR5K_RSSI_THR_BMISS_S;
1020 ath5k_hw_reg_write(ah, data, AR5K_RSSI_THR);
1021 }
1022
1023 /*
1024 * Set Rx/Tx DMA Configuration
1025 *
1026 * Set maximum DMA size (512) except for PCI-E cards since
1027 * it causes rx overruns and tx errors (tested on 5424 but since
1028 * rx overruns also occur on 5416/5418 with madwifi we set 128
1029 * for all PCI-E cards to be safe).
1030 *
1031 * In dumps this is 128 for allchips.
1032 *
1033 * XXX: need to check 5210 for this
1034 * TODO: Check out tx triger level, it's always 64 on dumps but I
1035 * guess we can tweak it and see how it goes ;-)
1036 */
1037 dma_size = (pdev->is_pcie) ? AR5K_DMASIZE_128B : AR5K_DMASIZE_512B;
1038 if (ah->ah_version != AR5K_AR5210) {
1039 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1040 AR5K_TXCFG_SDMAMR, dma_size);
1041 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
1042 AR5K_RXCFG_SDMAMW, dma_size);
1043 }
1044
1045 /*
1046 * Enable the PHY and wait until completion
1047 */
1048 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1049
1050 /*
1051 * 5111/5112 Specific
1052 */
1053 if (ah->ah_version != AR5K_AR5210) {
1054 data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
1055 AR5K_PHY_RX_DELAY_M;
1056 data = (channel->hw_value & CHANNEL_CCK) ?
1057 ((data << 2) / 22) : (data / 10);
1058
1059 udelay(100 + data);
1060 } else {
1061 mdelay(1);
1062 }
1063
1064 /*
1065 * Enable calibration and wait until completion
1066 */
1067 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1068 AR5K_PHY_AGCCTL_CAL);
1069
1070 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1071 AR5K_PHY_AGCCTL_CAL, 0, false)) {
1072 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1073 channel->center_freq);
1074 return -EAGAIN;
1075 }
1076
1077 ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
1078 if (ret)
1079 return ret;
1080
1081 ah->ah_calibration = false;
1082
1083 /* A and G modes can use QAM modulation which requires enabling
1084 * I and Q calibration. Don't bother in B mode. */
1085 if (!(mode == AR5K_MODE_11B)) {
1086 ah->ah_calibration = true;
1087 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1088 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1089 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1090 AR5K_PHY_IQ_RUN);
1091 }
1092
1093 /*
1094 * Reset queues and start beacon timers at the end of the reset routine
1095 */
1096 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
1097 /*No QCU on 5210*/
1098 if (ah->ah_version != AR5K_AR5210)
1099 AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(i), i);
1100
1101 ret = ath5k_hw_reset_tx_queue(ah, i);
1102 if (ret) {
1103 ATH5K_ERR(ah->ah_sc,
1104 "failed to reset TX queue #%d\n", i);
1105 return ret;
1106 }
1107 }
1108
1109 /* Pre-enable interrupts on 5211/5212*/
1110 if (ah->ah_version != AR5K_AR5210)
1111 ath5k_hw_set_intr(ah, AR5K_INT_RX | AR5K_INT_TX |
1112 AR5K_INT_FATAL);
1113
1114 /*
1115 * Set RF kill flags if supported by the device (read from the EEPROM)
1116 * Disable gpio_intr for now since it results system hang.
1117 * TODO: Handle this in ath5k_intr
1118 */
1119 #if 0
1120 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) {
1121 ath5k_hw_set_gpio_input(ah, 0);
1122 ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0);
1123 if (ah->ah_gpio[0] == 0)
1124 ath5k_hw_set_gpio_intr(ah, 0, 1);
1125 else
1126 ath5k_hw_set_gpio_intr(ah, 0, 0);
1127 }
1128 #endif
1129
1130 /*
1131 * Set the 32MHz reference clock on 5212 phy clock sleep register
1132 *
1133 * TODO: Find out how to switch to external 32Khz clock to save power
1134 */
1135 if (ah->ah_version == AR5K_AR5212) {
1136 ath5k_hw_reg_write(ah, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR);
1137 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
1138 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL);
1139 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
1140 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
1141 ath5k_hw_reg_write(ah, ah->ah_phy_spending, AR5K_PHY_SPENDING);
1142 }
1143
1144 if (ah->ah_version == AR5K_AR5212) {
1145 ath5k_hw_reg_write(ah, 0x000100aa, 0x8118);
1146 ath5k_hw_reg_write(ah, 0x00003210, 0x811c);
1147 ath5k_hw_reg_write(ah, 0x00000052, 0x8108);
1148 if (ah->ah_mac_srev >= AR5K_SREV_VER_AR2413)
1149 ath5k_hw_reg_write(ah, 0x00000004, 0x8120);
1150 }
1151
1152 /*
1153 * Disable beacons and reset the register
1154 */
1155 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE |
1156 AR5K_BEACON_RESET_TSF);
1157
1158 return 0;
1159 }
1160
1161 /*
1162 * Reset chipset
1163 */
1164 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
1165 {
1166 int ret;
1167 u32 mask = val ? val : ~0U;
1168
1169 ATH5K_TRACE(ah->ah_sc);
1170
1171 /* Read-and-clear RX Descriptor Pointer*/
1172 ath5k_hw_reg_read(ah, AR5K_RXDP);
1173
1174 /*
1175 * Reset the device and wait until success
1176 */
1177 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
1178
1179 /* Wait at least 128 PCI clocks */
1180 udelay(15);
1181
1182 if (ah->ah_version == AR5K_AR5210) {
1183 val &= AR5K_RESET_CTL_CHIP;
1184 mask &= AR5K_RESET_CTL_CHIP;
1185 } else {
1186 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1187 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1188 }
1189
1190 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
1191
1192 /*
1193 * Reset configuration register (for hw byte-swap). Note that this
1194 * is only set for big endian. We do the necessary magic in
1195 * AR5K_INIT_CFG.
1196 */
1197 if ((val & AR5K_RESET_CTL_PCU) == 0)
1198 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
1199
1200 return ret;
1201 }
1202
1203 /*
1204 * Power management functions
1205 */
1206
1207 /*
1208 * Sleep control
1209 */
1210 int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
1211 bool set_chip, u16 sleep_duration)
1212 {
1213 unsigned int i;
1214 u32 staid;
1215
1216 ATH5K_TRACE(ah->ah_sc);
1217 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
1218
1219 switch (mode) {
1220 case AR5K_PM_AUTO:
1221 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
1222 /* fallthrough */
1223 case AR5K_PM_NETWORK_SLEEP:
1224 if (set_chip)
1225 ath5k_hw_reg_write(ah,
1226 AR5K_SLEEP_CTL_SLE | sleep_duration,
1227 AR5K_SLEEP_CTL);
1228
1229 staid |= AR5K_STA_ID1_PWR_SV;
1230 break;
1231
1232 case AR5K_PM_FULL_SLEEP:
1233 if (set_chip)
1234 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
1235 AR5K_SLEEP_CTL);
1236
1237 staid |= AR5K_STA_ID1_PWR_SV;
1238 break;
1239
1240 case AR5K_PM_AWAKE:
1241 if (!set_chip)
1242 goto commit;
1243
1244 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
1245 AR5K_SLEEP_CTL);
1246
1247 for (i = 5000; i > 0; i--) {
1248 /* Check if the chip did wake up */
1249 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1250 AR5K_PCICFG_SPWR_DN) == 0)
1251 break;
1252
1253 /* Wait a bit and retry */
1254 udelay(200);
1255 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
1256 AR5K_SLEEP_CTL);
1257 }
1258
1259 /* Fail if the chip didn't wake up */
1260 if (i <= 0)
1261 return -EIO;
1262
1263 staid &= ~AR5K_STA_ID1_PWR_SV;
1264 break;
1265
1266 default:
1267 return -EINVAL;
1268 }
1269
1270 commit:
1271 ah->ah_power_mode = mode;
1272 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
1273
1274 return 0;
1275 }
1276
1277 /***********************\
1278 DMA Related Functions
1279 \***********************/
1280
1281 /*
1282 * Receive functions
1283 */
1284
1285 /*
1286 * Start DMA receive
1287 */
1288 void ath5k_hw_start_rx(struct ath5k_hw *ah)
1289 {
1290 ATH5K_TRACE(ah->ah_sc);
1291 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
1292 }
1293
1294 /*
1295 * Stop DMA receive
1296 */
1297 int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
1298 {
1299 unsigned int i;
1300
1301 ATH5K_TRACE(ah->ah_sc);
1302 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
1303
1304 /*
1305 * It may take some time to disable the DMA receive unit
1306 */
1307 for (i = 2000; i > 0 &&
1308 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
1309 i--)
1310 udelay(10);
1311
1312 return i ? 0 : -EBUSY;
1313 }
1314
1315 /*
1316 * Get the address of the RX Descriptor
1317 */
1318 u32 ath5k_hw_get_rx_buf(struct ath5k_hw *ah)
1319 {
1320 return ath5k_hw_reg_read(ah, AR5K_RXDP);
1321 }
1322
1323 /*
1324 * Set the address of the RX Descriptor
1325 */
1326 void ath5k_hw_put_rx_buf(struct ath5k_hw *ah, u32 phys_addr)
1327 {
1328 ATH5K_TRACE(ah->ah_sc);
1329
1330 /*TODO:Shouldn't we check if RX is enabled first ?*/
1331 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
1332 }
1333
1334 /*
1335 * Transmit functions
1336 */
1337
1338 /*
1339 * Start DMA transmit for a specific queue
1340 * (see also QCU/DCU functions)
1341 */
1342 int ath5k_hw_tx_start(struct ath5k_hw *ah, unsigned int queue)
1343 {
1344 u32 tx_queue;
1345
1346 ATH5K_TRACE(ah->ah_sc);
1347 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1348
1349 /* Return if queue is declared inactive */
1350 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1351 return -EIO;
1352
1353 if (ah->ah_version == AR5K_AR5210) {
1354 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1355
1356 /*
1357 * Set the queue by type on 5210
1358 */
1359 switch (ah->ah_txq[queue].tqi_type) {
1360 case AR5K_TX_QUEUE_DATA:
1361 tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
1362 break;
1363 case AR5K_TX_QUEUE_BEACON:
1364 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1365 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
1366 AR5K_BSR);
1367 break;
1368 case AR5K_TX_QUEUE_CAB:
1369 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1370 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |
1371 AR5K_BCR_BDMAE, AR5K_BSR);
1372 break;
1373 default:
1374 return -EINVAL;
1375 }
1376 /* Start queue */
1377 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1378 } else {
1379 /* Return if queue is disabled */
1380 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
1381 return -EIO;
1382
1383 /* Start queue */
1384 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
1385 }
1386
1387 return 0;
1388 }
1389
1390 /*
1391 * Stop DMA transmit for a specific queue
1392 * (see also QCU/DCU functions)
1393 */
1394 int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
1395 {
1396 unsigned int i = 100;
1397 u32 tx_queue, pending;
1398
1399 ATH5K_TRACE(ah->ah_sc);
1400 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1401
1402 /* Return if queue is declared inactive */
1403 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1404 return -EIO;
1405
1406 if (ah->ah_version == AR5K_AR5210) {
1407 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1408
1409 /*
1410 * Set by queue type
1411 */
1412 switch (ah->ah_txq[queue].tqi_type) {
1413 case AR5K_TX_QUEUE_DATA:
1414 tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
1415 break;
1416 case AR5K_TX_QUEUE_BEACON:
1417 case AR5K_TX_QUEUE_CAB:
1418 /* XXX Fix me... */
1419 tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
1420 ath5k_hw_reg_write(ah, 0, AR5K_BSR);
1421 break;
1422 default:
1423 return -EINVAL;
1424 }
1425
1426 /* Stop queue */
1427 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1428 ath5k_hw_reg_read(ah, AR5K_CR);
1429 } else {
1430 /*
1431 * Schedule TX disable and wait until queue is empty
1432 */
1433 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
1434
1435 /*Check for pending frames*/
1436 do {
1437 pending = ath5k_hw_reg_read(ah,
1438 AR5K_QUEUE_STATUS(queue)) &
1439 AR5K_QCU_STS_FRMPENDCNT;
1440 udelay(100);
1441 } while (--i && pending);
1442
1443 /* Clear register */
1444 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
1445 if (pending)
1446 return -EBUSY;
1447 }
1448
1449 /* TODO: Check for success else return error */
1450 return 0;
1451 }
1452
1453 /*
1454 * Get the address of the TX Descriptor for a specific queue
1455 * (see also QCU/DCU functions)
1456 */
1457 u32 ath5k_hw_get_tx_buf(struct ath5k_hw *ah, unsigned int queue)
1458 {
1459 u16 tx_reg;
1460
1461 ATH5K_TRACE(ah->ah_sc);
1462 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1463
1464 /*
1465 * Get the transmit queue descriptor pointer from the selected queue
1466 */
1467 /*5210 doesn't have QCU*/
1468 if (ah->ah_version == AR5K_AR5210) {
1469 switch (ah->ah_txq[queue].tqi_type) {
1470 case AR5K_TX_QUEUE_DATA:
1471 tx_reg = AR5K_NOQCU_TXDP0;
1472 break;
1473 case AR5K_TX_QUEUE_BEACON:
1474 case AR5K_TX_QUEUE_CAB:
1475 tx_reg = AR5K_NOQCU_TXDP1;
1476 break;
1477 default:
1478 return 0xffffffff;
1479 }
1480 } else {
1481 tx_reg = AR5K_QUEUE_TXDP(queue);
1482 }
1483
1484 return ath5k_hw_reg_read(ah, tx_reg);
1485 }
1486
1487 /*
1488 * Set the address of the TX Descriptor for a specific queue
1489 * (see also QCU/DCU functions)
1490 */
1491 int ath5k_hw_put_tx_buf(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
1492 {
1493 u16 tx_reg;
1494
1495 ATH5K_TRACE(ah->ah_sc);
1496 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1497
1498 /*
1499 * Set the transmit queue descriptor pointer register by type
1500 * on 5210
1501 */
1502 if (ah->ah_version == AR5K_AR5210) {
1503 switch (ah->ah_txq[queue].tqi_type) {
1504 case AR5K_TX_QUEUE_DATA:
1505 tx_reg = AR5K_NOQCU_TXDP0;
1506 break;
1507 case AR5K_TX_QUEUE_BEACON:
1508 case AR5K_TX_QUEUE_CAB:
1509 tx_reg = AR5K_NOQCU_TXDP1;
1510 break;
1511 default:
1512 return -EINVAL;
1513 }
1514 } else {
1515 /*
1516 * Set the transmit queue descriptor pointer for
1517 * the selected queue on QCU for 5211+
1518 * (this won't work if the queue is still active)
1519 */
1520 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
1521 return -EIO;
1522
1523 tx_reg = AR5K_QUEUE_TXDP(queue);
1524 }
1525
1526 /* Set descriptor pointer */
1527 ath5k_hw_reg_write(ah, phys_addr, tx_reg);
1528
1529 return 0;
1530 }
1531
1532 /*
1533 * Update tx trigger level
1534 */
1535 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
1536 {
1537 u32 trigger_level, imr;
1538 int ret = -EIO;
1539
1540 ATH5K_TRACE(ah->ah_sc);
1541
1542 /*
1543 * Disable interrupts by setting the mask
1544 */
1545 imr = ath5k_hw_set_intr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);
1546
1547 /*TODO: Boundary check on trigger_level*/
1548 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
1549 AR5K_TXCFG_TXFULL);
1550
1551 if (!increase) {
1552 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
1553 goto done;
1554 } else
1555 trigger_level +=
1556 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
1557
1558 /*
1559 * Update trigger level on success
1560 */
1561 if (ah->ah_version == AR5K_AR5210)
1562 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
1563 else
1564 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1565 AR5K_TXCFG_TXFULL, trigger_level);
1566
1567 ret = 0;
1568
1569 done:
1570 /*
1571 * Restore interrupt mask
1572 */
1573 ath5k_hw_set_intr(ah, imr);
1574
1575 return ret;
1576 }
1577
1578 /*
1579 * Interrupt handling
1580 */
1581
1582 /*
1583 * Check if we have pending interrupts
1584 */
1585 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
1586 {
1587 ATH5K_TRACE(ah->ah_sc);
1588 return ath5k_hw_reg_read(ah, AR5K_INTPEND);
1589 }
1590
1591 /*
1592 * Get interrupt mask (ISR)
1593 */
1594 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
1595 {
1596 u32 data;
1597
1598 ATH5K_TRACE(ah->ah_sc);
1599
1600 /*
1601 * Read interrupt status from the Interrupt Status register
1602 * on 5210
1603 */
1604 if (ah->ah_version == AR5K_AR5210) {
1605 data = ath5k_hw_reg_read(ah, AR5K_ISR);
1606 if (unlikely(data == AR5K_INT_NOCARD)) {
1607 *interrupt_mask = data;
1608 return -ENODEV;
1609 }
1610 } else {
1611 /*
1612 * Read interrupt status from the Read-And-Clear shadow register
1613 * Note: PISR/SISR Not available on 5210
1614 */
1615 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR);
1616 }
1617
1618 /*
1619 * Get abstract interrupt mask (driver-compatible)
1620 */
1621 *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;
1622
1623 if (unlikely(data == AR5K_INT_NOCARD))
1624 return -ENODEV;
1625
1626 if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR))
1627 *interrupt_mask |= AR5K_INT_RX;
1628
1629 if (data & (AR5K_ISR_TXOK | AR5K_ISR_TXERR
1630 | AR5K_ISR_TXDESC | AR5K_ISR_TXEOL))
1631 *interrupt_mask |= AR5K_INT_TX;
1632
1633 if (ah->ah_version != AR5K_AR5210) {
1634 /*HIU = Host Interface Unit (PCI etc)*/
1635 if (unlikely(data & (AR5K_ISR_HIUERR)))
1636 *interrupt_mask |= AR5K_INT_FATAL;
1637
1638 /*Beacon Not Ready*/
1639 if (unlikely(data & (AR5K_ISR_BNR)))
1640 *interrupt_mask |= AR5K_INT_BNR;
1641 }
1642
1643 /*
1644 * XXX: BMISS interrupts may occur after association.
1645 * I found this on 5210 code but it needs testing. If this is
1646 * true we should disable them before assoc and re-enable them
1647 * after a successfull assoc + some jiffies.
1648 */
1649 #if 0
1650 interrupt_mask &= ~AR5K_INT_BMISS;
1651 #endif
1652
1653 /*
1654 * In case we didn't handle anything,
1655 * print the register value.
1656 */
1657 if (unlikely(*interrupt_mask == 0 && net_ratelimit()))
1658 ATH5K_PRINTF("0x%08x\n", data);
1659
1660 return 0;
1661 }
1662
1663 /*
1664 * Set interrupt mask
1665 */
1666 enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask)
1667 {
1668 enum ath5k_int old_mask, int_mask;
1669
1670 /*
1671 * Disable card interrupts to prevent any race conditions
1672 * (they will be re-enabled afterwards).
1673 */
1674 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);
1675
1676 old_mask = ah->ah_imr;
1677
1678 /*
1679 * Add additional, chipset-dependent interrupt mask flags
1680 * and write them to the IMR (interrupt mask register).
1681 */
1682 int_mask = new_mask & AR5K_INT_COMMON;
1683
1684 if (new_mask & AR5K_INT_RX)
1685 int_mask |= AR5K_IMR_RXOK | AR5K_IMR_RXERR | AR5K_IMR_RXORN |
1686 AR5K_IMR_RXDESC;
1687
1688 if (new_mask & AR5K_INT_TX)
1689 int_mask |= AR5K_IMR_TXOK | AR5K_IMR_TXERR | AR5K_IMR_TXDESC |
1690 AR5K_IMR_TXURN;
1691
1692 if (ah->ah_version != AR5K_AR5210) {
1693 if (new_mask & AR5K_INT_FATAL) {
1694 int_mask |= AR5K_IMR_HIUERR;
1695 AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_MCABT |
1696 AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR);
1697 }
1698 }
1699
1700 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
1701
1702 /* Store new interrupt mask */
1703 ah->ah_imr = new_mask;
1704
1705 /* ..re-enable interrupts */
1706 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER);
1707 ath5k_hw_reg_read(ah, AR5K_IER);
1708
1709 return old_mask;
1710 }
1711
1712
1713 /*************************\
1714 EEPROM access functions
1715 \*************************/
1716
1717 /*
1718 * Read from eeprom
1719 */
1720 static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
1721 {
1722 u32 status, timeout;
1723
1724 ATH5K_TRACE(ah->ah_sc);
1725 /*
1726 * Initialize EEPROM access
1727 */
1728 if (ah->ah_version == AR5K_AR5210) {
1729 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1730 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
1731 } else {
1732 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1733 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1734 AR5K_EEPROM_CMD_READ);
1735 }
1736
1737 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1738 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1739 if (status & AR5K_EEPROM_STAT_RDDONE) {
1740 if (status & AR5K_EEPROM_STAT_RDERR)
1741 return -EIO;
1742 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
1743 0xffff);
1744 return 0;
1745 }
1746 udelay(15);
1747 }
1748
1749 return -ETIMEDOUT;
1750 }
1751
1752 /*
1753 * Write to eeprom - currently disabled, use at your own risk
1754 */
1755 #if 0
1756 static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data)
1757 {
1758
1759 u32 status, timeout;
1760
1761 ATH5K_TRACE(ah->ah_sc);
1762
1763 /*
1764 * Initialize eeprom access
1765 */
1766
1767 if (ah->ah_version == AR5K_AR5210) {
1768 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1769 } else {
1770 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1771 AR5K_EEPROM_CMD_RESET);
1772 }
1773
1774 /*
1775 * Write data to data register
1776 */
1777
1778 if (ah->ah_version == AR5K_AR5210) {
1779 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_BASE + (4 * offset));
1780 } else {
1781 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1782 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_DATA);
1783 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1784 AR5K_EEPROM_CMD_WRITE);
1785 }
1786
1787 /*
1788 * Check status
1789 */
1790
1791 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1792 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1793 if (status & AR5K_EEPROM_STAT_WRDONE) {
1794 if (status & AR5K_EEPROM_STAT_WRERR)
1795 return EIO;
1796 return 0;
1797 }
1798 udelay(15);
1799 }
1800
1801 ATH5K_ERR(ah->ah_sc, "EEPROM Write is disabled!");
1802 return -EIO;
1803 }
1804 #endif
1805
1806 /*
1807 * Translate binary channel representation in EEPROM to frequency
1808 */
1809 static u16 ath5k_eeprom_bin2freq(struct ath5k_hw *ah, u16 bin, unsigned int mode)
1810 {
1811 u16 val;
1812
1813 if (bin == AR5K_EEPROM_CHANNEL_DIS)
1814 return bin;
1815
1816 if (mode == AR5K_EEPROM_MODE_11A) {
1817 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1818 val = (5 * bin) + 4800;
1819 else
1820 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
1821 (bin * 10) + 5100;
1822 } else {
1823 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1824 val = bin + 2300;
1825 else
1826 val = bin + 2400;
1827 }
1828
1829 return val;
1830 }
1831
1832 /*
1833 * Read antenna infos from eeprom
1834 */
1835 static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
1836 unsigned int mode)
1837 {
1838 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1839 u32 o = *offset;
1840 u16 val;
1841 int ret, i = 0;
1842
1843 AR5K_EEPROM_READ(o++, val);
1844 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
1845 ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f;
1846 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1847
1848 AR5K_EEPROM_READ(o++, val);
1849 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1850 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1851 ee->ee_ant_control[mode][i++] = val & 0x3f;
1852
1853 AR5K_EEPROM_READ(o++, val);
1854 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
1855 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
1856 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
1857
1858 AR5K_EEPROM_READ(o++, val);
1859 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
1860 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
1861 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
1862 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1863
1864 AR5K_EEPROM_READ(o++, val);
1865 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1866 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1867 ee->ee_ant_control[mode][i++] = val & 0x3f;
1868
1869 /* Get antenna modes */
1870 ah->ah_antenna[mode][0] =
1871 (ee->ee_ant_control[mode][0] << 4) | 0x1;
1872 ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
1873 ee->ee_ant_control[mode][1] |
1874 (ee->ee_ant_control[mode][2] << 6) |
1875 (ee->ee_ant_control[mode][3] << 12) |
1876 (ee->ee_ant_control[mode][4] << 18) |
1877 (ee->ee_ant_control[mode][5] << 24);
1878 ah->ah_antenna[mode][AR5K_ANT_FIXED_B] =
1879 ee->ee_ant_control[mode][6] |
1880 (ee->ee_ant_control[mode][7] << 6) |
1881 (ee->ee_ant_control[mode][8] << 12) |
1882 (ee->ee_ant_control[mode][9] << 18) |
1883 (ee->ee_ant_control[mode][10] << 24);
1884
1885 /* return new offset */
1886 *offset = o;
1887
1888 return 0;
1889 }
1890
1891 /*
1892 * Read supported modes from eeprom
1893 */
1894 static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
1895 unsigned int mode)
1896 {
1897 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1898 u32 o = *offset;
1899 u16 val;
1900 int ret;
1901
1902 AR5K_EEPROM_READ(o++, val);
1903 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
1904 ee->ee_thr_62[mode] = val & 0xff;
1905
1906 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1907 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
1908
1909 AR5K_EEPROM_READ(o++, val);
1910 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
1911 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
1912
1913 AR5K_EEPROM_READ(o++, val);
1914 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
1915
1916 if ((val & 0xff) & 0x80)
1917 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
1918 else
1919 ee->ee_noise_floor_thr[mode] = val & 0xff;
1920
1921 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1922 ee->ee_noise_floor_thr[mode] =
1923 mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
1924
1925 AR5K_EEPROM_READ(o++, val);
1926 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
1927 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
1928 ee->ee_xpd[mode] = val & 0x1;
1929
1930 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
1931 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
1932
1933 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
1934 AR5K_EEPROM_READ(o++, val);
1935 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
1936
1937 if (mode == AR5K_EEPROM_MODE_11A)
1938 ee->ee_xr_power[mode] = val & 0x3f;
1939 else {
1940 ee->ee_ob[mode][0] = val & 0x7;
1941 ee->ee_db[mode][0] = (val >> 3) & 0x7;
1942 }
1943 }
1944
1945 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
1946 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
1947 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
1948 } else {
1949 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
1950
1951 AR5K_EEPROM_READ(o++, val);
1952 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
1953
1954 if (mode == AR5K_EEPROM_MODE_11G)
1955 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
1956 }
1957
1958 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
1959 mode == AR5K_EEPROM_MODE_11A) {
1960 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
1961 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
1962 }
1963
1964 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 &&
1965 mode == AR5K_EEPROM_MODE_11G)
1966 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
1967
1968 /* return new offset */
1969 *offset = o;
1970
1971 return 0;
1972 }
1973
1974 /*
1975 * Initialize eeprom & capabilities structs
1976 */
1977 static int ath5k_eeprom_init(struct ath5k_hw *ah)
1978 {
1979 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1980 unsigned int mode, i;
1981 int ret;
1982 u32 offset;
1983 u16 val;
1984
1985 /* Initial TX thermal adjustment values */
1986 ee->ee_tx_clip = 4;
1987 ee->ee_pwd_84 = ee->ee_pwd_90 = 1;
1988 ee->ee_gain_select = 1;
1989
1990 /*
1991 * Read values from EEPROM and store them in the capability structure
1992 */
1993 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
1994 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
1995 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
1996 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
1997 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
1998
1999 /* Return if we have an old EEPROM */
2000 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
2001 return 0;
2002
2003 #ifdef notyet
2004 /*
2005 * Validate the checksum of the EEPROM date. There are some
2006 * devices with invalid EEPROMs.
2007 */
2008 for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
2009 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
2010 cksum ^= val;
2011 }
2012 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
2013 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM checksum 0x%04x\n", cksum);
2014 return -EIO;
2015 }
2016 #endif
2017
2018 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
2019 ee_ant_gain);
2020
2021 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
2022 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
2023 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
2024 }
2025
2026 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
2027 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
2028 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
2029 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
2030
2031 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
2032 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
2033 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
2034 }
2035
2036 /*
2037 * Get conformance test limit values
2038 */
2039 offset = AR5K_EEPROM_CTL(ah->ah_ee_version);
2040 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ah->ah_ee_version);
2041
2042 for (i = 0; i < ee->ee_ctls; i++) {
2043 AR5K_EEPROM_READ(offset++, val);
2044 ee->ee_ctl[i] = (val >> 8) & 0xff;
2045 ee->ee_ctl[i + 1] = val & 0xff;
2046 }
2047
2048 /*
2049 * Get values for 802.11a (5GHz)
2050 */
2051 mode = AR5K_EEPROM_MODE_11A;
2052
2053 ee->ee_turbo_max_power[mode] =
2054 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
2055
2056 offset = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
2057
2058 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
2059 if (ret)
2060 return ret;
2061
2062 AR5K_EEPROM_READ(offset++, val);
2063 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
2064 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
2065 ee->ee_db[mode][3] = (val >> 2) & 0x7;
2066 ee->ee_ob[mode][2] = (val << 1) & 0x7;
2067
2068 AR5K_EEPROM_READ(offset++, val);
2069 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
2070 ee->ee_db[mode][2] = (val >> 12) & 0x7;
2071 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
2072 ee->ee_db[mode][1] = (val >> 6) & 0x7;
2073 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
2074 ee->ee_db[mode][0] = val & 0x7;
2075
2076 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
2077 if (ret)
2078 return ret;
2079
2080 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
2081 AR5K_EEPROM_READ(offset++, val);
2082 ee->ee_margin_tx_rx[mode] = val & 0x3f;
2083 }
2084
2085 /*
2086 * Get values for 802.11b (2.4GHz)
2087 */
2088 mode = AR5K_EEPROM_MODE_11B;
2089 offset = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
2090
2091 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
2092 if (ret)
2093 return ret;
2094
2095 AR5K_EEPROM_READ(offset++, val);
2096 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
2097 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
2098 ee->ee_db[mode][1] = val & 0x7;
2099
2100 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
2101 if (ret)
2102 return ret;
2103
2104 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
2105 AR5K_EEPROM_READ(offset++, val);
2106 ee->ee_cal_pier[mode][0] =
2107 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2108 ee->ee_cal_pier[mode][1] =
2109 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
2110
2111 AR5K_EEPROM_READ(offset++, val);
2112 ee->ee_cal_pier[mode][2] =
2113 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2114 }
2115
2116 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
2117 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
2118
2119 /*
2120 * Get values for 802.11g (2.4GHz)
2121 */
2122 mode = AR5K_EEPROM_MODE_11G;
2123 offset = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
2124
2125 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
2126 if (ret)
2127 return ret;
2128
2129 AR5K_EEPROM_READ(offset++, val);
2130 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
2131 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
2132 ee->ee_db[mode][1] = val & 0x7;
2133
2134 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
2135 if (ret)
2136 return ret;
2137
2138 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
2139 AR5K_EEPROM_READ(offset++, val);
2140 ee->ee_cal_pier[mode][0] =
2141 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2142 ee->ee_cal_pier[mode][1] =
2143 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
2144
2145 AR5K_EEPROM_READ(offset++, val);
2146 ee->ee_turbo_max_power[mode] = val & 0x7f;
2147 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
2148
2149 AR5K_EEPROM_READ(offset++, val);
2150 ee->ee_cal_pier[mode][2] =
2151 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2152
2153 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
2154 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
2155
2156 AR5K_EEPROM_READ(offset++, val);
2157 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
2158 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
2159
2160 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
2161 AR5K_EEPROM_READ(offset++, val);
2162 ee->ee_cck_ofdm_gain_delta = val & 0xff;
2163 }
2164 }
2165
2166 /*
2167 * Read 5GHz EEPROM channels
2168 */
2169
2170 return 0;
2171 }
2172
2173 /*
2174 * Read the MAC address from eeprom
2175 */
2176 static int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
2177 {
2178 u8 mac_d[ETH_ALEN];
2179 u32 total, offset;
2180 u16 data;
2181 int octet, ret;
2182
2183 memset(mac, 0, ETH_ALEN);
2184 memset(mac_d, 0, ETH_ALEN);
2185
2186 ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
2187 if (ret)
2188 return ret;
2189
2190 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
2191 ret = ath5k_hw_eeprom_read(ah, offset, &data);
2192 if (ret)
2193 return ret;
2194
2195 total += data;
2196 mac_d[octet + 1] = data & 0xff;
2197 mac_d[octet] = data >> 8;
2198 octet += 2;
2199 }
2200
2201 memcpy(mac, mac_d, ETH_ALEN);
2202
2203 if (!total || total == 3 * 0xffff)
2204 return -EINVAL;
2205
2206 return 0;
2207 }
2208
2209 /*
2210 * Fill the capabilities struct
2211 */
2212 static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
2213 {
2214 u16 ee_header;
2215
2216 ATH5K_TRACE(ah->ah_sc);
2217 /* Capabilities stored in the EEPROM */
2218 ee_header = ah->ah_capabilities.cap_eeprom.ee_header;
2219
2220 if (ah->ah_version == AR5K_AR5210) {
2221 /*
2222 * Set radio capabilities
2223 * (The AR5110 only supports the middle 5GHz band)
2224 */
2225 ah->ah_capabilities.cap_range.range_5ghz_min = 5120;
2226 ah->ah_capabilities.cap_range.range_5ghz_max = 5430;
2227 ah->ah_capabilities.cap_range.range_2ghz_min = 0;
2228 ah->ah_capabilities.cap_range.range_2ghz_max = 0;
2229
2230 /* Set supported modes */
2231 __set_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode);
2232 __set_bit(AR5K_MODE_11A_TURBO, ah->ah_capabilities.cap_mode);
2233 } else {
2234 /*
2235 * XXX The tranceiver supports frequencies from 4920 to 6100GHz
2236 * XXX and from 2312 to 2732GHz. There are problems with the
2237 * XXX current ieee80211 implementation because the IEEE
2238 * XXX channel mapping does not support negative channel
2239 * XXX numbers (2312MHz is channel -19). Of course, this
2240 * XXX doesn't matter because these channels are out of range
2241 * XXX but some regulation domains like MKK (Japan) will
2242 * XXX support frequencies somewhere around 4.8GHz.
2243 */
2244
2245 /*
2246 * Set radio capabilities
2247 */
2248
2249 if (AR5K_EEPROM_HDR_11A(ee_header)) {
2250 ah->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */
2251 ah->ah_capabilities.cap_range.range_5ghz_max = 6100;
2252
2253 /* Set supported modes */
2254 __set_bit(AR5K_MODE_11A,
2255 ah->ah_capabilities.cap_mode);
2256 __set_bit(AR5K_MODE_11A_TURBO,
2257 ah->ah_capabilities.cap_mode);
2258 if (ah->ah_version == AR5K_AR5212)
2259 __set_bit(AR5K_MODE_11G_TURBO,
2260 ah->ah_capabilities.cap_mode);
2261 }
2262
2263 /* Enable 802.11b if a 2GHz capable radio (2111/5112) is
2264 * connected */
2265 if (AR5K_EEPROM_HDR_11B(ee_header) ||
2266 AR5K_EEPROM_HDR_11G(ee_header)) {
2267 ah->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
2268 ah->ah_capabilities.cap_range.range_2ghz_max = 2732;
2269
2270 if (AR5K_EEPROM_HDR_11B(ee_header))
2271 __set_bit(AR5K_MODE_11B,
2272 ah->ah_capabilities.cap_mode);
2273
2274 if (AR5K_EEPROM_HDR_11G(ee_header))
2275 __set_bit(AR5K_MODE_11G,
2276 ah->ah_capabilities.cap_mode);
2277 }
2278 }
2279
2280 /* GPIO */
2281 ah->ah_gpio_npins = AR5K_NUM_GPIO;
2282
2283 /* Set number of supported TX queues */
2284 if (ah->ah_version == AR5K_AR5210)
2285 ah->ah_capabilities.cap_queues.q_tx_num =
2286 AR5K_NUM_TX_QUEUES_NOQCU;
2287 else
2288 ah->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
2289
2290 return 0;
2291 }
2292
2293 /*********************************\
2294 Protocol Control Unit Functions
2295 \*********************************/
2296
2297 /*
2298 * Set Operation mode
2299 */
2300 int ath5k_hw_set_opmode(struct ath5k_hw *ah)
2301 {
2302 u32 pcu_reg, beacon_reg, low_id, high_id;
2303
2304 pcu_reg = 0;
2305 beacon_reg = 0;
2306
2307 ATH5K_TRACE(ah->ah_sc);
2308
2309 switch (ah->ah_op_mode) {
2310 case IEEE80211_IF_TYPE_IBSS:
2311 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_DESC_ANTENNA |
2312 (ah->ah_version == AR5K_AR5210 ?
2313 AR5K_STA_ID1_NO_PSPOLL : 0);
2314 beacon_reg |= AR5K_BCR_ADHOC;
2315 break;
2316
2317 case IEEE80211_IF_TYPE_AP:
2318 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_RTS_DEF_ANTENNA |
2319 (ah->ah_version == AR5K_AR5210 ?
2320 AR5K_STA_ID1_NO_PSPOLL : 0);
2321 beacon_reg |= AR5K_BCR_AP;
2322 break;
2323
2324 case IEEE80211_IF_TYPE_STA:
2325 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2326 (ah->ah_version == AR5K_AR5210 ?
2327 AR5K_STA_ID1_PWR_SV : 0);
2328 case IEEE80211_IF_TYPE_MNTR:
2329 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2330 (ah->ah_version == AR5K_AR5210 ?
2331 AR5K_STA_ID1_NO_PSPOLL : 0);
2332 break;
2333
2334 default:
2335 return -EINVAL;
2336 }
2337
2338 /*
2339 * Set PCU registers
2340 */
2341 low_id = AR5K_LOW_ID(ah->ah_sta_id);
2342 high_id = AR5K_HIGH_ID(ah->ah_sta_id);
2343 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2344 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
2345
2346 /*
2347 * Set Beacon Control Register on 5210
2348 */
2349 if (ah->ah_version == AR5K_AR5210)
2350 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
2351
2352 return 0;
2353 }
2354
2355 /*
2356 * BSSID Functions
2357 */
2358
2359 /*
2360 * Get station id
2361 */
2362 void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac)
2363 {
2364 ATH5K_TRACE(ah->ah_sc);
2365 memcpy(mac, ah->ah_sta_id, ETH_ALEN);
2366 }
2367
2368 /*
2369 * Set station id
2370 */
2371 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
2372 {
2373 u32 low_id, high_id;
2374
2375 ATH5K_TRACE(ah->ah_sc);
2376 /* Set new station ID */
2377 memcpy(ah->ah_sta_id, mac, ETH_ALEN);
2378
2379 low_id = AR5K_LOW_ID(mac);
2380 high_id = AR5K_HIGH_ID(mac);
2381
2382 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2383 ath5k_hw_reg_write(ah, high_id, AR5K_STA_ID1);
2384
2385 return 0;
2386 }
2387
2388 /*
2389 * Set BSSID
2390 */
2391 void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
2392 {
2393 u32 low_id, high_id;
2394 u16 tim_offset = 0;
2395
2396 /*
2397 * Set simple BSSID mask on 5212
2398 */
2399 if (ah->ah_version == AR5K_AR5212) {
2400 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM0);
2401 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM1);
2402 }
2403
2404 /*
2405 * Set BSSID which triggers the "SME Join" operation
2406 */
2407 low_id = AR5K_LOW_ID(bssid);
2408 high_id = AR5K_HIGH_ID(bssid);
2409 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_ID0);
2410 ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) <<
2411 AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1);
2412
2413 if (assoc_id == 0) {
2414 ath5k_hw_disable_pspoll(ah);
2415 return;
2416 }
2417
2418 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
2419 tim_offset ? tim_offset + 4 : 0);
2420
2421 ath5k_hw_enable_pspoll(ah, NULL, 0);
2422 }
2423 /**
2424 * ath5k_hw_set_bssid_mask - set common bits we should listen to
2425 *
2426 * The bssid_mask is a utility used by AR5212 hardware to inform the hardware
2427 * which bits of the interface's MAC address should be looked at when trying
2428 * to decide which packets to ACK. In station mode every bit matters. In AP
2429 * mode with a single BSS every bit matters as well. In AP mode with
2430 * multiple BSSes not every bit matters.
2431 *
2432 * @ah: the &struct ath5k_hw
2433 * @mask: the bssid_mask, a u8 array of size ETH_ALEN
2434 *
2435 * Note that this is a simple filter and *does* not filter out all
2436 * relevant frames. Some non-relevant frames will get through, probability
2437 * jocks are welcomed to compute.
2438 *
2439 * When handling multiple BSSes (or VAPs) you can get the BSSID mask by
2440 * computing the set of:
2441 *
2442 * ~ ( MAC XOR BSSID )
2443 *
2444 * When you do this you are essentially computing the common bits. Later it
2445 * is assumed the harware will "and" (&) the BSSID mask with the MAC address
2446 * to obtain the relevant bits which should match on the destination frame.
2447 *
2448 * Simple example: on your card you have have two BSSes you have created with
2449 * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address.
2450 * There is another BSSID-03 but you are not part of it. For simplicity's sake,
2451 * assuming only 4 bits for a mac address and for BSSIDs you can then have:
2452 *
2453 * \
2454 * MAC: 0001 |
2455 * BSSID-01: 0100 | --> Belongs to us
2456 * BSSID-02: 1001 |
2457 * /
2458 * -------------------
2459 * BSSID-03: 0110 | --> External
2460 * -------------------
2461 *
2462 * Our bssid_mask would then be:
2463 *
2464 * On loop iteration for BSSID-01:
2465 * ~(0001 ^ 0100) -> ~(0101)
2466 * -> 1010
2467 * bssid_mask = 1010
2468 *
2469 * On loop iteration for BSSID-02:
2470 * bssid_mask &= ~(0001 ^ 1001)
2471 * bssid_mask = (1010) & ~(0001 ^ 1001)
2472 * bssid_mask = (1010) & ~(1001)
2473 * bssid_mask = (1010) & (0110)
2474 * bssid_mask = 0010
2475 *
2476 * A bssid_mask of 0010 means "only pay attention to the second least
2477 * significant bit". This is because its the only bit common
2478 * amongst the MAC and all BSSIDs we support. To findout what the real
2479 * common bit is we can simply "&" the bssid_mask now with any BSSID we have
2480 * or our MAC address (we assume the hardware uses the MAC address).
2481 *
2482 * Now, suppose there's an incoming frame for BSSID-03:
2483 *
2484 * IFRAME-01: 0110
2485 *
2486 * An easy eye-inspeciton of this already should tell you that this frame
2487 * will not pass our check. This is beacuse the bssid_mask tells the
2488 * hardware to only look at the second least significant bit and the
2489 * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB
2490 * as 1, which does not match 0.
2491 *
2492 * So with IFRAME-01 we *assume* the hardware will do:
2493 *
2494 * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2495 * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0;
2496 * --> allow = (0010) == 0000 ? 1 : 0;
2497 * --> allow = 0
2498 *
2499 * Lets now test a frame that should work:
2500 *
2501 * IFRAME-02: 0001 (we should allow)
2502 *
2503 * allow = (0001 & 1010) == 1010
2504 *
2505 * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2506 * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0;
2507 * --> allow = (0010) == (0010)
2508 * --> allow = 1
2509 *
2510 * Other examples:
2511 *
2512 * IFRAME-03: 0100 --> allowed
2513 * IFRAME-04: 1001 --> allowed
2514 * IFRAME-05: 1101 --> allowed but its not for us!!!
2515 *
2516 */
2517 int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
2518 {
2519 u32 low_id, high_id;
2520 ATH5K_TRACE(ah->ah_sc);
2521
2522 if (ah->ah_version == AR5K_AR5212) {
2523 low_id = AR5K_LOW_ID(mask);
2524 high_id = AR5K_HIGH_ID(mask);
2525
2526 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_IDM0);
2527 ath5k_hw_reg_write(ah, high_id, AR5K_BSS_IDM1);
2528
2529 return 0;
2530 }
2531
2532 return -EIO;
2533 }
2534
2535 /*
2536 * Receive start/stop functions
2537 */
2538
2539 /*
2540 * Start receive on PCU
2541 */
2542 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
2543 {
2544 ATH5K_TRACE(ah->ah_sc);
2545 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2546
2547 /* TODO: ANI Support */
2548 }
2549
2550 /*
2551 * Stop receive on PCU
2552 */
2553 void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah)
2554 {
2555 ATH5K_TRACE(ah->ah_sc);
2556 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2557
2558 /* TODO: ANI Support */
2559 }
2560
2561 /*
2562 * RX Filter functions
2563 */
2564
2565 /*
2566 * Set multicast filter
2567 */
2568 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
2569 {
2570 ATH5K_TRACE(ah->ah_sc);
2571 /* Set the multicat filter */
2572 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
2573 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
2574 }
2575
2576 /*
2577 * Set multicast filter by index
2578 */
2579 int ath5k_hw_set_mcast_filterindex(struct ath5k_hw *ah, u32 index)
2580 {
2581
2582 ATH5K_TRACE(ah->ah_sc);
2583 if (index >= 64)
2584 return -EINVAL;
2585 else if (index >= 32)
2586 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER1,
2587 (1 << (index - 32)));
2588 else
2589 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2590
2591 return 0;
2592 }
2593
2594 /*
2595 * Clear Multicast filter by index
2596 */
2597 int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index)
2598 {
2599
2600 ATH5K_TRACE(ah->ah_sc);
2601 if (index >= 64)
2602 return -EINVAL;
2603 else if (index >= 32)
2604 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER1,
2605 (1 << (index - 32)));
2606 else
2607 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2608
2609 return 0;
2610 }
2611
2612 /*
2613 * Get current rx filter
2614 */
2615 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
2616 {
2617 u32 data, filter = 0;
2618
2619 ATH5K_TRACE(ah->ah_sc);
2620 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
2621
2622 /*Radar detection for 5212*/
2623 if (ah->ah_version == AR5K_AR5212) {
2624 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
2625
2626 if (data & AR5K_PHY_ERR_FIL_RADAR)
2627 filter |= AR5K_RX_FILTER_RADARERR;
2628 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
2629 filter |= AR5K_RX_FILTER_PHYERR;
2630 }
2631
2632 return filter;
2633 }
2634
2635 /*
2636 * Set rx filter
2637 */
2638 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
2639 {
2640 u32 data = 0;
2641
2642 ATH5K_TRACE(ah->ah_sc);
2643
2644 /* Set PHY error filter register on 5212*/
2645 if (ah->ah_version == AR5K_AR5212) {
2646 if (filter & AR5K_RX_FILTER_RADARERR)
2647 data |= AR5K_PHY_ERR_FIL_RADAR;
2648 if (filter & AR5K_RX_FILTER_PHYERR)
2649 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
2650 }
2651
2652 /*
2653 * The AR5210 uses promiscous mode to detect radar activity
2654 */
2655 if (ah->ah_version == AR5K_AR5210 &&
2656 (filter & AR5K_RX_FILTER_RADARERR)) {
2657 filter &= ~AR5K_RX_FILTER_RADARERR;
2658 filter |= AR5K_RX_FILTER_PROM;
2659 }
2660
2661 /*Zero length DMA*/
2662 if (data)
2663 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2664 else
2665 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2666
2667 /*Write RX Filter register*/
2668 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
2669
2670 /*Write PHY error filter register on 5212*/
2671 if (ah->ah_version == AR5K_AR5212)
2672 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
2673
2674 }
2675
2676 /*
2677 * Beacon related functions
2678 */
2679
2680 /*
2681 * Get a 32bit TSF
2682 */
2683 u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah)
2684 {
2685 ATH5K_TRACE(ah->ah_sc);
2686 return ath5k_hw_reg_read(ah, AR5K_TSF_L32);
2687 }
2688
2689 /*
2690 * Get the full 64bit TSF
2691 */
2692 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
2693 {
2694 u64 tsf = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
2695 ATH5K_TRACE(ah->ah_sc);
2696
2697 return ath5k_hw_reg_read(ah, AR5K_TSF_L32) | (tsf << 32);
2698 }
2699
2700 /*
2701 * Force a TSF reset
2702 */
2703 void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
2704 {
2705 ATH5K_TRACE(ah->ah_sc);
2706 AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_RESET_TSF);
2707 }
2708
2709 /*
2710 * Initialize beacon timers
2711 */
2712 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
2713 {
2714 u32 timer1, timer2, timer3;
2715
2716 ATH5K_TRACE(ah->ah_sc);
2717 /*
2718 * Set the additional timers by mode
2719 */
2720 switch (ah->ah_op_mode) {
2721 case IEEE80211_IF_TYPE_STA:
2722 if (ah->ah_version == AR5K_AR5210) {
2723 timer1 = 0xffffffff;
2724 timer2 = 0xffffffff;
2725 } else {
2726 timer1 = 0x0000ffff;
2727 timer2 = 0x0007ffff;
2728 }
2729 break;
2730
2731 default:
2732 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
2733 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
2734 }
2735
2736 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
2737
2738 /*
2739 * Set the beacon register and enable all timers.
2740 * (next beacon, DMA beacon, software beacon, ATIM window time)
2741 */
2742 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
2743 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
2744 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
2745 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
2746
2747 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
2748 AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE),
2749 AR5K_BEACON);
2750 }
2751
2752 #if 0
2753 /*
2754 * Set beacon timers
2755 */
2756 int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah,
2757 const struct ath5k_beacon_state *state)
2758 {
2759 u32 cfp_period, next_cfp, dtim, interval, next_beacon;
2760
2761 /*
2762 * TODO: should be changed through *state
2763 * review struct ath5k_beacon_state struct
2764 *
2765 * XXX: These are used for cfp period bellow, are they
2766 * ok ? Is it O.K. for tsf here to be 0 or should we use
2767 * get_tsf ?
2768 */
2769 u32 dtim_count = 0; /* XXX */
2770 u32 cfp_count = 0; /* XXX */
2771 u32 tsf = 0; /* XXX */
2772
2773 ATH5K_TRACE(ah->ah_sc);
2774 /* Return on an invalid beacon state */
2775 if (state->bs_interval < 1)
2776 return -EINVAL;
2777
2778 interval = state->bs_interval;
2779 dtim = state->bs_dtim_period;
2780
2781 /*
2782 * PCF support?
2783 */
2784 if (state->bs_cfp_period > 0) {
2785 /*
2786 * Enable PCF mode and set the CFP
2787 * (Contention Free Period) and timer registers
2788 */
2789 cfp_period = state->bs_cfp_period * state->bs_dtim_period *
2790 state->bs_interval;
2791 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
2792 state->bs_interval;
2793
2794 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
2795 AR5K_STA_ID1_DEFAULT_ANTENNA |
2796 AR5K_STA_ID1_PCF);
2797 ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD);
2798 ath5k_hw_reg_write(ah, state->bs_cfp_max_duration,
2799 AR5K_CFP_DUR);
2800 ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period :
2801 next_cfp)) << 3, AR5K_TIMER2);
2802 } else {
2803 /* Disable PCF mode */
2804 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2805 AR5K_STA_ID1_DEFAULT_ANTENNA |
2806 AR5K_STA_ID1_PCF);
2807 }
2808
2809 /*
2810 * Enable the beacon timer register
2811 */
2812 ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0);
2813
2814 /*
2815 * Start the beacon timers
2816 */
2817 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) &~
2818 (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) |
2819 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
2820 AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
2821 AR5K_BEACON_PERIOD), AR5K_BEACON);
2822
2823 /*
2824 * Write new beacon miss threshold, if it appears to be valid
2825 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max
2826 * and return if its not in range. We can test this by reading value and
2827 * setting value to a largest value and seeing which values register.
2828 */
2829
2830 AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS,
2831 state->bs_bmiss_threshold);
2832
2833 /*
2834 * Set sleep control register
2835 * XXX: Didn't find this in 5210 code but since this register
2836 * exists also in ar5k's 5210 headers i leave it as common code.
2837 */
2838 AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR,
2839 (state->bs_sleep_duration - 3) << 3);
2840
2841 /*
2842 * Set enhanced sleep registers on 5212
2843 */
2844 if (ah->ah_version == AR5K_AR5212) {
2845 if (state->bs_sleep_duration > state->bs_interval &&
2846 roundup(state->bs_sleep_duration, interval) ==
2847 state->bs_sleep_duration)
2848 interval = state->bs_sleep_duration;
2849
2850 if (state->bs_sleep_duration > dtim && (dtim == 0 ||
2851 roundup(state->bs_sleep_duration, dtim) ==
2852 state->bs_sleep_duration))
2853 dtim = state->bs_sleep_duration;
2854
2855 if (interval > dtim)
2856 return -EINVAL;
2857
2858 next_beacon = interval == dtim ? state->bs_next_dtim :
2859 state->bs_next_beacon;
2860
2861 ath5k_hw_reg_write(ah,
2862 AR5K_REG_SM((state->bs_next_dtim - 3) << 3,
2863 AR5K_SLEEP0_NEXT_DTIM) |
2864 AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) |
2865 AR5K_SLEEP0_ENH_SLEEP_EN |
2866 AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0);
2867
2868 ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3,
2869 AR5K_SLEEP1_NEXT_TIM) |
2870 AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1);
2871
2872 ath5k_hw_reg_write(ah,
2873 AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) |
2874 AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2);
2875 }
2876
2877 return 0;
2878 }
2879
2880 /*
2881 * Reset beacon timers
2882 */
2883 void ath5k_hw_reset_beacon(struct ath5k_hw *ah)
2884 {
2885 ATH5K_TRACE(ah->ah_sc);
2886 /*
2887 * Disable beacon timer
2888 */
2889 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
2890
2891 /*
2892 * Disable some beacon register values
2893 */
2894 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2895 AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF);
2896 ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON);
2897 }
2898
2899 /*
2900 * Wait for beacon queue to finish
2901 */
2902 int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
2903 {
2904 unsigned int i;
2905 int ret;
2906
2907 ATH5K_TRACE(ah->ah_sc);
2908
2909 /* 5210 doesn't have QCU*/
2910 if (ah->ah_version == AR5K_AR5210) {
2911 /*
2912 * Wait for beaconn queue to finish by checking
2913 * Control Register and Beacon Status Register.
2914 */
2915 for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) {
2916 if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F)
2917 ||
2918 !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F))
2919 break;
2920 udelay(10);
2921 }
2922
2923 /* Timeout... */
2924 if (i <= 0) {
2925 /*
2926 * Re-schedule the beacon queue
2927 */
2928 ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1);
2929 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
2930 AR5K_BCR);
2931
2932 return -EIO;
2933 }
2934 ret = 0;
2935 } else {
2936 /*5211/5212*/
2937 ret = ath5k_hw_register_timeout(ah,
2938 AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
2939 AR5K_QCU_STS_FRMPENDCNT, 0, false);
2940
2941 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
2942 return -EIO;
2943 }
2944
2945 return ret;
2946 }
2947 #endif
2948
2949 /*
2950 * Update mib counters (statistics)
2951 */
2952 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
2953 struct ieee80211_low_level_stats *stats)
2954 {
2955 ATH5K_TRACE(ah->ah_sc);
2956
2957 /* Read-And-Clear */
2958 stats->dot11ACKFailureCount += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
2959 stats->dot11RTSFailureCount += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
2960 stats->dot11RTSSuccessCount += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
2961 stats->dot11FCSErrorCount += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
2962
2963 /* XXX: Should we use this to track beacon count ?
2964 * -we read it anyway to clear the register */
2965 ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
2966
2967 /* Reset profile count registers on 5212*/
2968 if (ah->ah_version == AR5K_AR5212) {
2969 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX);
2970 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX);
2971 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR);
2972 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE);
2973 }
2974 }
2975
2976 /** ath5k_hw_set_ack_bitrate - set bitrate for ACKs
2977 *
2978 * @ah: the &struct ath5k_hw
2979 * @high: determines if to use low bit rate or now
2980 */
2981 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
2982 {
2983 if (ah->ah_version != AR5K_AR5212)
2984 return;
2985 else {
2986 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
2987 if (high)
2988 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
2989 else
2990 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
2991 }
2992 }
2993
2994
2995 /*
2996 * ACK/CTS Timeouts
2997 */
2998
2999 /*
3000 * Set ACK timeout on PCU
3001 */
3002 int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
3003 {
3004 ATH5K_TRACE(ah->ah_sc);
3005 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK),
3006 ah->ah_turbo) <= timeout)
3007 return -EINVAL;
3008
3009 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
3010 ath5k_hw_htoclock(timeout, ah->ah_turbo));
3011
3012 return 0;
3013 }
3014
3015 /*
3016 * Read the ACK timeout from PCU
3017 */
3018 unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah)
3019 {
3020 ATH5K_TRACE(ah->ah_sc);
3021
3022 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
3023 AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), ah->ah_turbo);
3024 }
3025
3026 /*
3027 * Set CTS timeout on PCU
3028 */
3029 int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
3030 {
3031 ATH5K_TRACE(ah->ah_sc);
3032 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS),
3033 ah->ah_turbo) <= timeout)
3034 return -EINVAL;
3035
3036 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
3037 ath5k_hw_htoclock(timeout, ah->ah_turbo));
3038
3039 return 0;
3040 }
3041
3042 /*
3043 * Read CTS timeout from PCU
3044 */
3045 unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah)
3046 {
3047 ATH5K_TRACE(ah->ah_sc);
3048 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
3049 AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), ah->ah_turbo);
3050 }
3051
3052 /*
3053 * Key table (WEP) functions
3054 */
3055
3056 int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
3057 {
3058 unsigned int i;
3059
3060 ATH5K_TRACE(ah->ah_sc);
3061 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
3062
3063 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
3064 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
3065
3066 /*
3067 * Set NULL encryption on AR5212+
3068 *
3069 * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5)
3070 * AR5K_KEYTABLE_TYPE_NULL -> 0x00000007
3071 *
3072 * Note2: Windows driver (ndiswrapper) sets this to
3073 * 0x00000714 instead of 0x00000007
3074 */
3075 if (ah->ah_version > AR5K_AR5211)
3076 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
3077 AR5K_KEYTABLE_TYPE(entry));
3078
3079 return 0;
3080 }
3081
3082 int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry)
3083 {
3084 ATH5K_TRACE(ah->ah_sc);
3085 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
3086
3087 /* Check the validation flag at the end of the entry */
3088 return ath5k_hw_reg_read(ah, AR5K_KEYTABLE_MAC1(entry)) &
3089 AR5K_KEYTABLE_VALID;
3090 }
3091
3092 int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
3093 const struct ieee80211_key_conf *key, const u8 *mac)
3094 {
3095 unsigned int i;
3096 __le32 key_v[5] = {};
3097 u32 keytype;
3098
3099 ATH5K_TRACE(ah->ah_sc);
3100
3101 /* key->keylen comes in from mac80211 in bytes */
3102
3103 if (key->keylen > AR5K_KEYTABLE_SIZE / 8)
3104 return -EOPNOTSUPP;
3105
3106 switch (key->keylen) {
3107 /* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit */
3108 case 40 / 8:
3109 memcpy(&key_v[0], key->key, 5);
3110 keytype = AR5K_KEYTABLE_TYPE_40;
3111 break;
3112
3113 /* WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit */
3114 case 104 / 8:
3115 memcpy(&key_v[0], &key->key[0], 6);
3116 memcpy(&key_v[2], &key->key[6], 6);
3117 memcpy(&key_v[4], &key->key[12], 1);
3118 keytype = AR5K_KEYTABLE_TYPE_104;
3119 break;
3120 /* WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit */
3121 case 128 / 8:
3122 memcpy(&key_v[0], &key->key[0], 6);
3123 memcpy(&key_v[2], &key->key[6], 6);
3124 memcpy(&key_v[4], &key->key[12], 4);
3125 keytype = AR5K_KEYTABLE_TYPE_128;
3126 break;
3127
3128 default:
3129 return -EINVAL; /* shouldn't happen */
3130 }
3131
3132 for (i = 0; i < ARRAY_SIZE(key_v); i++)
3133 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
3134 AR5K_KEYTABLE_OFF(entry, i));
3135
3136 ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry));
3137
3138 return ath5k_hw_set_key_lladdr(ah, entry, mac);
3139 }
3140
3141 int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
3142 {
3143 u32 low_id, high_id;
3144
3145 ATH5K_TRACE(ah->ah_sc);
3146 /* Invalid entry (key table overflow) */
3147 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
3148
3149 /* MAC may be NULL if it's a broadcast key. In this case no need to
3150 * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */
3151 if (unlikely(mac == NULL)) {
3152 low_id = 0xffffffff;
3153 high_id = 0xffff | AR5K_KEYTABLE_VALID;
3154 } else {
3155 low_id = AR5K_LOW_ID(mac);
3156 high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID;
3157 }
3158
3159 ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry));
3160 ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry));
3161
3162 return 0;
3163 }
3164
3165
3166 /********************************************\
3167 Queue Control Unit, DFS Control Unit Functions
3168 \********************************************/
3169
3170 /*
3171 * Initialize a transmit queue
3172 */
3173 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
3174 struct ath5k_txq_info *queue_info)
3175 {
3176 unsigned int queue;
3177 int ret;
3178
3179 ATH5K_TRACE(ah->ah_sc);
3180
3181 /*
3182 * Get queue by type
3183 */
3184 /*5210 only has 2 queues*/
3185 if (ah->ah_version == AR5K_AR5210) {
3186 switch (queue_type) {
3187 case AR5K_TX_QUEUE_DATA:
3188 queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
3189 break;
3190 case AR5K_TX_QUEUE_BEACON:
3191 case AR5K_TX_QUEUE_CAB:
3192 queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
3193 break;
3194 default:
3195 return -EINVAL;
3196 }
3197 } else {
3198 switch (queue_type) {
3199 case AR5K_TX_QUEUE_DATA:
3200 for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
3201 ah->ah_txq[queue].tqi_type !=
3202 AR5K_TX_QUEUE_INACTIVE; queue++) {
3203
3204 if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
3205 return -EINVAL;
3206 }
3207 break;
3208 case AR5K_TX_QUEUE_UAPSD:
3209 queue = AR5K_TX_QUEUE_ID_UAPSD;
3210 break;
3211 case AR5K_TX_QUEUE_BEACON:
3212 queue = AR5K_TX_QUEUE_ID_BEACON;
3213 break;
3214 case AR5K_TX_QUEUE_CAB:
3215 queue = AR5K_TX_QUEUE_ID_CAB;
3216 break;
3217 case AR5K_TX_QUEUE_XR_DATA:
3218 if (ah->ah_version != AR5K_AR5212)
3219 ATH5K_ERR(ah->ah_sc,
3220 "XR data queues only supported in"
3221 " 5212!\n");
3222 queue = AR5K_TX_QUEUE_ID_XR_DATA;
3223 break;
3224 default:
3225 return -EINVAL;
3226 }
3227 }
3228
3229 /*
3230 * Setup internal queue structure
3231 */
3232 memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));
3233 ah->ah_txq[queue].tqi_type = queue_type;
3234
3235 if (queue_info != NULL) {
3236 queue_info->tqi_type = queue_type;
3237 ret = ath5k_hw_setup_tx_queueprops(ah, queue, queue_info);
3238 if (ret)
3239 return ret;
3240 }
3241 /*
3242 * We use ah_txq_status to hold a temp value for
3243 * the Secondary interrupt mask registers on 5211+
3244 * check out ath5k_hw_reset_tx_queue
3245 */
3246 AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue);
3247
3248 return queue;
3249 }
3250
3251 /*
3252 * Setup a transmit queue
3253 */
3254 int ath5k_hw_setup_tx_queueprops(struct ath5k_hw *ah, int queue,
3255 const struct ath5k_txq_info *queue_info)
3256 {
3257 ATH5K_TRACE(ah->ah_sc);
3258 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3259
3260 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3261 return -EIO;
3262
3263 memcpy(&ah->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
3264
3265 /*XXX: Is this supported on 5210 ?*/
3266 if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA &&
3267 ((queue_info->tqi_subtype == AR5K_WME_AC_VI) ||
3268 (queue_info->tqi_subtype == AR5K_WME_AC_VO))) ||
3269 queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD)
3270 ah->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
3271
3272 return 0;
3273 }
3274
3275 /*
3276 * Get properties for a specific transmit queue
3277 */
3278 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
3279 struct ath5k_txq_info *queue_info)
3280 {
3281 ATH5K_TRACE(ah->ah_sc);
3282 memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
3283 return 0;
3284 }
3285
3286 /*
3287 * Set a transmit queue inactive
3288 */
3289 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3290 {
3291 ATH5K_TRACE(ah->ah_sc);
3292 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
3293 return;
3294
3295 /* This queue will be skipped in further operations */
3296 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
3297 /*For SIMR setup*/
3298 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
3299 }
3300
3301 /*
3302 * Set DFS params for a transmit queue
3303 */
3304 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3305 {
3306 u32 cw_min, cw_max, retry_lg, retry_sh;
3307 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
3308
3309 ATH5K_TRACE(ah->ah_sc);
3310 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3311
3312 tq = &ah->ah_txq[queue];
3313
3314 if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
3315 return 0;
3316
3317 if (ah->ah_version == AR5K_AR5210) {
3318 /* Only handle data queues, others will be ignored */
3319 if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
3320 return 0;
3321
3322 /* Set Slot time */
3323 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3324 AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
3325 AR5K_SLOT_TIME);
3326 /* Set ACK_CTS timeout */
3327 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3328 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
3329 AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
3330 /* Set Transmit Latency */
3331 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3332 AR5K_INIT_TRANSMIT_LATENCY_TURBO :
3333 AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
3334 /* Set IFS0 */
3335 if (ah->ah_turbo)
3336 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
3337 (ah->ah_aifs + tq->tqi_aifs) *
3338 AR5K_INIT_SLOT_TIME_TURBO) <<
3339 AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
3340 AR5K_IFS0);
3341 else
3342 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
3343 (ah->ah_aifs + tq->tqi_aifs) *
3344 AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) |
3345 AR5K_INIT_SIFS, AR5K_IFS0);
3346
3347 /* Set IFS1 */
3348 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3349 AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
3350 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
3351 /* Set AR5K_PHY_SETTLING */
3352 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3353 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
3354 | 0x38 :
3355 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
3356 | 0x1C,
3357 AR5K_PHY_SETTLING);
3358 /* Set Frame Control Register */
3359 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3360 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
3361 AR5K_PHY_TURBO_SHORT | 0x2020) :
3362 (AR5K_PHY_FRAME_CTL_INI | 0x1020),
3363 AR5K_PHY_FRAME_CTL_5210);
3364 }
3365
3366 /*
3367 * Calculate cwmin/max by channel mode
3368 */
3369 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
3370 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
3371 ah->ah_aifs = AR5K_TUNE_AIFS;
3372 /*XR is only supported on 5212*/
3373 if (IS_CHAN_XR(ah->ah_current_channel) &&
3374 ah->ah_version == AR5K_AR5212) {
3375 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
3376 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
3377 ah->ah_aifs = AR5K_TUNE_AIFS_XR;
3378 /*B mode is not supported on 5210*/
3379 } else if (IS_CHAN_B(ah->ah_current_channel) &&
3380 ah->ah_version != AR5K_AR5210) {
3381 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
3382 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
3383 ah->ah_aifs = AR5K_TUNE_AIFS_11B;
3384 }
3385
3386 cw_min = 1;
3387 while (cw_min < ah->ah_cw_min)
3388 cw_min = (cw_min << 1) | 1;
3389
3390 cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
3391 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
3392 cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
3393 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
3394
3395 /*
3396 * Calculate and set retry limits
3397 */
3398 if (ah->ah_software_retry) {
3399 /* XXX Need to test this */
3400 retry_lg = ah->ah_limit_tx_retries;
3401 retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
3402 AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
3403 } else {
3404 retry_lg = AR5K_INIT_LG_RETRY;
3405 retry_sh = AR5K_INIT_SH_RETRY;
3406 }
3407
3408 /*No QCU/DCU [5210]*/
3409 if (ah->ah_version == AR5K_AR5210) {
3410 ath5k_hw_reg_write(ah,
3411 (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
3412 | AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3413 AR5K_NODCU_RETRY_LMT_SLG_RETRY)
3414 | AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3415 AR5K_NODCU_RETRY_LMT_SSH_RETRY)
3416 | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY)
3417 | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY),
3418 AR5K_NODCU_RETRY_LMT);
3419 } else {
3420 /*QCU/DCU [5211+]*/
3421 ath5k_hw_reg_write(ah,
3422 AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3423 AR5K_DCU_RETRY_LMT_SLG_RETRY) |
3424 AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3425 AR5K_DCU_RETRY_LMT_SSH_RETRY) |
3426 AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) |
3427 AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY),
3428 AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
3429
3430 /*===Rest is also for QCU/DCU only [5211+]===*/
3431
3432 /*
3433 * Set initial content window (cw_min/cw_max)
3434 * and arbitrated interframe space (aifs)...
3435 */
3436 ath5k_hw_reg_write(ah,
3437 AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
3438 AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
3439 AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
3440 AR5K_DCU_LCL_IFS_AIFS),
3441 AR5K_QUEUE_DFS_LOCAL_IFS(queue));
3442
3443 /*
3444 * Set misc registers
3445 */
3446 ath5k_hw_reg_write(ah, AR5K_QCU_MISC_DCU_EARLY,
3447 AR5K_QUEUE_MISC(queue));
3448
3449 if (tq->tqi_cbr_period) {
3450 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
3451 AR5K_QCU_CBRCFG_INTVAL) |
3452 AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
3453 AR5K_QCU_CBRCFG_ORN_THRES),
3454 AR5K_QUEUE_CBRCFG(queue));
3455 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3456 AR5K_QCU_MISC_FRSHED_CBR);
3457 if (tq->tqi_cbr_overflow_limit)
3458 AR5K_REG_ENABLE_BITS(ah,
3459 AR5K_QUEUE_MISC(queue),
3460 AR5K_QCU_MISC_CBR_THRES_ENABLE);
3461 }
3462
3463 if (tq->tqi_ready_time)
3464 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
3465 AR5K_QCU_RDYTIMECFG_INTVAL) |
3466 AR5K_QCU_RDYTIMECFG_ENABLE,
3467 AR5K_QUEUE_RDYTIMECFG(queue));
3468
3469 if (tq->tqi_burst_time) {
3470 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
3471 AR5K_DCU_CHAN_TIME_DUR) |
3472 AR5K_DCU_CHAN_TIME_ENABLE,
3473 AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
3474
3475 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
3476 AR5K_REG_ENABLE_BITS(ah,
3477 AR5K_QUEUE_MISC(queue),
3478 AR5K_QCU_MISC_TXE);
3479 }
3480
3481 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
3482 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
3483 AR5K_QUEUE_DFS_MISC(queue));
3484
3485 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
3486 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
3487 AR5K_QUEUE_DFS_MISC(queue));
3488
3489 /*
3490 * Set registers by queue type
3491 */
3492 switch (tq->tqi_type) {
3493 case AR5K_TX_QUEUE_BEACON:
3494 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3495 AR5K_QCU_MISC_FRSHED_DBA_GT |
3496 AR5K_QCU_MISC_CBREXP_BCN |
3497 AR5K_QCU_MISC_BCN_ENABLE);
3498
3499 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3500 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3501 AR5K_DCU_MISC_ARBLOCK_CTL_S) |
3502 AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
3503 AR5K_DCU_MISC_BCN_ENABLE);
3504
3505 ath5k_hw_reg_write(ah, ((AR5K_TUNE_BEACON_INTERVAL -
3506 (AR5K_TUNE_SW_BEACON_RESP -
3507 AR5K_TUNE_DMA_BEACON_RESP) -
3508 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
3509 AR5K_QCU_RDYTIMECFG_ENABLE,
3510 AR5K_QUEUE_RDYTIMECFG(queue));
3511 break;
3512
3513 case AR5K_TX_QUEUE_CAB:
3514 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3515 AR5K_QCU_MISC_FRSHED_DBA_GT |
3516 AR5K_QCU_MISC_CBREXP |
3517 AR5K_QCU_MISC_CBREXP_BCN);
3518
3519 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3520 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3521 AR5K_DCU_MISC_ARBLOCK_CTL_S));
3522 break;
3523
3524 case AR5K_TX_QUEUE_UAPSD:
3525 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3526 AR5K_QCU_MISC_CBREXP);
3527 break;
3528
3529 case AR5K_TX_QUEUE_DATA:
3530 default:
3531 break;
3532 }
3533
3534 /*
3535 * Enable interrupts for this tx queue
3536 * in the secondary interrupt mask registers
3537 */
3538 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
3539 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
3540
3541 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
3542 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
3543
3544 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
3545 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
3546
3547 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
3548 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
3549
3550 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
3551 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
3552
3553
3554 /* Update secondary interrupt mask registers */
3555 ah->ah_txq_imr_txok &= ah->ah_txq_status;
3556 ah->ah_txq_imr_txerr &= ah->ah_txq_status;
3557 ah->ah_txq_imr_txurn &= ah->ah_txq_status;
3558 ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
3559 ah->ah_txq_imr_txeol &= ah->ah_txq_status;
3560
3561 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
3562 AR5K_SIMR0_QCU_TXOK) |
3563 AR5K_REG_SM(ah->ah_txq_imr_txdesc,
3564 AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
3565 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
3566 AR5K_SIMR1_QCU_TXERR) |
3567 AR5K_REG_SM(ah->ah_txq_imr_txeol,
3568 AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1);
3569 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txurn,
3570 AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2);
3571 }
3572
3573 return 0;
3574 }
3575
3576 /*
3577 * Get number of pending frames
3578 * for a specific queue [5211+]
3579 */
3580 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue) {
3581 ATH5K_TRACE(ah->ah_sc);
3582 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3583
3584 /* Return if queue is declared inactive */
3585 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3586 return false;
3587
3588 /* XXX: How about AR5K_CFG_TXCNT ? */
3589 if (ah->ah_version == AR5K_AR5210)
3590 return false;
3591
3592 return AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT;
3593 }
3594
3595 /*
3596 * Set slot time
3597 */
3598 int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
3599 {
3600 ATH5K_TRACE(ah->ah_sc);
3601 if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
3602 return -EINVAL;
3603
3604 if (ah->ah_version == AR5K_AR5210)
3605 ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time,
3606 ah->ah_turbo), AR5K_SLOT_TIME);
3607 else
3608 ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT);
3609
3610 return 0;
3611 }
3612
3613 /*
3614 * Get slot time
3615 */
3616 unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah)
3617 {
3618 ATH5K_TRACE(ah->ah_sc);
3619 if (ah->ah_version == AR5K_AR5210)
3620 return ath5k_hw_clocktoh(ath5k_hw_reg_read(ah,
3621 AR5K_SLOT_TIME) & 0xffff, ah->ah_turbo);
3622 else
3623 return ath5k_hw_reg_read(ah, AR5K_DCU_GBL_IFS_SLOT) & 0xffff;
3624 }
3625
3626
3627 /******************************\
3628 Hardware Descriptor Functions
3629 \******************************/
3630
3631 /*
3632 * TX Descriptor
3633 */
3634
3635 /*
3636 * Initialize the 2-word tx descriptor on 5210/5211
3637 */
3638 static int
3639 ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3640 unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
3641 unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
3642 unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
3643 unsigned int rtscts_rate, unsigned int rtscts_duration)
3644 {
3645 u32 frame_type;
3646 struct ath5k_hw_2w_tx_ctl *tx_ctl;
3647 unsigned int frame_len;
3648
3649 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
3650
3651 /*
3652 * Validate input
3653 * - Zero retries don't make sense.
3654 * - A zero rate will put the HW into a mode where it continously sends
3655 * noise on the channel, so it is important to avoid this.
3656 */
3657 if (unlikely(tx_tries0 == 0)) {
3658 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3659 WARN_ON(1);
3660 return -EINVAL;
3661 }
3662 if (unlikely(tx_rate0 == 0)) {
3663 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3664 WARN_ON(1);
3665 return -EINVAL;
3666 }
3667
3668 /* Clear descriptor */
3669 memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
3670
3671 /* Setup control descriptor */
3672
3673 /* Verify and set frame length */
3674
3675 /* remove padding we might have added before */
3676 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3677
3678 if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
3679 return -EINVAL;
3680
3681 tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
3682
3683 /* Verify and set buffer length */
3684
3685 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3686 if(type == AR5K_PKT_TYPE_BEACON)
3687 pkt_len = roundup(pkt_len, 4);
3688
3689 if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
3690 return -EINVAL;
3691
3692 tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
3693
3694 /*
3695 * Verify and set header length
3696 * XXX: I only found that on 5210 code, does it work on 5211 ?
3697 */
3698 if (ah->ah_version == AR5K_AR5210) {
3699 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
3700 return -EINVAL;
3701 tx_ctl->tx_control_0 |=
3702 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
3703 }
3704
3705 /*Diferences between 5210-5211*/
3706 if (ah->ah_version == AR5K_AR5210) {
3707 switch (type) {
3708 case AR5K_PKT_TYPE_BEACON:
3709 case AR5K_PKT_TYPE_PROBE_RESP:
3710 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
3711 case AR5K_PKT_TYPE_PIFS:
3712 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
3713 default:
3714 frame_type = type /*<< 2 ?*/;
3715 }
3716
3717 tx_ctl->tx_control_0 |=
3718 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
3719 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3720 } else {
3721 tx_ctl->tx_control_0 |=
3722 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
3723 AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
3724 tx_ctl->tx_control_1 |=
3725 AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
3726 }
3727 #define _TX_FLAGS(_c, _flag) \
3728 if (flags & AR5K_TXDESC_##_flag) \
3729 tx_ctl->tx_control_##_c |= \
3730 AR5K_2W_TX_DESC_CTL##_c##_##_flag
3731
3732 _TX_FLAGS(0, CLRDMASK);
3733 _TX_FLAGS(0, VEOL);
3734 _TX_FLAGS(0, INTREQ);
3735 _TX_FLAGS(0, RTSENA);
3736 _TX_FLAGS(1, NOACK);
3737
3738 #undef _TX_FLAGS
3739
3740 /*
3741 * WEP crap
3742 */
3743 if (key_index != AR5K_TXKEYIX_INVALID) {
3744 tx_ctl->tx_control_0 |=
3745 AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3746 tx_ctl->tx_control_1 |=
3747 AR5K_REG_SM(key_index,
3748 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3749 }
3750
3751 /*
3752 * RTS/CTS Duration [5210 ?]
3753 */
3754 if ((ah->ah_version == AR5K_AR5210) &&
3755 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
3756 tx_ctl->tx_control_1 |= rtscts_duration &
3757 AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
3758
3759 return 0;
3760 }
3761
3762 /*
3763 * Initialize the 4-word tx descriptor on 5212
3764 */
3765 static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
3766 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
3767 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
3768 unsigned int tx_tries0, unsigned int key_index,
3769 unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate,
3770 unsigned int rtscts_duration)
3771 {
3772 struct ath5k_hw_4w_tx_ctl *tx_ctl;
3773 unsigned int frame_len;
3774
3775 ATH5K_TRACE(ah->ah_sc);
3776 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
3777
3778 /*
3779 * Validate input
3780 * - Zero retries don't make sense.
3781 * - A zero rate will put the HW into a mode where it continously sends
3782 * noise on the channel, so it is important to avoid this.
3783 */
3784 if (unlikely(tx_tries0 == 0)) {
3785 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3786 WARN_ON(1);
3787 return -EINVAL;
3788 }
3789 if (unlikely(tx_rate0 == 0)) {
3790 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3791 WARN_ON(1);
3792 return -EINVAL;
3793 }
3794
3795 /* Clear descriptor */
3796 memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
3797
3798 /* Setup control descriptor */
3799
3800 /* Verify and set frame length */
3801
3802 /* remove padding we might have added before */
3803 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3804
3805 if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
3806 return -EINVAL;
3807
3808 tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
3809
3810 /* Verify and set buffer length */
3811
3812 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3813 if(type == AR5K_PKT_TYPE_BEACON)
3814 pkt_len = roundup(pkt_len, 4);
3815
3816 if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
3817 return -EINVAL;
3818
3819 tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
3820
3821 tx_ctl->tx_control_0 |=
3822 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
3823 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
3824 tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
3825 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
3826 tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
3827 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
3828 tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
3829
3830 #define _TX_FLAGS(_c, _flag) \
3831 if (flags & AR5K_TXDESC_##_flag) \
3832 tx_ctl->tx_control_##_c |= \
3833 AR5K_4W_TX_DESC_CTL##_c##_##_flag
3834
3835 _TX_FLAGS(0, CLRDMASK);
3836 _TX_FLAGS(0, VEOL);
3837 _TX_FLAGS(0, INTREQ);
3838 _TX_FLAGS(0, RTSENA);
3839 _TX_FLAGS(0, CTSENA);
3840 _TX_FLAGS(1, NOACK);
3841
3842 #undef _TX_FLAGS
3843
3844 /*
3845 * WEP crap
3846 */
3847 if (key_index != AR5K_TXKEYIX_INVALID) {
3848 tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3849 tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
3850 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3851 }
3852
3853 /*
3854 * RTS/CTS
3855 */
3856 if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
3857 if ((flags & AR5K_TXDESC_RTSENA) &&
3858 (flags & AR5K_TXDESC_CTSENA))
3859 return -EINVAL;
3860 tx_ctl->tx_control_2 |= rtscts_duration &
3861 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
3862 tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
3863 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
3864 }
3865
3866 return 0;
3867 }
3868
3869 /*
3870 * Initialize a 4-word multirate tx descriptor on 5212
3871 */
3872 static int
3873 ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3874 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
3875 unsigned int tx_rate3, u_int tx_tries3)
3876 {
3877 struct ath5k_hw_4w_tx_ctl *tx_ctl;
3878
3879 /*
3880 * Rates can be 0 as long as the retry count is 0 too.
3881 * A zero rate and nonzero retry count will put the HW into a mode where
3882 * it continously sends noise on the channel, so it is important to
3883 * avoid this.
3884 */
3885 if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
3886 (tx_rate2 == 0 && tx_tries2 != 0) ||
3887 (tx_rate3 == 0 && tx_tries3 != 0))) {
3888 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3889 WARN_ON(1);
3890 return -EINVAL;
3891 }
3892
3893 if (ah->ah_version == AR5K_AR5212) {
3894 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
3895
3896 #define _XTX_TRIES(_n) \
3897 if (tx_tries##_n) { \
3898 tx_ctl->tx_control_2 |= \
3899 AR5K_REG_SM(tx_tries##_n, \
3900 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \
3901 tx_ctl->tx_control_3 |= \
3902 AR5K_REG_SM(tx_rate##_n, \
3903 AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \
3904 }
3905
3906 _XTX_TRIES(1);
3907 _XTX_TRIES(2);
3908 _XTX_TRIES(3);
3909
3910 #undef _XTX_TRIES
3911
3912 return 1;
3913 }
3914
3915 return 0;
3916 }
3917
3918 /*
3919 * Proccess the tx status descriptor on 5210/5211
3920 */
3921 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
3922 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
3923 {
3924 struct ath5k_hw_2w_tx_ctl *tx_ctl;
3925 struct ath5k_hw_tx_status *tx_status;
3926
3927 ATH5K_TRACE(ah->ah_sc);
3928
3929 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
3930 tx_status = &desc->ud.ds_tx5210.tx_stat;
3931
3932 /* No frame has been send or error */
3933 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
3934 return -EINPROGRESS;
3935
3936 /*
3937 * Get descriptor status
3938 */
3939 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3940 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3941 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3942 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3943 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3944 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3945 /*TODO: ts->ts_virtcol + test*/
3946 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3947 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3948 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
3949 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
3950 ts->ts_antenna = 1;
3951 ts->ts_status = 0;
3952 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_0,
3953 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3954
3955 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
3956 if (tx_status->tx_status_0 &
3957 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
3958 ts->ts_status |= AR5K_TXERR_XRETRY;
3959
3960 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
3961 ts->ts_status |= AR5K_TXERR_FIFO;
3962
3963 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
3964 ts->ts_status |= AR5K_TXERR_FILT;
3965 }
3966
3967 return 0;
3968 }
3969
3970 /*
3971 * Proccess a tx descriptor on 5212
3972 */
3973 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
3974 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
3975 {
3976 struct ath5k_hw_4w_tx_ctl *tx_ctl;
3977 struct ath5k_hw_tx_status *tx_status;
3978
3979 ATH5K_TRACE(ah->ah_sc);
3980
3981 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
3982 tx_status = &desc->ud.ds_tx5212.tx_stat;
3983
3984 /* No frame has been send or error */
3985 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
3986 return -EINPROGRESS;
3987
3988 /*
3989 * Get descriptor status
3990 */
3991 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3992 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3993 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3994 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3995 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3996 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3997 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3998 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3999 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
4000 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
4001 ts->ts_antenna = (tx_status->tx_status_1 &
4002 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
4003 ts->ts_status = 0;
4004
4005 switch (AR5K_REG_MS(tx_status->tx_status_1,
4006 AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) {
4007 case 0:
4008 ts->ts_rate = tx_ctl->tx_control_3 &
4009 AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
4010 break;
4011 case 1:
4012 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
4013 AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
4014 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
4015 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
4016 break;
4017 case 2:
4018 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
4019 AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
4020 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
4021 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
4022 break;
4023 case 3:
4024 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
4025 AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
4026 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
4027 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3);
4028 break;
4029 }
4030
4031 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
4032 if (tx_status->tx_status_0 &
4033 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
4034 ts->ts_status |= AR5K_TXERR_XRETRY;
4035
4036 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
4037 ts->ts_status |= AR5K_TXERR_FIFO;
4038
4039 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
4040 ts->ts_status |= AR5K_TXERR_FILT;
4041 }
4042
4043 return 0;
4044 }
4045
4046 /*
4047 * RX Descriptor
4048 */
4049
4050 /*
4051 * Initialize an rx descriptor
4052 */
4053 int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
4054 u32 size, unsigned int flags)
4055 {
4056 struct ath5k_hw_rx_ctl *rx_ctl;
4057
4058 ATH5K_TRACE(ah->ah_sc);
4059 rx_ctl = &desc->ud.ds_rx.rx_ctl;
4060
4061 /*
4062 * Clear the descriptor
4063 * If we don't clean the status descriptor,
4064 * while scanning we get too many results,
4065 * most of them virtual, after some secs
4066 * of scanning system hangs. M.F.
4067 */
4068 memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
4069
4070 /* Setup descriptor */
4071 rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
4072 if (unlikely(rx_ctl->rx_control_1 != size))
4073 return -EINVAL;
4074
4075 if (flags & AR5K_RXDESC_INTREQ)
4076 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
4077
4078 return 0;
4079 }
4080
4081 /*
4082 * Proccess the rx status descriptor on 5210/5211
4083 */
4084 static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
4085 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
4086 {
4087 struct ath5k_hw_rx_status *rx_status;
4088
4089 rx_status = &desc->ud.ds_rx.u.rx_stat;
4090
4091 /* No frame received / not ready */
4092 if (unlikely((rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_DONE)
4093 == 0))
4094 return -EINPROGRESS;
4095
4096 /*
4097 * Frame receive status
4098 */
4099 rs->rs_datalen = rx_status->rx_status_0 &
4100 AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
4101 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
4102 AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
4103 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
4104 AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
4105 rs->rs_antenna = rx_status->rx_status_0 &
4106 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA;
4107 rs->rs_more = rx_status->rx_status_0 &
4108 AR5K_5210_RX_DESC_STATUS0_MORE;
4109 /* TODO: this timestamp is 13 bit, later on we assume 15 bit */
4110 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
4111 AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
4112 rs->rs_status = 0;
4113 rs->rs_phyerr = 0;
4114
4115 /*
4116 * Key table status
4117 */
4118 if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID)
4119 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
4120 AR5K_5210_RX_DESC_STATUS1_KEY_INDEX);
4121 else
4122 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
4123
4124 /*
4125 * Receive/descriptor errors
4126 */
4127 if ((rx_status->rx_status_1 &
4128 AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4129 if (rx_status->rx_status_1 &
4130 AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
4131 rs->rs_status |= AR5K_RXERR_CRC;
4132
4133 if (rx_status->rx_status_1 &
4134 AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN)
4135 rs->rs_status |= AR5K_RXERR_FIFO;
4136
4137 if (rx_status->rx_status_1 &
4138 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
4139 rs->rs_status |= AR5K_RXERR_PHY;
4140 rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1,
4141 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
4142 }
4143
4144 if (rx_status->rx_status_1 &
4145 AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4146 rs->rs_status |= AR5K_RXERR_DECRYPT;
4147 }
4148
4149 return 0;
4150 }
4151
4152 /*
4153 * Proccess the rx status descriptor on 5212
4154 */
4155 static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
4156 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
4157 {
4158 struct ath5k_hw_rx_status *rx_status;
4159 struct ath5k_hw_rx_error *rx_err;
4160
4161 ATH5K_TRACE(ah->ah_sc);
4162 rx_status = &desc->ud.ds_rx.u.rx_stat;
4163
4164 /* Overlay on error */
4165 rx_err = &desc->ud.ds_rx.u.rx_err;
4166
4167 /* No frame received / not ready */
4168 if (unlikely((rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_DONE)
4169 == 0))
4170 return -EINPROGRESS;
4171
4172 /*
4173 * Frame receive status
4174 */
4175 rs->rs_datalen = rx_status->rx_status_0 &
4176 AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
4177 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
4178 AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
4179 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
4180 AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
4181 rs->rs_antenna = rx_status->rx_status_0 &
4182 AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA;
4183 rs->rs_more = rx_status->rx_status_0 &
4184 AR5K_5212_RX_DESC_STATUS0_MORE;
4185 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
4186 AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
4187 rs->rs_status = 0;
4188 rs->rs_phyerr = 0;
4189
4190 /*
4191 * Key table status
4192 */
4193 if (rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID)
4194 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
4195 AR5K_5212_RX_DESC_STATUS1_KEY_INDEX);
4196 else
4197 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
4198
4199 /*
4200 * Receive/descriptor errors
4201 */
4202 if ((rx_status->rx_status_1 &
4203 AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4204 if (rx_status->rx_status_1 &
4205 AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
4206 rs->rs_status |= AR5K_RXERR_CRC;
4207
4208 if (rx_status->rx_status_1 &
4209 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
4210 rs->rs_status |= AR5K_RXERR_PHY;
4211 rs->rs_phyerr |= AR5K_REG_MS(rx_err->rx_error_1,
4212 AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
4213 }
4214
4215 if (rx_status->rx_status_1 &
4216 AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4217 rs->rs_status |= AR5K_RXERR_DECRYPT;
4218
4219 if (rx_status->rx_status_1 &
4220 AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
4221 rs->rs_status |= AR5K_RXERR_MIC;
4222 }
4223
4224 return 0;
4225 }
4226
4227
4228 /****************\
4229 GPIO Functions
4230 \****************/
4231
4232 /*
4233 * Set led state
4234 */
4235 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
4236 {
4237 u32 led;
4238 /*5210 has different led mode handling*/
4239 u32 led_5210;
4240
4241 ATH5K_TRACE(ah->ah_sc);
4242
4243 /*Reset led status*/
4244 if (ah->ah_version != AR5K_AR5210)
4245 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
4246 AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED);
4247 else
4248 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_LED);
4249
4250 /*
4251 * Some blinking values, define at your wish
4252 */
4253 switch (state) {
4254 case AR5K_LED_SCAN:
4255 case AR5K_LED_AUTH:
4256 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_PEND;
4257 led_5210 = AR5K_PCICFG_LED_PEND | AR5K_PCICFG_LED_BCTL;
4258 break;
4259
4260 case AR5K_LED_INIT:
4261 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_NONE;
4262 led_5210 = AR5K_PCICFG_LED_PEND;
4263 break;
4264
4265 case AR5K_LED_ASSOC:
4266 case AR5K_LED_RUN:
4267 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_ASSOC;
4268 led_5210 = AR5K_PCICFG_LED_ASSOC;
4269 break;
4270
4271 default:
4272 led = AR5K_PCICFG_LEDMODE_PROM | AR5K_PCICFG_LED_NONE;
4273 led_5210 = AR5K_PCICFG_LED_PEND;
4274 break;
4275 }
4276
4277 /*Write new status to the register*/
4278 if (ah->ah_version != AR5K_AR5210)
4279 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led);
4280 else
4281 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led_5210);
4282 }
4283
4284 /*
4285 * Set GPIO outputs
4286 */
4287 int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
4288 {
4289 ATH5K_TRACE(ah->ah_sc);
4290 if (gpio > AR5K_NUM_GPIO)
4291 return -EINVAL;
4292
4293 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4294 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR);
4295
4296 return 0;
4297 }
4298
4299 /*
4300 * Set GPIO inputs
4301 */
4302 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
4303 {
4304 ATH5K_TRACE(ah->ah_sc);
4305 if (gpio > AR5K_NUM_GPIO)
4306 return -EINVAL;
4307
4308 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4309 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR);
4310
4311 return 0;
4312 }
4313
4314 /*
4315 * Get GPIO state
4316 */
4317 u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
4318 {
4319 ATH5K_TRACE(ah->ah_sc);
4320 if (gpio > AR5K_NUM_GPIO)
4321 return 0xffffffff;
4322
4323 /* GPIO input magic */
4324 return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) &
4325 0x1;
4326 }
4327
4328 /*
4329 * Set GPIO state
4330 */
4331 int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
4332 {
4333 u32 data;
4334 ATH5K_TRACE(ah->ah_sc);
4335
4336 if (gpio > AR5K_NUM_GPIO)
4337 return -EINVAL;
4338
4339 /* GPIO output magic */
4340 data = ath5k_hw_reg_read(ah, AR5K_GPIODO);
4341
4342 data &= ~(1 << gpio);
4343 data |= (val & 1) << gpio;
4344
4345 ath5k_hw_reg_write(ah, data, AR5K_GPIODO);
4346
4347 return 0;
4348 }
4349
4350 /*
4351 * Initialize the GPIO interrupt (RFKill switch)
4352 */
4353 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
4354 u32 interrupt_level)
4355 {
4356 u32 data;
4357
4358 ATH5K_TRACE(ah->ah_sc);
4359 if (gpio > AR5K_NUM_GPIO)
4360 return;
4361
4362 /*
4363 * Set the GPIO interrupt
4364 */
4365 data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &
4366 ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH |
4367 AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) |
4368 (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA);
4369
4370 ath5k_hw_reg_write(ah, interrupt_level ? data :
4371 (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR);
4372
4373 ah->ah_imr |= AR5K_IMR_GPIO;
4374
4375 /* Enable GPIO interrupts */
4376 AR5K_REG_ENABLE_BITS(ah, AR5K_PIMR, AR5K_IMR_GPIO);
4377 }
4378
4379
4380
4381
4382 /****************\
4383 Misc functions
4384 \****************/
4385
4386 int ath5k_hw_get_capability(struct ath5k_hw *ah,
4387 enum ath5k_capability_type cap_type,
4388 u32 capability, u32 *result)
4389 {
4390 ATH5K_TRACE(ah->ah_sc);
4391
4392 switch (cap_type) {
4393 case AR5K_CAP_NUM_TXQUEUES:
4394 if (result) {
4395 if (ah->ah_version == AR5K_AR5210)
4396 *result = AR5K_NUM_TX_QUEUES_NOQCU;
4397 else
4398 *result = AR5K_NUM_TX_QUEUES;
4399 goto yes;
4400 }
4401 case AR5K_CAP_VEOL:
4402 goto yes;
4403 case AR5K_CAP_COMPRESSION:
4404 if (ah->ah_version == AR5K_AR5212)
4405 goto yes;
4406 else
4407 goto no;
4408 case AR5K_CAP_BURST:
4409 goto yes;
4410 case AR5K_CAP_TPC:
4411 goto yes;
4412 case AR5K_CAP_BSSIDMASK:
4413 if (ah->ah_version == AR5K_AR5212)
4414 goto yes;
4415 else
4416 goto no;
4417 case AR5K_CAP_XR:
4418 if (ah->ah_version == AR5K_AR5212)
4419 goto yes;
4420 else
4421 goto no;
4422 default:
4423 goto no;
4424 }
4425
4426 no:
4427 return -EINVAL;
4428 yes:
4429 return 0;
4430 }
4431
4432 static int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid,
4433 u16 assoc_id)
4434 {
4435 ATH5K_TRACE(ah->ah_sc);
4436
4437 if (ah->ah_version == AR5K_AR5210) {
4438 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
4439 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4440 return 0;
4441 }
4442
4443 return -EIO;
4444 }
4445
4446 static int ath5k_hw_disable_pspoll(struct ath5k_hw *ah)
4447 {
4448 ATH5K_TRACE(ah->ah_sc);
4449
4450 if (ah->ah_version == AR5K_AR5210) {
4451 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
4452 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4453 return 0;
4454 }
4455
4456 return -EIO;
4457 }
Linux 2.6 libata-dev (mirror)