1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2007-2010 Broadcom Corporation.
13 #define TG3_64BIT_REG_HIGH 0x00UL
14 #define TG3_64BIT_REG_LOW 0x04UL
16 /* Descriptor block info. */
17 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
18 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
19 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
20 #define BDINFO_FLAGS_DISABLED 0x00000002
21 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
22 #define BDINFO_FLAGS_MAXLEN_SHIFT 16
23 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
24 #define TG3_BDINFO_SIZE 0x10UL
26 #define RX_COPY_THRESHOLD 256
28 #define TG3_RX_INTERNAL_RING_SZ_5906 32
30 #define RX_STD_MAX_SIZE 1536
31 #define RX_STD_MAX_SIZE_5705 512
32 #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
34 /* First 256 bytes are a mirror of PCI config space. */
35 #define TG3PCI_VENDOR 0x00000000
36 #define TG3PCI_VENDOR_BROADCOM 0x14e4
37 #define TG3PCI_DEVICE 0x00000002
38 #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
39 #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
40 #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
41 #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
42 #define TG3PCI_DEVICE_TIGON3_5761S 0x1688
43 #define TG3PCI_DEVICE_TIGON3_5761SE 0x1689
44 #define TG3PCI_DEVICE_TIGON3_57780 0x1692
45 #define TG3PCI_DEVICE_TIGON3_57760 0x1690
46 #define TG3PCI_DEVICE_TIGON3_57790 0x1694
47 #define TG3PCI_DEVICE_TIGON3_57788 0x1691
48 #define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */
49 #define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */
50 #define TG3PCI_DEVICE_TIGON3_5717 0x1655
51 #define TG3PCI_DEVICE_TIGON3_5718 0x1656
52 #define TG3PCI_DEVICE_TIGON3_5724 0x165c
53 #define TG3PCI_DEVICE_TIGON3_57781 0x16b1
54 #define TG3PCI_DEVICE_TIGON3_57785 0x16b5
55 #define TG3PCI_DEVICE_TIGON3_57761 0x16b0
56 #define TG3PCI_DEVICE_TIGON3_57765 0x16b4
57 #define TG3PCI_DEVICE_TIGON3_57791 0x16b2
58 #define TG3PCI_DEVICE_TIGON3_57795 0x16b6
59 /* 0x04 --> 0x64 unused */
60 #define TG3PCI_MSI_DATA 0x00000064
61 /* 0x66 --> 0x68 unused */
62 #define TG3PCI_MISC_HOST_CTRL 0x00000068
63 #define MISC_HOST_CTRL_CLEAR_INT 0x00000001
64 #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
65 #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
66 #define MISC_HOST_CTRL_WORD_SWAP 0x00000008
67 #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
68 #define MISC_HOST_CTRL_CLKREG_RW 0x00000020
69 #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
70 #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
71 #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
72 #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
73 #define MISC_HOST_CTRL_CHIPREV 0xffff0000
74 #define MISC_HOST_CTRL_CHIPREV_SHIFT 16
75 #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
76 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
77 MISC_HOST_CTRL_CHIPREV_SHIFT)
78 #define CHIPREV_ID_5700_A0 0x7000
79 #define CHIPREV_ID_5700_A1 0x7001
80 #define CHIPREV_ID_5700_B0 0x7100
81 #define CHIPREV_ID_5700_B1 0x7101
82 #define CHIPREV_ID_5700_B3 0x7102
83 #define CHIPREV_ID_5700_ALTIMA 0x7104
84 #define CHIPREV_ID_5700_C0 0x7200
85 #define CHIPREV_ID_5701_A0 0x0000
86 #define CHIPREV_ID_5701_B0 0x0100
87 #define CHIPREV_ID_5701_B2 0x0102
88 #define CHIPREV_ID_5701_B5 0x0105
89 #define CHIPREV_ID_5703_A0 0x1000
90 #define CHIPREV_ID_5703_A1 0x1001
91 #define CHIPREV_ID_5703_A2 0x1002
92 #define CHIPREV_ID_5703_A3 0x1003
93 #define CHIPREV_ID_5704_A0 0x2000
94 #define CHIPREV_ID_5704_A1 0x2001
95 #define CHIPREV_ID_5704_A2 0x2002
96 #define CHIPREV_ID_5704_A3 0x2003
97 #define CHIPREV_ID_5705_A0 0x3000
98 #define CHIPREV_ID_5705_A1 0x3001
99 #define CHIPREV_ID_5705_A2 0x3002
100 #define CHIPREV_ID_5705_A3 0x3003
101 #define CHIPREV_ID_5750_A0 0x4000
102 #define CHIPREV_ID_5750_A1 0x4001
103 #define CHIPREV_ID_5750_A3 0x4003
104 #define CHIPREV_ID_5750_C2 0x4202
105 #define CHIPREV_ID_5752_A0_HW 0x5000
106 #define CHIPREV_ID_5752_A0 0x6000
107 #define CHIPREV_ID_5752_A1 0x6001
108 #define CHIPREV_ID_5714_A2 0x9002
109 #define CHIPREV_ID_5906_A1 0xc001
110 #define CHIPREV_ID_57780_A0 0x57780000
111 #define CHIPREV_ID_57780_A1 0x57780001
112 #define CHIPREV_ID_5717_A0 0x05717000
113 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
114 #define ASIC_REV_5700 0x07
115 #define ASIC_REV_5701 0x00
116 #define ASIC_REV_5703 0x01
117 #define ASIC_REV_5704 0x02
118 #define ASIC_REV_5705 0x03
119 #define ASIC_REV_5750 0x04
120 #define ASIC_REV_5752 0x06
121 #define ASIC_REV_5780 0x08
122 #define ASIC_REV_5714 0x09
123 #define ASIC_REV_5755 0x0a
124 #define ASIC_REV_5787 0x0b
125 #define ASIC_REV_5906 0x0c
126 #define ASIC_REV_USE_PROD_ID_REG 0x0f
127 #define ASIC_REV_5784 0x5784
128 #define ASIC_REV_5761 0x5761
129 #define ASIC_REV_5785 0x5785
130 #define ASIC_REV_57780 0x57780
131 #define ASIC_REV_5717 0x5717
132 #define ASIC_REV_57765 0x57785
133 #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
134 #define CHIPREV_5700_AX 0x70
135 #define CHIPREV_5700_BX 0x71
136 #define CHIPREV_5700_CX 0x72
137 #define CHIPREV_5701_AX 0x00
138 #define CHIPREV_5703_AX 0x10
139 #define CHIPREV_5704_AX 0x20
140 #define CHIPREV_5704_BX 0x21
141 #define CHIPREV_5750_AX 0x40
142 #define CHIPREV_5750_BX 0x41
143 #define CHIPREV_5784_AX 0x57840
144 #define CHIPREV_5761_AX 0x57610
145 #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
146 #define METAL_REV_A0 0x00
147 #define METAL_REV_A1 0x01
148 #define METAL_REV_B0 0x00
149 #define METAL_REV_B1 0x01
150 #define METAL_REV_B2 0x02
151 #define TG3PCI_DMA_RW_CTRL 0x0000006c
152 #define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001
153 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
154 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
155 #define DMA_RWCTRL_READ_BNDRY_16 0x00000100
156 #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
157 #define DMA_RWCTRL_READ_BNDRY_32 0x00000200
158 #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
159 #define DMA_RWCTRL_READ_BNDRY_64 0x00000300
160 #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
161 #define DMA_RWCTRL_READ_BNDRY_128 0x00000400
162 #define DMA_RWCTRL_READ_BNDRY_256 0x00000500
163 #define DMA_RWCTRL_READ_BNDRY_512 0x00000600
164 #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
165 #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
166 #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
167 #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
168 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
169 #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
170 #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
171 #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
172 #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
173 #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
174 #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
175 #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
176 #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
177 #define DMA_RWCTRL_ONE_DMA 0x00004000
178 #define DMA_RWCTRL_READ_WATER 0x00070000
179 #define DMA_RWCTRL_READ_WATER_SHIFT 16
180 #define DMA_RWCTRL_WRITE_WATER 0x00380000
181 #define DMA_RWCTRL_WRITE_WATER_SHIFT 19
182 #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
183 #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
184 #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
185 #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
186 #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
187 #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
188 #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
189 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
190 #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
191 #define TG3PCI_PCISTATE 0x00000070
192 #define PCISTATE_FORCE_RESET 0x00000001
193 #define PCISTATE_INT_NOT_ACTIVE 0x00000002
194 #define PCISTATE_CONV_PCI_MODE 0x00000004
195 #define PCISTATE_BUS_SPEED_HIGH 0x00000008
196 #define PCISTATE_BUS_32BIT 0x00000010
197 #define PCISTATE_ROM_ENABLE 0x00000020
198 #define PCISTATE_ROM_RETRY_ENABLE 0x00000040
199 #define PCISTATE_FLAT_VIEW 0x00000100
200 #define PCISTATE_RETRY_SAME_DMA 0x00002000
201 #define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
202 #define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
203 #define TG3PCI_CLOCK_CTRL 0x00000074
204 #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
205 #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
206 #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
207 #define CLOCK_CTRL_ALTCLK 0x00001000
208 #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
209 #define CLOCK_CTRL_44MHZ_CORE 0x00040000
210 #define CLOCK_CTRL_625_CORE 0x00100000
211 #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
212 #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
213 #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
214 #define TG3PCI_REG_BASE_ADDR 0x00000078
215 #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
216 #define TG3PCI_REG_DATA 0x00000080
217 #define TG3PCI_MEM_WIN_DATA 0x00000084
218 #define TG3PCI_MISC_LOCAL_CTRL 0x00000090
219 /* 0x94 --> 0x98 unused */
220 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
221 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
222 /* 0xa0 --> 0xb8 unused */
223 #define TG3PCI_DUAL_MAC_CTRL 0x000000b8
224 #define DUAL_MAC_CTRL_CH_MASK 0x00000003
225 #define DUAL_MAC_CTRL_ID 0x00000004
226 #define TG3PCI_PRODID_ASICREV 0x000000bc
227 #define PROD_ID_ASIC_REV_MASK 0x0fffffff
228 /* 0xc0 --> 0xf4 unused */
230 #define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4
231 #define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc
232 /* 0xf8 --> 0x200 unused */
234 #define TG3_CORR_ERR_STAT 0x00000110
235 #define TG3_CORR_ERR_STAT_CLEAR 0xffffffff
236 /* 0x114 --> 0x200 unused */
238 /* Mailbox registers */
239 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
240 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
241 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
242 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
243 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
244 #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
245 #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
246 #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
247 #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
248 #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
249 #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
250 #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
251 #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
252 #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
253 #define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \
255 #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
256 #define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \
258 #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
259 #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
260 #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
261 #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
262 #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
263 #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
264 #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
265 #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
266 #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
267 #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
268 #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
269 #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
270 #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
271 #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
272 #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
273 #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
274 #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
275 #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
276 #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
277 #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
278 #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
279 #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
280 #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
281 #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
282 #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
283 #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
284 #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
285 #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
286 #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
287 #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
288 #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
289 #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
290 #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
291 #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
292 #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
293 #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
294 #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
295 #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
296 #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
297 #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
298 #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
299 #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
300 #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
301 #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
302 #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
303 #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
304 #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
305 #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
306 #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
308 /* MAC control registers */
309 #define MAC_MODE 0x00000400
310 #define MAC_MODE_RESET 0x00000001
311 #define MAC_MODE_HALF_DUPLEX 0x00000002
312 #define MAC_MODE_PORT_MODE_MASK 0x0000000c
313 #define MAC_MODE_PORT_MODE_TBI 0x0000000c
314 #define MAC_MODE_PORT_MODE_GMII 0x00000008
315 #define MAC_MODE_PORT_MODE_MII 0x00000004
316 #define MAC_MODE_PORT_MODE_NONE 0x00000000
317 #define MAC_MODE_PORT_INT_LPBACK 0x00000010
318 #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
319 #define MAC_MODE_TX_BURSTING 0x00000100
320 #define MAC_MODE_MAX_DEFER 0x00000200
321 #define MAC_MODE_LINK_POLARITY 0x00000400
322 #define MAC_MODE_RXSTAT_ENABLE 0x00000800
323 #define MAC_MODE_RXSTAT_CLEAR 0x00001000
324 #define MAC_MODE_RXSTAT_FLUSH 0x00002000
325 #define MAC_MODE_TXSTAT_ENABLE 0x00004000
326 #define MAC_MODE_TXSTAT_CLEAR 0x00008000
327 #define MAC_MODE_TXSTAT_FLUSH 0x00010000
328 #define MAC_MODE_SEND_CONFIGS 0x00020000
329 #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
330 #define MAC_MODE_ACPI_ENABLE 0x00080000
331 #define MAC_MODE_MIP_ENABLE 0x00100000
332 #define MAC_MODE_TDE_ENABLE 0x00200000
333 #define MAC_MODE_RDE_ENABLE 0x00400000
334 #define MAC_MODE_FHDE_ENABLE 0x00800000
335 #define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000
336 #define MAC_MODE_APE_RX_EN 0x08000000
337 #define MAC_MODE_APE_TX_EN 0x10000000
338 #define MAC_STATUS 0x00000404
339 #define MAC_STATUS_PCS_SYNCED 0x00000001
340 #define MAC_STATUS_SIGNAL_DET 0x00000002
341 #define MAC_STATUS_RCVD_CFG 0x00000004
342 #define MAC_STATUS_CFG_CHANGED 0x00000008
343 #define MAC_STATUS_SYNC_CHANGED 0x00000010
344 #define MAC_STATUS_PORT_DEC_ERR 0x00000400
345 #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
346 #define MAC_STATUS_MI_COMPLETION 0x00400000
347 #define MAC_STATUS_MI_INTERRUPT 0x00800000
348 #define MAC_STATUS_AP_ERROR 0x01000000
349 #define MAC_STATUS_ODI_ERROR 0x02000000
350 #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
351 #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
352 #define MAC_EVENT 0x00000408
353 #define MAC_EVENT_PORT_DECODE_ERR 0x00000400
354 #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
355 #define MAC_EVENT_MI_COMPLETION 0x00400000
356 #define MAC_EVENT_MI_INTERRUPT 0x00800000
357 #define MAC_EVENT_AP_ERROR 0x01000000
358 #define MAC_EVENT_ODI_ERROR 0x02000000
359 #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
360 #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
361 #define MAC_LED_CTRL 0x0000040c
362 #define LED_CTRL_LNKLED_OVERRIDE 0x00000001
363 #define LED_CTRL_1000MBPS_ON 0x00000002
364 #define LED_CTRL_100MBPS_ON 0x00000004
365 #define LED_CTRL_10MBPS_ON 0x00000008
366 #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
367 #define LED_CTRL_TRAFFIC_BLINK 0x00000020
368 #define LED_CTRL_TRAFFIC_LED 0x00000040
369 #define LED_CTRL_1000MBPS_STATUS 0x00000080
370 #define LED_CTRL_100MBPS_STATUS 0x00000100
371 #define LED_CTRL_10MBPS_STATUS 0x00000200
372 #define LED_CTRL_TRAFFIC_STATUS 0x00000400
373 #define LED_CTRL_MODE_MAC 0x00000000
374 #define LED_CTRL_MODE_PHY_1 0x00000800
375 #define LED_CTRL_MODE_PHY_2 0x00001000
376 #define LED_CTRL_MODE_SHASTA_MAC 0x00002000
377 #define LED_CTRL_MODE_SHARED 0x00004000
378 #define LED_CTRL_MODE_COMBO 0x00008000
379 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
380 #define LED_CTRL_BLINK_RATE_SHIFT 19
381 #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
382 #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
383 #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
384 #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
385 #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
386 #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
387 #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
388 #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
389 #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
390 #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
391 #define MAC_ACPI_MBUF_PTR 0x00000430
392 #define MAC_ACPI_LEN_OFFSET 0x00000434
393 #define ACPI_LENOFF_LEN_MASK 0x0000ffff
394 #define ACPI_LENOFF_LEN_SHIFT 0
395 #define ACPI_LENOFF_OFF_MASK 0x0fff0000
396 #define ACPI_LENOFF_OFF_SHIFT 16
397 #define MAC_TX_BACKOFF_SEED 0x00000438
398 #define TX_BACKOFF_SEED_MASK 0x000003ff
399 #define MAC_RX_MTU_SIZE 0x0000043c
400 #define RX_MTU_SIZE_MASK 0x0000ffff
401 #define MAC_PCS_TEST 0x00000440
402 #define PCS_TEST_PATTERN_MASK 0x000fffff
403 #define PCS_TEST_PATTERN_SHIFT 0
404 #define PCS_TEST_ENABLE 0x00100000
405 #define MAC_TX_AUTO_NEG 0x00000444
406 #define TX_AUTO_NEG_MASK 0x0000ffff
407 #define TX_AUTO_NEG_SHIFT 0
408 #define MAC_RX_AUTO_NEG 0x00000448
409 #define RX_AUTO_NEG_MASK 0x0000ffff
410 #define RX_AUTO_NEG_SHIFT 0
411 #define MAC_MI_COM 0x0000044c
412 #define MI_COM_CMD_MASK 0x0c000000
413 #define MI_COM_CMD_WRITE 0x04000000
414 #define MI_COM_CMD_READ 0x08000000
415 #define MI_COM_READ_FAILED 0x10000000
416 #define MI_COM_START 0x20000000
417 #define MI_COM_BUSY 0x20000000
418 #define MI_COM_PHY_ADDR_MASK 0x03e00000
419 #define MI_COM_PHY_ADDR_SHIFT 21
420 #define MI_COM_REG_ADDR_MASK 0x001f0000
421 #define MI_COM_REG_ADDR_SHIFT 16
422 #define MI_COM_DATA_MASK 0x0000ffff
423 #define MAC_MI_STAT 0x00000450
424 #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
425 #define MAC_MI_STAT_10MBPS_MODE 0x00000002
426 #define MAC_MI_MODE 0x00000454
427 #define MAC_MI_MODE_CLK_10MHZ 0x00000001
428 #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
429 #define MAC_MI_MODE_AUTO_POLL 0x00000010
430 #define MAC_MI_MODE_500KHZ_CONST 0x00008000
431 #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
432 #define MAC_AUTO_POLL_STATUS 0x00000458
433 #define MAC_AUTO_POLL_ERROR 0x00000001
434 #define MAC_TX_MODE 0x0000045c
435 #define TX_MODE_RESET 0x00000001
436 #define TX_MODE_ENABLE 0x00000002
437 #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
438 #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
439 #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
440 #define MAC_TX_STATUS 0x00000460
441 #define TX_STATUS_XOFFED 0x00000001
442 #define TX_STATUS_SENT_XOFF 0x00000002
443 #define TX_STATUS_SENT_XON 0x00000004
444 #define TX_STATUS_LINK_UP 0x00000008
445 #define TX_STATUS_ODI_UNDERRUN 0x00000010
446 #define TX_STATUS_ODI_OVERRUN 0x00000020
447 #define MAC_TX_LENGTHS 0x00000464
448 #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
449 #define TX_LENGTHS_SLOT_TIME_SHIFT 0
450 #define TX_LENGTHS_IPG_MASK 0x00000f00
451 #define TX_LENGTHS_IPG_SHIFT 8
452 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000
453 #define TX_LENGTHS_IPG_CRS_SHIFT 12
454 #define MAC_RX_MODE 0x00000468
455 #define RX_MODE_RESET 0x00000001
456 #define RX_MODE_ENABLE 0x00000002
457 #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
458 #define RX_MODE_KEEP_MAC_CTRL 0x00000008
459 #define RX_MODE_KEEP_PAUSE 0x00000010
460 #define RX_MODE_ACCEPT_OVERSIZED 0x00000020
461 #define RX_MODE_ACCEPT_RUNTS 0x00000040
462 #define RX_MODE_LEN_CHECK 0x00000080
463 #define RX_MODE_PROMISC 0x00000100
464 #define RX_MODE_NO_CRC_CHECK 0x00000200
465 #define RX_MODE_KEEP_VLAN_TAG 0x00000400
466 #define RX_MODE_RSS_IPV4_HASH_EN 0x00010000
467 #define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000
468 #define RX_MODE_RSS_IPV6_HASH_EN 0x00040000
469 #define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000
470 #define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000
471 #define RX_MODE_RSS_ENABLE 0x00800000
472 #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
473 #define MAC_RX_STATUS 0x0000046c
474 #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
475 #define RX_STATUS_XOFF_RCVD 0x00000002
476 #define RX_STATUS_XON_RCVD 0x00000004
477 #define MAC_HASH_REG_0 0x00000470
478 #define MAC_HASH_REG_1 0x00000474
479 #define MAC_HASH_REG_2 0x00000478
480 #define MAC_HASH_REG_3 0x0000047c
481 #define MAC_RCV_RULE_0 0x00000480
482 #define MAC_RCV_VALUE_0 0x00000484
483 #define MAC_RCV_RULE_1 0x00000488
484 #define MAC_RCV_VALUE_1 0x0000048c
485 #define MAC_RCV_RULE_2 0x00000490
486 #define MAC_RCV_VALUE_2 0x00000494
487 #define MAC_RCV_RULE_3 0x00000498
488 #define MAC_RCV_VALUE_3 0x0000049c
489 #define MAC_RCV_RULE_4 0x000004a0
490 #define MAC_RCV_VALUE_4 0x000004a4
491 #define MAC_RCV_RULE_5 0x000004a8
492 #define MAC_RCV_VALUE_5 0x000004ac
493 #define MAC_RCV_RULE_6 0x000004b0
494 #define MAC_RCV_VALUE_6 0x000004b4
495 #define MAC_RCV_RULE_7 0x000004b8
496 #define MAC_RCV_VALUE_7 0x000004bc
497 #define MAC_RCV_RULE_8 0x000004c0
498 #define MAC_RCV_VALUE_8 0x000004c4
499 #define MAC_RCV_RULE_9 0x000004c8
500 #define MAC_RCV_VALUE_9 0x000004cc
501 #define MAC_RCV_RULE_10 0x000004d0
502 #define MAC_RCV_VALUE_10 0x000004d4
503 #define MAC_RCV_RULE_11 0x000004d8
504 #define MAC_RCV_VALUE_11 0x000004dc
505 #define MAC_RCV_RULE_12 0x000004e0
506 #define MAC_RCV_VALUE_12 0x000004e4
507 #define MAC_RCV_RULE_13 0x000004e8
508 #define MAC_RCV_VALUE_13 0x000004ec
509 #define MAC_RCV_RULE_14 0x000004f0
510 #define MAC_RCV_VALUE_14 0x000004f4
511 #define MAC_RCV_RULE_15 0x000004f8
512 #define MAC_RCV_VALUE_15 0x000004fc
513 #define RCV_RULE_DISABLE_MASK 0x7fffffff
514 #define MAC_RCV_RULE_CFG 0x00000500
515 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
516 #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
517 /* 0x508 --> 0x520 unused */
518 #define MAC_HASHREGU_0 0x00000520
519 #define MAC_HASHREGU_1 0x00000524
520 #define MAC_HASHREGU_2 0x00000528
521 #define MAC_HASHREGU_3 0x0000052c
522 #define MAC_EXTADDR_0_HIGH 0x00000530
523 #define MAC_EXTADDR_0_LOW 0x00000534
524 #define MAC_EXTADDR_1_HIGH 0x00000538
525 #define MAC_EXTADDR_1_LOW 0x0000053c
526 #define MAC_EXTADDR_2_HIGH 0x00000540
527 #define MAC_EXTADDR_2_LOW 0x00000544
528 #define MAC_EXTADDR_3_HIGH 0x00000548
529 #define MAC_EXTADDR_3_LOW 0x0000054c
530 #define MAC_EXTADDR_4_HIGH 0x00000550
531 #define MAC_EXTADDR_4_LOW 0x00000554
532 #define MAC_EXTADDR_5_HIGH 0x00000558
533 #define MAC_EXTADDR_5_LOW 0x0000055c
534 #define MAC_EXTADDR_6_HIGH 0x00000560
535 #define MAC_EXTADDR_6_LOW 0x00000564
536 #define MAC_EXTADDR_7_HIGH 0x00000568
537 #define MAC_EXTADDR_7_LOW 0x0000056c
538 #define MAC_EXTADDR_8_HIGH 0x00000570
539 #define MAC_EXTADDR_8_LOW 0x00000574
540 #define MAC_EXTADDR_9_HIGH 0x00000578
541 #define MAC_EXTADDR_9_LOW 0x0000057c
542 #define MAC_EXTADDR_10_HIGH 0x00000580
543 #define MAC_EXTADDR_10_LOW 0x00000584
544 #define MAC_EXTADDR_11_HIGH 0x00000588
545 #define MAC_EXTADDR_11_LOW 0x0000058c
546 #define MAC_SERDES_CFG 0x00000590
547 #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
548 #define MAC_SERDES_STAT 0x00000594
549 /* 0x598 --> 0x5a0 unused */
550 #define MAC_PHYCFG1 0x000005a0
551 #define MAC_PHYCFG1_RGMII_INT 0x00000001
552 #define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0
553 #define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000
554 #define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000
555 #define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000
556 #define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000
557 #define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000
558 #define MAC_PHYCFG1_TXC_DRV 0x20000000
559 #define MAC_PHYCFG2 0x000005a4
560 #define MAC_PHYCFG2_INBAND_ENABLE 0x00000001
561 #define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0
562 #define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0
563 #define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100
564 #define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000
565 #define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0
566 #define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00
567 #define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600
568 #define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400
569 #define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800
570 #define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000
571 #define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000
572 #define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000
573 #define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000
574 #define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000
575 #define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000
576 #define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000
577 #define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000
578 #define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000
579 #define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000
580 #define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000
581 #define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000
582 #define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000
583 #define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000
584 #define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000
585 #define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000
586 #define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000
587 #define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000
588 #define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000
589 #define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000
590 #define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000
591 #define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000
592 #define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000
593 #define MAC_PHYCFG2_ACT_MASK_50610 0x01000000
594 #define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000
595 #define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000
596 #define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000
597 #define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000
598 #define MAC_PHYCFG2_ACT_COMP_50610 0x00000000
599 #define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000
600 #define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000
601 #define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000
602 #define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000
603 #define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000
604 #define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000
605 #define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000
606 #define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000
607 #define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000
608 #define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000
609 #define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000
610 #define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000
611 #define MAC_PHYCFG2_50610_LED_MODES \
612 (MAC_PHYCFG2_EMODE_MASK_50610 | \
613 MAC_PHYCFG2_EMODE_COMP_50610 | \
614 MAC_PHYCFG2_FMODE_MASK_50610 | \
615 MAC_PHYCFG2_FMODE_COMP_50610 | \
616 MAC_PHYCFG2_GMODE_MASK_50610 | \
617 MAC_PHYCFG2_GMODE_COMP_50610 | \
618 MAC_PHYCFG2_ACT_MASK_50610 | \
619 MAC_PHYCFG2_ACT_COMP_50610 | \
620 MAC_PHYCFG2_QUAL_MASK_50610 | \
621 MAC_PHYCFG2_QUAL_COMP_50610)
622 #define MAC_PHYCFG2_AC131_LED_MODES \
623 (MAC_PHYCFG2_EMODE_MASK_AC131 | \
624 MAC_PHYCFG2_EMODE_COMP_AC131 | \
625 MAC_PHYCFG2_FMODE_MASK_AC131 | \
626 MAC_PHYCFG2_FMODE_COMP_AC131 | \
627 MAC_PHYCFG2_GMODE_MASK_AC131 | \
628 MAC_PHYCFG2_GMODE_COMP_AC131 | \
629 MAC_PHYCFG2_ACT_MASK_AC131 | \
630 MAC_PHYCFG2_ACT_COMP_AC131 | \
631 MAC_PHYCFG2_QUAL_MASK_AC131 | \
632 MAC_PHYCFG2_QUAL_COMP_AC131)
633 #define MAC_PHYCFG2_RTL8211C_LED_MODES \
634 (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
635 MAC_PHYCFG2_EMODE_COMP_RT8211 | \
636 MAC_PHYCFG2_FMODE_MASK_RT8211 | \
637 MAC_PHYCFG2_FMODE_COMP_RT8211 | \
638 MAC_PHYCFG2_GMODE_MASK_RT8211 | \
639 MAC_PHYCFG2_GMODE_COMP_RT8211 | \
640 MAC_PHYCFG2_ACT_MASK_RT8211 | \
641 MAC_PHYCFG2_ACT_COMP_RT8211 | \
642 MAC_PHYCFG2_QUAL_MASK_RT8211 | \
643 MAC_PHYCFG2_QUAL_COMP_RT8211)
644 #define MAC_PHYCFG2_RTL8201E_LED_MODES \
645 (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
646 MAC_PHYCFG2_EMODE_COMP_RT8201 | \
647 MAC_PHYCFG2_FMODE_MASK_RT8201 | \
648 MAC_PHYCFG2_FMODE_COMP_RT8201 | \
649 MAC_PHYCFG2_GMODE_MASK_RT8201 | \
650 MAC_PHYCFG2_GMODE_COMP_RT8201 | \
651 MAC_PHYCFG2_ACT_MASK_RT8201 | \
652 MAC_PHYCFG2_ACT_COMP_RT8201 | \
653 MAC_PHYCFG2_QUAL_MASK_RT8201 | \
654 MAC_PHYCFG2_QUAL_COMP_RT8201)
655 #define MAC_EXT_RGMII_MODE 0x000005a8
656 #define MAC_RGMII_MODE_TX_ENABLE 0x00000001
657 #define MAC_RGMII_MODE_TX_LOWPWR 0x00000002
658 #define MAC_RGMII_MODE_TX_RESET 0x00000004
659 #define MAC_RGMII_MODE_RX_INT_B 0x00000100
660 #define MAC_RGMII_MODE_RX_QUALITY 0x00000200
661 #define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400
662 #define MAC_RGMII_MODE_RX_ENG_DET 0x00000800
663 /* 0x5ac --> 0x5b0 unused */
664 #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
665 #define SERDES_RX_SIG_DETECT 0x00000400
666 #define SG_DIG_CTRL 0x000005b0
667 #define SG_DIG_USING_HW_AUTONEG 0x80000000
668 #define SG_DIG_SOFT_RESET 0x40000000
669 #define SG_DIG_DISABLE_LINKRDY 0x20000000
670 #define SG_DIG_CRC16_CLEAR_N 0x01000000
671 #define SG_DIG_EN10B 0x00800000
672 #define SG_DIG_CLEAR_STATUS 0x00400000
673 #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
674 #define SG_DIG_LOCAL_LINK_STATUS 0x00100000
675 #define SG_DIG_SPEED_STATUS_MASK 0x000c0000
676 #define SG_DIG_SPEED_STATUS_SHIFT 18
677 #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
678 #define SG_DIG_RESTART_AUTONEG 0x00010000
679 #define SG_DIG_FIBER_MODE 0x00008000
680 #define SG_DIG_REMOTE_FAULT_MASK 0x00006000
681 #define SG_DIG_PAUSE_MASK 0x00001800
682 #define SG_DIG_PAUSE_CAP 0x00000800
683 #define SG_DIG_ASYM_PAUSE 0x00001000
684 #define SG_DIG_GBIC_ENABLE 0x00000400
685 #define SG_DIG_CHECK_END_ENABLE 0x00000200
686 #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
687 #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
688 #define SG_DIG_GMII_INPUT_SELECT 0x00000040
689 #define SG_DIG_MRADV_CRC16_SELECT 0x00000020
690 #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
691 #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
692 #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
693 #define SG_DIG_REMOTE_LOOPBACK 0x00000002
694 #define SG_DIG_LOOPBACK 0x00000001
695 #define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
696 SG_DIG_LOCAL_DUPLEX_STATUS | \
697 SG_DIG_LOCAL_LINK_STATUS | \
698 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
699 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
700 #define SG_DIG_STATUS 0x000005b4
701 #define SG_DIG_CRC16_BUS_MASK 0xffff0000
702 #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
703 #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
704 #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
705 #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
706 #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
707 #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
708 #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
709 #define SG_DIG_IS_SERDES 0x00000100
710 #define SG_DIG_COMMA_DETECTOR 0x00000008
711 #define SG_DIG_MAC_ACK_STATUS 0x00000004
712 #define SG_DIG_AUTONEG_COMPLETE 0x00000002
713 #define SG_DIG_AUTONEG_ERROR 0x00000001
714 /* 0x5b8 --> 0x600 unused */
715 #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
716 #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
717 /* 0x624 --> 0x670 unused */
719 #define MAC_RSS_INDIR_TBL_0 0x00000630
721 #define MAC_RSS_HASH_KEY_0 0x00000670
722 #define MAC_RSS_HASH_KEY_1 0x00000674
723 #define MAC_RSS_HASH_KEY_2 0x00000678
724 #define MAC_RSS_HASH_KEY_3 0x0000067c
725 #define MAC_RSS_HASH_KEY_4 0x00000680
726 #define MAC_RSS_HASH_KEY_5 0x00000684
727 #define MAC_RSS_HASH_KEY_6 0x00000688
728 #define MAC_RSS_HASH_KEY_7 0x0000068c
729 #define MAC_RSS_HASH_KEY_8 0x00000690
730 #define MAC_RSS_HASH_KEY_9 0x00000694
731 /* 0x698 --> 0x800 unused */
733 #define MAC_TX_STATS_OCTETS 0x00000800
734 #define MAC_TX_STATS_RESV1 0x00000804
735 #define MAC_TX_STATS_COLLISIONS 0x00000808
736 #define MAC_TX_STATS_XON_SENT 0x0000080c
737 #define MAC_TX_STATS_XOFF_SENT 0x00000810
738 #define MAC_TX_STATS_RESV2 0x00000814
739 #define MAC_TX_STATS_MAC_ERRORS 0x00000818
740 #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
741 #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
742 #define MAC_TX_STATS_DEFERRED 0x00000824
743 #define MAC_TX_STATS_RESV3 0x00000828
744 #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
745 #define MAC_TX_STATS_LATE_COL 0x00000830
746 #define MAC_TX_STATS_RESV4_1 0x00000834
747 #define MAC_TX_STATS_RESV4_2 0x00000838
748 #define MAC_TX_STATS_RESV4_3 0x0000083c
749 #define MAC_TX_STATS_RESV4_4 0x00000840
750 #define MAC_TX_STATS_RESV4_5 0x00000844
751 #define MAC_TX_STATS_RESV4_6 0x00000848
752 #define MAC_TX_STATS_RESV4_7 0x0000084c
753 #define MAC_TX_STATS_RESV4_8 0x00000850
754 #define MAC_TX_STATS_RESV4_9 0x00000854
755 #define MAC_TX_STATS_RESV4_10 0x00000858
756 #define MAC_TX_STATS_RESV4_11 0x0000085c
757 #define MAC_TX_STATS_RESV4_12 0x00000860
758 #define MAC_TX_STATS_RESV4_13 0x00000864
759 #define MAC_TX_STATS_RESV4_14 0x00000868
760 #define MAC_TX_STATS_UCAST 0x0000086c
761 #define MAC_TX_STATS_MCAST 0x00000870
762 #define MAC_TX_STATS_BCAST 0x00000874
763 #define MAC_TX_STATS_RESV5_1 0x00000878
764 #define MAC_TX_STATS_RESV5_2 0x0000087c
765 #define MAC_RX_STATS_OCTETS 0x00000880
766 #define MAC_RX_STATS_RESV1 0x00000884
767 #define MAC_RX_STATS_FRAGMENTS 0x00000888
768 #define MAC_RX_STATS_UCAST 0x0000088c
769 #define MAC_RX_STATS_MCAST 0x00000890
770 #define MAC_RX_STATS_BCAST 0x00000894
771 #define MAC_RX_STATS_FCS_ERRORS 0x00000898
772 #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
773 #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
774 #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
775 #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
776 #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
777 #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
778 #define MAC_RX_STATS_JABBERS 0x000008b4
779 #define MAC_RX_STATS_UNDERSIZE 0x000008b8
780 /* 0x8bc --> 0xc00 unused */
782 /* Send data initiator control registers */
783 #define SNDDATAI_MODE 0x00000c00
784 #define SNDDATAI_MODE_RESET 0x00000001
785 #define SNDDATAI_MODE_ENABLE 0x00000002
786 #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
787 #define SNDDATAI_STATUS 0x00000c04
788 #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
789 #define SNDDATAI_STATSCTRL 0x00000c08
790 #define SNDDATAI_SCTRL_ENABLE 0x00000001
791 #define SNDDATAI_SCTRL_FASTUPD 0x00000002
792 #define SNDDATAI_SCTRL_CLEAR 0x00000004
793 #define SNDDATAI_SCTRL_FLUSH 0x00000008
794 #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
795 #define SNDDATAI_STATSENAB 0x00000c0c
796 #define SNDDATAI_STATSINCMASK 0x00000c10
797 #define ISO_PKT_TX 0x00000c20
798 /* 0xc24 --> 0xc80 unused */
799 #define SNDDATAI_COS_CNT_0 0x00000c80
800 #define SNDDATAI_COS_CNT_1 0x00000c84
801 #define SNDDATAI_COS_CNT_2 0x00000c88
802 #define SNDDATAI_COS_CNT_3 0x00000c8c
803 #define SNDDATAI_COS_CNT_4 0x00000c90
804 #define SNDDATAI_COS_CNT_5 0x00000c94
805 #define SNDDATAI_COS_CNT_6 0x00000c98
806 #define SNDDATAI_COS_CNT_7 0x00000c9c
807 #define SNDDATAI_COS_CNT_8 0x00000ca0
808 #define SNDDATAI_COS_CNT_9 0x00000ca4
809 #define SNDDATAI_COS_CNT_10 0x00000ca8
810 #define SNDDATAI_COS_CNT_11 0x00000cac
811 #define SNDDATAI_COS_CNT_12 0x00000cb0
812 #define SNDDATAI_COS_CNT_13 0x00000cb4
813 #define SNDDATAI_COS_CNT_14 0x00000cb8
814 #define SNDDATAI_COS_CNT_15 0x00000cbc
815 #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
816 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
817 #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
818 #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
819 #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
820 #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
821 #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
822 #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
823 /* 0xce0 --> 0x1000 unused */
825 /* Send data completion control registers */
826 #define SNDDATAC_MODE 0x00001000
827 #define SNDDATAC_MODE_RESET 0x00000001
828 #define SNDDATAC_MODE_ENABLE 0x00000002
829 #define SNDDATAC_MODE_CDELAY 0x00000010
830 /* 0x1004 --> 0x1400 unused */
832 /* Send BD ring selector */
833 #define SNDBDS_MODE 0x00001400
834 #define SNDBDS_MODE_RESET 0x00000001
835 #define SNDBDS_MODE_ENABLE 0x00000002
836 #define SNDBDS_MODE_ATTN_ENABLE 0x00000004
837 #define SNDBDS_STATUS 0x00001404
838 #define SNDBDS_STATUS_ERROR_ATTN 0x00000004
839 #define SNDBDS_HWDIAG 0x00001408
840 /* 0x140c --> 0x1440 */
841 #define SNDBDS_SEL_CON_IDX_0 0x00001440
842 #define SNDBDS_SEL_CON_IDX_1 0x00001444
843 #define SNDBDS_SEL_CON_IDX_2 0x00001448
844 #define SNDBDS_SEL_CON_IDX_3 0x0000144c
845 #define SNDBDS_SEL_CON_IDX_4 0x00001450
846 #define SNDBDS_SEL_CON_IDX_5 0x00001454
847 #define SNDBDS_SEL_CON_IDX_6 0x00001458
848 #define SNDBDS_SEL_CON_IDX_7 0x0000145c
849 #define SNDBDS_SEL_CON_IDX_8 0x00001460
850 #define SNDBDS_SEL_CON_IDX_9 0x00001464
851 #define SNDBDS_SEL_CON_IDX_10 0x00001468
852 #define SNDBDS_SEL_CON_IDX_11 0x0000146c
853 #define SNDBDS_SEL_CON_IDX_12 0x00001470
854 #define SNDBDS_SEL_CON_IDX_13 0x00001474
855 #define SNDBDS_SEL_CON_IDX_14 0x00001478
856 #define SNDBDS_SEL_CON_IDX_15 0x0000147c
857 /* 0x1480 --> 0x1800 unused */
859 /* Send BD initiator control registers */
860 #define SNDBDI_MODE 0x00001800
861 #define SNDBDI_MODE_RESET 0x00000001
862 #define SNDBDI_MODE_ENABLE 0x00000002
863 #define SNDBDI_MODE_ATTN_ENABLE 0x00000004
864 #define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020
865 #define SNDBDI_STATUS 0x00001804
866 #define SNDBDI_STATUS_ERROR_ATTN 0x00000004
867 #define SNDBDI_IN_PROD_IDX_0 0x00001808
868 #define SNDBDI_IN_PROD_IDX_1 0x0000180c
869 #define SNDBDI_IN_PROD_IDX_2 0x00001810
870 #define SNDBDI_IN_PROD_IDX_3 0x00001814
871 #define SNDBDI_IN_PROD_IDX_4 0x00001818
872 #define SNDBDI_IN_PROD_IDX_5 0x0000181c
873 #define SNDBDI_IN_PROD_IDX_6 0x00001820
874 #define SNDBDI_IN_PROD_IDX_7 0x00001824
875 #define SNDBDI_IN_PROD_IDX_8 0x00001828
876 #define SNDBDI_IN_PROD_IDX_9 0x0000182c
877 #define SNDBDI_IN_PROD_IDX_10 0x00001830
878 #define SNDBDI_IN_PROD_IDX_11 0x00001834
879 #define SNDBDI_IN_PROD_IDX_12 0x00001838
880 #define SNDBDI_IN_PROD_IDX_13 0x0000183c
881 #define SNDBDI_IN_PROD_IDX_14 0x00001840
882 #define SNDBDI_IN_PROD_IDX_15 0x00001844
883 /* 0x1848 --> 0x1c00 unused */
885 /* Send BD completion control registers */
886 #define SNDBDC_MODE 0x00001c00
887 #define SNDBDC_MODE_RESET 0x00000001
888 #define SNDBDC_MODE_ENABLE 0x00000002
889 #define SNDBDC_MODE_ATTN_ENABLE 0x00000004
890 /* 0x1c04 --> 0x2000 unused */
892 /* Receive list placement control registers */
893 #define RCVLPC_MODE 0x00002000
894 #define RCVLPC_MODE_RESET 0x00000001
895 #define RCVLPC_MODE_ENABLE 0x00000002
896 #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
897 #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
898 #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
899 #define RCVLPC_STATUS 0x00002004
900 #define RCVLPC_STATUS_CLASS0 0x00000004
901 #define RCVLPC_STATUS_MAPOOR 0x00000008
902 #define RCVLPC_STATUS_STAT_OFLOW 0x00000010
903 #define RCVLPC_LOCK 0x00002008
904 #define RCVLPC_LOCK_REQ_MASK 0x0000ffff
905 #define RCVLPC_LOCK_REQ_SHIFT 0
906 #define RCVLPC_LOCK_GRANT_MASK 0xffff0000
907 #define RCVLPC_LOCK_GRANT_SHIFT 16
908 #define RCVLPC_NON_EMPTY_BITS 0x0000200c
909 #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
910 #define RCVLPC_CONFIG 0x00002010
911 #define RCVLPC_STATSCTRL 0x00002014
912 #define RCVLPC_STATSCTRL_ENABLE 0x00000001
913 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002
914 #define RCVLPC_STATS_ENABLE 0x00002018
915 #define RCVLPC_STATSENAB_ASF_FIX 0x00000002
916 #define RCVLPC_STATSENAB_DACK_FIX 0x00040000
917 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
918 #define RCVLPC_STATS_INCMASK 0x0000201c
919 /* 0x2020 --> 0x2100 unused */
920 #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
921 #define SELLST_TAIL 0x00000004
922 #define SELLST_CONT 0x00000008
923 #define SELLST_UNUSED 0x0000000c
924 #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
925 #define RCVLPC_DROP_FILTER_CNT 0x00002240
926 #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
927 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
928 #define RCVLPC_NO_RCV_BD_CNT 0x0000224c
929 #define RCVLPC_IN_DISCARDS_CNT 0x00002250
930 #define RCVLPC_IN_ERRORS_CNT 0x00002254
931 #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
932 /* 0x225c --> 0x2400 unused */
934 /* Receive Data and Receive BD Initiator Control */
935 #define RCVDBDI_MODE 0x00002400
936 #define RCVDBDI_MODE_RESET 0x00000001
937 #define RCVDBDI_MODE_ENABLE 0x00000002
938 #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
939 #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
940 #define RCVDBDI_MODE_INV_RING_SZ 0x00000010
941 #define RCVDBDI_STATUS 0x00002404
942 #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
943 #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
944 #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
945 #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
946 /* 0x240c --> 0x2440 unused */
947 #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
948 #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
949 #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
950 #define RCVDBDI_JUMBO_CON_IDX 0x00002470
951 #define RCVDBDI_STD_CON_IDX 0x00002474
952 #define RCVDBDI_MINI_CON_IDX 0x00002478
953 /* 0x247c --> 0x2480 unused */
954 #define RCVDBDI_BD_PROD_IDX_0 0x00002480
955 #define RCVDBDI_BD_PROD_IDX_1 0x00002484
956 #define RCVDBDI_BD_PROD_IDX_2 0x00002488
957 #define RCVDBDI_BD_PROD_IDX_3 0x0000248c
958 #define RCVDBDI_BD_PROD_IDX_4 0x00002490
959 #define RCVDBDI_BD_PROD_IDX_5 0x00002494
960 #define RCVDBDI_BD_PROD_IDX_6 0x00002498
961 #define RCVDBDI_BD_PROD_IDX_7 0x0000249c
962 #define RCVDBDI_BD_PROD_IDX_8 0x000024a0
963 #define RCVDBDI_BD_PROD_IDX_9 0x000024a4
964 #define RCVDBDI_BD_PROD_IDX_10 0x000024a8
965 #define RCVDBDI_BD_PROD_IDX_11 0x000024ac
966 #define RCVDBDI_BD_PROD_IDX_12 0x000024b0
967 #define RCVDBDI_BD_PROD_IDX_13 0x000024b4
968 #define RCVDBDI_BD_PROD_IDX_14 0x000024b8
969 #define RCVDBDI_BD_PROD_IDX_15 0x000024bc
970 #define RCVDBDI_HWDIAG 0x000024c0
971 /* 0x24c4 --> 0x2800 unused */
973 /* Receive Data Completion Control */
974 #define RCVDCC_MODE 0x00002800
975 #define RCVDCC_MODE_RESET 0x00000001
976 #define RCVDCC_MODE_ENABLE 0x00000002
977 #define RCVDCC_MODE_ATTN_ENABLE 0x00000004
978 /* 0x2804 --> 0x2c00 unused */
980 /* Receive BD Initiator Control Registers */
981 #define RCVBDI_MODE 0x00002c00
982 #define RCVBDI_MODE_RESET 0x00000001
983 #define RCVBDI_MODE_ENABLE 0x00000002
984 #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
985 #define RCVBDI_STATUS 0x00002c04
986 #define RCVBDI_STATUS_RCB_ATTN 0x00000004
987 #define RCVBDI_JUMBO_PROD_IDX 0x00002c08
988 #define RCVBDI_STD_PROD_IDX 0x00002c0c
989 #define RCVBDI_MINI_PROD_IDX 0x00002c10
990 #define RCVBDI_MINI_THRESH 0x00002c14
991 #define RCVBDI_STD_THRESH 0x00002c18
992 #define RCVBDI_JUMBO_THRESH 0x00002c1c
993 /* 0x2c20 --> 0x2d00 unused */
995 #define STD_REPLENISH_LWM 0x00002d00
996 #define JMB_REPLENISH_LWM 0x00002d04
997 /* 0x2d08 --> 0x3000 unused */
999 /* Receive BD Completion Control Registers */
1000 #define RCVCC_MODE 0x00003000
1001 #define RCVCC_MODE_RESET 0x00000001
1002 #define RCVCC_MODE_ENABLE 0x00000002
1003 #define RCVCC_MODE_ATTN_ENABLE 0x00000004
1004 #define RCVCC_STATUS 0x00003004
1005 #define RCVCC_STATUS_ERROR_ATTN 0x00000004
1006 #define RCVCC_JUMP_PROD_IDX 0x00003008
1007 #define RCVCC_STD_PROD_IDX 0x0000300c
1008 #define RCVCC_MINI_PROD_IDX 0x00003010
1009 /* 0x3014 --> 0x3400 unused */
1011 /* Receive list selector control registers */
1012 #define RCVLSC_MODE 0x00003400
1013 #define RCVLSC_MODE_RESET 0x00000001
1014 #define RCVLSC_MODE_ENABLE 0x00000002
1015 #define RCVLSC_MODE_ATTN_ENABLE 0x00000004
1016 #define RCVLSC_STATUS 0x00003404
1017 #define RCVLSC_STATUS_ERROR_ATTN 0x00000004
1018 /* 0x3408 --> 0x3600 unused */
1020 /* CPMU registers */
1021 #define TG3_CPMU_CTRL 0x00003600
1022 #define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
1023 #define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
1024 #define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
1025 #define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
1026 #define TG3_CPMU_LSPD_10MB_CLK 0x00003604
1027 #define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000
1028 #define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
1029 /* 0x3608 --> 0x360c unused */
1031 #define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c
1032 #define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
1033 #define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
1034 #define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000
1035 #define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610
1036 #define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000
1037 #define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
1038 /* 0x3614 --> 0x361c unused */
1040 #define TG3_CPMU_HST_ACC 0x0000361c
1041 #define CPMU_HST_ACC_MACCLK_MASK 0x001f0000
1042 #define CPMU_HST_ACC_MACCLK_6_25 0x00130000
1043 /* 0x3620 --> 0x362c unused */
1045 #define TG3_CPMU_STATUS 0x0000362c
1046 #define TG3_CPMU_STATUS_PCIE_FUNC 0x20000000
1047 #define TG3_CPMU_CLCK_STAT 0x00003630
1048 #define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
1049 #define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
1050 #define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
1051 #define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
1052 /* 0x3634 --> 0x365c unused */
1054 #define TG3_CPMU_MUTEX_REQ 0x0000365c
1055 #define CPMU_MUTEX_REQ_DRIVER 0x00001000
1056 #define TG3_CPMU_MUTEX_GNT 0x00003660
1057 #define CPMU_MUTEX_GNT_DRIVER 0x00001000
1058 #define TG3_CPMU_PHY_STRAP 0x00003664
1059 #define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020
1060 /* 0x3664 --> 0x3800 unused */
1062 /* Mbuf cluster free registers */
1063 #define MBFREE_MODE 0x00003800
1064 #define MBFREE_MODE_RESET 0x00000001
1065 #define MBFREE_MODE_ENABLE 0x00000002
1066 #define MBFREE_STATUS 0x00003804
1067 /* 0x3808 --> 0x3c00 unused */
1069 /* Host coalescing control registers */
1070 #define HOSTCC_MODE 0x00003c00
1071 #define HOSTCC_MODE_RESET 0x00000001
1072 #define HOSTCC_MODE_ENABLE 0x00000002
1073 #define HOSTCC_MODE_ATTN 0x00000004
1074 #define HOSTCC_MODE_NOW 0x00000008
1075 #define HOSTCC_MODE_FULL_STATUS 0x00000000
1076 #define HOSTCC_MODE_64BYTE 0x00000080
1077 #define HOSTCC_MODE_32BYTE 0x00000100
1078 #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
1079 #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
1080 #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
1081 #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
1082 #define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000
1083 #define HOSTCC_STATUS 0x00003c04
1084 #define HOSTCC_STATUS_ERROR_ATTN 0x00000004
1085 #define HOSTCC_RXCOL_TICKS 0x00003c08
1086 #define LOW_RXCOL_TICKS 0x00000032
1087 #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
1088 #define DEFAULT_RXCOL_TICKS 0x00000048
1089 #define HIGH_RXCOL_TICKS 0x00000096
1090 #define MAX_RXCOL_TICKS 0x000003ff
1091 #define HOSTCC_TXCOL_TICKS 0x00003c0c
1092 #define LOW_TXCOL_TICKS 0x00000096
1093 #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
1094 #define DEFAULT_TXCOL_TICKS 0x0000012c
1095 #define HIGH_TXCOL_TICKS 0x00000145
1096 #define MAX_TXCOL_TICKS 0x000003ff
1097 #define HOSTCC_RXMAX_FRAMES 0x00003c10
1098 #define LOW_RXMAX_FRAMES 0x00000005
1099 #define DEFAULT_RXMAX_FRAMES 0x00000008
1100 #define HIGH_RXMAX_FRAMES 0x00000012
1101 #define MAX_RXMAX_FRAMES 0x000000ff
1102 #define HOSTCC_TXMAX_FRAMES 0x00003c14
1103 #define LOW_TXMAX_FRAMES 0x00000035
1104 #define DEFAULT_TXMAX_FRAMES 0x0000004b
1105 #define HIGH_TXMAX_FRAMES 0x00000052
1106 #define MAX_TXMAX_FRAMES 0x000000ff
1107 #define HOSTCC_RXCOAL_TICK_INT 0x00003c18
1108 #define DEFAULT_RXCOAL_TICK_INT 0x00000019
1109 #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
1110 #define MAX_RXCOAL_TICK_INT 0x000003ff
1111 #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
1112 #define DEFAULT_TXCOAL_TICK_INT 0x00000019
1113 #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
1114 #define MAX_TXCOAL_TICK_INT 0x000003ff
1115 #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
1116 #define DEFAULT_RXCOAL_MAXF_INT 0x00000005
1117 #define MAX_RXCOAL_MAXF_INT 0x000000ff
1118 #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
1119 #define DEFAULT_TXCOAL_MAXF_INT 0x00000005
1120 #define MAX_TXCOAL_MAXF_INT 0x000000ff
1121 #define HOSTCC_STAT_COAL_TICKS 0x00003c28
1122 #define DEFAULT_STAT_COAL_TICKS 0x000f4240
1123 #define MAX_STAT_COAL_TICKS 0xd693d400
1124 #define MIN_STAT_COAL_TICKS 0x00000064
1125 /* 0x3c2c --> 0x3c30 unused */
1126 #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
1127 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
1128 #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
1129 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
1130 #define HOSTCC_FLOW_ATTN 0x00003c48
1131 /* 0x3c4c --> 0x3c50 unused */
1132 #define HOSTCC_JUMBO_CON_IDX 0x00003c50
1133 #define HOSTCC_STD_CON_IDX 0x00003c54
1134 #define HOSTCC_MINI_CON_IDX 0x00003c58
1135 /* 0x3c5c --> 0x3c80 unused */
1136 #define HOSTCC_RET_PROD_IDX_0 0x00003c80
1137 #define HOSTCC_RET_PROD_IDX_1 0x00003c84
1138 #define HOSTCC_RET_PROD_IDX_2 0x00003c88
1139 #define HOSTCC_RET_PROD_IDX_3 0x00003c8c
1140 #define HOSTCC_RET_PROD_IDX_4 0x00003c90
1141 #define HOSTCC_RET_PROD_IDX_5 0x00003c94
1142 #define HOSTCC_RET_PROD_IDX_6 0x00003c98
1143 #define HOSTCC_RET_PROD_IDX_7 0x00003c9c
1144 #define HOSTCC_RET_PROD_IDX_8 0x00003ca0
1145 #define HOSTCC_RET_PROD_IDX_9 0x00003ca4
1146 #define HOSTCC_RET_PROD_IDX_10 0x00003ca8
1147 #define HOSTCC_RET_PROD_IDX_11 0x00003cac
1148 #define HOSTCC_RET_PROD_IDX_12 0x00003cb0
1149 #define HOSTCC_RET_PROD_IDX_13 0x00003cb4
1150 #define HOSTCC_RET_PROD_IDX_14 0x00003cb8
1151 #define HOSTCC_RET_PROD_IDX_15 0x00003cbc
1152 #define HOSTCC_SND_CON_IDX_0 0x00003cc0
1153 #define HOSTCC_SND_CON_IDX_1 0x00003cc4
1154 #define HOSTCC_SND_CON_IDX_2 0x00003cc8
1155 #define HOSTCC_SND_CON_IDX_3 0x00003ccc
1156 #define HOSTCC_SND_CON_IDX_4 0x00003cd0
1157 #define HOSTCC_SND_CON_IDX_5 0x00003cd4
1158 #define HOSTCC_SND_CON_IDX_6 0x00003cd8
1159 #define HOSTCC_SND_CON_IDX_7 0x00003cdc
1160 #define HOSTCC_SND_CON_IDX_8 0x00003ce0
1161 #define HOSTCC_SND_CON_IDX_9 0x00003ce4
1162 #define HOSTCC_SND_CON_IDX_10 0x00003ce8
1163 #define HOSTCC_SND_CON_IDX_11 0x00003cec
1164 #define HOSTCC_SND_CON_IDX_12 0x00003cf0
1165 #define HOSTCC_SND_CON_IDX_13 0x00003cf4
1166 #define HOSTCC_SND_CON_IDX_14 0x00003cf8
1167 #define HOSTCC_SND_CON_IDX_15 0x00003cfc
1168 #define HOSTCC_STATBLCK_RING1 0x00003d00
1169 /* 0x3d00 --> 0x3d80 unused */
1171 #define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80
1172 #define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84
1173 #define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88
1174 #define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c
1175 #define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90
1176 #define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94
1177 /* 0x3d98 --> 0x4000 unused */
1179 /* Memory arbiter control registers */
1180 #define MEMARB_MODE 0x00004000
1181 #define MEMARB_MODE_RESET 0x00000001
1182 #define MEMARB_MODE_ENABLE 0x00000002
1183 #define MEMARB_STATUS 0x00004004
1184 #define MEMARB_TRAP_ADDR_LOW 0x00004008
1185 #define MEMARB_TRAP_ADDR_HIGH 0x0000400c
1186 /* 0x4010 --> 0x4400 unused */
1188 /* Buffer manager control registers */
1189 #define BUFMGR_MODE 0x00004400
1190 #define BUFMGR_MODE_RESET 0x00000001
1191 #define BUFMGR_MODE_ENABLE 0x00000002
1192 #define BUFMGR_MODE_ATTN_ENABLE 0x00000004
1193 #define BUFMGR_MODE_BM_TEST 0x00000008
1194 #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
1195 #define BUFMGR_STATUS 0x00004404
1196 #define BUFMGR_STATUS_ERROR 0x00000004
1197 #define BUFMGR_STATUS_MBLOW 0x00000010
1198 #define BUFMGR_MB_POOL_ADDR 0x00004408
1199 #define BUFMGR_MB_POOL_SIZE 0x0000440c
1200 #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
1201 #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
1202 #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
1203 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
1204 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
1205 #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
1206 #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
1207 #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
1208 #define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004
1209 #define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a
1210 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1211 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
1212 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e
1213 #define BUFMGR_MB_HIGH_WATER 0x00004418
1214 #define DEFAULT_MB_HIGH_WATER 0x00000060
1215 #define DEFAULT_MB_HIGH_WATER_5705 0x00000060
1216 #define DEFAULT_MB_HIGH_WATER_5906 0x00000010
1217 #define DEFAULT_MB_HIGH_WATER_57765 0x000000a0
1218 #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
1219 #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1220 #define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea
1221 #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
1222 #define BUFMGR_MB_ALLOC_BIT 0x10000000
1223 #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
1224 #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
1225 #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
1226 #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
1227 #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
1228 #define BUFMGR_DMA_LOW_WATER 0x00004434
1229 #define DEFAULT_DMA_LOW_WATER 0x00000005
1230 #define BUFMGR_DMA_HIGH_WATER 0x00004438
1231 #define DEFAULT_DMA_HIGH_WATER 0x0000000a
1232 #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
1233 #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
1234 #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
1235 #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1236 #define BUFMGR_HWDIAG_0 0x0000444c
1237 #define BUFMGR_HWDIAG_1 0x00004450
1238 #define BUFMGR_HWDIAG_2 0x00004454
1239 /* 0x4458 --> 0x4800 unused */
1241 /* Read DMA control registers */
1242 #define RDMAC_MODE 0x00004800
1243 #define RDMAC_MODE_RESET 0x00000001
1244 #define RDMAC_MODE_ENABLE 0x00000002
1245 #define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1246 #define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1247 #define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1248 #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1249 #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1250 #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1251 #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1252 #define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1253 #define RDMAC_MODE_SPLIT_ENABLE 0x00000800
1254 #define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800
1255 #define RDMAC_MODE_SPLIT_RESET 0x00001000
1256 #define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000
1257 #define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000
1258 #define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1259 #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
1260 #define RDMAC_MODE_IPV4_LSO_EN 0x08000000
1261 #define RDMAC_MODE_IPV6_LSO_EN 0x10000000
1262 #define RDMAC_STATUS 0x00004804
1263 #define RDMAC_STATUS_TGTABORT 0x00000004
1264 #define RDMAC_STATUS_MSTABORT 0x00000008
1265 #define RDMAC_STATUS_PARITYERR 0x00000010
1266 #define RDMAC_STATUS_ADDROFLOW 0x00000020
1267 #define RDMAC_STATUS_FIFOOFLOW 0x00000040
1268 #define RDMAC_STATUS_FIFOURUN 0x00000080
1269 #define RDMAC_STATUS_FIFOOREAD 0x00000100
1270 #define RDMAC_STATUS_LNGREAD 0x00000200
1271 /* 0x4808 --> 0x4c00 unused */
1273 /* Write DMA control registers */
1274 #define WDMAC_MODE 0x00004c00
1275 #define WDMAC_MODE_RESET 0x00000001
1276 #define WDMAC_MODE_ENABLE 0x00000002
1277 #define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1278 #define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1279 #define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1280 #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1281 #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1282 #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1283 #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1284 #define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1285 #define WDMAC_MODE_RX_ACCEL 0x00000400
1286 #define WDMAC_MODE_STATUS_TAG_FIX 0x20000000
1287 #define WDMAC_MODE_BURST_ALL_DATA 0xc0000000
1288 #define WDMAC_STATUS 0x00004c04
1289 #define WDMAC_STATUS_TGTABORT 0x00000004
1290 #define WDMAC_STATUS_MSTABORT 0x00000008
1291 #define WDMAC_STATUS_PARITYERR 0x00000010
1292 #define WDMAC_STATUS_ADDROFLOW 0x00000020
1293 #define WDMAC_STATUS_FIFOOFLOW 0x00000040
1294 #define WDMAC_STATUS_FIFOURUN 0x00000080
1295 #define WDMAC_STATUS_FIFOOREAD 0x00000100
1296 #define WDMAC_STATUS_LNGREAD 0x00000200
1297 /* 0x4c08 --> 0x5000 unused */
1299 /* Per-cpu register offsets (arm9) */
1300 #define CPU_MODE 0x00000000
1301 #define CPU_MODE_RESET 0x00000001
1302 #define CPU_MODE_HALT 0x00000400
1303 #define CPU_STATE 0x00000004
1304 #define CPU_EVTMASK 0x00000008
1305 /* 0xc --> 0x1c reserved */
1306 #define CPU_PC 0x0000001c
1307 #define CPU_INSN 0x00000020
1308 #define CPU_SPAD_UFLOW 0x00000024
1309 #define CPU_WDOG_CLEAR 0x00000028
1310 #define CPU_WDOG_VECTOR 0x0000002c
1311 #define CPU_WDOG_PC 0x00000030
1312 #define CPU_HW_BP 0x00000034
1313 /* 0x38 --> 0x44 unused */
1314 #define CPU_WDOG_SAVED_STATE 0x00000044
1315 #define CPU_LAST_BRANCH_ADDR 0x00000048
1316 #define CPU_SPAD_UFLOW_SET 0x0000004c
1317 /* 0x50 --> 0x200 unused */
1318 #define CPU_R0 0x00000200
1319 #define CPU_R1 0x00000204
1320 #define CPU_R2 0x00000208
1321 #define CPU_R3 0x0000020c
1322 #define CPU_R4 0x00000210
1323 #define CPU_R5 0x00000214
1324 #define CPU_R6 0x00000218
1325 #define CPU_R7 0x0000021c
1326 #define CPU_R8 0x00000220
1327 #define CPU_R9 0x00000224
1328 #define CPU_R10 0x00000228
1329 #define CPU_R11 0x0000022c
1330 #define CPU_R12 0x00000230
1331 #define CPU_R13 0x00000234
1332 #define CPU_R14 0x00000238
1333 #define CPU_R15 0x0000023c
1334 #define CPU_R16 0x00000240
1335 #define CPU_R17 0x00000244
1336 #define CPU_R18 0x00000248
1337 #define CPU_R19 0x0000024c
1338 #define CPU_R20 0x00000250
1339 #define CPU_R21 0x00000254
1340 #define CPU_R22 0x00000258
1341 #define CPU_R23 0x0000025c
1342 #define CPU_R24 0x00000260
1343 #define CPU_R25 0x00000264
1344 #define CPU_R26 0x00000268
1345 #define CPU_R27 0x0000026c
1346 #define CPU_R28 0x00000270
1347 #define CPU_R29 0x00000274
1348 #define CPU_R30 0x00000278
1349 #define CPU_R31 0x0000027c
1350 /* 0x280 --> 0x400 unused */
1352 #define RX_CPU_BASE 0x00005000
1353 #define RX_CPU_MODE 0x00005000
1354 #define RX_CPU_STATE 0x00005004
1355 #define RX_CPU_PGMCTR 0x0000501c
1356 #define RX_CPU_HWBKPT 0x00005034
1357 #define TX_CPU_BASE 0x00005400
1358 #define TX_CPU_MODE 0x00005400
1359 #define TX_CPU_STATE 0x00005404
1360 #define TX_CPU_PGMCTR 0x0000541c
1362 #define VCPU_STATUS 0x00005100
1363 #define VCPU_STATUS_INIT_DONE 0x04000000
1364 #define VCPU_STATUS_DRV_RESET 0x08000000
1366 #define VCPU_CFGSHDW 0x00005104
1367 #define VCPU_CFGSHDW_WOL_ENABLE 0x00000001
1368 #define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004
1369 #define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
1372 #define GRCMBOX_BASE 0x00005600
1373 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1374 #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1375 #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1376 #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1377 #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1378 #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1379 #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1380 #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1381 #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1382 #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1383 #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1384 #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1385 #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1386 #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1387 #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1388 #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1389 #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1390 #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1391 #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1392 #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1393 #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1394 #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1395 #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1396 #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1397 #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1398 #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1399 #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1400 #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1401 #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1402 #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1403 #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1404 #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1405 #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1406 #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1407 #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1408 #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1409 #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1410 #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1411 #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1412 #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1413 #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1414 #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1415 #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1416 #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1417 #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1418 #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1419 #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1420 #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1421 #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1422 #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1423 #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1424 #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1425 #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1426 #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1427 #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1428 #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1429 #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1430 #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1431 #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1432 #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1433 #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1434 #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1435 #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1436 #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1437 #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1438 #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1439 #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1440 #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1441 /* 0x5a10 --> 0x5c00 */
1443 /* Flow Through queues */
1444 #define FTQ_RESET 0x00005c00
1445 /* 0x5c04 --> 0x5c10 unused */
1446 #define FTQ_DMA_NORM_READ_CTL 0x00005c10
1447 #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1448 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1449 #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1450 #define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1451 #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1452 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1453 #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1454 #define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1455 #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1456 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1457 #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1458 #define FTQ_SEND_BD_COMP_CTL 0x00005c40
1459 #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1460 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1461 #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1462 #define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1463 #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1464 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1465 #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1466 #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1467 #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1468 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1469 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1470 #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1471 #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1472 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1473 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1474 #define FTQ_SWTYPE1_CTL 0x00005c80
1475 #define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1476 #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1477 #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1478 #define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1479 #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1480 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1481 #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1482 #define FTQ_HOST_COAL_CTL 0x00005ca0
1483 #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1484 #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1485 #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1486 #define FTQ_MAC_TX_CTL 0x00005cb0
1487 #define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1488 #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1489 #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1490 #define FTQ_MB_FREE_CTL 0x00005cc0
1491 #define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1492 #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1493 #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1494 #define FTQ_RCVBD_COMP_CTL 0x00005cd0
1495 #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1496 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1497 #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1498 #define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1499 #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1500 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1501 #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1502 #define FTQ_RCVDATA_INI_CTL 0x00005cf0
1503 #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1504 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1505 #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1506 #define FTQ_RCVDATA_COMP_CTL 0x00005d00
1507 #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1508 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1509 #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1510 #define FTQ_SWTYPE2_CTL 0x00005d10
1511 #define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1512 #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1513 #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1514 /* 0x5d20 --> 0x6000 unused */
1516 /* Message signaled interrupt registers */
1517 #define MSGINT_MODE 0x00006000
1518 #define MSGINT_MODE_RESET 0x00000001
1519 #define MSGINT_MODE_ENABLE 0x00000002
1520 #define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020
1521 #define MSGINT_MODE_MULTIVEC_EN 0x00000080
1522 #define MSGINT_STATUS 0x00006004
1523 #define MSGINT_FIFO 0x00006008
1524 /* 0x600c --> 0x6400 unused */
1526 /* DMA completion registers */
1527 #define DMAC_MODE 0x00006400
1528 #define DMAC_MODE_RESET 0x00000001
1529 #define DMAC_MODE_ENABLE 0x00000002
1530 /* 0x6404 --> 0x6800 unused */
1533 #define GRC_MODE 0x00006800
1534 #define GRC_MODE_UPD_ON_COAL 0x00000001
1535 #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1536 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1537 #define GRC_MODE_BSWAP_DATA 0x00000010
1538 #define GRC_MODE_WSWAP_DATA 0x00000020
1539 #define GRC_MODE_SPLITHDR 0x00000100
1540 #define GRC_MODE_NOFRM_CRACKING 0x00000200
1541 #define GRC_MODE_INCL_CRC 0x00000400
1542 #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1543 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1544 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1545 #define GRC_MODE_FORCE_PCI32BIT 0x00008000
1546 #define GRC_MODE_HOST_STACKUP 0x00010000
1547 #define GRC_MODE_HOST_SENDBDS 0x00020000
1548 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1549 #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
1550 #define GRC_MODE_PCIE_TL_SEL 0x00000000
1551 #define GRC_MODE_PCIE_PL_SEL 0x00400000
1552 #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1553 #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1554 #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1555 #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1556 #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1557 #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1558 #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1559 #define GRC_MODE_PCIE_DL_SEL 0x20000000
1560 #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1561 #define GRC_MODE_PCIE_HI_1K_EN 0x80000000
1562 #define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \
1563 GRC_MODE_PCIE_PL_SEL | \
1564 GRC_MODE_PCIE_DL_SEL | \
1565 GRC_MODE_PCIE_HI_1K_EN)
1566 #define GRC_MISC_CFG 0x00006804
1567 #define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1568 #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1569 #define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1570 #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1571 #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1572 #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1573 #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1574 #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1575 #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1576 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1577 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1578 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1579 #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1580 #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1581 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1582 #define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
1583 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1584 #define GRC_LOCAL_CTRL 0x00006808
1585 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1586 #define GRC_LCLCTRL_CLEARINT 0x00000002
1587 #define GRC_LCLCTRL_SETINT 0x00000004
1588 #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1589 #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
1590 #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
1591 #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
1592 #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1593 #define GRC_LCLCTRL_GPIO_OE3 0x00000040
1594 #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
1595 #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1596 #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1597 #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1598 #define GRC_LCLCTRL_GPIO_OE0 0x00000800
1599 #define GRC_LCLCTRL_GPIO_OE1 0x00001000
1600 #define GRC_LCLCTRL_GPIO_OE2 0x00002000
1601 #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1602 #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1603 #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1604 #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1605 #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1606 #define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1607 #define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1608 #define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1609 #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1610 #define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1611 #define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1612 #define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1613 #define GRC_LCLCTRL_BANK_SELECT 0x00200000
1614 #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1615 #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1616 #define GRC_TIMER 0x0000680c
1617 #define GRC_RX_CPU_EVENT 0x00006810
1618 #define GRC_RX_CPU_DRIVER_EVENT 0x00004000
1619 #define GRC_RX_TIMER_REF 0x00006814
1620 #define GRC_RX_CPU_SEM 0x00006818
1621 #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1622 #define GRC_TX_CPU_EVENT 0x00006820
1623 #define GRC_TX_TIMER_REF 0x00006824
1624 #define GRC_TX_CPU_SEM 0x00006828
1625 #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1626 #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1627 #define GRC_EEPROM_ADDR 0x00006838
1628 #define EEPROM_ADDR_WRITE 0x00000000
1629 #define EEPROM_ADDR_READ 0x80000000
1630 #define EEPROM_ADDR_COMPLETE 0x40000000
1631 #define EEPROM_ADDR_FSM_RESET 0x20000000
1632 #define EEPROM_ADDR_DEVID_MASK 0x1c000000
1633 #define EEPROM_ADDR_DEVID_SHIFT 26
1634 #define EEPROM_ADDR_START 0x02000000
1635 #define EEPROM_ADDR_CLKPERD_SHIFT 16
1636 #define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1637 #define EEPROM_ADDR_ADDR_SHIFT 0
1638 #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1639 #define EEPROM_CHIP_SIZE (64 * 1024)
1640 #define GRC_EEPROM_DATA 0x0000683c
1641 #define GRC_EEPROM_CTRL 0x00006840
1642 #define GRC_MDI_CTRL 0x00006844
1643 #define GRC_SEEPROM_DELAY 0x00006848
1644 /* 0x684c --> 0x6890 unused */
1645 #define GRC_VCPU_EXT_CTRL 0x00006890
1646 #define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1647 #define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1648 #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
1650 /* 0x6c00 --> 0x7000 unused */
1652 /* NVRAM Control registers */
1653 #define NVRAM_CMD 0x00007000
1654 #define NVRAM_CMD_RESET 0x00000001
1655 #define NVRAM_CMD_DONE 0x00000008
1656 #define NVRAM_CMD_GO 0x00000010
1657 #define NVRAM_CMD_WR 0x00000020
1658 #define NVRAM_CMD_RD 0x00000000
1659 #define NVRAM_CMD_ERASE 0x00000040
1660 #define NVRAM_CMD_FIRST 0x00000080
1661 #define NVRAM_CMD_LAST 0x00000100
1662 #define NVRAM_CMD_WREN 0x00010000
1663 #define NVRAM_CMD_WRDI 0x00020000
1664 #define NVRAM_STAT 0x00007004
1665 #define NVRAM_WRDATA 0x00007008
1666 #define NVRAM_ADDR 0x0000700c
1667 #define NVRAM_ADDR_MSK 0x00ffffff
1668 #define NVRAM_RDDATA 0x00007010
1669 #define NVRAM_CFG1 0x00007014
1670 #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1671 #define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1672 #define NVRAM_CFG1_PASS_THRU 0x00000004
1673 #define NVRAM_CFG1_STATUS_BITS 0x00000070
1674 #define NVRAM_CFG1_BIT_BANG 0x00000008
1675 #define NVRAM_CFG1_FLASH_SIZE 0x02000000
1676 #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1677 #define NVRAM_CFG1_VENDOR_MASK 0x03000003
1678 #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
1679 #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1680 #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
1681 #define FLASH_VENDOR_ST 0x03000001
1682 #define FLASH_VENDOR_SAIFUN 0x01000003
1683 #define FLASH_VENDOR_SST_SMALL 0x00000001
1684 #define FLASH_VENDOR_SST_LARGE 0x02000001
1685 #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
1686 #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
1687 #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
1688 #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1689 #define FLASH_5752VENDOR_ST_M45PE10 0x02400000
1690 #define FLASH_5752VENDOR_ST_M45PE20 0x02400002
1691 #define FLASH_5752VENDOR_ST_M45PE40 0x02400001
1692 #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
1693 #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
1694 #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
1695 #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
1696 #define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003
1697 #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
1698 #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
1699 #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
1700 #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1701 #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1702 #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
1703 #define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003
1704 #define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000
1705 #define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002
1706 #define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001
1707 #define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003
1708 #define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000
1709 #define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002
1710 #define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001
1711 #define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001
1712 #define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000
1713 #define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002
1714 #define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003
1715 #define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001
1716 #define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1717 #define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1718 #define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
1719 #define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
1720 #define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
1721 #define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
1722 #define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
1723 #define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
1724 #define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
1725 #define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001
1726 #define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003
1727 #define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001
1728 #define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003
1729 #define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000
1730 #define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002
1731 #define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001
1732 #define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003
1733 #define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000
1734 #define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002
1735 #define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001
1736 #define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003
1737 #define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000
1738 #define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002
1739 #define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001
1740 #define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003
1741 #define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000
1742 #define FLASH_5717VENDOR_ST_25USPT 0x03400002
1743 #define FLASH_5717VENDOR_ST_45USPT 0x03400001
1744 #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1745 #define FLASH_5752PAGE_SIZE_256 0x00000000
1746 #define FLASH_5752PAGE_SIZE_512 0x10000000
1747 #define FLASH_5752PAGE_SIZE_1K 0x20000000
1748 #define FLASH_5752PAGE_SIZE_2K 0x30000000
1749 #define FLASH_5752PAGE_SIZE_4K 0x40000000
1750 #define FLASH_5752PAGE_SIZE_264 0x50000000
1751 #define FLASH_5752PAGE_SIZE_528 0x60000000
1752 #define NVRAM_CFG2 0x00007018
1753 #define NVRAM_CFG3 0x0000701c
1754 #define NVRAM_SWARB 0x00007020
1755 #define SWARB_REQ_SET0 0x00000001
1756 #define SWARB_REQ_SET1 0x00000002
1757 #define SWARB_REQ_SET2 0x00000004
1758 #define SWARB_REQ_SET3 0x00000008
1759 #define SWARB_REQ_CLR0 0x00000010
1760 #define SWARB_REQ_CLR1 0x00000020
1761 #define SWARB_REQ_CLR2 0x00000040
1762 #define SWARB_REQ_CLR3 0x00000080
1763 #define SWARB_GNT0 0x00000100
1764 #define SWARB_GNT1 0x00000200
1765 #define SWARB_GNT2 0x00000400
1766 #define SWARB_GNT3 0x00000800
1767 #define SWARB_REQ0 0x00001000
1768 #define SWARB_REQ1 0x00002000
1769 #define SWARB_REQ2 0x00004000
1770 #define SWARB_REQ3 0x00008000
1771 #define NVRAM_ACCESS 0x00007024
1772 #define ACCESS_ENABLE 0x00000001
1773 #define ACCESS_WR_ENABLE 0x00000002
1774 #define NVRAM_WRITE1 0x00007028
1777 #define NVRAM_ADDR_LOCKOUT 0x00007030
1778 /* 0x7034 --> 0x7500 unused */
1780 #define OTP_MODE 0x00007500
1781 #define OTP_MODE_OTP_THRU_GRC 0x00000001
1782 #define OTP_CTRL 0x00007504
1783 #define OTP_CTRL_OTP_PROG_ENABLE 0x00200000
1784 #define OTP_CTRL_OTP_CMD_READ 0x00000000
1785 #define OTP_CTRL_OTP_CMD_INIT 0x00000008
1786 #define OTP_CTRL_OTP_CMD_START 0x00000001
1787 #define OTP_STATUS 0x00007508
1788 #define OTP_STATUS_CMD_DONE 0x00000001
1789 #define OTP_ADDRESS 0x0000750c
1790 #define OTP_ADDRESS_MAGIC1 0x000000a0
1791 #define OTP_ADDRESS_MAGIC2 0x00000080
1794 #define OTP_READ_DATA 0x00007514
1795 /* 0x7518 --> 0x7c04 unused */
1797 #define PCIE_TRANSACTION_CFG 0x00007c04
1798 #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
1799 #define PCIE_TRANS_CFG_LOM 0x00000020
1800 /* 0x7c08 --> 0x7d28 unused */
1802 #define PCIE_PWR_MGMT_THRESH 0x00007d28
1803 #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
1804 #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00
1805 #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000
1806 /* 0x7d2c --> 0x7d54 unused */
1808 #define TG3_PCIE_LNKCTL 0x00007d54
1809 #define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008
1810 #define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080
1811 /* 0x7d58 --> 0x7e70 unused */
1813 #define TG3_PCIE_EIDLE_DELAY 0x00007e70
1814 #define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f
1815 #define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c
1816 /* 0x7e74 --> 0x8000 unused */
1819 /* Alternate PCIE definitions */
1820 #define TG3_PCIE_TLDLPL_PORT 0x00007c00
1821 #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004
1822 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000
1824 /* OTP bit definitions */
1825 #define TG3_OTP_AGCTGT_MASK 0x000000e0
1826 #define TG3_OTP_AGCTGT_SHIFT 1
1827 #define TG3_OTP_HPFFLTR_MASK 0x00000300
1828 #define TG3_OTP_HPFFLTR_SHIFT 1
1829 #define TG3_OTP_HPFOVER_MASK 0x00000400
1830 #define TG3_OTP_HPFOVER_SHIFT 1
1831 #define TG3_OTP_LPFDIS_MASK 0x00000800
1832 #define TG3_OTP_LPFDIS_SHIFT 11
1833 #define TG3_OTP_VDAC_MASK 0xff000000
1834 #define TG3_OTP_VDAC_SHIFT 24
1835 #define TG3_OTP_10BTAMP_MASK 0x0000f000
1836 #define TG3_OTP_10BTAMP_SHIFT 8
1837 #define TG3_OTP_ROFF_MASK 0x00e00000
1838 #define TG3_OTP_ROFF_SHIFT 11
1839 #define TG3_OTP_RCOFF_MASK 0x001c0000
1840 #define TG3_OTP_RCOFF_SHIFT 16
1842 #define TG3_OTP_DEFAULT 0x286c1640
1845 /* Hardware Legacy NVRAM layout */
1846 #define TG3_NVM_VPD_OFF 0x100
1847 #define TG3_NVM_VPD_LEN 256
1849 /* Hardware Selfboot NVRAM layout */
1850 #define TG3_NVM_HWSB_CFG1 0x00000004
1851 #define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000
1852 #define TG3_NVM_HWSB_CFG1_MAJSFT 27
1853 #define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000
1854 #define TG3_NVM_HWSB_CFG1_MINSFT 22
1856 #define TG3_EEPROM_MAGIC 0x669955aa
1857 #define TG3_EEPROM_MAGIC_FW 0xa5000000
1858 #define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
1859 #define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000
1860 #define TG3_EEPROM_SB_FORMAT_1 0x00200000
1861 #define TG3_EEPROM_SB_REVISION_MASK 0x001f0000
1862 #define TG3_EEPROM_SB_REVISION_0 0x00000000
1863 #define TG3_EEPROM_SB_REVISION_2 0x00020000
1864 #define TG3_EEPROM_SB_REVISION_3 0x00030000
1865 #define TG3_EEPROM_MAGIC_HW 0xabcd
1866 #define TG3_EEPROM_MAGIC_HW_MSK 0xffff
1868 #define TG3_NVM_DIR_START 0x18
1869 #define TG3_NVM_DIR_END 0x78
1870 #define TG3_NVM_DIRENT_SIZE 0xc
1871 #define TG3_NVM_DIRTYPE_SHIFT 24
1872 #define TG3_NVM_DIRTYPE_ASFINI 1
1873 #define TG3_NVM_PTREV_BCVER 0x94
1874 #define TG3_NVM_BCVER_MAJMSK 0x0000ff00
1875 #define TG3_NVM_BCVER_MAJSFT 8
1876 #define TG3_NVM_BCVER_MINMSK 0x000000ff
1878 #define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10
1879 #define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14
1880 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
1881 #define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18
1882 #define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700
1883 #define TG3_EEPROM_SB_EDH_MAJ_SHFT 8
1884 #define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff
1885 #define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800
1886 #define TG3_EEPROM_SB_EDH_BLD_SHFT 11
1889 /* 32K Window into NIC internal memory */
1890 #define NIC_SRAM_WIN_BASE 0x00008000
1892 /* Offsets into first 32k of NIC internal memory. */
1893 #define NIC_SRAM_PAGE_ZERO 0x00000000
1894 #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
1895 #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
1896 #define NIC_SRAM_STATS_BLK 0x00000300
1897 #define NIC_SRAM_STATUS_BLK 0x00000b00
1899 #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
1900 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
1901 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
1903 #define NIC_SRAM_DATA_SIG 0x00000b54
1904 #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
1906 #define NIC_SRAM_DATA_CFG 0x00000b58
1907 #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
1908 #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
1909 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
1910 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
1911 #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
1912 #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
1913 #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
1914 #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
1915 #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
1916 #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
1917 #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
1918 #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
1919 #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
1920 #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
1921 #define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000
1923 #define NIC_SRAM_DATA_VER 0x00000b5c
1924 #define NIC_SRAM_DATA_VER_SHIFT 16
1926 #define NIC_SRAM_DATA_PHY_ID 0x00000b74
1927 #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
1928 #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
1930 #define NIC_SRAM_FW_CMD_MBOX 0x00000b78
1931 #define FWCMD_NICDRV_ALIVE 0x00000001
1932 #define FWCMD_NICDRV_PAUSE_FW 0x00000002
1933 #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
1934 #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
1935 #define FWCMD_NICDRV_FIX_DMAR 0x00000005
1936 #define FWCMD_NICDRV_FIX_DMAW 0x00000006
1937 #define FWCMD_NICDRV_LINK_UPDATE 0x0000000c
1938 #define FWCMD_NICDRV_ALIVE2 0x0000000d
1939 #define FWCMD_NICDRV_ALIVE3 0x0000000e
1940 #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
1941 #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
1942 #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
1943 #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
1944 #define DRV_STATE_START 0x00000001
1945 #define DRV_STATE_START_DONE 0x80000001
1946 #define DRV_STATE_UNLOAD 0x00000002
1947 #define DRV_STATE_UNLOAD_DONE 0x80000002
1948 #define DRV_STATE_WOL 0x00000003
1949 #define DRV_STATE_SUSPEND 0x00000004
1951 #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
1953 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
1954 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
1956 #define NIC_SRAM_WOL_MBOX 0x00000d30
1957 #define WOL_SIGNATURE 0x474c0000
1958 #define WOL_DRV_STATE_SHUTDOWN 0x00000001
1959 #define WOL_DRV_WOL 0x00000002
1960 #define WOL_SET_MAGIC_PKT 0x00000004
1962 #define NIC_SRAM_DATA_CFG_2 0x00000d38
1964 #define NIC_SRAM_DATA_CFG_2_APD_EN 0x00000400
1965 #define SHASTA_EXT_LED_MODE_MASK 0x00018000
1966 #define SHASTA_EXT_LED_LEGACY 0x00000000
1967 #define SHASTA_EXT_LED_SHARED 0x00008000
1968 #define SHASTA_EXT_LED_MAC 0x00010000
1969 #define SHASTA_EXT_LED_COMBO 0x00018000
1971 #define NIC_SRAM_DATA_CFG_3 0x00000d3c
1972 #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
1974 #define NIC_SRAM_DATA_CFG_4 0x00000d60
1975 #define NIC_SRAM_GMII_MODE 0x00000002
1976 #define NIC_SRAM_RGMII_STD_IBND_DISABLE 0x00000004
1977 #define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
1978 #define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
1980 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
1982 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
1983 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
1984 #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
1985 #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
1986 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
1987 #define NIC_SRAM_MBUF_POOL_BASE 0x00008000
1988 #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
1989 #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
1990 #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
1991 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
1994 /* Currently this is fixed. */
1995 #define TG3_PHY_PCIE_ADDR 0x00
1996 #define TG3_PHY_MII_ADDR 0x01
1999 /*** Tigon3 specific PHY PCIE registers. ***/
2001 #define TG3_PCIEPHY_BLOCK_ADDR 0x1f
2002 #define TG3_PCIEPHY_XGXS_BLK1 0x0801
2003 #define TG3_PCIEPHY_TXB_BLK 0x0861
2004 #define TG3_PCIEPHY_BLOCK_SHIFT 4
2006 /* TG3_PCIEPHY_TXB_BLK */
2007 #define TG3_PCIEPHY_TX0CTRL1 0x15
2008 #define TG3_PCIEPHY_TX0CTRL1_TXOCM 0x0003
2009 #define TG3_PCIEPHY_TX0CTRL1_RDCTL 0x0008
2010 #define TG3_PCIEPHY_TX0CTRL1_TXCMV 0x0030
2011 #define TG3_PCIEPHY_TX0CTRL1_TKSEL 0x0040
2012 #define TG3_PCIEPHY_TX0CTRL1_NB_EN 0x0400
2014 /* TG3_PCIEPHY_XGXS_BLK1 */
2015 #define TG3_PCIEPHY_PWRMGMT4 0x1a
2016 #define TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN 0x0038
2017 #define TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN 0x4000
2020 /*** Tigon3 specific PHY MII registers. ***/
2021 #define TG3_BMCR_SPEED1000 0x0040
2023 #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
2024 #define MII_TG3_CTRL_ADV_1000_HALF 0x0100
2025 #define MII_TG3_CTRL_ADV_1000_FULL 0x0200
2026 #define MII_TG3_CTRL_AS_MASTER 0x0800
2027 #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
2029 #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
2030 #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
2031 #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
2032 #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
2033 #define MII_TG3_EXT_CTRL_TBI 0x8000
2035 #define MII_TG3_EXT_STAT 0x11 /* Extended status register */
2036 #define MII_TG3_EXT_STAT_LPASS 0x0100
2038 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
2040 #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
2042 #define MII_TG3_DSP_TAP1 0x0001
2043 #define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007
2044 #define MII_TG3_DSP_AADJ1CH0 0x001f
2045 #define MII_TG3_DSP_AADJ1CH3 0x601f
2046 #define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
2047 #define MII_TG3_DSP_EXP8 0x0708
2048 #define MII_TG3_DSP_EXP8_REJ2MHz 0x0001
2049 #define MII_TG3_DSP_EXP8_AEDW 0x0200
2050 #define MII_TG3_DSP_EXP75 0x0f75
2051 #define MII_TG3_DSP_EXP96 0x0f96
2052 #define MII_TG3_DSP_EXP97 0x0f97
2054 #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
2056 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
2057 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
2058 #define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180
2059 #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
2061 #define MII_TG3_AUXCTL_MISC_WREN 0x8000
2062 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
2063 #define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
2064 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
2066 #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
2067 #define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
2068 #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
2070 #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
2071 #define MII_TG3_AUX_STAT_LPASS 0x0004
2072 #define MII_TG3_AUX_STAT_SPDMASK 0x0700
2073 #define MII_TG3_AUX_STAT_10HALF 0x0100
2074 #define MII_TG3_AUX_STAT_10FULL 0x0200
2075 #define MII_TG3_AUX_STAT_100HALF 0x0300
2076 #define MII_TG3_AUX_STAT_100_4 0x0400
2077 #define MII_TG3_AUX_STAT_100FULL 0x0500
2078 #define MII_TG3_AUX_STAT_1000HALF 0x0600
2079 #define MII_TG3_AUX_STAT_1000FULL 0x0700
2080 #define MII_TG3_AUX_STAT_100 0x0008
2081 #define MII_TG3_AUX_STAT_FULL 0x0001
2083 #define MII_TG3_ISTAT 0x1a /* IRQ status register */
2084 #define MII_TG3_IMASK 0x1b /* IRQ mask register */
2086 /* ISTAT/IMASK event bits */
2087 #define MII_TG3_INT_LINKCHG 0x0002
2088 #define MII_TG3_INT_SPEEDCHG 0x0004
2089 #define MII_TG3_INT_DUPLEXCHG 0x0008
2090 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400
2092 #define MII_TG3_MISC_SHDW 0x1c
2093 #define MII_TG3_MISC_SHDW_WREN 0x8000
2095 #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
2096 #define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020
2097 #define MII_TG3_MISC_SHDW_APD_SEL 0x2800
2099 #define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001
2100 #define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002
2101 #define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004
2102 #define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008
2103 #define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010
2104 #define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400
2106 #define MII_TG3_TEST1 0x1e
2107 #define MII_TG3_TEST1_TRIM_EN 0x0010
2108 #define MII_TG3_TEST1_CRC_EN 0x8000
2111 /* Fast Ethernet Tranceiver definitions */
2112 #define MII_TG3_FET_PTEST 0x17
2113 #define MII_TG3_FET_TEST 0x1f
2114 #define MII_TG3_FET_SHADOW_EN 0x0080
2116 #define MII_TG3_FET_SHDW_MISCCTRL 0x10
2117 #define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
2119 #define MII_TG3_FET_SHDW_AUXMODE4 0x1a
2120 #define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008
2122 #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b
2123 #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020
2126 /* APE registers. Accessible through BAR1 */
2127 #define TG3_APE_EVENT 0x000c
2128 #define APE_EVENT_1 0x00000001
2129 #define TG3_APE_LOCK_REQ 0x002c
2130 #define APE_LOCK_REQ_DRIVER 0x00001000
2131 #define TG3_APE_LOCK_GRANT 0x004c
2132 #define APE_LOCK_GRANT_DRIVER 0x00001000
2133 #define TG3_APE_SEG_SIG 0x4000
2134 #define APE_SEG_SIG_MAGIC 0x41504521
2136 /* APE shared memory. Accessible through BAR1 */
2137 #define TG3_APE_FW_STATUS 0x400c
2138 #define APE_FW_STATUS_READY 0x00000100
2139 #define TG3_APE_FW_VERSION 0x4018
2140 #define APE_FW_VERSION_MAJMSK 0xff000000
2141 #define APE_FW_VERSION_MAJSFT 24
2142 #define APE_FW_VERSION_MINMSK 0x00ff0000
2143 #define APE_FW_VERSION_MINSFT 16
2144 #define APE_FW_VERSION_REVMSK 0x0000ff00
2145 #define APE_FW_VERSION_REVSFT 8
2146 #define APE_FW_VERSION_BLDMSK 0x000000ff
2147 #define TG3_APE_HOST_SEG_SIG 0x4200
2148 #define APE_HOST_SEG_SIG_MAGIC 0x484f5354
2149 #define TG3_APE_HOST_SEG_LEN 0x4204
2150 #define APE_HOST_SEG_LEN_MAGIC 0x0000001c
2151 #define TG3_APE_HOST_INIT_COUNT 0x4208
2152 #define TG3_APE_HOST_DRIVER_ID 0x420c
2153 #define APE_HOST_DRIVER_ID_MAGIC 0xf0035100
2154 #define TG3_APE_HOST_BEHAVIOR 0x4210
2155 #define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
2156 #define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214
2157 #define APE_HOST_HEARTBEAT_INT_DISABLE 0
2158 #define APE_HOST_HEARTBEAT_INT_5SEC 5000
2159 #define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218
2161 #define TG3_APE_EVENT_STATUS 0x4300
2163 #define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
2164 #define APE_EVENT_STATUS_STATE_CHNGE 0x00000500
2165 #define APE_EVENT_STATUS_STATE_START 0x00010000
2166 #define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
2167 #define APE_EVENT_STATUS_STATE_WOL 0x00030000
2168 #define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
2169 #define APE_EVENT_STATUS_EVENT_PENDING 0x80000000
2171 /* APE convenience enumerations. */
2172 #define TG3_APE_LOCK_GRC 1
2173 #define TG3_APE_LOCK_MEM 4
2175 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2178 /* There are two ways to manage the TX descriptors on the tigon3.
2179 * Either the descriptors are in host DMA'able memory, or they
2180 * exist only in the cards on-chip SRAM. All 16 send bds are under
2181 * the same mode, they may not be configured individually.
2183 * This driver always uses host memory TX descriptors.
2185 * To use host memory TX descriptors:
2186 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
2187 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
2188 * 2) Allocate DMA'able memory.
2189 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2190 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
2191 * obtained in step 2
2192 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
2193 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
2194 * of TX descriptors. Leave flags field clear.
2195 * 4) Access TX descriptors via host memory. The chip
2196 * will refetch into local SRAM as needed when producer
2197 * index mailboxes are updated.
2199 * To use on-chip TX descriptors:
2200 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
2201 * Make sure GRC_MODE_HOST_SENDBDS is clear.
2202 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2203 * a) Set TG3_BDINFO_HOST_ADDR to zero.
2204 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
2205 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
2206 * 3) Access TX descriptors directly in on-chip SRAM
2207 * using normal {read,write}l(). (and not using
2208 * pointer dereferencing of ioremap()'d memory like
2209 * the broken Broadcom driver does)
2211 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
2212 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
2214 struct tg3_tx_buffer_desc
{
2219 #define TXD_FLAG_TCPUDP_CSUM 0x0001
2220 #define TXD_FLAG_IP_CSUM 0x0002
2221 #define TXD_FLAG_END 0x0004
2222 #define TXD_FLAG_IP_FRAG 0x0008
2223 #define TXD_FLAG_JMB_PKT 0x0008
2224 #define TXD_FLAG_IP_FRAG_END 0x0010
2225 #define TXD_FLAG_VLAN 0x0040
2226 #define TXD_FLAG_COAL_NOW 0x0080
2227 #define TXD_FLAG_CPU_PRE_DMA 0x0100
2228 #define TXD_FLAG_CPU_POST_DMA 0x0200
2229 #define TXD_FLAG_ADD_SRC_ADDR 0x1000
2230 #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
2231 #define TXD_FLAG_NO_CRC 0x8000
2232 #define TXD_LEN_SHIFT 16
2235 #define TXD_VLAN_TAG_SHIFT 0
2236 #define TXD_MSS_SHIFT 16
2239 #define TXD_ADDR 0x00UL /* 64-bit */
2240 #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
2241 #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
2242 #define TXD_SIZE 0x10UL
2244 struct tg3_rx_buffer_desc
{
2249 #define RXD_IDX_MASK 0xffff0000
2250 #define RXD_IDX_SHIFT 16
2251 #define RXD_LEN_MASK 0x0000ffff
2252 #define RXD_LEN_SHIFT 0
2255 #define RXD_TYPE_SHIFT 16
2256 #define RXD_FLAGS_SHIFT 0
2258 #define RXD_FLAG_END 0x0004
2259 #define RXD_FLAG_MINI 0x0800
2260 #define RXD_FLAG_JUMBO 0x0020
2261 #define RXD_FLAG_VLAN 0x0040
2262 #define RXD_FLAG_ERROR 0x0400
2263 #define RXD_FLAG_IP_CSUM 0x1000
2264 #define RXD_FLAG_TCPUDP_CSUM 0x2000
2265 #define RXD_FLAG_IS_TCP 0x4000
2268 #define RXD_IPCSUM_MASK 0xffff0000
2269 #define RXD_IPCSUM_SHIFT 16
2270 #define RXD_TCPCSUM_MASK 0x0000ffff
2271 #define RXD_TCPCSUM_SHIFT 0
2275 #define RXD_VLAN_MASK 0x0000ffff
2277 #define RXD_ERR_BAD_CRC 0x00010000
2278 #define RXD_ERR_COLLISION 0x00020000
2279 #define RXD_ERR_LINK_LOST 0x00040000
2280 #define RXD_ERR_PHY_DECODE 0x00080000
2281 #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
2282 #define RXD_ERR_MAC_ABRT 0x00200000
2283 #define RXD_ERR_TOO_SMALL 0x00400000
2284 #define RXD_ERR_NO_RESOURCES 0x00800000
2285 #define RXD_ERR_HUGE_FRAME 0x01000000
2286 #define RXD_ERR_MASK 0xffff0000
2290 #define RXD_OPAQUE_INDEX_MASK 0x0000ffff
2291 #define RXD_OPAQUE_INDEX_SHIFT 0
2292 #define RXD_OPAQUE_RING_STD 0x00010000
2293 #define RXD_OPAQUE_RING_JUMBO 0x00020000
2294 #define RXD_OPAQUE_RING_MINI 0x00040000
2295 #define RXD_OPAQUE_RING_MASK 0x00070000
2298 struct tg3_ext_rx_buffer_desc
{
2305 struct tg3_rx_buffer_desc std
;
2308 /* We only use this when testing out the DMA engine
2309 * at probe time. This is the internal format of buffer
2310 * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
2312 struct tg3_internal_buffer_desc
{
2330 #define TG3_HW_STATUS_SIZE 0x50
2331 struct tg3_hw_status
{
2333 #define SD_STATUS_UPDATED 0x00000001
2334 #define SD_STATUS_LINK_CHG 0x00000002
2335 #define SD_STATUS_ERROR 0x00000004
2341 u16 rx_jumbo_consumer
;
2343 u16 rx_jumbo_consumer
;
2349 u16 rx_mini_consumer
;
2351 u16 rx_mini_consumer
;
2369 struct tg3_hw_stats
{
2370 u8 __reserved0
[0x400-0x300];
2372 /* Statistics maintained by Receive MAC. */
2373 tg3_stat64_t rx_octets
;
2375 tg3_stat64_t rx_fragments
;
2376 tg3_stat64_t rx_ucast_packets
;
2377 tg3_stat64_t rx_mcast_packets
;
2378 tg3_stat64_t rx_bcast_packets
;
2379 tg3_stat64_t rx_fcs_errors
;
2380 tg3_stat64_t rx_align_errors
;
2381 tg3_stat64_t rx_xon_pause_rcvd
;
2382 tg3_stat64_t rx_xoff_pause_rcvd
;
2383 tg3_stat64_t rx_mac_ctrl_rcvd
;
2384 tg3_stat64_t rx_xoff_entered
;
2385 tg3_stat64_t rx_frame_too_long_errors
;
2386 tg3_stat64_t rx_jabbers
;
2387 tg3_stat64_t rx_undersize_packets
;
2388 tg3_stat64_t rx_in_length_errors
;
2389 tg3_stat64_t rx_out_length_errors
;
2390 tg3_stat64_t rx_64_or_less_octet_packets
;
2391 tg3_stat64_t rx_65_to_127_octet_packets
;
2392 tg3_stat64_t rx_128_to_255_octet_packets
;
2393 tg3_stat64_t rx_256_to_511_octet_packets
;
2394 tg3_stat64_t rx_512_to_1023_octet_packets
;
2395 tg3_stat64_t rx_1024_to_1522_octet_packets
;
2396 tg3_stat64_t rx_1523_to_2047_octet_packets
;
2397 tg3_stat64_t rx_2048_to_4095_octet_packets
;
2398 tg3_stat64_t rx_4096_to_8191_octet_packets
;
2399 tg3_stat64_t rx_8192_to_9022_octet_packets
;
2403 /* Statistics maintained by Transmit MAC. */
2404 tg3_stat64_t tx_octets
;
2406 tg3_stat64_t tx_collisions
;
2407 tg3_stat64_t tx_xon_sent
;
2408 tg3_stat64_t tx_xoff_sent
;
2409 tg3_stat64_t tx_flow_control
;
2410 tg3_stat64_t tx_mac_errors
;
2411 tg3_stat64_t tx_single_collisions
;
2412 tg3_stat64_t tx_mult_collisions
;
2413 tg3_stat64_t tx_deferred
;
2415 tg3_stat64_t tx_excessive_collisions
;
2416 tg3_stat64_t tx_late_collisions
;
2417 tg3_stat64_t tx_collide_2times
;
2418 tg3_stat64_t tx_collide_3times
;
2419 tg3_stat64_t tx_collide_4times
;
2420 tg3_stat64_t tx_collide_5times
;
2421 tg3_stat64_t tx_collide_6times
;
2422 tg3_stat64_t tx_collide_7times
;
2423 tg3_stat64_t tx_collide_8times
;
2424 tg3_stat64_t tx_collide_9times
;
2425 tg3_stat64_t tx_collide_10times
;
2426 tg3_stat64_t tx_collide_11times
;
2427 tg3_stat64_t tx_collide_12times
;
2428 tg3_stat64_t tx_collide_13times
;
2429 tg3_stat64_t tx_collide_14times
;
2430 tg3_stat64_t tx_collide_15times
;
2431 tg3_stat64_t tx_ucast_packets
;
2432 tg3_stat64_t tx_mcast_packets
;
2433 tg3_stat64_t tx_bcast_packets
;
2434 tg3_stat64_t tx_carrier_sense_errors
;
2435 tg3_stat64_t tx_discards
;
2436 tg3_stat64_t tx_errors
;
2440 /* Statistics maintained by Receive List Placement. */
2441 tg3_stat64_t COS_rx_packets
[16];
2442 tg3_stat64_t COS_rx_filter_dropped
;
2443 tg3_stat64_t dma_writeq_full
;
2444 tg3_stat64_t dma_write_prioq_full
;
2445 tg3_stat64_t rxbds_empty
;
2446 tg3_stat64_t rx_discards
;
2447 tg3_stat64_t rx_errors
;
2448 tg3_stat64_t rx_threshold_hit
;
2452 /* Statistics maintained by Send Data Initiator. */
2453 tg3_stat64_t COS_out_packets
[16];
2454 tg3_stat64_t dma_readq_full
;
2455 tg3_stat64_t dma_read_prioq_full
;
2456 tg3_stat64_t tx_comp_queue_full
;
2458 /* Statistics maintained by Host Coalescing. */
2459 tg3_stat64_t ring_set_send_prod_index
;
2460 tg3_stat64_t ring_status_update
;
2461 tg3_stat64_t nic_irqs
;
2462 tg3_stat64_t nic_avoided_irqs
;
2463 tg3_stat64_t nic_tx_threshold_hit
;
2465 u8 __reserved4
[0xb00-0x9c0];
2468 /* 'mapping' is superfluous as the chip does not write into
2469 * the tx/rx post rings so we could just fetch it from there.
2470 * But the cache behavior is better how we are doing it now.
2473 struct sk_buff
*skb
;
2474 DECLARE_PCI_UNMAP_ADDR(mapping
)
2477 struct tg3_config_info
{
2481 struct tg3_link_config
{
2482 /* Describes what we're trying to get. */
2489 /* Describes what we actually have. */
2493 #define SPEED_INVALID 0xffff
2494 #define DUPLEX_INVALID 0xff
2495 #define AUTONEG_INVALID 0xff
2498 /* When we go in and out of low power mode we need
2499 * to swap with this state.
2501 int phy_is_low_power
;
2505 u32 orig_advertising
;
2508 struct tg3_bufmgr_config
{
2509 u32 mbuf_read_dma_low_water
;
2510 u32 mbuf_mac_rx_low_water
;
2511 u32 mbuf_high_water
;
2513 u32 mbuf_read_dma_low_water_jumbo
;
2514 u32 mbuf_mac_rx_low_water_jumbo
;
2515 u32 mbuf_high_water_jumbo
;
2521 struct tg3_ethtool_stats
{
2522 /* Statistics maintained by Receive MAC. */
2525 u64 rx_ucast_packets
;
2526 u64 rx_mcast_packets
;
2527 u64 rx_bcast_packets
;
2529 u64 rx_align_errors
;
2530 u64 rx_xon_pause_rcvd
;
2531 u64 rx_xoff_pause_rcvd
;
2532 u64 rx_mac_ctrl_rcvd
;
2533 u64 rx_xoff_entered
;
2534 u64 rx_frame_too_long_errors
;
2536 u64 rx_undersize_packets
;
2537 u64 rx_in_length_errors
;
2538 u64 rx_out_length_errors
;
2539 u64 rx_64_or_less_octet_packets
;
2540 u64 rx_65_to_127_octet_packets
;
2541 u64 rx_128_to_255_octet_packets
;
2542 u64 rx_256_to_511_octet_packets
;
2543 u64 rx_512_to_1023_octet_packets
;
2544 u64 rx_1024_to_1522_octet_packets
;
2545 u64 rx_1523_to_2047_octet_packets
;
2546 u64 rx_2048_to_4095_octet_packets
;
2547 u64 rx_4096_to_8191_octet_packets
;
2548 u64 rx_8192_to_9022_octet_packets
;
2550 /* Statistics maintained by Transmit MAC. */
2555 u64 tx_flow_control
;
2557 u64 tx_single_collisions
;
2558 u64 tx_mult_collisions
;
2560 u64 tx_excessive_collisions
;
2561 u64 tx_late_collisions
;
2562 u64 tx_collide_2times
;
2563 u64 tx_collide_3times
;
2564 u64 tx_collide_4times
;
2565 u64 tx_collide_5times
;
2566 u64 tx_collide_6times
;
2567 u64 tx_collide_7times
;
2568 u64 tx_collide_8times
;
2569 u64 tx_collide_9times
;
2570 u64 tx_collide_10times
;
2571 u64 tx_collide_11times
;
2572 u64 tx_collide_12times
;
2573 u64 tx_collide_13times
;
2574 u64 tx_collide_14times
;
2575 u64 tx_collide_15times
;
2576 u64 tx_ucast_packets
;
2577 u64 tx_mcast_packets
;
2578 u64 tx_bcast_packets
;
2579 u64 tx_carrier_sense_errors
;
2583 /* Statistics maintained by Receive List Placement. */
2584 u64 dma_writeq_full
;
2585 u64 dma_write_prioq_full
;
2589 u64 rx_threshold_hit
;
2591 /* Statistics maintained by Send Data Initiator. */
2593 u64 dma_read_prioq_full
;
2594 u64 tx_comp_queue_full
;
2596 /* Statistics maintained by Host Coalescing. */
2597 u64 ring_set_send_prod_index
;
2598 u64 ring_status_update
;
2600 u64 nic_avoided_irqs
;
2601 u64 nic_tx_threshold_hit
;
2604 struct tg3_rx_prodring_set
{
2605 u32 rx_std_prod_idx
;
2606 u32 rx_std_cons_idx
;
2607 u32 rx_jmb_prod_idx
;
2608 u32 rx_jmb_cons_idx
;
2609 struct tg3_rx_buffer_desc
*rx_std
;
2610 struct tg3_ext_rx_buffer_desc
*rx_jmb
;
2611 struct ring_info
*rx_std_buffers
;
2612 struct ring_info
*rx_jmb_buffers
;
2613 dma_addr_t rx_std_mapping
;
2614 dma_addr_t rx_jmb_mapping
;
2617 #define TG3_IRQ_MAX_VECS 5
2620 struct napi_struct napi ____cacheline_aligned
;
2622 struct tg3_hw_status
*hw_status
;
2635 u16
*rx_rcb_prod_idx
;
2636 struct tg3_rx_prodring_set
*prodring
;
2638 struct tg3_rx_buffer_desc
*rx_rcb
;
2639 struct tg3_tx_buffer_desc
*tx_ring
;
2640 struct ring_info
*tx_buffers
;
2642 dma_addr_t status_mapping
;
2643 dma_addr_t rx_rcb_mapping
;
2644 dma_addr_t tx_desc_mapping
;
2646 char irq_lbl
[IFNAMSIZ
];
2647 unsigned int irq_vec
;
2651 /* begin "general, frequently-used members" cacheline section */
2653 /* If the IRQ handler (which runs lockless) needs to be
2654 * quiesced, the following bitmask state is used. The
2655 * SYNC flag is set by non-IRQ context code to initiate
2658 * When the IRQ handler notices that SYNC is set, it
2659 * disables interrupts and returns.
2661 * When all outstanding IRQ handlers have returned after
2662 * the SYNC flag has been set, the setter can be assured
2663 * that interrupts will no longer get run.
2665 * In this way all SMP driver locks are never acquired
2666 * in hw IRQ context, only sw IRQ context or lower.
2668 unsigned int irq_sync
;
2670 /* SMP locking strategy:
2672 * lock: Held during reset, PHY access, timer, and when
2673 * updating tg3_flags and tg3_flags2.
2675 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
2676 * netif_tx_lock when it needs to call
2679 * Both of these locks are to be held with BH safety.
2681 * Because the IRQ handler, tg3_poll, and tg3_start_xmit
2682 * are running lockless, it is necessary to completely
2683 * quiesce the chip with tg3_netif_stop and tg3_full_lock
2684 * before reconfiguring the device.
2686 * indirect_lock: Held when accessing registers indirectly
2687 * with IRQ disabling.
2690 spinlock_t indirect_lock
;
2692 u32 (*read32
) (struct tg3
*, u32
);
2693 void (*write32
) (struct tg3
*, u32
, u32
);
2694 u32 (*read32_mbox
) (struct tg3
*, u32
);
2695 void (*write32_mbox
) (struct tg3
*, u32
,
2698 void __iomem
*aperegs
;
2699 struct net_device
*dev
;
2700 struct pci_dev
*pdev
;
2704 /* begin "tx thread" cacheline section */
2705 void (*write32_tx_mbox
) (struct tg3
*, u32
,
2708 /* begin "rx thread" cacheline section */
2709 struct tg3_napi napi
[TG3_IRQ_MAX_VECS
];
2710 void (*write32_rx_mbox
) (struct tg3
*, u32
,
2713 u32 rx_jumbo_pending
;
2714 u32 rx_std_max_post
;
2716 #if TG3_VLAN_TAG_USED
2717 struct vlan_group
*vlgrp
;
2720 struct tg3_rx_prodring_set prodring
[TG3_IRQ_MAX_VECS
];
2723 /* begin "everything else" cacheline(s) section */
2724 struct net_device_stats net_stats
;
2725 struct net_device_stats net_stats_prev
;
2726 struct tg3_ethtool_stats estats
;
2727 struct tg3_ethtool_stats estats_prev
;
2730 unsigned long phy_crc_errors
;
2731 unsigned long last_event_jiffies
;
2736 #define TG3_FLAG_TAGGED_STATUS 0x00000001
2737 #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
2738 #define TG3_FLAG_RX_CHECKSUMS 0x00000004
2739 #define TG3_FLAG_USE_LINKCHG_REG 0x00000008
2740 #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
2741 #define TG3_FLAG_ENABLE_ASF 0x00000020
2742 #define TG3_FLAG_ASPM_WORKAROUND 0x00000040
2743 #define TG3_FLAG_POLL_SERDES 0x00000080
2744 #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
2745 #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
2746 #define TG3_FLAG_WOL_SPEED_100MB 0x00000400
2747 #define TG3_FLAG_WOL_ENABLE 0x00000800
2748 #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
2749 #define TG3_FLAG_NVRAM 0x00002000
2750 #define TG3_FLAG_NVRAM_BUFFERED 0x00004000
2751 #define TG3_FLAG_SUPPORT_MSI 0x00008000
2752 #define TG3_FLAG_SUPPORT_MSIX 0x00010000
2753 #define TG3_FLAG_SUPPORT_MSI_OR_MSIX (TG3_FLAG_SUPPORT_MSI | \
2754 TG3_FLAG_SUPPORT_MSIX)
2755 #define TG3_FLAG_PCIX_MODE 0x00020000
2756 #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
2757 #define TG3_FLAG_PCI_32BIT 0x00080000
2758 #define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
2759 #define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
2760 #define TG3_FLAG_WOL_CAP 0x00400000
2761 #define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
2762 #define TG3_FLAG_10_100_ONLY 0x01000000
2763 #define TG3_FLAG_PAUSE_AUTONEG 0x02000000
2764 #define TG3_FLAG_CPMU_PRESENT 0x04000000
2765 #define TG3_FLAG_40BIT_DMA_BUG 0x08000000
2766 #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
2767 #define TG3_FLAG_JUMBO_CAPABLE 0x20000000
2768 #define TG3_FLAG_CHIP_RESETTING 0x40000000
2769 #define TG3_FLAG_INIT_COMPLETE 0x80000000
2771 #define TG3_FLG2_RESTART_TIMER 0x00000001
2772 #define TG3_FLG2_TSO_BUG 0x00000002
2773 #define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
2774 #define TG3_FLG2_IS_5788 0x00000008
2775 #define TG3_FLG2_MAX_RXPEND_64 0x00000010
2776 #define TG3_FLG2_TSO_CAPABLE 0x00000020
2777 #define TG3_FLG2_PHY_ADC_BUG 0x00000040
2778 #define TG3_FLG2_PHY_5704_A0_BUG 0x00000080
2779 #define TG3_FLG2_PHY_BER_BUG 0x00000100
2780 #define TG3_FLG2_PCI_EXPRESS 0x00000200
2781 #define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
2782 #define TG3_FLG2_HW_AUTONEG 0x00000800
2783 #define TG3_FLG2_IS_NIC 0x00001000
2784 #define TG3_FLG2_PHY_SERDES 0x00002000
2785 #define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000
2786 #define TG3_FLG2_FLASH 0x00008000
2787 #define TG3_FLG2_HW_TSO_1 0x00010000
2788 #define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
2789 #define TG3_FLG2_5705_PLUS 0x00040000
2790 #define TG3_FLG2_5750_PLUS 0x00080000
2791 #define TG3_FLG2_HW_TSO_3 0x00100000
2792 #define TG3_FLG2_USING_MSI 0x00200000
2793 #define TG3_FLG2_USING_MSIX 0x00400000
2794 #define TG3_FLG2_USING_MSI_OR_MSIX (TG3_FLG2_USING_MSI | \
2795 TG3_FLG2_USING_MSIX)
2796 #define TG3_FLG2_MII_SERDES 0x00800000
2797 #define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \
2798 TG3_FLG2_MII_SERDES)
2799 #define TG3_FLG2_PARALLEL_DETECT 0x01000000
2800 #define TG3_FLG2_ICH_WORKAROUND 0x02000000
2801 #define TG3_FLG2_5780_CLASS 0x04000000
2802 #define TG3_FLG2_HW_TSO_2 0x08000000
2803 #define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | \
2804 TG3_FLG2_HW_TSO_2 | \
2806 #define TG3_FLG2_1SHOT_MSI 0x10000000
2807 #define TG3_FLG2_PHY_JITTER_BUG 0x20000000
2808 #define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
2809 #define TG3_FLG2_PHY_ADJUST_TRIM 0x80000000
2811 #define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001
2812 #define TG3_FLG3_ENABLE_APE 0x00000002
2813 #define TG3_FLG3_PROTECTED_NVRAM 0x00000004
2814 #define TG3_FLG3_5701_DMA_BUG 0x00000008
2815 #define TG3_FLG3_USE_PHYLIB 0x00000010
2816 #define TG3_FLG3_MDIOBUS_INITED 0x00000020
2817 #define TG3_FLG3_PHY_CONNECTED 0x00000080
2818 #define TG3_FLG3_RGMII_STD_IBND_DISABLE 0x00000100
2819 #define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200
2820 #define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400
2821 #define TG3_FLG3_CLKREQ_BUG 0x00000800
2822 #define TG3_FLG3_PHY_ENABLE_APD 0x00001000
2823 #define TG3_FLG3_5755_PLUS 0x00002000
2824 #define TG3_FLG3_NO_NVRAM 0x00004000
2825 #define TG3_FLG3_PHY_IS_FET 0x00010000
2826 #define TG3_FLG3_ENABLE_RSS 0x00020000
2827 #define TG3_FLG3_ENABLE_TSS 0x00040000
2828 #define TG3_FLG3_4G_DMA_BNDRY_BUG 0x00080000
2829 #define TG3_FLG3_40BIT_DMA_LIMIT_BUG 0x00100000
2830 #define TG3_FLG3_SHORT_DMA_BUG 0x00200000
2831 #define TG3_FLG3_USE_JUMBO_BDFLAG 0x00400000
2832 #define TG3_FLG3_L1PLLPD_EN 0x00800000
2834 struct timer_list timer
;
2836 u16 timer_multiplier
;
2841 /* 1 second counter for transient serdes link events */
2843 #define SERDES_AN_TIMEOUT_5704S 2
2844 #define SERDES_PARALLEL_DET_TIMEOUT 1
2845 #define SERDES_AN_TIMEOUT_5714S 1
2847 struct tg3_link_config link_config
;
2848 struct tg3_bufmgr_config bufmgr_config
;
2850 /* cache h/w values, often passed straight to h/w */
2863 u32 pci_chip_rev_id
;
2865 u8 pci_cacheline_sz
;
2875 struct mii_bus
*mdio_bus
;
2876 int mdio_irq
[PHY_MAX_ADDR
];
2882 #define PHY_ID_MASK 0xfffffff0
2883 #define PHY_ID_BCM5400 0x60008040
2884 #define PHY_ID_BCM5401 0x60008050
2885 #define PHY_ID_BCM5411 0x60008070
2886 #define PHY_ID_BCM5701 0x60008110
2887 #define PHY_ID_BCM5703 0x60008160
2888 #define PHY_ID_BCM5704 0x60008190
2889 #define PHY_ID_BCM5705 0x600081a0
2890 #define PHY_ID_BCM5750 0x60008180
2891 #define PHY_ID_BCM5752 0x60008100
2892 #define PHY_ID_BCM5714 0x60008340
2893 #define PHY_ID_BCM5780 0x60008350
2894 #define PHY_ID_BCM5755 0xbc050cc0
2895 #define PHY_ID_BCM5787 0xbc050ce0
2896 #define PHY_ID_BCM5756 0xbc050ed0
2897 #define PHY_ID_BCM5784 0xbc050fa0
2898 #define PHY_ID_BCM5761 0xbc050fd0
2899 #define PHY_ID_BCM5718C 0x5c0d8a00
2900 #define PHY_ID_BCM5718S 0xbc050ff0
2901 #define PHY_ID_BCM57765 0x5c0d8a40
2902 #define PHY_ID_BCM5906 0xdc00ac40
2903 #define PHY_ID_BCM8002 0x60010140
2904 #define PHY_ID_INVALID 0xffffffff
2905 #define PHY_ID_REV_MASK 0x0000000f
2906 #define PHY_REV_BCM5401_B0 0x1
2907 #define PHY_REV_BCM5401_B2 0x3
2908 #define PHY_REV_BCM5401_C0 0x6
2909 #define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
2910 #define TG3_PHY_ID_BCM50610 0x143bd60
2911 #define TG3_PHY_ID_BCM50610M 0x143bd70
2912 #define TG3_PHY_ID_BCMAC131 0x143bc70
2913 #define TG3_PHY_ID_RTL8211C 0x001cc910
2914 #define TG3_PHY_ID_RTL8201E 0x00008200
2915 #define TG3_PHY_ID_BCM57780 0x03625d90
2916 #define TG3_PHY_OUI_MASK 0xfffffc00
2917 #define TG3_PHY_OUI_1 0x00206000
2918 #define TG3_PHY_OUI_2 0x0143bc00
2919 #define TG3_PHY_OUI_3 0x03625c00
2924 #define TG3_BPN_SIZE 24
2925 char board_part_number
[TG3_BPN_SIZE
];
2926 #define TG3_VER_SIZE ETHTOOL_FWVERS_LEN
2927 char fw_ver
[TG3_VER_SIZE
];
2928 u32 nic_sram_data_cfg
;
2930 struct pci_dev
*pdev_peer
;
2932 /* This macro assumes the passed PHY ID is already masked
2935 #define KNOWN_PHY_ID(X) \
2936 ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2937 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2938 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2939 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
2940 (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
2941 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
2942 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
2943 (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
2944 (X) == PHY_ID_BCM5718C || (X) == PHY_ID_BCM5718S || \
2945 (X) == PHY_ID_BCM57765 || (X) == PHY_ID_BCM8002)
2947 struct tg3_hw_stats
*hw_stats
;
2948 dma_addr_t stats_mapping
;
2949 struct work_struct reset_task
;
2953 #define TG3_NVRAM_SIZE_64KB 0x00010000
2954 #define TG3_NVRAM_SIZE_128KB 0x00020000
2955 #define TG3_NVRAM_SIZE_256KB 0x00040000
2956 #define TG3_NVRAM_SIZE_512KB 0x00080000
2957 #define TG3_NVRAM_SIZE_1MB 0x00100000
2958 #define TG3_NVRAM_SIZE_2MB 0x00200000
2963 #define JEDEC_ATMEL 0x1f
2964 #define JEDEC_ST 0x20
2965 #define JEDEC_SAIFUN 0x4f
2966 #define JEDEC_SST 0xbf
2968 #define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB
2969 #define ATMEL_AT24C64_PAGE_SIZE (32)
2971 #define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB
2972 #define ATMEL_AT24C512_PAGE_SIZE (128)
2974 #define ATMEL_AT45DB0X1B_PAGE_POS 9
2975 #define ATMEL_AT45DB0X1B_PAGE_SIZE 264
2977 #define ATMEL_AT25F512_PAGE_SIZE 256
2979 #define ST_M45PEX0_PAGE_SIZE 256
2981 #define SAIFUN_SA25F0XX_PAGE_SIZE 256
2983 #define SST_25VF0X0_PAGE_SIZE 4098
2985 unsigned int irq_max
;
2986 unsigned int irq_cnt
;
2988 struct ethtool_coalesce coal
;
2991 const char *fw_needed
;
2992 const struct firmware
*fw
;
2993 u32 fw_len
; /* includes BSS */
2996 #endif /* !(_T3_H) */