drivers/iommu/tegra-gart.c

   1 /*
   2  * IOMMU API for GART in Tegra20
   3  *
   4  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #define pr_fmt(fmt)     "%s(): " fmt, __func__
  21
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/slab.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/mm.h>
  28 #include <linux/list.h>
  29 #include <linux/device.h>
  30 #include <linux/io.h>
  31 #include <linux/iommu.h>
  32 #include <linux/of.h>
  33
  34 #include <asm/cacheflush.h>
  35
  36 /* bitmap of the page sizes currently supported */
  37 #define GART_IOMMU_PGSIZES      (SZ_4K)
  38
  39 #define GART_REG_BASE           0x24
  40 #define GART_CONFIG             (0x24 - GART_REG_BASE)
  41 #define GART_ENTRY_ADDR         (0x28 - GART_REG_BASE)
  42 #define GART_ENTRY_DATA         (0x2c - GART_REG_BASE)
  43 #define GART_ENTRY_PHYS_ADDR_VALID      (1 << 31)
  44
  45 #define GART_PAGE_SHIFT         12
  46 #define GART_PAGE_SIZE          (1 << GART_PAGE_SHIFT)
  47 #define GART_PAGE_MASK                                          \
  48         (~(GART_PAGE_SIZE - 1) & ~GART_ENTRY_PHYS_ADDR_VALID)
  49
  50 struct gart_client {
  51         struct device           *dev;
  52         struct list_head        list;
  53 };
  54
  55 struct gart_device {
  56         void __iomem            *regs;
  57         u32                     *savedata;
  58         u32                     page_count;     /* total remappable size */
  59         dma_addr_t              iovmm_base;     /* offset to vmm_area */
  60         spinlock_t              pte_lock;       /* for pagetable */
  61         struct list_head        client;
  62         spinlock_t              client_lock;    /* for client list */
  63         struct device           *dev;
  64 };
  65
  66 static struct gart_device *gart_handle; /* unique for a system */
  67
  68 #define GART_PTE(_pfn)                                          \
  69         (GART_ENTRY_PHYS_ADDR_VALID | ((_pfn) << PAGE_SHIFT))
  70
  71 /*
  72  * Any interaction between any block on PPSB and a block on APB or AHB
  73  * must have these read-back to ensure the APB/AHB bus transaction is
  74  * complete before initiating activity on the PPSB block.
  75  */
  76 #define FLUSH_GART_REGS(gart)   ((void)readl((gart)->regs + GART_CONFIG))
  77
  78 #define for_each_gart_pte(gart, iova)                                   \
  79         for (iova = gart->iovmm_base;                                   \
  80              iova < gart->iovmm_base + GART_PAGE_SIZE * gart->page_count; \
  81              iova += GART_PAGE_SIZE)
  82
  83 static inline void gart_set_pte(struct gart_device *gart,
  84                                 unsigned long offs, u32 pte)
  85 {
  86         writel(offs, gart->regs + GART_ENTRY_ADDR);
  87         writel(pte, gart->regs + GART_ENTRY_DATA);
  88
  89         dev_dbg(gart->dev, "%s %08lx:%08x\n",
  90                  pte ? "map" : "unmap", offs, pte & GART_PAGE_MASK);
  91 }
  92
  93 static inline unsigned long gart_read_pte(struct gart_device *gart,
  94                                           unsigned long offs)
  95 {
  96         unsigned long pte;
  97
  98         writel(offs, gart->regs + GART_ENTRY_ADDR);
  99         pte = readl(gart->regs + GART_ENTRY_DATA);
 100
 101         return pte;
 102 }
 103
 104 static void do_gart_setup(struct gart_device *gart, const u32 *data)
 105 {
 106         unsigned long iova;
 107
 108         for_each_gart_pte(gart, iova)
 109                 gart_set_pte(gart, iova, data ? *(data++) : 0);
 110
 111         writel(1, gart->regs + GART_CONFIG);
 112         FLUSH_GART_REGS(gart);
 113 }
 114
 115 #ifdef DEBUG
 116 static void gart_dump_table(struct gart_device *gart)
 117 {
 118         unsigned long iova;
 119         unsigned long flags;
 120
 121         spin_lock_irqsave(&gart->pte_lock, flags);
 122         for_each_gart_pte(gart, iova) {
 123                 unsigned long pte;
 124
 125                 pte = gart_read_pte(gart, iova);
 126
 127                 dev_dbg(gart->dev, "%s %08lx:%08lx\n",
 128                         (GART_ENTRY_PHYS_ADDR_VALID & pte) ? "v" : " ",
 129                         iova, pte & GART_PAGE_MASK);
 130         }
 131         spin_unlock_irqrestore(&gart->pte_lock, flags);
 132 }
 133 #else
 134 static inline void gart_dump_table(struct gart_device *gart)
 135 {
 136 }
 137 #endif
 138
 139 static inline bool gart_iova_range_valid(struct gart_device *gart,
 140                                          unsigned long iova, size_t bytes)
 141 {
 142         unsigned long iova_start, iova_end, gart_start, gart_end;
 143
 144         iova_start = iova;
 145         iova_end = iova_start + bytes - 1;
 146         gart_start = gart->iovmm_base;
 147         gart_end = gart_start + gart->page_count * GART_PAGE_SIZE - 1;
 148
 149         if (iova_start < gart_start)
 150                 return false;
 151         if (iova_end > gart_end)
 152                 return false;
 153         return true;
 154 }
 155
 156 static int gart_iommu_attach_dev(struct iommu_domain *domain,
 157                                  struct device *dev)
 158 {
 159         struct gart_device *gart;
 160         struct gart_client *client, *c;
 161         int err = 0;
 162
 163         gart = gart_handle;
 164         if (!gart)
 165                 return -EINVAL;
 166         domain->priv = gart;
 167
 168         client = devm_kzalloc(gart->dev, sizeof(*c), GFP_KERNEL);
 169         if (!client)
 170                 return -ENOMEM;
 171         client->dev = dev;
 172
 173         spin_lock(&gart->client_lock);
 174         list_for_each_entry(c, &gart->client, list) {
 175                 if (c->dev == dev) {
 176                         dev_err(gart->dev,
 177                                 "%s is already attached\n", dev_name(dev));
 178                         err = -EINVAL;
 179                         goto fail;
 180                 }
 181         }
 182         list_add(&client->list, &gart->client);
 183         spin_unlock(&gart->client_lock);
 184         dev_dbg(gart->dev, "Attached %s\n", dev_name(dev));
 185         return 0;
 186
 187 fail:
 188         devm_kfree(gart->dev, client);
 189         spin_unlock(&gart->client_lock);
 190         return err;
 191 }
 192
 193 static void gart_iommu_detach_dev(struct iommu_domain *domain,
 194                                   struct device *dev)
 195 {
 196         struct gart_device *gart = domain->priv;
 197         struct gart_client *c;
 198
 199         spin_lock(&gart->client_lock);
 200
 201         list_for_each_entry(c, &gart->client, list) {
 202                 if (c->dev == dev) {
 203                         list_del(&c->list);
 204                         devm_kfree(gart->dev, c);
 205                         dev_dbg(gart->dev, "Detached %s\n", dev_name(dev));
 206                         goto out;
 207                 }
 208         }
 209         dev_err(gart->dev, "Couldn't find\n");
 210 out:
 211         spin_unlock(&gart->client_lock);
 212 }
 213
 214 static int gart_iommu_domain_init(struct iommu_domain *domain)
 215 {
 216         return 0;
 217 }
 218
 219 static void gart_iommu_domain_destroy(struct iommu_domain *domain)
 220 {
 221         struct gart_device *gart = domain->priv;
 222
 223         if (!gart)
 224                 return;
 225
 226         spin_lock(&gart->client_lock);
 227         if (!list_empty(&gart->client)) {
 228                 struct gart_client *c;
 229
 230                 list_for_each_entry(c, &gart->client, list)
 231                         gart_iommu_detach_dev(domain, c->dev);
 232         }
 233         spin_unlock(&gart->client_lock);
 234         domain->priv = NULL;
 235 }
 236
 237 static int gart_iommu_map(struct iommu_domain *domain, unsigned long iova,
 238                           phys_addr_t pa, size_t bytes, int prot)
 239 {
 240         struct gart_device *gart = domain->priv;
 241         unsigned long flags;
 242         unsigned long pfn;
 243
 244         if (!gart_iova_range_valid(gart, iova, bytes))
 245                 return -EINVAL;
 246
 247         spin_lock_irqsave(&gart->pte_lock, flags);
 248         pfn = __phys_to_pfn(pa);
 249         if (!pfn_valid(pfn)) {
 250                 dev_err(gart->dev, "Invalid page: %08x\n", pa);
 251                 spin_unlock_irqrestore(&gart->pte_lock, flags);
 252                 return -EINVAL;
 253         }
 254         gart_set_pte(gart, iova, GART_PTE(pfn));
 255         FLUSH_GART_REGS(gart);
 256         spin_unlock_irqrestore(&gart->pte_lock, flags);
 257         return 0;
 258 }
 259
 260 static size_t gart_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
 261                                size_t bytes)
 262 {
 263         struct gart_device *gart = domain->priv;
 264         unsigned long flags;
 265
 266         if (!gart_iova_range_valid(gart, iova, bytes))
 267                 return 0;
 268
 269         spin_lock_irqsave(&gart->pte_lock, flags);
 270         gart_set_pte(gart, iova, 0);
 271         FLUSH_GART_REGS(gart);
 272         spin_unlock_irqrestore(&gart->pte_lock, flags);
 273         return 0;
 274 }
 275
 276 static phys_addr_t gart_iommu_iova_to_phys(struct iommu_domain *domain,
 277                                            unsigned long iova)
 278 {
 279         struct gart_device *gart = domain->priv;
 280         unsigned long pte;
 281         phys_addr_t pa;
 282         unsigned long flags;
 283
 284         if (!gart_iova_range_valid(gart, iova, 0))
 285                 return -EINVAL;
 286
 287         spin_lock_irqsave(&gart->pte_lock, flags);
 288         pte = gart_read_pte(gart, iova);
 289         spin_unlock_irqrestore(&gart->pte_lock, flags);
 290
 291         pa = (pte & GART_PAGE_MASK);
 292         if (!pfn_valid(__phys_to_pfn(pa))) {
 293                 dev_err(gart->dev, "No entry for %08lx:%08x\n", iova, pa);
 294                 gart_dump_table(gart);
 295                 return -EINVAL;
 296         }
 297         return pa;
 298 }
 299
 300 static int gart_iommu_domain_has_cap(struct iommu_domain *domain,
 301                                      unsigned long cap)
 302 {
 303         return 0;
 304 }
 305
 306 static struct iommu_ops gart_iommu_ops = {
 307         .domain_init    = gart_iommu_domain_init,
 308         .domain_destroy = gart_iommu_domain_destroy,
 309         .attach_dev     = gart_iommu_attach_dev,
 310         .detach_dev     = gart_iommu_detach_dev,
 311         .map            = gart_iommu_map,
 312         .unmap          = gart_iommu_unmap,
 313         .iova_to_phys   = gart_iommu_iova_to_phys,
 314         .domain_has_cap = gart_iommu_domain_has_cap,
 315         .pgsize_bitmap  = GART_IOMMU_PGSIZES,
 316 };
 317
 318 static int tegra_gart_suspend(struct device *dev)
 319 {
 320         struct gart_device *gart = dev_get_drvdata(dev);
 321         unsigned long iova;
 322         u32 *data = gart->savedata;
 323         unsigned long flags;
 324
 325         spin_lock_irqsave(&gart->pte_lock, flags);
 326         for_each_gart_pte(gart, iova)
 327                 *(data++) = gart_read_pte(gart, iova);
 328         spin_unlock_irqrestore(&gart->pte_lock, flags);
 329         return 0;
 330 }
 331
 332 static int tegra_gart_resume(struct device *dev)
 333 {
 334         struct gart_device *gart = dev_get_drvdata(dev);
 335         unsigned long flags;
 336
 337         spin_lock_irqsave(&gart->pte_lock, flags);
 338         do_gart_setup(gart, gart->savedata);
 339         spin_unlock_irqrestore(&gart->pte_lock, flags);
 340         return 0;
 341 }
 342
 343 static int tegra_gart_probe(struct platform_device *pdev)
 344 {
 345         struct gart_device *gart;
 346         struct resource *res, *res_remap;
 347         void __iomem *gart_regs;
 348         int err;
 349         struct device *dev = &pdev->dev;
 350
 351         if (gart_handle)
 352                 return -EIO;
 353
 354         BUILD_BUG_ON(PAGE_SHIFT != GART_PAGE_SHIFT);
 355
 356         /* the GART memory aperture is required */
 357         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 358         res_remap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 359         if (!res || !res_remap) {
 360                 dev_err(dev, "GART memory aperture expected\n");
 361                 return -ENXIO;
 362         }
 363
 364         gart = devm_kzalloc(dev, sizeof(*gart), GFP_KERNEL);
 365         if (!gart) {
 366                 dev_err(dev, "failed to allocate gart_device\n");
 367                 return -ENOMEM;
 368         }
 369
 370         gart_regs = devm_ioremap(dev, res->start, resource_size(res));
 371         if (!gart_regs) {
 372                 dev_err(dev, "failed to remap GART registers\n");
 373                 err = -ENXIO;
 374                 goto fail;
 375         }
 376
 377         gart->dev = &pdev->dev;
 378         spin_lock_init(&gart->pte_lock);
 379         spin_lock_init(&gart->client_lock);
 380         INIT_LIST_HEAD(&gart->client);
 381         gart->regs = gart_regs;
 382         gart->iovmm_base = (dma_addr_t)res_remap->start;
 383         gart->page_count = (resource_size(res_remap) >> GART_PAGE_SHIFT);
 384
 385         gart->savedata = vmalloc(sizeof(u32) * gart->page_count);
 386         if (!gart->savedata) {
 387                 dev_err(dev, "failed to allocate context save area\n");
 388                 err = -ENOMEM;
 389                 goto fail;
 390         }
 391
 392         platform_set_drvdata(pdev, gart);
 393         do_gart_setup(gart, NULL);
 394
 395         gart_handle = gart;
 396         return 0;
 397
 398 fail:
 399         if (gart_regs)
 400                 devm_iounmap(dev, gart_regs);
 401         if (gart && gart->savedata)
 402                 vfree(gart->savedata);
 403         devm_kfree(dev, gart);
 404         return err;
 405 }
 406
 407 static int tegra_gart_remove(struct platform_device *pdev)
 408 {
 409         struct gart_device *gart = platform_get_drvdata(pdev);
 410         struct device *dev = gart->dev;
 411
 412         writel(0, gart->regs + GART_CONFIG);
 413         if (gart->savedata)
 414                 vfree(gart->savedata);
 415         if (gart->regs)
 416                 devm_iounmap(dev, gart->regs);
 417         devm_kfree(dev, gart);
 418         gart_handle = NULL;
 419         return 0;
 420 }
 421
 422 const struct dev_pm_ops tegra_gart_pm_ops = {
 423         .suspend        = tegra_gart_suspend,
 424         .resume         = tegra_gart_resume,
 425 };
 426
 427 #ifdef CONFIG_OF
 428 static struct of_device_id tegra_gart_of_match[] __devinitdata = {
 429         { .compatible = "nvidia,tegra20-gart", },
 430         { },
 431 };
 432 MODULE_DEVICE_TABLE(of, tegra_gart_of_match);
 433 #endif
 434
 435 static struct platform_driver tegra_gart_driver = {
 436         .probe          = tegra_gart_probe,
 437         .remove         = tegra_gart_remove,
 438         .driver = {
 439                 .owner  = THIS_MODULE,
 440                 .name   = "tegra-gart",
 441                 .pm     = &tegra_gart_pm_ops,
 442                 .of_match_table = of_match_ptr(tegra_gart_of_match),
 443         },
 444 };
 445
 446 static int __devinit tegra_gart_init(void)
 447 {
 448         bus_set_iommu(&platform_bus_type, &gart_iommu_ops);
 449         return platform_driver_register(&tegra_gart_driver);
 450 }
 451
 452 static void __exit tegra_gart_exit(void)
 453 {
 454         platform_driver_unregister(&tegra_gart_driver);
 455 }
 456
 457 subsys_initcall(tegra_gart_init);
 458 module_exit(tegra_gart_exit);
 459
 460 MODULE_DESCRIPTION("IOMMU API for GART in Tegra20");
 461 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
 462 MODULE_ALIAS("platform:tegra-gart");
 463 MODULE_LICENSE("GPL v2");