?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
staging: rtl819su: update MgntQuery_MgntFrameTxRate()
[linux-2.6/libata-dev.git] / drivers / ata / libahci.c
blob261f86d102e8ba520105dfd10efac3930a9d7a12
1 /*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47 #include "ahci.h"
48
49 static int ahci_skip_host_reset;
50 int ahci_ignore_sss;
51 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
52
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
58
59 static int ahci_enable_alpm(struct ata_port *ap,
60 enum link_pm policy);
61 static void ahci_disable_alpm(struct ata_port *ap);
62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 size_t size);
65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
66 ssize_t size);
67
68
69
70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
72 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74 static int ahci_port_start(struct ata_port *ap);
75 static void ahci_port_stop(struct ata_port *ap);
76 static void ahci_qc_prep(struct ata_queued_cmd *qc);
77 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78 static void ahci_freeze(struct ata_port *ap);
79 static void ahci_thaw(struct ata_port *ap);
80 static void ahci_enable_fbs(struct ata_port *ap);
81 static void ahci_disable_fbs(struct ata_port *ap);
82 static void ahci_pmp_attach(struct ata_port *ap);
83 static void ahci_pmp_detach(struct ata_port *ap);
84 static int ahci_softreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static void ahci_postreset(struct ata_link *link, unsigned int *class);
89 static void ahci_error_handler(struct ata_port *ap);
90 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
91 static int ahci_port_resume(struct ata_port *ap);
92 static void ahci_dev_config(struct ata_device *dev);
93 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
94 u32 opts);
95 #ifdef CONFIG_PM
96 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
97 #endif
98 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
99 static ssize_t ahci_activity_store(struct ata_device *dev,
100 enum sw_activity val);
101 static void ahci_init_sw_activity(struct ata_link *link);
102
103 static ssize_t ahci_show_host_caps(struct device *dev,
104 struct device_attribute *attr, char *buf);
105 static ssize_t ahci_show_host_cap2(struct device *dev,
106 struct device_attribute *attr, char *buf);
107 static ssize_t ahci_show_host_version(struct device *dev,
108 struct device_attribute *attr, char *buf);
109 static ssize_t ahci_show_port_cmd(struct device *dev,
110 struct device_attribute *attr, char *buf);
111 static ssize_t ahci_read_em_buffer(struct device *dev,
112 struct device_attribute *attr, char *buf);
113 static ssize_t ahci_store_em_buffer(struct device *dev,
114 struct device_attribute *attr,
115 const char *buf, size_t size);
116
117 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
118 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
119 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
120 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
121 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
122 ahci_read_em_buffer, ahci_store_em_buffer);
123
124 static struct device_attribute *ahci_shost_attrs[] = {
125 &dev_attr_link_power_management_policy,
126 &dev_attr_em_message_type,
127 &dev_attr_em_message,
128 &dev_attr_ahci_host_caps,
129 &dev_attr_ahci_host_cap2,
130 &dev_attr_ahci_host_version,
131 &dev_attr_ahci_port_cmd,
132 &dev_attr_em_buffer,
133 NULL
134 };
135
136 static struct device_attribute *ahci_sdev_attrs[] = {
137 &dev_attr_sw_activity,
138 &dev_attr_unload_heads,
139 NULL
140 };
141
142 struct scsi_host_template ahci_sht = {
143 ATA_NCQ_SHT("ahci"),
144 .can_queue = AHCI_MAX_CMDS - 1,
145 .sg_tablesize = AHCI_MAX_SG,
146 .dma_boundary = AHCI_DMA_BOUNDARY,
147 .shost_attrs = ahci_shost_attrs,
148 .sdev_attrs = ahci_sdev_attrs,
149 };
150 EXPORT_SYMBOL_GPL(ahci_sht);
151
152 struct ata_port_operations ahci_ops = {
153 .inherits = &sata_pmp_port_ops,
154
155 .qc_defer = ahci_pmp_qc_defer,
156 .qc_prep = ahci_qc_prep,
157 .qc_issue = ahci_qc_issue,
158 .qc_fill_rtf = ahci_qc_fill_rtf,
159
160 .freeze = ahci_freeze,
161 .thaw = ahci_thaw,
162 .softreset = ahci_softreset,
163 .hardreset = ahci_hardreset,
164 .postreset = ahci_postreset,
165 .pmp_softreset = ahci_softreset,
166 .error_handler = ahci_error_handler,
167 .post_internal_cmd = ahci_post_internal_cmd,
168 .dev_config = ahci_dev_config,
169
170 .scr_read = ahci_scr_read,
171 .scr_write = ahci_scr_write,
172 .pmp_attach = ahci_pmp_attach,
173 .pmp_detach = ahci_pmp_detach,
174
175 .enable_pm = ahci_enable_alpm,
176 .disable_pm = ahci_disable_alpm,
177 .em_show = ahci_led_show,
178 .em_store = ahci_led_store,
179 .sw_activity_show = ahci_activity_show,
180 .sw_activity_store = ahci_activity_store,
181 #ifdef CONFIG_PM
182 .port_suspend = ahci_port_suspend,
183 .port_resume = ahci_port_resume,
184 #endif
185 .port_start = ahci_port_start,
186 .port_stop = ahci_port_stop,
187 };
188 EXPORT_SYMBOL_GPL(ahci_ops);
189
190 int ahci_em_messages = 1;
191 EXPORT_SYMBOL_GPL(ahci_em_messages);
192 module_param(ahci_em_messages, int, 0444);
193 /* add other LED protocol types when they become supported */
194 MODULE_PARM_DESC(ahci_em_messages,
195 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
196
197 static void ahci_enable_ahci(void __iomem *mmio)
198 {
199 int i;
200 u32 tmp;
201
202 /* turn on AHCI_EN */
203 tmp = readl(mmio + HOST_CTL);
204 if (tmp & HOST_AHCI_EN)
205 return;
206
207 /* Some controllers need AHCI_EN to be written multiple times.
208 * Try a few times before giving up.
209 */
210 for (i = 0; i < 5; i++) {
211 tmp |= HOST_AHCI_EN;
212 writel(tmp, mmio + HOST_CTL);
213 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
214 if (tmp & HOST_AHCI_EN)
215 return;
216 msleep(10);
217 }
218
219 WARN_ON(1);
220 }
221
222 static ssize_t ahci_show_host_caps(struct device *dev,
223 struct device_attribute *attr, char *buf)
224 {
225 struct Scsi_Host *shost = class_to_shost(dev);
226 struct ata_port *ap = ata_shost_to_port(shost);
227 struct ahci_host_priv *hpriv = ap->host->private_data;
228
229 return sprintf(buf, "%x\n", hpriv->cap);
230 }
231
232 static ssize_t ahci_show_host_cap2(struct device *dev,
233 struct device_attribute *attr, char *buf)
234 {
235 struct Scsi_Host *shost = class_to_shost(dev);
236 struct ata_port *ap = ata_shost_to_port(shost);
237 struct ahci_host_priv *hpriv = ap->host->private_data;
238
239 return sprintf(buf, "%x\n", hpriv->cap2);
240 }
241
242 static ssize_t ahci_show_host_version(struct device *dev,
243 struct device_attribute *attr, char *buf)
244 {
245 struct Scsi_Host *shost = class_to_shost(dev);
246 struct ata_port *ap = ata_shost_to_port(shost);
247 struct ahci_host_priv *hpriv = ap->host->private_data;
248 void __iomem *mmio = hpriv->mmio;
249
250 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
251 }
252
253 static ssize_t ahci_show_port_cmd(struct device *dev,
254 struct device_attribute *attr, char *buf)
255 {
256 struct Scsi_Host *shost = class_to_shost(dev);
257 struct ata_port *ap = ata_shost_to_port(shost);
258 void __iomem *port_mmio = ahci_port_base(ap);
259
260 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
261 }
262
263 static ssize_t ahci_read_em_buffer(struct device *dev,
264 struct device_attribute *attr, char *buf)
265 {
266 struct Scsi_Host *shost = class_to_shost(dev);
267 struct ata_port *ap = ata_shost_to_port(shost);
268 struct ahci_host_priv *hpriv = ap->host->private_data;
269 void __iomem *mmio = hpriv->mmio;
270 void __iomem *em_mmio = mmio + hpriv->em_loc;
271 u32 em_ctl, msg;
272 unsigned long flags;
273 size_t count;
274 int i;
275
276 spin_lock_irqsave(ap->lock, flags);
277
278 em_ctl = readl(mmio + HOST_EM_CTL);
279 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
280 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
281 spin_unlock_irqrestore(ap->lock, flags);
282 return -EINVAL;
283 }
284
285 if (!(em_ctl & EM_CTL_MR)) {
286 spin_unlock_irqrestore(ap->lock, flags);
287 return -EAGAIN;
288 }
289
290 if (!(em_ctl & EM_CTL_SMB))
291 em_mmio += hpriv->em_buf_sz;
292
293 count = hpriv->em_buf_sz;
294
295 /* the count should not be larger than PAGE_SIZE */
296 if (count > PAGE_SIZE) {
297 if (printk_ratelimit())
298 ata_port_printk(ap, KERN_WARNING,
299 "EM read buffer size too large: "
300 "buffer size %u, page size %lu\n",
301 hpriv->em_buf_sz, PAGE_SIZE);
302 count = PAGE_SIZE;
303 }
304
305 for (i = 0; i < count; i += 4) {
306 msg = readl(em_mmio + i);
307 buf[i] = msg & 0xff;
308 buf[i + 1] = (msg >> 8) & 0xff;
309 buf[i + 2] = (msg >> 16) & 0xff;
310 buf[i + 3] = (msg >> 24) & 0xff;
311 }
312
313 spin_unlock_irqrestore(ap->lock, flags);
314
315 return i;
316 }
317
318 static ssize_t ahci_store_em_buffer(struct device *dev,
319 struct device_attribute *attr,
320 const char *buf, size_t size)
321 {
322 struct Scsi_Host *shost = class_to_shost(dev);
323 struct ata_port *ap = ata_shost_to_port(shost);
324 struct ahci_host_priv *hpriv = ap->host->private_data;
325 void __iomem *mmio = hpriv->mmio;
326 void __iomem *em_mmio = mmio + hpriv->em_loc;
327 u32 em_ctl, msg;
328 unsigned long flags;
329 int i;
330
331 /* check size validity */
332 if (!(ap->flags & ATA_FLAG_EM) ||
333 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
334 size % 4 || size > hpriv->em_buf_sz)
335 return -EINVAL;
336
337 spin_lock_irqsave(ap->lock, flags);
338
339 em_ctl = readl(mmio + HOST_EM_CTL);
340 if (em_ctl & EM_CTL_TM) {
341 spin_unlock_irqrestore(ap->lock, flags);
342 return -EBUSY;
343 }
344
345 for (i = 0; i < size; i += 4) {
346 msg = buf[i] | buf[i + 1] << 8 |
347 buf[i + 2] << 16 | buf[i + 3] << 24;
348 writel(msg, em_mmio + i);
349 }
350
351 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
352
353 spin_unlock_irqrestore(ap->lock, flags);
354
355 return size;
356 }
357
358 /**
359 * ahci_save_initial_config - Save and fixup initial config values
360 * @dev: target AHCI device
361 * @hpriv: host private area to store config values
362 * @force_port_map: force port map to a specified value
363 * @mask_port_map: mask out particular bits from port map
364 *
365 * Some registers containing configuration info might be setup by
366 * BIOS and might be cleared on reset. This function saves the
367 * initial values of those registers into @hpriv such that they
368 * can be restored after controller reset.
369 *
370 * If inconsistent, config values are fixed up by this function.
371 *
372 * LOCKING:
373 * None.
374 */
375 void ahci_save_initial_config(struct device *dev,
376 struct ahci_host_priv *hpriv,
377 unsigned int force_port_map,
378 unsigned int mask_port_map)
379 {
380 void __iomem *mmio = hpriv->mmio;
381 u32 cap, cap2, vers, port_map;
382 int i;
383
384 /* make sure AHCI mode is enabled before accessing CAP */
385 ahci_enable_ahci(mmio);
386
387 /* Values prefixed with saved_ are written back to host after
388 * reset. Values without are used for driver operation.
389 */
390 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
391 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
392
393 /* CAP2 register is only defined for AHCI 1.2 and later */
394 vers = readl(mmio + HOST_VERSION);
395 if ((vers >> 16) > 1 ||
396 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
397 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
398 else
399 hpriv->saved_cap2 = cap2 = 0;
400
401 /* some chips have errata preventing 64bit use */
402 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
403 dev_printk(KERN_INFO, dev,
404 "controller can't do 64bit DMA, forcing 32bit\n");
405 cap &= ~HOST_CAP_64;
406 }
407
408 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
409 dev_printk(KERN_INFO, dev,
410 "controller can't do NCQ, turning off CAP_NCQ\n");
411 cap &= ~HOST_CAP_NCQ;
412 }
413
414 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
415 dev_printk(KERN_INFO, dev,
416 "controller can do NCQ, turning on CAP_NCQ\n");
417 cap |= HOST_CAP_NCQ;
418 }
419
420 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
421 dev_printk(KERN_INFO, dev,
422 "controller can't do PMP, turning off CAP_PMP\n");
423 cap &= ~HOST_CAP_PMP;
424 }
425
426 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
427 dev_printk(KERN_INFO, dev,
428 "controller can't do SNTF, turning off CAP_SNTF\n");
429 cap &= ~HOST_CAP_SNTF;
430 }
431
432 if (force_port_map && port_map != force_port_map) {
433 dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",
434 port_map, force_port_map);
435 port_map = force_port_map;
436 }
437
438 if (mask_port_map) {
439 dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n",
440 port_map,
441 port_map & mask_port_map);
442 port_map &= mask_port_map;
443 }
444
445 /* cross check port_map and cap.n_ports */
446 if (port_map) {
447 int map_ports = 0;
448
449 for (i = 0; i < AHCI_MAX_PORTS; i++)
450 if (port_map & (1 << i))
451 map_ports++;
452
453 /* If PI has more ports than n_ports, whine, clear
454 * port_map and let it be generated from n_ports.
455 */
456 if (map_ports > ahci_nr_ports(cap)) {
457 dev_printk(KERN_WARNING, dev,
458 "implemented port map (0x%x) contains more "
459 "ports than nr_ports (%u), using nr_ports\n",
460 port_map, ahci_nr_ports(cap));
461 port_map = 0;
462 }
463 }
464
465 /* fabricate port_map from cap.nr_ports */
466 if (!port_map) {
467 port_map = (1 << ahci_nr_ports(cap)) - 1;
468 dev_printk(KERN_WARNING, dev,
469 "forcing PORTS_IMPL to 0x%x\n", port_map);
470
471 /* write the fixed up value to the PI register */
472 hpriv->saved_port_map = port_map;
473 }
474
475 /* record values to use during operation */
476 hpriv->cap = cap;
477 hpriv->cap2 = cap2;
478 hpriv->port_map = port_map;
479 }
480 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
481
482 /**
483 * ahci_restore_initial_config - Restore initial config
484 * @host: target ATA host
485 *
486 * Restore initial config stored by ahci_save_initial_config().
487 *
488 * LOCKING:
489 * None.
490 */
491 static void ahci_restore_initial_config(struct ata_host *host)
492 {
493 struct ahci_host_priv *hpriv = host->private_data;
494 void __iomem *mmio = hpriv->mmio;
495
496 writel(hpriv->saved_cap, mmio + HOST_CAP);
497 if (hpriv->saved_cap2)
498 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
499 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
500 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
501 }
502
503 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
504 {
505 static const int offset[] = {
506 [SCR_STATUS] = PORT_SCR_STAT,
507 [SCR_CONTROL] = PORT_SCR_CTL,
508 [SCR_ERROR] = PORT_SCR_ERR,
509 [SCR_ACTIVE] = PORT_SCR_ACT,
510 [SCR_NOTIFICATION] = PORT_SCR_NTF,
511 };
512 struct ahci_host_priv *hpriv = ap->host->private_data;
513
514 if (sc_reg < ARRAY_SIZE(offset) &&
515 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
516 return offset[sc_reg];
517 return 0;
518 }
519
520 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
521 {
522 void __iomem *port_mmio = ahci_port_base(link->ap);
523 int offset = ahci_scr_offset(link->ap, sc_reg);
524
525 if (offset) {
526 *val = readl(port_mmio + offset);
527 return 0;
528 }
529 return -EINVAL;
530 }
531
532 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
533 {
534 void __iomem *port_mmio = ahci_port_base(link->ap);
535 int offset = ahci_scr_offset(link->ap, sc_reg);
536
537 if (offset) {
538 writel(val, port_mmio + offset);
539 return 0;
540 }
541 return -EINVAL;
542 }
543
544 void ahci_start_engine(struct ata_port *ap)
545 {
546 void __iomem *port_mmio = ahci_port_base(ap);
547 u32 tmp;
548
549 /* start DMA */
550 tmp = readl(port_mmio + PORT_CMD);
551 tmp |= PORT_CMD_START;
552 writel(tmp, port_mmio + PORT_CMD);
553 readl(port_mmio + PORT_CMD); /* flush */
554 }
555 EXPORT_SYMBOL_GPL(ahci_start_engine);
556
557 int ahci_stop_engine(struct ata_port *ap)
558 {
559 void __iomem *port_mmio = ahci_port_base(ap);
560 u32 tmp;
561
562 tmp = readl(port_mmio + PORT_CMD);
563
564 /* check if the HBA is idle */
565 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
566 return 0;
567
568 /* setting HBA to idle */
569 tmp &= ~PORT_CMD_START;
570 writel(tmp, port_mmio + PORT_CMD);
571
572 /* wait for engine to stop. This could be as long as 500 msec */
573 tmp = ata_wait_register(port_mmio + PORT_CMD,
574 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
575 if (tmp & PORT_CMD_LIST_ON)
576 return -EIO;
577
578 return 0;
579 }
580 EXPORT_SYMBOL_GPL(ahci_stop_engine);
581
582 static void ahci_start_fis_rx(struct ata_port *ap)
583 {
584 void __iomem *port_mmio = ahci_port_base(ap);
585 struct ahci_host_priv *hpriv = ap->host->private_data;
586 struct ahci_port_priv *pp = ap->private_data;
587 u32 tmp;
588
589 /* set FIS registers */
590 if (hpriv->cap & HOST_CAP_64)
591 writel((pp->cmd_slot_dma >> 16) >> 16,
592 port_mmio + PORT_LST_ADDR_HI);
593 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
594
595 if (hpriv->cap & HOST_CAP_64)
596 writel((pp->rx_fis_dma >> 16) >> 16,
597 port_mmio + PORT_FIS_ADDR_HI);
598 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
599
600 /* enable FIS reception */
601 tmp = readl(port_mmio + PORT_CMD);
602 tmp |= PORT_CMD_FIS_RX;
603 writel(tmp, port_mmio + PORT_CMD);
604
605 /* flush */
606 readl(port_mmio + PORT_CMD);
607 }
608
609 static int ahci_stop_fis_rx(struct ata_port *ap)
610 {
611 void __iomem *port_mmio = ahci_port_base(ap);
612 u32 tmp;
613
614 /* disable FIS reception */
615 tmp = readl(port_mmio + PORT_CMD);
616 tmp &= ~PORT_CMD_FIS_RX;
617 writel(tmp, port_mmio + PORT_CMD);
618
619 /* wait for completion, spec says 500ms, give it 1000 */
620 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
621 PORT_CMD_FIS_ON, 10, 1000);
622 if (tmp & PORT_CMD_FIS_ON)
623 return -EBUSY;
624
625 return 0;
626 }
627
628 static void ahci_power_up(struct ata_port *ap)
629 {
630 struct ahci_host_priv *hpriv = ap->host->private_data;
631 void __iomem *port_mmio = ahci_port_base(ap);
632 u32 cmd;
633
634 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
635
636 /* spin up device */
637 if (hpriv->cap & HOST_CAP_SSS) {
638 cmd |= PORT_CMD_SPIN_UP;
639 writel(cmd, port_mmio + PORT_CMD);
640 }
641
642 /* wake up link */
643 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
644 }
645
646 static void ahci_disable_alpm(struct ata_port *ap)
647 {
648 struct ahci_host_priv *hpriv = ap->host->private_data;
649 void __iomem *port_mmio = ahci_port_base(ap);
650 u32 cmd;
651 struct ahci_port_priv *pp = ap->private_data;
652
653 /* IPM bits should be disabled by libata-core */
654 /* get the existing command bits */
655 cmd = readl(port_mmio + PORT_CMD);
656
657 /* disable ALPM and ASP */
658 cmd &= ~PORT_CMD_ASP;
659 cmd &= ~PORT_CMD_ALPE;
660
661 /* force the interface back to active */
662 cmd |= PORT_CMD_ICC_ACTIVE;
663
664 /* write out new cmd value */
665 writel(cmd, port_mmio + PORT_CMD);
666 cmd = readl(port_mmio + PORT_CMD);
667
668 /* wait 10ms to be sure we've come out of any low power state */
669 msleep(10);
670
671 /* clear out any PhyRdy stuff from interrupt status */
672 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
673
674 /* go ahead and clean out PhyRdy Change from Serror too */
675 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
676
677 /*
678 * Clear flag to indicate that we should ignore all PhyRdy
679 * state changes
680 */
681 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
682
683 /*
684 * Enable interrupts on Phy Ready.
685 */
686 pp->intr_mask |= PORT_IRQ_PHYRDY;
687 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
688
689 /*
690 * don't change the link pm policy - we can be called
691 * just to turn of link pm temporarily
692 */
693 }
694
695 static int ahci_enable_alpm(struct ata_port *ap,
696 enum link_pm policy)
697 {
698 struct ahci_host_priv *hpriv = ap->host->private_data;
699 void __iomem *port_mmio = ahci_port_base(ap);
700 u32 cmd;
701 struct ahci_port_priv *pp = ap->private_data;
702 u32 asp;
703
704 /* Make sure the host is capable of link power management */
705 if (!(hpriv->cap & HOST_CAP_ALPM))
706 return -EINVAL;
707
708 switch (policy) {
709 case MAX_PERFORMANCE:
710 case NOT_AVAILABLE:
711 /*
712 * if we came here with NOT_AVAILABLE,
713 * it just means this is the first time we
714 * have tried to enable - default to max performance,
715 * and let the user go to lower power modes on request.
716 */
717 ahci_disable_alpm(ap);
718 return 0;
719 case MIN_POWER:
720 /* configure HBA to enter SLUMBER */
721 asp = PORT_CMD_ASP;
722 break;
723 case MEDIUM_POWER:
724 /* configure HBA to enter PARTIAL */
725 asp = 0;
726 break;
727 default:
728 return -EINVAL;
729 }
730
731 /*
732 * Disable interrupts on Phy Ready. This keeps us from
733 * getting woken up due to spurious phy ready interrupts
734 * TBD - Hot plug should be done via polling now, is
735 * that even supported?
736 */
737 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
738 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
739
740 /*
741 * Set a flag to indicate that we should ignore all PhyRdy
742 * state changes since these can happen now whenever we
743 * change link state
744 */
745 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
746
747 /* get the existing command bits */
748 cmd = readl(port_mmio + PORT_CMD);
749
750 /*
751 * Set ASP based on Policy
752 */
753 cmd |= asp;
754
755 /*
756 * Setting this bit will instruct the HBA to aggressively
757 * enter a lower power link state when it's appropriate and
758 * based on the value set above for ASP
759 */
760 cmd |= PORT_CMD_ALPE;
761
762 /* write out new cmd value */
763 writel(cmd, port_mmio + PORT_CMD);
764 cmd = readl(port_mmio + PORT_CMD);
765
766 /* IPM bits should be set by libata-core */
767 return 0;
768 }
769
770 #ifdef CONFIG_PM
771 static void ahci_power_down(struct ata_port *ap)
772 {
773 struct ahci_host_priv *hpriv = ap->host->private_data;
774 void __iomem *port_mmio = ahci_port_base(ap);
775 u32 cmd, scontrol;
776
777 if (!(hpriv->cap & HOST_CAP_SSS))
778 return;
779
780 /* put device into listen mode, first set PxSCTL.DET to 0 */
781 scontrol = readl(port_mmio + PORT_SCR_CTL);
782 scontrol &= ~0xf;
783 writel(scontrol, port_mmio + PORT_SCR_CTL);
784
785 /* then set PxCMD.SUD to 0 */
786 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
787 cmd &= ~PORT_CMD_SPIN_UP;
788 writel(cmd, port_mmio + PORT_CMD);
789 }
790 #endif
791
792 static void ahci_start_port(struct ata_port *ap)
793 {
794 struct ahci_port_priv *pp = ap->private_data;
795 struct ata_link *link;
796 struct ahci_em_priv *emp;
797 ssize_t rc;
798 int i;
799
800 /* enable FIS reception */
801 ahci_start_fis_rx(ap);
802
803 /* enable DMA */
804 ahci_start_engine(ap);
805
806 /* turn on LEDs */
807 if (ap->flags & ATA_FLAG_EM) {
808 ata_for_each_link(link, ap, EDGE) {
809 emp = &pp->em_priv[link->pmp];
810
811 /* EM Transmit bit maybe busy during init */
812 for (i = 0; i < EM_MAX_RETRY; i++) {
813 rc = ahci_transmit_led_message(ap,
814 emp->led_state,
815 4);
816 if (rc == -EBUSY)
817 msleep(1);
818 else
819 break;
820 }
821 }
822 }
823
824 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
825 ata_for_each_link(link, ap, EDGE)
826 ahci_init_sw_activity(link);
827
828 }
829
830 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
831 {
832 int rc;
833
834 /* disable DMA */
835 rc = ahci_stop_engine(ap);
836 if (rc) {
837 *emsg = "failed to stop engine";
838 return rc;
839 }
840
841 /* disable FIS reception */
842 rc = ahci_stop_fis_rx(ap);
843 if (rc) {
844 *emsg = "failed stop FIS RX";
845 return rc;
846 }
847
848 return 0;
849 }
850
851 int ahci_reset_controller(struct ata_host *host)
852 {
853 struct ahci_host_priv *hpriv = host->private_data;
854 void __iomem *mmio = hpriv->mmio;
855 u32 tmp;
856
857 /* we must be in AHCI mode, before using anything
858 * AHCI-specific, such as HOST_RESET.
859 */
860 ahci_enable_ahci(mmio);
861
862 /* global controller reset */
863 if (!ahci_skip_host_reset) {
864 tmp = readl(mmio + HOST_CTL);
865 if ((tmp & HOST_RESET) == 0) {
866 writel(tmp | HOST_RESET, mmio + HOST_CTL);
867 readl(mmio + HOST_CTL); /* flush */
868 }
869
870 /*
871 * to perform host reset, OS should set HOST_RESET
872 * and poll until this bit is read to be "0".
873 * reset must complete within 1 second, or
874 * the hardware should be considered fried.
875 */
876 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
877 HOST_RESET, 10, 1000);
878
879 if (tmp & HOST_RESET) {
880 dev_printk(KERN_ERR, host->dev,
881 "controller reset failed (0x%x)\n", tmp);
882 return -EIO;
883 }
884
885 /* turn on AHCI mode */
886 ahci_enable_ahci(mmio);
887
888 /* Some registers might be cleared on reset. Restore
889 * initial values.
890 */
891 ahci_restore_initial_config(host);
892 } else
893 dev_printk(KERN_INFO, host->dev,
894 "skipping global host reset\n");
895
896 return 0;
897 }
898 EXPORT_SYMBOL_GPL(ahci_reset_controller);
899
900 static void ahci_sw_activity(struct ata_link *link)
901 {
902 struct ata_port *ap = link->ap;
903 struct ahci_port_priv *pp = ap->private_data;
904 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
905
906 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
907 return;
908
909 emp->activity++;
910 if (!timer_pending(&emp->timer))
911 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
912 }
913
914 static void ahci_sw_activity_blink(unsigned long arg)
915 {
916 struct ata_link *link = (struct ata_link *)arg;
917 struct ata_port *ap = link->ap;
918 struct ahci_port_priv *pp = ap->private_data;
919 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
920 unsigned long led_message = emp->led_state;
921 u32 activity_led_state;
922 unsigned long flags;
923
924 led_message &= EM_MSG_LED_VALUE;
925 led_message |= ap->port_no | (link->pmp << 8);
926
927 /* check to see if we've had activity. If so,
928 * toggle state of LED and reset timer. If not,
929 * turn LED to desired idle state.
930 */
931 spin_lock_irqsave(ap->lock, flags);
932 if (emp->saved_activity != emp->activity) {
933 emp->saved_activity = emp->activity;
934 /* get the current LED state */
935 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
936
937 if (activity_led_state)
938 activity_led_state = 0;
939 else
940 activity_led_state = 1;
941
942 /* clear old state */
943 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
944
945 /* toggle state */
946 led_message |= (activity_led_state << 16);
947 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
948 } else {
949 /* switch to idle */
950 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
951 if (emp->blink_policy == BLINK_OFF)
952 led_message |= (1 << 16);
953 }
954 spin_unlock_irqrestore(ap->lock, flags);
955 ahci_transmit_led_message(ap, led_message, 4);
956 }
957
958 static void ahci_init_sw_activity(struct ata_link *link)
959 {
960 struct ata_port *ap = link->ap;
961 struct ahci_port_priv *pp = ap->private_data;
962 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
963
964 /* init activity stats, setup timer */
965 emp->saved_activity = emp->activity = 0;
966 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
967
968 /* check our blink policy and set flag for link if it's enabled */
969 if (emp->blink_policy)
970 link->flags |= ATA_LFLAG_SW_ACTIVITY;
971 }
972
973 int ahci_reset_em(struct ata_host *host)
974 {
975 struct ahci_host_priv *hpriv = host->private_data;
976 void __iomem *mmio = hpriv->mmio;
977 u32 em_ctl;
978
979 em_ctl = readl(mmio + HOST_EM_CTL);
980 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
981 return -EINVAL;
982
983 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
984 return 0;
985 }
986 EXPORT_SYMBOL_GPL(ahci_reset_em);
987
988 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
989 ssize_t size)
990 {
991 struct ahci_host_priv *hpriv = ap->host->private_data;
992 struct ahci_port_priv *pp = ap->private_data;
993 void __iomem *mmio = hpriv->mmio;
994 u32 em_ctl;
995 u32 message[] = {0, 0};
996 unsigned long flags;
997 int pmp;
998 struct ahci_em_priv *emp;
999
1000 /* get the slot number from the message */
1001 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1002 if (pmp < EM_MAX_SLOTS)
1003 emp = &pp->em_priv[pmp];
1004 else
1005 return -EINVAL;
1006
1007 spin_lock_irqsave(ap->lock, flags);
1008
1009 /*
1010 * if we are still busy transmitting a previous message,
1011 * do not allow
1012 */
1013 em_ctl = readl(mmio + HOST_EM_CTL);
1014 if (em_ctl & EM_CTL_TM) {
1015 spin_unlock_irqrestore(ap->lock, flags);
1016 return -EBUSY;
1017 }
1018
1019 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1020 /*
1021 * create message header - this is all zero except for
1022 * the message size, which is 4 bytes.
1023 */
1024 message[0] |= (4 << 8);
1025
1026 /* ignore 0:4 of byte zero, fill in port info yourself */
1027 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1028
1029 /* write message to EM_LOC */
1030 writel(message[0], mmio + hpriv->em_loc);
1031 writel(message[1], mmio + hpriv->em_loc+4);
1032
1033 /*
1034 * tell hardware to transmit the message
1035 */
1036 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1037 }
1038
1039 /* save off new led state for port/slot */
1040 emp->led_state = state;
1041
1042 spin_unlock_irqrestore(ap->lock, flags);
1043 return size;
1044 }
1045
1046 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1047 {
1048 struct ahci_port_priv *pp = ap->private_data;
1049 struct ata_link *link;
1050 struct ahci_em_priv *emp;
1051 int rc = 0;
1052
1053 ata_for_each_link(link, ap, EDGE) {
1054 emp = &pp->em_priv[link->pmp];
1055 rc += sprintf(buf, "%lx\n", emp->led_state);
1056 }
1057 return rc;
1058 }
1059
1060 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1061 size_t size)
1062 {
1063 int state;
1064 int pmp;
1065 struct ahci_port_priv *pp = ap->private_data;
1066 struct ahci_em_priv *emp;
1067
1068 state = simple_strtoul(buf, NULL, 0);
1069
1070 /* get the slot number from the message */
1071 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1072 if (pmp < EM_MAX_SLOTS)
1073 emp = &pp->em_priv[pmp];
1074 else
1075 return -EINVAL;
1076
1077 /* mask off the activity bits if we are in sw_activity
1078 * mode, user should turn off sw_activity before setting
1079 * activity led through em_message
1080 */
1081 if (emp->blink_policy)
1082 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1083
1084 return ahci_transmit_led_message(ap, state, size);
1085 }
1086
1087 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1088 {
1089 struct ata_link *link = dev->link;
1090 struct ata_port *ap = link->ap;
1091 struct ahci_port_priv *pp = ap->private_data;
1092 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1093 u32 port_led_state = emp->led_state;
1094
1095 /* save the desired Activity LED behavior */
1096 if (val == OFF) {
1097 /* clear LFLAG */
1098 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1099
1100 /* set the LED to OFF */
1101 port_led_state &= EM_MSG_LED_VALUE_OFF;
1102 port_led_state |= (ap->port_no | (link->pmp << 8));
1103 ahci_transmit_led_message(ap, port_led_state, 4);
1104 } else {
1105 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1106 if (val == BLINK_OFF) {
1107 /* set LED to ON for idle */
1108 port_led_state &= EM_MSG_LED_VALUE_OFF;
1109 port_led_state |= (ap->port_no | (link->pmp << 8));
1110 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1111 ahci_transmit_led_message(ap, port_led_state, 4);
1112 }
1113 }
1114 emp->blink_policy = val;
1115 return 0;
1116 }
1117
1118 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1119 {
1120 struct ata_link *link = dev->link;
1121 struct ata_port *ap = link->ap;
1122 struct ahci_port_priv *pp = ap->private_data;
1123 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1124
1125 /* display the saved value of activity behavior for this
1126 * disk.
1127 */
1128 return sprintf(buf, "%d\n", emp->blink_policy);
1129 }
1130
1131 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1132 int port_no, void __iomem *mmio,
1133 void __iomem *port_mmio)
1134 {
1135 const char *emsg = NULL;
1136 int rc;
1137 u32 tmp;
1138
1139 /* make sure port is not active */
1140 rc = ahci_deinit_port(ap, &emsg);
1141 if (rc)
1142 dev_warn(dev, "%s (%d)\n", emsg, rc);
1143
1144 /* clear SError */
1145 tmp = readl(port_mmio + PORT_SCR_ERR);
1146 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1147 writel(tmp, port_mmio + PORT_SCR_ERR);
1148
1149 /* clear port IRQ */
1150 tmp = readl(port_mmio + PORT_IRQ_STAT);
1151 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1152 if (tmp)
1153 writel(tmp, port_mmio + PORT_IRQ_STAT);
1154
1155 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1156 }
1157
1158 void ahci_init_controller(struct ata_host *host)
1159 {
1160 struct ahci_host_priv *hpriv = host->private_data;
1161 void __iomem *mmio = hpriv->mmio;
1162 int i;
1163 void __iomem *port_mmio;
1164 u32 tmp;
1165
1166 for (i = 0; i < host->n_ports; i++) {
1167 struct ata_port *ap = host->ports[i];
1168
1169 port_mmio = ahci_port_base(ap);
1170 if (ata_port_is_dummy(ap))
1171 continue;
1172
1173 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1174 }
1175
1176 tmp = readl(mmio + HOST_CTL);
1177 VPRINTK("HOST_CTL 0x%x\n", tmp);
1178 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1179 tmp = readl(mmio + HOST_CTL);
1180 VPRINTK("HOST_CTL 0x%x\n", tmp);
1181 }
1182 EXPORT_SYMBOL_GPL(ahci_init_controller);
1183
1184 static void ahci_dev_config(struct ata_device *dev)
1185 {
1186 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1187
1188 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1189 dev->max_sectors = 255;
1190 ata_dev_printk(dev, KERN_INFO,
1191 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1192 }
1193 }
1194
1195 static unsigned int ahci_dev_classify(struct ata_port *ap)
1196 {
1197 void __iomem *port_mmio = ahci_port_base(ap);
1198 struct ata_taskfile tf;
1199 u32 tmp;
1200
1201 tmp = readl(port_mmio + PORT_SIG);
1202 tf.lbah = (tmp >> 24) & 0xff;
1203 tf.lbam = (tmp >> 16) & 0xff;
1204 tf.lbal = (tmp >> 8) & 0xff;
1205 tf.nsect = (tmp) & 0xff;
1206
1207 return ata_dev_classify(&tf);
1208 }
1209
1210 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1211 u32 opts)
1212 {
1213 dma_addr_t cmd_tbl_dma;
1214
1215 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1216
1217 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1218 pp->cmd_slot[tag].status = 0;
1219 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1220 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1221 }
1222
1223 int ahci_kick_engine(struct ata_port *ap)
1224 {
1225 void __iomem *port_mmio = ahci_port_base(ap);
1226 struct ahci_host_priv *hpriv = ap->host->private_data;
1227 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1228 u32 tmp;
1229 int busy, rc;
1230
1231 /* stop engine */
1232 rc = ahci_stop_engine(ap);
1233 if (rc)
1234 goto out_restart;
1235
1236 /* need to do CLO?
1237 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1238 */
1239 busy = status & (ATA_BUSY | ATA_DRQ);
1240 if (!busy && !sata_pmp_attached(ap)) {
1241 rc = 0;
1242 goto out_restart;
1243 }
1244
1245 if (!(hpriv->cap & HOST_CAP_CLO)) {
1246 rc = -EOPNOTSUPP;
1247 goto out_restart;
1248 }
1249
1250 /* perform CLO */
1251 tmp = readl(port_mmio + PORT_CMD);
1252 tmp |= PORT_CMD_CLO;
1253 writel(tmp, port_mmio + PORT_CMD);
1254
1255 rc = 0;
1256 tmp = ata_wait_register(port_mmio + PORT_CMD,
1257 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1258 if (tmp & PORT_CMD_CLO)
1259 rc = -EIO;
1260
1261 /* restart engine */
1262 out_restart:
1263 ahci_start_engine(ap);
1264 return rc;
1265 }
1266 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1267
1268 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1269 struct ata_taskfile *tf, int is_cmd, u16 flags,
1270 unsigned long timeout_msec)
1271 {
1272 const u32 cmd_fis_len = 5; /* five dwords */
1273 struct ahci_port_priv *pp = ap->private_data;
1274 void __iomem *port_mmio = ahci_port_base(ap);
1275 u8 *fis = pp->cmd_tbl;
1276 u32 tmp;
1277
1278 /* prep the command */
1279 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1280 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1281
1282 /* issue & wait */
1283 writel(1, port_mmio + PORT_CMD_ISSUE);
1284
1285 if (timeout_msec) {
1286 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1287 1, timeout_msec);
1288 if (tmp & 0x1) {
1289 ahci_kick_engine(ap);
1290 return -EBUSY;
1291 }
1292 } else
1293 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1294
1295 return 0;
1296 }
1297
1298 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1299 int pmp, unsigned long deadline,
1300 int (*check_ready)(struct ata_link *link))
1301 {
1302 struct ata_port *ap = link->ap;
1303 struct ahci_host_priv *hpriv = ap->host->private_data;
1304 const char *reason = NULL;
1305 unsigned long now, msecs;
1306 struct ata_taskfile tf;
1307 int rc;
1308
1309 DPRINTK("ENTER\n");
1310
1311 /* prepare for SRST (AHCI-1.1 10.4.1) */
1312 rc = ahci_kick_engine(ap);
1313 if (rc && rc != -EOPNOTSUPP)
1314 ata_link_printk(link, KERN_WARNING,
1315 "failed to reset engine (errno=%d)\n", rc);
1316
1317 ata_tf_init(link->device, &tf);
1318
1319 /* issue the first D2H Register FIS */
1320 msecs = 0;
1321 now = jiffies;
1322 if (time_after(now, deadline))
1323 msecs = jiffies_to_msecs(deadline - now);
1324
1325 tf.ctl |= ATA_SRST;
1326 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1327 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1328 rc = -EIO;
1329 reason = "1st FIS failed";
1330 goto fail;
1331 }
1332
1333 /* spec says at least 5us, but be generous and sleep for 1ms */
1334 msleep(1);
1335
1336 /* issue the second D2H Register FIS */
1337 tf.ctl &= ~ATA_SRST;
1338 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1339
1340 /* wait for link to become ready */
1341 rc = ata_wait_after_reset(link, deadline, check_ready);
1342 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1343 /*
1344 * Workaround for cases where link online status can't
1345 * be trusted. Treat device readiness timeout as link
1346 * offline.
1347 */
1348 ata_link_printk(link, KERN_INFO,
1349 "device not ready, treating as offline\n");
1350 *class = ATA_DEV_NONE;
1351 } else if (rc) {
1352 /* link occupied, -ENODEV too is an error */
1353 reason = "device not ready";
1354 goto fail;
1355 } else
1356 *class = ahci_dev_classify(ap);
1357
1358 DPRINTK("EXIT, class=%u\n", *class);
1359 return 0;
1360
1361 fail:
1362 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1363 return rc;
1364 }
1365
1366 int ahci_check_ready(struct ata_link *link)
1367 {
1368 void __iomem *port_mmio = ahci_port_base(link->ap);
1369 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1370
1371 return ata_check_ready(status);
1372 }
1373 EXPORT_SYMBOL_GPL(ahci_check_ready);
1374
1375 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1376 unsigned long deadline)
1377 {
1378 int pmp = sata_srst_pmp(link);
1379
1380 DPRINTK("ENTER\n");
1381
1382 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1383 }
1384 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1385
1386 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1387 unsigned long deadline)
1388 {
1389 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1390 struct ata_port *ap = link->ap;
1391 struct ahci_port_priv *pp = ap->private_data;
1392 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1393 struct ata_taskfile tf;
1394 bool online;
1395 int rc;
1396
1397 DPRINTK("ENTER\n");
1398
1399 ahci_stop_engine(ap);
1400
1401 /* clear D2H reception area to properly wait for D2H FIS */
1402 ata_tf_init(link->device, &tf);
1403 tf.command = 0x80;
1404 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1405
1406 rc = sata_link_hardreset(link, timing, deadline, &online,
1407 ahci_check_ready);
1408
1409 ahci_start_engine(ap);
1410
1411 if (online)
1412 *class = ahci_dev_classify(ap);
1413
1414 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1415 return rc;
1416 }
1417
1418 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1419 {
1420 struct ata_port *ap = link->ap;
1421 void __iomem *port_mmio = ahci_port_base(ap);
1422 u32 new_tmp, tmp;
1423
1424 ata_std_postreset(link, class);
1425
1426 /* Make sure port's ATAPI bit is set appropriately */
1427 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1428 if (*class == ATA_DEV_ATAPI)
1429 new_tmp |= PORT_CMD_ATAPI;
1430 else
1431 new_tmp &= ~PORT_CMD_ATAPI;
1432 if (new_tmp != tmp) {
1433 writel(new_tmp, port_mmio + PORT_CMD);
1434 readl(port_mmio + PORT_CMD); /* flush */
1435 }
1436 }
1437
1438 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1439 {
1440 struct scatterlist *sg;
1441 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1442 unsigned int si;
1443
1444 VPRINTK("ENTER\n");
1445
1446 /*
1447 * Next, the S/G list.
1448 */
1449 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1450 dma_addr_t addr = sg_dma_address(sg);
1451 u32 sg_len = sg_dma_len(sg);
1452
1453 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1454 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1455 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1456 }
1457
1458 return si;
1459 }
1460
1461 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1462 {
1463 struct ata_port *ap = qc->ap;
1464 struct ahci_port_priv *pp = ap->private_data;
1465
1466 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1467 return ata_std_qc_defer(qc);
1468 else
1469 return sata_pmp_qc_defer_cmd_switch(qc);
1470 }
1471
1472 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1473 {
1474 struct ata_port *ap = qc->ap;
1475 struct ahci_port_priv *pp = ap->private_data;
1476 int is_atapi = ata_is_atapi(qc->tf.protocol);
1477 void *cmd_tbl;
1478 u32 opts;
1479 const u32 cmd_fis_len = 5; /* five dwords */
1480 unsigned int n_elem;
1481
1482 /*
1483 * Fill in command table information. First, the header,
1484 * a SATA Register - Host to Device command FIS.
1485 */
1486 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1487
1488 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1489 if (is_atapi) {
1490 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1491 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1492 }
1493
1494 n_elem = 0;
1495 if (qc->flags & ATA_QCFLAG_DMAMAP)
1496 n_elem = ahci_fill_sg(qc, cmd_tbl);
1497
1498 /*
1499 * Fill in command slot information.
1500 */
1501 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1502 if (qc->tf.flags & ATA_TFLAG_WRITE)
1503 opts |= AHCI_CMD_WRITE;
1504 if (is_atapi)
1505 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1506
1507 ahci_fill_cmd_slot(pp, qc->tag, opts);
1508 }
1509
1510 static void ahci_fbs_dec_intr(struct ata_port *ap)
1511 {
1512 struct ahci_port_priv *pp = ap->private_data;
1513 void __iomem *port_mmio = ahci_port_base(ap);
1514 u32 fbs = readl(port_mmio + PORT_FBS);
1515 int retries = 3;
1516
1517 DPRINTK("ENTER\n");
1518 BUG_ON(!pp->fbs_enabled);
1519
1520 /* time to wait for DEC is not specified by AHCI spec,
1521 * add a retry loop for safety.
1522 */
1523 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1524 fbs = readl(port_mmio + PORT_FBS);
1525 while ((fbs & PORT_FBS_DEC) && retries--) {
1526 udelay(1);
1527 fbs = readl(port_mmio + PORT_FBS);
1528 }
1529
1530 if (fbs & PORT_FBS_DEC)
1531 dev_printk(KERN_ERR, ap->host->dev,
1532 "failed to clear device error\n");
1533 }
1534
1535 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1536 {
1537 struct ahci_host_priv *hpriv = ap->host->private_data;
1538 struct ahci_port_priv *pp = ap->private_data;
1539 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1540 struct ata_link *link = NULL;
1541 struct ata_queued_cmd *active_qc;
1542 struct ata_eh_info *active_ehi;
1543 bool fbs_need_dec = false;
1544 u32 serror;
1545
1546 /* determine active link with error */
1547 if (pp->fbs_enabled) {
1548 void __iomem *port_mmio = ahci_port_base(ap);
1549 u32 fbs = readl(port_mmio + PORT_FBS);
1550 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1551
1552 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
1553 ata_link_online(&ap->pmp_link[pmp])) {
1554 link = &ap->pmp_link[pmp];
1555 fbs_need_dec = true;
1556 }
1557
1558 } else
1559 ata_for_each_link(link, ap, EDGE)
1560 if (ata_link_active(link))
1561 break;
1562
1563 if (!link)
1564 link = &ap->link;
1565
1566 active_qc = ata_qc_from_tag(ap, link->active_tag);
1567 active_ehi = &link->eh_info;
1568
1569 /* record irq stat */
1570 ata_ehi_clear_desc(host_ehi);
1571 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1572
1573 /* AHCI needs SError cleared; otherwise, it might lock up */
1574 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1575 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1576 host_ehi->serror |= serror;
1577
1578 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1579 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1580 irq_stat &= ~PORT_IRQ_IF_ERR;
1581
1582 if (irq_stat & PORT_IRQ_TF_ERR) {
1583 /* If qc is active, charge it; otherwise, the active
1584 * link. There's no active qc on NCQ errors. It will
1585 * be determined by EH by reading log page 10h.
1586 */
1587 if (active_qc)
1588 active_qc->err_mask |= AC_ERR_DEV;
1589 else
1590 active_ehi->err_mask |= AC_ERR_DEV;
1591
1592 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1593 host_ehi->serror &= ~SERR_INTERNAL;
1594 }
1595
1596 if (irq_stat & PORT_IRQ_UNK_FIS) {
1597 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1598
1599 active_ehi->err_mask |= AC_ERR_HSM;
1600 active_ehi->action |= ATA_EH_RESET;
1601 ata_ehi_push_desc(active_ehi,
1602 "unknown FIS %08x %08x %08x %08x" ,
1603 unk[0], unk[1], unk[2], unk[3]);
1604 }
1605
1606 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1607 active_ehi->err_mask |= AC_ERR_HSM;
1608 active_ehi->action |= ATA_EH_RESET;
1609 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1610 }
1611
1612 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1613 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1614 host_ehi->action |= ATA_EH_RESET;
1615 ata_ehi_push_desc(host_ehi, "host bus error");
1616 }
1617
1618 if (irq_stat & PORT_IRQ_IF_ERR) {
1619 if (fbs_need_dec)
1620 active_ehi->err_mask |= AC_ERR_DEV;
1621 else {
1622 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1623 host_ehi->action |= ATA_EH_RESET;
1624 }
1625
1626 ata_ehi_push_desc(host_ehi, "interface fatal error");
1627 }
1628
1629 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1630 ata_ehi_hotplugged(host_ehi);
1631 ata_ehi_push_desc(host_ehi, "%s",
1632 irq_stat & PORT_IRQ_CONNECT ?
1633 "connection status changed" : "PHY RDY changed");
1634 }
1635
1636 /* okay, let's hand over to EH */
1637
1638 if (irq_stat & PORT_IRQ_FREEZE)
1639 ata_port_freeze(ap);
1640 else if (fbs_need_dec) {
1641 ata_link_abort(link);
1642 ahci_fbs_dec_intr(ap);
1643 } else
1644 ata_port_abort(ap);
1645 }
1646
1647 static void ahci_port_intr(struct ata_port *ap)
1648 {
1649 void __iomem *port_mmio = ahci_port_base(ap);
1650 struct ata_eh_info *ehi = &ap->link.eh_info;
1651 struct ahci_port_priv *pp = ap->private_data;
1652 struct ahci_host_priv *hpriv = ap->host->private_data;
1653 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1654 u32 status, qc_active = 0;
1655 int rc;
1656
1657 status = readl(port_mmio + PORT_IRQ_STAT);
1658 writel(status, port_mmio + PORT_IRQ_STAT);
1659
1660 /* ignore BAD_PMP while resetting */
1661 if (unlikely(resetting))
1662 status &= ~PORT_IRQ_BAD_PMP;
1663
1664 /* If we are getting PhyRdy, this is
1665 * just a power state change, we should
1666 * clear out this, plus the PhyRdy/Comm
1667 * Wake bits from Serror
1668 */
1669 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1670 (status & PORT_IRQ_PHYRDY)) {
1671 status &= ~PORT_IRQ_PHYRDY;
1672 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
1673 }
1674
1675 if (unlikely(status & PORT_IRQ_ERROR)) {
1676 ahci_error_intr(ap, status);
1677 return;
1678 }
1679
1680 if (status & PORT_IRQ_SDB_FIS) {
1681 /* If SNotification is available, leave notification
1682 * handling to sata_async_notification(). If not,
1683 * emulate it by snooping SDB FIS RX area.
1684 *
1685 * Snooping FIS RX area is probably cheaper than
1686 * poking SNotification but some constrollers which
1687 * implement SNotification, ICH9 for example, don't
1688 * store AN SDB FIS into receive area.
1689 */
1690 if (hpriv->cap & HOST_CAP_SNTF)
1691 sata_async_notification(ap);
1692 else {
1693 /* If the 'N' bit in word 0 of the FIS is set,
1694 * we just received asynchronous notification.
1695 * Tell libata about it.
1696 *
1697 * Lack of SNotification should not appear in
1698 * ahci 1.2, so the workaround is unnecessary
1699 * when FBS is enabled.
1700 */
1701 if (pp->fbs_enabled)
1702 WARN_ON_ONCE(1);
1703 else {
1704 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1705 u32 f0 = le32_to_cpu(f[0]);
1706 if (f0 & (1 << 15))
1707 sata_async_notification(ap);
1708 }
1709 }
1710 }
1711
1712 /* pp->active_link is not reliable once FBS is enabled, both
1713 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1714 * NCQ and non-NCQ commands may be in flight at the same time.
1715 */
1716 if (pp->fbs_enabled) {
1717 if (ap->qc_active) {
1718 qc_active = readl(port_mmio + PORT_SCR_ACT);
1719 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1720 }
1721 } else {
1722 /* pp->active_link is valid iff any command is in flight */
1723 if (ap->qc_active && pp->active_link->sactive)
1724 qc_active = readl(port_mmio + PORT_SCR_ACT);
1725 else
1726 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1727 }
1728
1729
1730 rc = ata_qc_complete_multiple(ap, qc_active);
1731
1732 /* while resetting, invalid completions are expected */
1733 if (unlikely(rc < 0 && !resetting)) {
1734 ehi->err_mask |= AC_ERR_HSM;
1735 ehi->action |= ATA_EH_RESET;
1736 ata_port_freeze(ap);
1737 }
1738 }
1739
1740 irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1741 {
1742 struct ata_host *host = dev_instance;
1743 struct ahci_host_priv *hpriv;
1744 unsigned int i, handled = 0;
1745 void __iomem *mmio;
1746 u32 irq_stat, irq_masked;
1747
1748 VPRINTK("ENTER\n");
1749
1750 hpriv = host->private_data;
1751 mmio = hpriv->mmio;
1752
1753 /* sigh. 0xffffffff is a valid return from h/w */
1754 irq_stat = readl(mmio + HOST_IRQ_STAT);
1755 if (!irq_stat)
1756 return IRQ_NONE;
1757
1758 irq_masked = irq_stat & hpriv->port_map;
1759
1760 spin_lock(&host->lock);
1761
1762 for (i = 0; i < host->n_ports; i++) {
1763 struct ata_port *ap;
1764
1765 if (!(irq_masked & (1 << i)))
1766 continue;
1767
1768 ap = host->ports[i];
1769 if (ap) {
1770 ahci_port_intr(ap);
1771 VPRINTK("port %u\n", i);
1772 } else {
1773 VPRINTK("port %u (no irq)\n", i);
1774 if (ata_ratelimit())
1775 dev_printk(KERN_WARNING, host->dev,
1776 "interrupt on disabled port %u\n", i);
1777 }
1778
1779 handled = 1;
1780 }
1781
1782 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1783 * it should be cleared after all the port events are cleared;
1784 * otherwise, it will raise a spurious interrupt after each
1785 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1786 * information.
1787 *
1788 * Also, use the unmasked value to clear interrupt as spurious
1789 * pending event on a dummy port might cause screaming IRQ.
1790 */
1791 writel(irq_stat, mmio + HOST_IRQ_STAT);
1792
1793 spin_unlock(&host->lock);
1794
1795 VPRINTK("EXIT\n");
1796
1797 return IRQ_RETVAL(handled);
1798 }
1799 EXPORT_SYMBOL_GPL(ahci_interrupt);
1800
1801 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1802 {
1803 struct ata_port *ap = qc->ap;
1804 void __iomem *port_mmio = ahci_port_base(ap);
1805 struct ahci_port_priv *pp = ap->private_data;
1806
1807 /* Keep track of the currently active link. It will be used
1808 * in completion path to determine whether NCQ phase is in
1809 * progress.
1810 */
1811 pp->active_link = qc->dev->link;
1812
1813 if (qc->tf.protocol == ATA_PROT_NCQ)
1814 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1815
1816 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1817 u32 fbs = readl(port_mmio + PORT_FBS);
1818 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1819 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1820 writel(fbs, port_mmio + PORT_FBS);
1821 pp->fbs_last_dev = qc->dev->link->pmp;
1822 }
1823
1824 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1825
1826 ahci_sw_activity(qc->dev->link);
1827
1828 return 0;
1829 }
1830
1831 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1832 {
1833 struct ahci_port_priv *pp = qc->ap->private_data;
1834 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1835
1836 if (pp->fbs_enabled)
1837 d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1838
1839 ata_tf_from_fis(d2h_fis, &qc->result_tf);
1840 return true;
1841 }
1842
1843 static void ahci_freeze(struct ata_port *ap)
1844 {
1845 void __iomem *port_mmio = ahci_port_base(ap);
1846
1847 /* turn IRQ off */
1848 writel(0, port_mmio + PORT_IRQ_MASK);
1849 }
1850
1851 static void ahci_thaw(struct ata_port *ap)
1852 {
1853 struct ahci_host_priv *hpriv = ap->host->private_data;
1854 void __iomem *mmio = hpriv->mmio;
1855 void __iomem *port_mmio = ahci_port_base(ap);
1856 u32 tmp;
1857 struct ahci_port_priv *pp = ap->private_data;
1858
1859 /* clear IRQ */
1860 tmp = readl(port_mmio + PORT_IRQ_STAT);
1861 writel(tmp, port_mmio + PORT_IRQ_STAT);
1862 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1863
1864 /* turn IRQ back on */
1865 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1866 }
1867
1868 static void ahci_error_handler(struct ata_port *ap)
1869 {
1870 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1871 /* restart engine */
1872 ahci_stop_engine(ap);
1873 ahci_start_engine(ap);
1874 }
1875
1876 sata_pmp_error_handler(ap);
1877
1878 if (!ata_dev_enabled(ap->link.device))
1879 ahci_stop_engine(ap);
1880 }
1881
1882 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1883 {
1884 struct ata_port *ap = qc->ap;
1885
1886 /* make DMA engine forget about the failed command */
1887 if (qc->flags & ATA_QCFLAG_FAILED)
1888 ahci_kick_engine(ap);
1889 }
1890
1891 static void ahci_enable_fbs(struct ata_port *ap)
1892 {
1893 struct ahci_port_priv *pp = ap->private_data;
1894 void __iomem *port_mmio = ahci_port_base(ap);
1895 u32 fbs;
1896 int rc;
1897
1898 if (!pp->fbs_supported)
1899 return;
1900
1901 fbs = readl(port_mmio + PORT_FBS);
1902 if (fbs & PORT_FBS_EN) {
1903 pp->fbs_enabled = true;
1904 pp->fbs_last_dev = -1; /* initialization */
1905 return;
1906 }
1907
1908 rc = ahci_stop_engine(ap);
1909 if (rc)
1910 return;
1911
1912 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
1913 fbs = readl(port_mmio + PORT_FBS);
1914 if (fbs & PORT_FBS_EN) {
1915 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
1916 pp->fbs_enabled = true;
1917 pp->fbs_last_dev = -1; /* initialization */
1918 } else
1919 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
1920
1921 ahci_start_engine(ap);
1922 }
1923
1924 static void ahci_disable_fbs(struct ata_port *ap)
1925 {
1926 struct ahci_port_priv *pp = ap->private_data;
1927 void __iomem *port_mmio = ahci_port_base(ap);
1928 u32 fbs;
1929 int rc;
1930
1931 if (!pp->fbs_supported)
1932 return;
1933
1934 fbs = readl(port_mmio + PORT_FBS);
1935 if ((fbs & PORT_FBS_EN) == 0) {
1936 pp->fbs_enabled = false;
1937 return;
1938 }
1939
1940 rc = ahci_stop_engine(ap);
1941 if (rc)
1942 return;
1943
1944 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
1945 fbs = readl(port_mmio + PORT_FBS);
1946 if (fbs & PORT_FBS_EN)
1947 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
1948 else {
1949 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
1950 pp->fbs_enabled = false;
1951 }
1952
1953 ahci_start_engine(ap);
1954 }
1955
1956 static void ahci_pmp_attach(struct ata_port *ap)
1957 {
1958 void __iomem *port_mmio = ahci_port_base(ap);
1959 struct ahci_port_priv *pp = ap->private_data;
1960 u32 cmd;
1961
1962 cmd = readl(port_mmio + PORT_CMD);
1963 cmd |= PORT_CMD_PMP;
1964 writel(cmd, port_mmio + PORT_CMD);
1965
1966 ahci_enable_fbs(ap);
1967
1968 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1969 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1970 }
1971
1972 static void ahci_pmp_detach(struct ata_port *ap)
1973 {
1974 void __iomem *port_mmio = ahci_port_base(ap);
1975 struct ahci_port_priv *pp = ap->private_data;
1976 u32 cmd;
1977
1978 ahci_disable_fbs(ap);
1979
1980 cmd = readl(port_mmio + PORT_CMD);
1981 cmd &= ~PORT_CMD_PMP;
1982 writel(cmd, port_mmio + PORT_CMD);
1983
1984 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1985 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1986 }
1987
1988 static int ahci_port_resume(struct ata_port *ap)
1989 {
1990 ahci_power_up(ap);
1991 ahci_start_port(ap);
1992
1993 if (sata_pmp_attached(ap))
1994 ahci_pmp_attach(ap);
1995 else
1996 ahci_pmp_detach(ap);
1997
1998 return 0;
1999 }
2000
2001 #ifdef CONFIG_PM
2002 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2003 {
2004 const char *emsg = NULL;
2005 int rc;
2006
2007 rc = ahci_deinit_port(ap, &emsg);
2008 if (rc == 0)
2009 ahci_power_down(ap);
2010 else {
2011 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2012 ahci_start_port(ap);
2013 }
2014
2015 return rc;
2016 }
2017 #endif
2018
2019 static int ahci_port_start(struct ata_port *ap)
2020 {
2021 struct ahci_host_priv *hpriv = ap->host->private_data;
2022 struct device *dev = ap->host->dev;
2023 struct ahci_port_priv *pp;
2024 void *mem;
2025 dma_addr_t mem_dma;
2026 size_t dma_sz, rx_fis_sz;
2027
2028 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2029 if (!pp)
2030 return -ENOMEM;
2031
2032 /* check FBS capability */
2033 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2034 void __iomem *port_mmio = ahci_port_base(ap);
2035 u32 cmd = readl(port_mmio + PORT_CMD);
2036 if (cmd & PORT_CMD_FBSCP)
2037 pp->fbs_supported = true;
2038 else
2039 dev_printk(KERN_WARNING, dev,
2040 "The port is not capable of FBS\n");
2041 }
2042
2043 if (pp->fbs_supported) {
2044 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2045 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2046 } else {
2047 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2048 rx_fis_sz = AHCI_RX_FIS_SZ;
2049 }
2050
2051 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2052 if (!mem)
2053 return -ENOMEM;
2054 memset(mem, 0, dma_sz);
2055
2056 /*
2057 * First item in chunk of DMA memory: 32-slot command table,
2058 * 32 bytes each in size
2059 */
2060 pp->cmd_slot = mem;
2061 pp->cmd_slot_dma = mem_dma;
2062
2063 mem += AHCI_CMD_SLOT_SZ;
2064 mem_dma += AHCI_CMD_SLOT_SZ;
2065
2066 /*
2067 * Second item: Received-FIS area
2068 */
2069 pp->rx_fis = mem;
2070 pp->rx_fis_dma = mem_dma;
2071
2072 mem += rx_fis_sz;
2073 mem_dma += rx_fis_sz;
2074
2075 /*
2076 * Third item: data area for storing a single command
2077 * and its scatter-gather table
2078 */
2079 pp->cmd_tbl = mem;
2080 pp->cmd_tbl_dma = mem_dma;
2081
2082 /*
2083 * Save off initial list of interrupts to be enabled.
2084 * This could be changed later
2085 */
2086 pp->intr_mask = DEF_PORT_IRQ;
2087
2088 ap->private_data = pp;
2089
2090 /* engage engines, captain */
2091 return ahci_port_resume(ap);
2092 }
2093
2094 static void ahci_port_stop(struct ata_port *ap)
2095 {
2096 const char *emsg = NULL;
2097 int rc;
2098
2099 /* de-initialize port */
2100 rc = ahci_deinit_port(ap, &emsg);
2101 if (rc)
2102 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2103 }
2104
2105 void ahci_print_info(struct ata_host *host, const char *scc_s)
2106 {
2107 struct ahci_host_priv *hpriv = host->private_data;
2108 void __iomem *mmio = hpriv->mmio;
2109 u32 vers, cap, cap2, impl, speed;
2110 const char *speed_s;
2111
2112 vers = readl(mmio + HOST_VERSION);
2113 cap = hpriv->cap;
2114 cap2 = hpriv->cap2;
2115 impl = hpriv->port_map;
2116
2117 speed = (cap >> 20) & 0xf;
2118 if (speed == 1)
2119 speed_s = "1.5";
2120 else if (speed == 2)
2121 speed_s = "3";
2122 else if (speed == 3)
2123 speed_s = "6";
2124 else
2125 speed_s = "?";
2126
2127 dev_info(host->dev,
2128 "AHCI %02x%02x.%02x%02x "
2129 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2130 ,
2131
2132 (vers >> 24) & 0xff,
2133 (vers >> 16) & 0xff,
2134 (vers >> 8) & 0xff,
2135 vers & 0xff,
2136
2137 ((cap >> 8) & 0x1f) + 1,
2138 (cap & 0x1f) + 1,
2139 speed_s,
2140 impl,
2141 scc_s);
2142
2143 dev_info(host->dev,
2144 "flags: "
2145 "%s%s%s%s%s%s%s"
2146 "%s%s%s%s%s%s%s"
2147 "%s%s%s%s%s%s\n"
2148 ,
2149
2150 cap & HOST_CAP_64 ? "64bit " : "",
2151 cap & HOST_CAP_NCQ ? "ncq " : "",
2152 cap & HOST_CAP_SNTF ? "sntf " : "",
2153 cap & HOST_CAP_MPS ? "ilck " : "",
2154 cap & HOST_CAP_SSS ? "stag " : "",
2155 cap & HOST_CAP_ALPM ? "pm " : "",
2156 cap & HOST_CAP_LED ? "led " : "",
2157 cap & HOST_CAP_CLO ? "clo " : "",
2158 cap & HOST_CAP_ONLY ? "only " : "",
2159 cap & HOST_CAP_PMP ? "pmp " : "",
2160 cap & HOST_CAP_FBS ? "fbs " : "",
2161 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2162 cap & HOST_CAP_SSC ? "slum " : "",
2163 cap & HOST_CAP_PART ? "part " : "",
2164 cap & HOST_CAP_CCC ? "ccc " : "",
2165 cap & HOST_CAP_EMS ? "ems " : "",
2166 cap & HOST_CAP_SXS ? "sxs " : "",
2167 cap2 & HOST_CAP2_APST ? "apst " : "",
2168 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2169 cap2 & HOST_CAP2_BOH ? "boh " : ""
2170 );
2171 }
2172 EXPORT_SYMBOL_GPL(ahci_print_info);
2173
2174 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2175 struct ata_port_info *pi)
2176 {
2177 u8 messages;
2178 void __iomem *mmio = hpriv->mmio;
2179 u32 em_loc = readl(mmio + HOST_EM_LOC);
2180 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2181
2182 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2183 return;
2184
2185 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2186
2187 if (messages) {
2188 /* store em_loc */
2189 hpriv->em_loc = ((em_loc >> 16) * 4);
2190 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2191 hpriv->em_msg_type = messages;
2192 pi->flags |= ATA_FLAG_EM;
2193 if (!(em_ctl & EM_CTL_ALHD))
2194 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2195 }
2196 }
2197 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2198
2199 MODULE_AUTHOR("Jeff Garzik");
2200 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2201 MODULE_LICENSE("GPL");
Linux 2.6 libata-dev (mirror)