2 * linux/drivers/serial/cpm_uart.c
4 * Driver for CPM (SCC/SMC) serial ports; CPM1 definitions
6 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
7 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
9 * Copyright (C) 2004 Freescale Semiconductor, Inc.
10 * (C) 2004 Intracom, S.A.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/config.h>
29 #include <linux/module.h>
30 #include <linux/tty.h>
31 #include <linux/ioport.h>
32 #include <linux/init.h>
33 #include <linux/serial.h>
34 #include <linux/console.h>
35 #include <linux/sysrq.h>
36 #include <linux/device.h>
37 #include <linux/bootmem.h>
38 #include <linux/dma-mapping.h>
43 #include <linux/serial_core.h>
44 #include <linux/kernel.h>
48 /**************************************************************/
50 void cpm_line_cr_cmd(int line
, int cmd
)
53 volatile cpm8xx_t
*cp
= cpmp
;
57 val
= mk_cr_cmd(CPM_CR_CH_SMC1
, cmd
) | CPM_CR_FLG
;
60 val
= mk_cr_cmd(CPM_CR_CH_SMC2
, cmd
) | CPM_CR_FLG
;
63 val
= mk_cr_cmd(CPM_CR_CH_SCC1
, cmd
) | CPM_CR_FLG
;
66 val
= mk_cr_cmd(CPM_CR_CH_SCC2
, cmd
) | CPM_CR_FLG
;
69 val
= mk_cr_cmd(CPM_CR_CH_SCC3
, cmd
) | CPM_CR_FLG
;
72 val
= mk_cr_cmd(CPM_CR_CH_SCC4
, cmd
) | CPM_CR_FLG
;
79 while (cp
->cp_cpcr
& CPM_CR_FLG
) ;
82 void smc1_lineif(struct uart_cpm_port
*pinfo
)
87 void smc2_lineif(struct uart_cpm_port
*pinfo
)
92 void scc1_lineif(struct uart_cpm_port
*pinfo
)
94 /* XXX SCC1: insert port configuration here */
98 void scc2_lineif(struct uart_cpm_port
*pinfo
)
100 /* XXX SCC2: insert port configuration here */
104 void scc3_lineif(struct uart_cpm_port
*pinfo
)
106 /* XXX SCC3: insert port configuration here */
110 void scc4_lineif(struct uart_cpm_port
*pinfo
)
112 /* XXX SCC4: insert port configuration here */
117 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
118 * receive buffer descriptors from dual port ram, and a character
119 * buffer area from host mem. If we are allocating for the console we need
120 * to do it from bootmem
122 int cpm_uart_allocbuf(struct uart_cpm_port
*pinfo
, unsigned int is_con
)
128 dma_addr_t dma_addr
= 0;
130 pr_debug("CPM uart[%d]:allocbuf\n", pinfo
->port
.line
);
132 dpmemsz
= sizeof(cbd_t
) * (pinfo
->rx_nrfifos
+ pinfo
->tx_nrfifos
);
133 dp_offset
= cpm_dpalloc(dpmemsz
, 8);
134 if (IS_DPERR(dp_offset
)) {
136 "cpm_uart_cpm1.c: could not allocate buffer descriptors\n");
139 dp_mem
= cpm_dpram_addr(dp_offset
);
141 memsz
= L1_CACHE_ALIGN(pinfo
->rx_nrfifos
* pinfo
->rx_fifosize
) +
142 L1_CACHE_ALIGN(pinfo
->tx_nrfifos
* pinfo
->tx_fifosize
);
144 /* was hostalloc but changed cause it blows away the */
145 /* large tlb mapping when pinning the kernel area */
146 mem_addr
= (u8
*) cpm_dpram_addr(cpm_dpalloc(memsz
, 8));
149 mem_addr
= dma_alloc_coherent(NULL
, memsz
, &dma_addr
,
152 if (mem_addr
== NULL
) {
153 cpm_dpfree(dp_offset
);
155 "cpm_uart_cpm1.c: could not allocate coherent memory\n");
159 pinfo
->dp_addr
= dp_offset
;
160 pinfo
->mem_addr
= mem_addr
;
161 pinfo
->dma_addr
= dma_addr
;
163 pinfo
->rx_buf
= mem_addr
;
164 pinfo
->tx_buf
= pinfo
->rx_buf
+ L1_CACHE_ALIGN(pinfo
->rx_nrfifos
165 * pinfo
->rx_fifosize
);
167 pinfo
->rx_bd_base
= (volatile cbd_t
*)dp_mem
;
168 pinfo
->tx_bd_base
= pinfo
->rx_bd_base
+ pinfo
->rx_nrfifos
;
173 void cpm_uart_freebuf(struct uart_cpm_port
*pinfo
)
175 dma_free_coherent(NULL
, L1_CACHE_ALIGN(pinfo
->rx_nrfifos
*
176 pinfo
->rx_fifosize
) +
177 L1_CACHE_ALIGN(pinfo
->tx_nrfifos
*
178 pinfo
->tx_fifosize
), pinfo
->mem_addr
,
181 cpm_dpfree(pinfo
->dp_addr
);
184 /* Setup any dynamic params in the uart desc */
185 int cpm_uart_init_portdesc(void)
187 pr_debug("CPM uart[-]:init portdesc\n");
190 #ifdef CONFIG_SERIAL_CPM_SMC1
191 cpm_uart_ports
[UART_SMC1
].smcp
= &cpmp
->cp_smc
[0];
193 * Is SMC1 being relocated?
195 # ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH
196 cpm_uart_ports
[UART_SMC1
].smcup
=
197 (smc_uart_t
*) & cpmp
->cp_dparam
[0x3C0];
199 cpm_uart_ports
[UART_SMC1
].smcup
=
200 (smc_uart_t
*) & cpmp
->cp_dparam
[PROFF_SMC1
];
202 cpm_uart_ports
[UART_SMC1
].port
.mapbase
=
203 (unsigned long)&cpmp
->cp_smc
[0];
204 cpm_uart_ports
[UART_SMC1
].smcp
->smc_smcm
|= (SMCM_RX
| SMCM_TX
);
205 cpm_uart_ports
[UART_SMC1
].smcp
->smc_smcmr
&= ~(SMCMR_REN
| SMCMR_TEN
);
206 cpm_uart_ports
[UART_SMC1
].port
.uartclk
= (((bd_t
*) __res
)->bi_intfreq
);
207 cpm_uart_port_map
[cpm_uart_nr
++] = UART_SMC1
;
210 #ifdef CONFIG_SERIAL_CPM_SMC2
211 cpm_uart_ports
[UART_SMC2
].smcp
= &cpmp
->cp_smc
[1];
212 cpm_uart_ports
[UART_SMC2
].smcup
=
213 (smc_uart_t
*) & cpmp
->cp_dparam
[PROFF_SMC2
];
214 cpm_uart_ports
[UART_SMC2
].port
.mapbase
=
215 (unsigned long)&cpmp
->cp_smc
[1];
216 cpm_uart_ports
[UART_SMC2
].smcp
->smc_smcm
|= (SMCM_RX
| SMCM_TX
);
217 cpm_uart_ports
[UART_SMC2
].smcp
->smc_smcmr
&= ~(SMCMR_REN
| SMCMR_TEN
);
218 cpm_uart_ports
[UART_SMC2
].port
.uartclk
= (((bd_t
*) __res
)->bi_intfreq
);
219 cpm_uart_port_map
[cpm_uart_nr
++] = UART_SMC2
;
222 #ifdef CONFIG_SERIAL_CPM_SCC1
223 cpm_uart_ports
[UART_SCC1
].sccp
= &cpmp
->cp_scc
[0];
224 cpm_uart_ports
[UART_SCC1
].sccup
=
225 (scc_uart_t
*) & cpmp
->cp_dparam
[PROFF_SCC1
];
226 cpm_uart_ports
[UART_SCC1
].port
.mapbase
=
227 (unsigned long)&cpmp
->cp_scc
[0];
228 cpm_uart_ports
[UART_SCC1
].sccp
->scc_sccm
&=
229 ~(UART_SCCM_TX
| UART_SCCM_RX
);
230 cpm_uart_ports
[UART_SCC1
].sccp
->scc_gsmrl
&=
231 ~(SCC_GSMRL_ENR
| SCC_GSMRL_ENT
);
232 cpm_uart_ports
[UART_SCC1
].port
.uartclk
= (((bd_t
*) __res
)->bi_intfreq
);
233 cpm_uart_port_map
[cpm_uart_nr
++] = UART_SCC1
;
236 #ifdef CONFIG_SERIAL_CPM_SCC2
237 cpm_uart_ports
[UART_SCC2
].sccp
= &cpmp
->cp_scc
[1];
238 cpm_uart_ports
[UART_SCC2
].sccup
=
239 (scc_uart_t
*) & cpmp
->cp_dparam
[PROFF_SCC2
];
240 cpm_uart_ports
[UART_SCC2
].port
.mapbase
=
241 (unsigned long)&cpmp
->cp_scc
[1];
242 cpm_uart_ports
[UART_SCC2
].sccp
->scc_sccm
&=
243 ~(UART_SCCM_TX
| UART_SCCM_RX
);
244 cpm_uart_ports
[UART_SCC2
].sccp
->scc_gsmrl
&=
245 ~(SCC_GSMRL_ENR
| SCC_GSMRL_ENT
);
246 cpm_uart_ports
[UART_SCC2
].port
.uartclk
= (((bd_t
*) __res
)->bi_intfreq
);
247 cpm_uart_port_map
[cpm_uart_nr
++] = UART_SCC2
;
250 #ifdef CONFIG_SERIAL_CPM_SCC3
251 cpm_uart_ports
[UART_SCC3
].sccp
= &cpmp
->cp_scc
[2];
252 cpm_uart_ports
[UART_SCC3
].sccup
=
253 (scc_uart_t
*) & cpmp
->cp_dparam
[PROFF_SCC3
];
254 cpm_uart_ports
[UART_SCC3
].port
.mapbase
=
255 (unsigned long)&cpmp
->cp_scc
[2];
256 cpm_uart_ports
[UART_SCC3
].sccp
->scc_sccm
&=
257 ~(UART_SCCM_TX
| UART_SCCM_RX
);
258 cpm_uart_ports
[UART_SCC3
].sccp
->scc_gsmrl
&=
259 ~(SCC_GSMRL_ENR
| SCC_GSMRL_ENT
);
260 cpm_uart_ports
[UART_SCC3
].port
.uartclk
= (((bd_t
*) __res
)->bi_intfreq
);
261 cpm_uart_port_map
[cpm_uart_nr
++] = UART_SCC3
;
264 #ifdef CONFIG_SERIAL_CPM_SCC4
265 cpm_uart_ports
[UART_SCC4
].sccp
= &cpmp
->cp_scc
[3];
266 cpm_uart_ports
[UART_SCC4
].sccup
=
267 (scc_uart_t
*) & cpmp
->cp_dparam
[PROFF_SCC4
];
268 cpm_uart_ports
[UART_SCC4
].port
.mapbase
=
269 (unsigned long)&cpmp
->cp_scc
[3];
270 cpm_uart_ports
[UART_SCC4
].sccp
->scc_sccm
&=
271 ~(UART_SCCM_TX
| UART_SCCM_RX
);
272 cpm_uart_ports
[UART_SCC4
].sccp
->scc_gsmrl
&=
273 ~(SCC_GSMRL_ENR
| SCC_GSMRL_ENT
);
274 cpm_uart_ports
[UART_SCC4
].port
.uartclk
= (((bd_t
*) __res
)->bi_intfreq
);
275 cpm_uart_port_map
[cpm_uart_nr
++] = UART_SCC4
;