1 //------------------------------------------------------------------------------
2 // <copyright file="ar6k_events.c" company="Atheros">
3 // Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
6 // Permission to use, copy, modify, and/or distribute this software for any
7 // purpose with or without fee is hereby granted, provided that the above
8 // copyright notice and this permission notice appear in all copies.
10 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 //------------------------------------------------------------------------------
20 //==============================================================================
21 // AR6K Driver layer event handling (i.e. interrupts, message polling)
23 // Author(s): ="Atheros"
24 //==============================================================================
29 #include "AR6002/hw2.0/hw/mbox_host_reg.h"
31 #include "../htc_debug.h"
33 #include "htc_packet.h"
36 extern void AR6KFreeIOPacket(AR6K_DEVICE
*pDev
, HTC_PACKET
*pPacket
);
37 extern HTC_PACKET
*AR6KAllocIOPacket(AR6K_DEVICE
*pDev
);
39 static int DevServiceDebugInterrupt(AR6K_DEVICE
*pDev
);
41 #define DELAY_PER_INTERVAL_MS 10 /* 10 MS delay per polling interval */
43 /* completion routine for ALL HIF layer async I/O */
44 int DevRWCompletionHandler(void *context
, int status
)
46 HTC_PACKET
*pPacket
= (HTC_PACKET
*)context
;
48 AR_DEBUG_PRINTF(ATH_DEBUG_RECV
,
49 ("+DevRWCompletionHandler (Pkt:0x%lX) , Status: %d \n",
50 (unsigned long)pPacket
,
53 COMPLETE_HTC_PACKET(pPacket
,status
);
55 AR_DEBUG_PRINTF(ATH_DEBUG_RECV
,
56 ("-DevRWCompletionHandler\n"));
61 /* mailbox recv message polling */
62 int DevPollMboxMsgRecv(AR6K_DEVICE
*pDev
,
67 int timeout
= TimeoutMS
/DELAY_PER_INTERVAL_MS
;
69 A_ASSERT(timeout
> 0);
71 AR_DEBUG_PRINTF(ATH_DEBUG_RECV
,("+DevPollMboxMsgRecv \n"));
75 if (pDev
->GetPendingEventsFunc
!= NULL
) {
77 HIF_PENDING_EVENTS_INFO events
;
83 /* the HIF layer uses a special mechanism to get events, do this
85 status
= pDev
->GetPendingEventsFunc(pDev
->HIFDevice
,
90 AR_DEBUG_PRINTF(ATH_DEBUG_ERR
,("Failed to get pending events \n"));
94 if (events
.Events
& HIF_RECV_MSG_AVAIL
)
96 /* there is a message available, the lookahead should be valid now */
97 *pLookAhead
= events
.LookAhead
;
103 /* this is the standard HIF way.... */
104 /* load the register table */
105 status
= HIFReadWrite(pDev
->HIFDevice
,
106 HOST_INT_STATUS_ADDRESS
,
107 (u8
*)&pDev
->IrqProcRegisters
,
108 AR6K_IRQ_PROC_REGS_SIZE
,
109 HIF_RD_SYNC_BYTE_INC
,
113 AR_DEBUG_PRINTF(ATH_DEBUG_ERR
,("Failed to read register table \n"));
117 /* check for MBOX data and valid lookahead */
118 if (pDev
->IrqProcRegisters
.host_int_status
& (1 << HTC_MAILBOX
)) {
119 if (pDev
->IrqProcRegisters
.rx_lookahead_valid
& (1 << HTC_MAILBOX
))
121 /* mailbox has a message and the look ahead is valid */
122 *pLookAhead
= pDev
->IrqProcRegisters
.rx_lookahead
[HTC_MAILBOX
];
132 AR_DEBUG_PRINTF(ATH_DEBUG_ERR
, (" Timeout waiting for recv message \n"));
135 /* check if the target asserted */
136 if ( pDev
->IrqProcRegisters
.counter_int_status
& AR6K_TARGET_DEBUG_INTR_MASK
) {
137 /* target signaled an assert, process this pending interrupt
138 * this will call the target failure handler */
139 DevServiceDebugInterrupt(pDev
);
146 A_MDELAY(DELAY_PER_INTERVAL_MS
);
147 AR_DEBUG_PRINTF(ATH_DEBUG_RECV
,(" Retry Mbox Poll : %d \n",timeout
));
150 AR_DEBUG_PRINTF(ATH_DEBUG_RECV
,("-DevPollMboxMsgRecv \n"));
155 static int DevServiceCPUInterrupt(AR6K_DEVICE
*pDev
)
161 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
, ("CPU Interrupt\n"));
162 cpu_int_status
= pDev
->IrqProcRegisters
.cpu_int_status
&
163 pDev
->IrqEnableRegisters
.cpu_int_status_enable
;
164 A_ASSERT(cpu_int_status
);
165 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,
166 ("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n",
169 /* Clear the interrupt */
170 pDev
->IrqProcRegisters
.cpu_int_status
&= ~cpu_int_status
; /* W1C */
172 /* set up the register transfer buffer to hit the register 4 times , this is done
173 * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
174 * restrict bus transfer lengths to be a multiple of 4-bytes */
176 /* set W1C value to clear the interrupt, this hits the register first */
177 regBuffer
[0] = cpu_int_status
;
178 /* the remaining 4 values are set to zero which have no-effect */
183 status
= HIFReadWrite(pDev
->HIFDevice
,
184 CPU_INT_STATUS_ADDRESS
,
187 HIF_WR_SYNC_BYTE_FIX
,
190 A_ASSERT(status
== A_OK
);
195 static int DevServiceErrorInterrupt(AR6K_DEVICE
*pDev
)
201 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
, ("Error Interrupt\n"));
202 error_int_status
= pDev
->IrqProcRegisters
.error_int_status
& 0x0F;
203 A_ASSERT(error_int_status
);
204 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,
205 ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n",
208 if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status
)) {
210 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
, ("Error : Wakeup\n"));
213 if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status
)) {
215 AR_DEBUG_PRINTF(ATH_DEBUG_ERR
, ("Error : Rx Underflow\n"));
218 if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status
)) {
220 AR_DEBUG_PRINTF(ATH_DEBUG_ERR
, ("Error : Tx Overflow\n"));
223 /* Clear the interrupt */
224 pDev
->IrqProcRegisters
.error_int_status
&= ~error_int_status
; /* W1C */
226 /* set up the register transfer buffer to hit the register 4 times , this is done
227 * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
228 * restrict bus transfer lengths to be a multiple of 4-bytes */
230 /* set W1C value to clear the interrupt, this hits the register first */
231 regBuffer
[0] = error_int_status
;
232 /* the remaining 4 values are set to zero which have no-effect */
237 status
= HIFReadWrite(pDev
->HIFDevice
,
238 ERROR_INT_STATUS_ADDRESS
,
241 HIF_WR_SYNC_BYTE_FIX
,
244 A_ASSERT(status
== A_OK
);
248 static int DevServiceDebugInterrupt(AR6K_DEVICE
*pDev
)
253 /* Send a target failure event to the application */
254 AR_DEBUG_PRINTF(ATH_DEBUG_ERR
, ("Target debug interrupt\n"));
256 if (pDev
->TargetFailureCallback
!= NULL
) {
257 pDev
->TargetFailureCallback(pDev
->HTCContext
);
260 if (pDev
->GMboxEnabled
) {
261 DevNotifyGMboxTargetFailure(pDev
);
264 /* clear the interrupt , the debug error interrupt is
266 /* read counter to clear interrupt */
267 status
= HIFReadWrite(pDev
->HIFDevice
,
271 HIF_RD_SYNC_BYTE_INC
,
274 A_ASSERT(status
== A_OK
);
278 static int DevServiceCounterInterrupt(AR6K_DEVICE
*pDev
)
280 u8 counter_int_status
;
282 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
, ("Counter Interrupt\n"));
284 counter_int_status
= pDev
->IrqProcRegisters
.counter_int_status
&
285 pDev
->IrqEnableRegisters
.counter_int_status_enable
;
287 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,
288 ("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n",
289 counter_int_status
));
291 /* Check if the debug interrupt is pending
292 * NOTE: other modules like GMBOX may use the counter interrupt for
293 * credit flow control on other counters, we only need to check for the debug assertion
294 * counter interrupt */
295 if (counter_int_status
& AR6K_TARGET_DEBUG_INTR_MASK
) {
296 return DevServiceDebugInterrupt(pDev
);
302 /* callback when our fetch to get interrupt status registers completes */
303 static void DevGetEventAsyncHandler(void *Context
, HTC_PACKET
*pPacket
)
305 AR6K_DEVICE
*pDev
= (AR6K_DEVICE
*)Context
;
307 bool otherInts
= false;
309 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,("+DevGetEventAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev
));
313 if (pPacket
->Status
) {
314 AR_DEBUG_PRINTF(ATH_DEBUG_ERR
,
315 (" GetEvents I/O request failed, status:%d \n", pPacket
->Status
));
316 /* bail out, don't unmask HIF interrupt */
320 if (pDev
->GetPendingEventsFunc
!= NULL
) {
321 /* the HIF layer collected the information for us */
322 HIF_PENDING_EVENTS_INFO
*pEvents
= (HIF_PENDING_EVENTS_INFO
*)pPacket
->pBuffer
;
323 if (pEvents
->Events
& HIF_RECV_MSG_AVAIL
) {
324 lookAhead
= pEvents
->LookAhead
;
325 if (0 == lookAhead
) {
326 AR_DEBUG_PRINTF(ATH_DEBUG_ERR
,(" DevGetEventAsyncHandler1, lookAhead is zero! \n"));
329 if (pEvents
->Events
& HIF_OTHER_EVENTS
) {
333 /* standard interrupt table handling.... */
334 AR6K_IRQ_PROC_REGISTERS
*pReg
= (AR6K_IRQ_PROC_REGISTERS
*)pPacket
->pBuffer
;
337 host_int_status
= pReg
->host_int_status
& pDev
->IrqEnableRegisters
.int_status_enable
;
339 if (host_int_status
& (1 << HTC_MAILBOX
)) {
340 host_int_status
&= ~(1 << HTC_MAILBOX
);
341 if (pReg
->rx_lookahead_valid
& (1 << HTC_MAILBOX
)) {
342 /* mailbox has a message and the look ahead is valid */
343 lookAhead
= pReg
->rx_lookahead
[HTC_MAILBOX
];
344 if (0 == lookAhead
) {
345 AR_DEBUG_PRINTF(ATH_DEBUG_ERR
,(" DevGetEventAsyncHandler2, lookAhead is zero! \n"));
350 if (host_int_status
) {
351 /* there are other interrupts to handle */
356 if (otherInts
|| (lookAhead
== 0)) {
357 /* if there are other interrupts to process, we cannot do this in the async handler so
358 * ack the interrupt which will cause our sync handler to run again
359 * if however there are no more messages, we can now ack the interrupt */
360 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,
361 (" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n",
362 otherInts
, lookAhead
));
363 HIFAckInterrupt(pDev
->HIFDevice
);
368 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,
369 (" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n",
371 /* lookahead is non-zero and there are no other interrupts to service,
372 * go get the next message */
373 status
= pDev
->MessagePendingCallback(pDev
->HTCContext
, &lookAhead
, 1, NULL
, &fetched
);
375 if (!status
&& !fetched
) {
376 /* HTC layer could not pull out messages due to lack of resources, stop IRQ processing */
377 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,("MessagePendingCallback did not pull any messages, force-ack \n"));
378 DevAsyncIrqProcessComplete(pDev
);
384 /* free this IO packet */
385 AR6KFreeIOPacket(pDev
,pPacket
);
386 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,("-DevGetEventAsyncHandler \n"));
389 /* called by the HTC layer when it wants us to check if the device has any more pending
390 * recv messages, this starts off a series of async requests to read interrupt registers */
391 int DevCheckPendingRecvMsgsAsync(void *context
)
393 AR6K_DEVICE
*pDev
= (AR6K_DEVICE
*)context
;
395 HTC_PACKET
*pIOPacket
;
397 /* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can
398 * cause us to switch contexts */
400 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%lX)\n", (unsigned long)pDev
));
404 if (HIF_DEVICE_IRQ_SYNC_ONLY
== pDev
->HifIRQProcessingMode
) {
405 /* break the async processing chain right here, no need to continue.
406 * The DevDsrHandler() will handle things in a loop when things are driven
411 /* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake
412 * the target, if upper layers determine that we are in a low-throughput mode, we can
413 * rely on taking another interrupt rather than re-checking the status registers which can
414 * re-wake the target */
415 if (pDev
->RecheckIRQStatusCnt
== 0) {
416 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,("Bypassing IRQ Status re-check, re-acking HIF interrupts\n"));
418 HIFAckInterrupt(pDev
->HIFDevice
);
422 /* first allocate one of our HTC packets we created for async I/O
423 * we reuse HTC packet definitions so that we can use the completion mechanism
424 * in DevRWCompletionHandler() */
425 pIOPacket
= AR6KAllocIOPacket(pDev
);
427 if (NULL
== pIOPacket
) {
428 /* there should be only 1 asynchronous request out at a time to read these registers
429 * so this should actually never happen */
430 status
= A_NO_MEMORY
;
435 /* stick in our completion routine when the I/O operation completes */
436 pIOPacket
->Completion
= DevGetEventAsyncHandler
;
437 pIOPacket
->pContext
= pDev
;
439 if (pDev
->GetPendingEventsFunc
) {
440 /* HIF layer has it's own mechanism, pass the IO to it.. */
441 status
= pDev
->GetPendingEventsFunc(pDev
->HIFDevice
,
442 (HIF_PENDING_EVENTS_INFO
*)pIOPacket
->pBuffer
,
446 /* standard way, read the interrupt register table asynchronously again */
447 status
= HIFReadWrite(pDev
->HIFDevice
,
448 HOST_INT_STATUS_ADDRESS
,
450 AR6K_IRQ_PROC_REGS_SIZE
,
451 HIF_RD_ASYNC_BYTE_INC
,
455 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,(" Async IO issued to get interrupt status...\n"));
458 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,("-DevCheckPendingRecvMsgsAsync \n"));
463 void DevAsyncIrqProcessComplete(AR6K_DEVICE
*pDev
)
465 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,("DevAsyncIrqProcessComplete - forcing HIF IRQ ACK \n"));
466 HIFAckInterrupt(pDev
->HIFDevice
);
469 /* process pending interrupts synchronously */
470 static int ProcessPendingIRQs(AR6K_DEVICE
*pDev
, bool *pDone
, bool *pASyncProcessing
)
473 u8 host_int_status
= 0;
476 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,("+ProcessPendingIRQs: (dev: 0x%lX)\n", (unsigned long)pDev
));
478 /*** NOTE: the HIF implementation guarantees that the context of this call allows
479 * us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that
480 * can block or switch thread/task ontexts.
481 * This is a fully schedulable context.
485 if (pDev
->IrqEnableRegisters
.int_status_enable
== 0) {
486 /* interrupt enables have been cleared, do not try to process any pending interrupts that
487 * may result in more bus transactions. The target may be unresponsive at this
492 if (pDev
->GetPendingEventsFunc
!= NULL
) {
493 HIF_PENDING_EVENTS_INFO events
;
498 /* the HIF layer uses a special mechanism to get events
499 * get this synchronously */
500 status
= pDev
->GetPendingEventsFunc(pDev
->HIFDevice
,
508 if (events
.Events
& HIF_RECV_MSG_AVAIL
) {
509 lookAhead
= events
.LookAhead
;
510 if (0 == lookAhead
) {
511 AR_DEBUG_PRINTF(ATH_DEBUG_ERR
,(" ProcessPendingIRQs1 lookAhead is zero! \n"));
515 if (!(events
.Events
& HIF_OTHER_EVENTS
) ||
516 !(pDev
->IrqEnableRegisters
.int_status_enable
& OTHER_INTS_ENABLED
)) {
517 /* no need to read the register table, no other interesting interrupts.
518 * Some interfaces (like SPI) can shadow interrupt sources without
519 * requiring the host to do a full table read */
523 /* otherwise fall through and read the register table */
527 * Read the first 28 bytes of the HTC register table. This will yield us
528 * the value of different int status registers and the lookahead
530 * length = sizeof(int_status) + sizeof(cpu_int_status) +
531 * sizeof(error_int_status) + sizeof(counter_int_status) +
532 * sizeof(mbox_frame) + sizeof(rx_lookahead_valid) +
533 * sizeof(hole) + sizeof(rx_lookahead) +
534 * sizeof(int_status_enable) + sizeof(cpu_int_status_enable) +
535 * sizeof(error_status_enable) +
536 * sizeof(counter_int_status_enable);
539 #ifdef CONFIG_MMC_SDHCI_S3C
540 pDev
->IrqProcRegisters
.host_int_status
= 0;
541 pDev
->IrqProcRegisters
.rx_lookahead_valid
= 0;
542 pDev
->IrqProcRegisters
.host_int_status2
= 0;
543 pDev
->IrqProcRegisters
.rx_lookahead
[0] = 0;
544 pDev
->IrqProcRegisters
.rx_lookahead
[1] = 0xaaa5555;
545 #endif /* CONFIG_MMC_SDHCI_S3C */
546 status
= HIFReadWrite(pDev
->HIFDevice
,
547 HOST_INT_STATUS_ADDRESS
,
548 (u8
*)&pDev
->IrqProcRegisters
,
549 AR6K_IRQ_PROC_REGS_SIZE
,
550 HIF_RD_SYNC_BYTE_INC
,
557 #ifdef ATH_DEBUG_MODULE
558 if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ
)) {
559 DevDumpRegisters(pDev
,
560 &pDev
->IrqProcRegisters
,
561 &pDev
->IrqEnableRegisters
);
565 /* Update only those registers that are enabled */
566 host_int_status
= pDev
->IrqProcRegisters
.host_int_status
&
567 pDev
->IrqEnableRegisters
.int_status_enable
;
569 if (NULL
== pDev
->GetPendingEventsFunc
) {
570 /* only look at mailbox status if the HIF layer did not provide this function,
571 * on some HIF interfaces reading the RX lookahead is not valid to do */
572 if (host_int_status
& (1 << HTC_MAILBOX
)) {
573 /* mask out pending mailbox value, we use "lookAhead" as the real flag for
574 * mailbox processing below */
575 host_int_status
&= ~(1 << HTC_MAILBOX
);
576 if (pDev
->IrqProcRegisters
.rx_lookahead_valid
& (1 << HTC_MAILBOX
)) {
577 /* mailbox has a message and the look ahead is valid */
578 lookAhead
= pDev
->IrqProcRegisters
.rx_lookahead
[HTC_MAILBOX
];
579 if (0 == lookAhead
) {
580 AR_DEBUG_PRINTF(ATH_DEBUG_ERR
,(" ProcessPendingIRQs2, lookAhead is zero! \n"));
585 /* not valid to check if the HIF has another mechanism for reading mailbox pending status*/
586 host_int_status
&= ~(1 << HTC_MAILBOX
);
589 if (pDev
->GMboxEnabled
) {
590 /*call GMBOX layer to process any interrupts of interest */
591 status
= DevCheckGMboxInterrupts(pDev
);
599 /* did the interrupt status fetches succeed? */
604 if ((0 == host_int_status
) && (0 == lookAhead
)) {
605 /* nothing to process, the caller can use this to break out of a loop */
610 if (lookAhead
!= 0) {
613 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead
));
614 /* Mailbox Interrupt, the HTC layer may issue async requests to empty the
616 * When emptying the recv mailbox we use the async handler above called from the
617 * completion routine of the callers read request. This can improve performance
618 * by reducing context switching when we rapidly pull packets */
619 status
= pDev
->MessagePendingCallback(pDev
->HTCContext
, &lookAhead
, 1, pASyncProcessing
, &fetched
);
625 /* HTC could not pull any messages out due to lack of resources */
626 /* force DSR handler to ack the interrupt */
627 *pASyncProcessing
= false;
628 pDev
->RecheckIRQStatusCnt
= 0;
632 /* now handle the rest of them */
633 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,
634 (" Valid interrupt source(s) for OTHER interrupts: 0x%x\n",
637 if (HOST_INT_STATUS_CPU_GET(host_int_status
)) {
639 status
= DevServiceCPUInterrupt(pDev
);
645 if (HOST_INT_STATUS_ERROR_GET(host_int_status
)) {
646 /* Error Interrupt */
647 status
= DevServiceErrorInterrupt(pDev
);
653 if (HOST_INT_STATUS_COUNTER_GET(host_int_status
)) {
654 /* Counter Interrupt */
655 status
= DevServiceCounterInterrupt(pDev
);
663 /* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake
664 * the target, if upper layers determine that we are in a low-throughput mode, we can
665 * rely on taking another interrupt rather than re-checking the status registers which can
666 * re-wake the target.
668 * NOTE : for host interfaces that use the special GetPendingEventsFunc, this optimization cannot
669 * be used due to possible side-effects. For example, SPI requires the host to drain all
670 * messages from the mailbox before exiting the ISR routine. */
671 if (!(*pASyncProcessing
) && (pDev
->RecheckIRQStatusCnt
== 0) && (pDev
->GetPendingEventsFunc
== NULL
)) {
672 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,("Bypassing IRQ Status re-check, forcing done \n"));
676 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n",
677 *pDone
, *pASyncProcessing
, status
));
683 /* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/
684 int DevDsrHandler(void *context
)
686 AR6K_DEVICE
*pDev
= (AR6K_DEVICE
*)context
;
689 bool asyncProc
= false;
691 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,("+DevDsrHandler: (dev: 0x%lX)\n", (unsigned long)pDev
));
693 /* reset the recv counter that tracks when we need to yield from the DSR */
694 pDev
->CurrentDSRRecvCount
= 0;
695 /* reset counter used to flag a re-scan of IRQ status registers on the target */
696 pDev
->RecheckIRQStatusCnt
= 0;
699 status
= ProcessPendingIRQs(pDev
, &done
, &asyncProc
);
704 if (HIF_DEVICE_IRQ_SYNC_ONLY
== pDev
->HifIRQProcessingMode
) {
705 /* the HIF layer does not allow async IRQ processing, override the asyncProc flag */
707 /* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers.
708 * this has a nice side effect of blocking us until all async read requests are completed.
709 * This behavior is required on some HIF implementations that do not allow ASYNC
710 * processing in interrupt handlers (like Windows CE) */
712 if (pDev
->DSRCanYield
&& DEV_CHECK_RECV_YIELD(pDev
)) {
713 /* ProcessPendingIRQs() pulled enough recv messages to satisfy the yield count, stop
714 * checking for more messages and return */
720 /* the function performed some async I/O for performance, we
721 need to exit the ISR immediately, the check below will prevent the interrupt from being
722 Ack'd while we handle it asynchronously */
728 if (!status
&& !asyncProc
) {
729 /* Ack the interrupt only if :
730 * 1. we did not get any errors in processing interrupts
731 * 2. there are no outstanding async processing requests */
732 if (pDev
->DSRCanYield
) {
733 /* if the DSR can yield do not ACK the interrupt, there could be more pending messages.
734 * The HIF layer must ACK the interrupt on behalf of HTC */
735 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,(" Yield in effect (cur RX count: %d) \n", pDev
->CurrentDSRRecvCount
));
737 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,(" Acking interrupt from DevDsrHandler \n"));
738 HIFAckInterrupt(pDev
->HIFDevice
);
742 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ
,("-DevDsrHandler \n"));
746 #ifdef ATH_DEBUG_MODULE
747 void DumpAR6KDevState(AR6K_DEVICE
*pDev
)
750 AR6K_IRQ_ENABLE_REGISTERS regs
;
751 AR6K_IRQ_PROC_REGISTERS procRegs
;
754 /* copy into our temp area */
755 A_MEMCPY(®s
,&pDev
->IrqEnableRegisters
,AR6K_IRQ_ENABLE_REGS_SIZE
);
758 /* load the register table from the device */
759 status
= HIFReadWrite(pDev
->HIFDevice
,
760 HOST_INT_STATUS_ADDRESS
,
762 AR6K_IRQ_PROC_REGS_SIZE
,
763 HIF_RD_SYNC_BYTE_INC
,
767 AR_DEBUG_PRINTF(ATH_DEBUG_ERR
,
768 ("DumpAR6KDevState : Failed to read register table (%d) \n",status
));
772 DevDumpRegisters(pDev
,&procRegs
,®s
);
774 if (pDev
->GMboxInfo
.pStateDumpCallback
!= NULL
) {
775 pDev
->GMboxInfo
.pStateDumpCallback(pDev
->GMboxInfo
.pProtocolContext
);
778 /* dump any bus state at the HIF layer */
779 HIFConfigureDevice(pDev
->HIFDevice
,HIF_DEVICE_DEBUG_BUS_STATE
,NULL
,0);