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qlcnic: PCI ID addition
[linux-2.6/libata-dev.git] / drivers / net / qlcnic / qlcnic.h
blob1f5c10bc9376cf955d07f747d2a878d298b0e090
1 /*
2 * Copyright (C) 2009 - QLogic Corporation.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
22 *
23 */
24
25 #ifndef _QLCNIC_H_
26 #define _QLCNIC_H_
27
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/types.h>
31 #include <linux/ioport.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ip.h>
36 #include <linux/in.h>
37 #include <linux/tcp.h>
38 #include <linux/skbuff.h>
39 #include <linux/firmware.h>
40
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/timer.h>
44
45 #include <linux/vmalloc.h>
46
47 #include <linux/io.h>
48 #include <asm/byteorder.h>
49
50 #include "qlcnic_hdr.h"
51
52 #define _QLCNIC_LINUX_MAJOR 5
53 #define _QLCNIC_LINUX_MINOR 0
54 #define _QLCNIC_LINUX_SUBVERSION 8
55 #define QLCNIC_LINUX_VERSIONID "5.0.8"
56 #define QLCNIC_DRV_IDC_VER 0x01
57 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
58 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
59
60 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
61 #define _major(v) (((v) >> 24) & 0xff)
62 #define _minor(v) (((v) >> 16) & 0xff)
63 #define _build(v) ((v) & 0xffff)
64
65 /* version in image has weird encoding:
66 * 7:0 - major
67 * 15:8 - minor
68 * 31:16 - build (little endian)
69 */
70 #define QLCNIC_DECODE_VERSION(v) \
71 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
72
73 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
74 #define QLCNIC_NUM_FLASH_SECTORS (64)
75 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
76 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
77 * QLCNIC_FLASH_SECTOR_SIZE)
78
79 #define RCV_DESC_RINGSIZE(rds_ring) \
80 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
81 #define RCV_BUFF_RINGSIZE(rds_ring) \
82 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
83 #define STATUS_DESC_RINGSIZE(sds_ring) \
84 (sizeof(struct status_desc) * (sds_ring)->num_desc)
85 #define TX_BUFF_RINGSIZE(tx_ring) \
86 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
87 #define TX_DESC_RINGSIZE(tx_ring) \
88 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
89
90 #define QLCNIC_P3P_A0 0x50
91
92 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
93
94 #define FIRST_PAGE_GROUP_START 0
95 #define FIRST_PAGE_GROUP_END 0x100000
96
97 #define P3_MAX_MTU (9600)
98 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
99
100 #define QLCNIC_P3_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
101 #define QLCNIC_P3_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3_MAX_MTU)
102 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
103 #define QLCNIC_LRO_BUFFER_EXTRA 2048
104
105 /* Opcodes to be used with the commands */
106 #define TX_ETHER_PKT 0x01
107 #define TX_TCP_PKT 0x02
108 #define TX_UDP_PKT 0x03
109 #define TX_IP_PKT 0x04
110 #define TX_TCP_LSO 0x05
111 #define TX_TCP_LSO6 0x06
112 #define TX_IPSEC 0x07
113 #define TX_IPSEC_CMD 0x0a
114 #define TX_TCPV6_PKT 0x0b
115 #define TX_UDPV6_PKT 0x0c
116
117 /* Tx defines */
118 #define MAX_TSO_HEADER_DESC 2
119 #define MGMT_CMD_DESC_RESV 4
120 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
121 + MGMT_CMD_DESC_RESV)
122 #define QLCNIC_MAX_TX_TIMEOUTS 2
123
124 /*
125 * Following are the states of the Phantom. Phantom will set them and
126 * Host will read to check if the fields are correct.
127 */
128 #define PHAN_INITIALIZE_FAILED 0xffff
129 #define PHAN_INITIALIZE_COMPLETE 0xff01
130
131 /* Host writes the following to notify that it has done the init-handshake */
132 #define PHAN_INITIALIZE_ACK 0xf00f
133 #define PHAN_PEG_RCV_INITIALIZED 0xff01
134
135 #define NUM_RCV_DESC_RINGS 3
136 #define NUM_STS_DESC_RINGS 4
137
138 #define RCV_RING_NORMAL 0
139 #define RCV_RING_JUMBO 1
140
141 #define MIN_CMD_DESCRIPTORS 64
142 #define MIN_RCV_DESCRIPTORS 64
143 #define MIN_JUMBO_DESCRIPTORS 32
144
145 #define MAX_CMD_DESCRIPTORS 1024
146 #define MAX_RCV_DESCRIPTORS_1G 4096
147 #define MAX_RCV_DESCRIPTORS_10G 8192
148 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
149 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
150
151 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
152 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
153 #define MAX_RDS_RINGS 2
154
155 #define get_next_index(index, length) \
156 (((index) + 1) & ((length) - 1))
157
158 /*
159 * Following data structures describe the descriptors that will be used.
160 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
161 * we are doing LSO (above the 1500 size packet) only.
162 */
163
164 #define FLAGS_VLAN_TAGGED 0x10
165 #define FLAGS_VLAN_OOB 0x40
166
167 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
168 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
169 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
170 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
171 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
172 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
173
174 #define qlcnic_set_tx_port(_desc, _port) \
175 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
176
177 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
178 ((_desc)->flags_opcode |= \
179 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
180
181 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
182 ((_desc)->nfrags__length = \
183 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
184
185 struct cmd_desc_type0 {
186 u8 tcp_hdr_offset; /* For LSO only */
187 u8 ip_hdr_offset; /* For LSO only */
188 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
189 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
190
191 __le64 addr_buffer2;
192
193 __le16 reference_handle;
194 __le16 mss;
195 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
196 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
197 __le16 conn_id; /* IPSec offoad only */
198
199 __le64 addr_buffer3;
200 __le64 addr_buffer1;
201
202 __le16 buffer_length[4];
203
204 __le64 addr_buffer4;
205
206 u8 eth_addr[ETH_ALEN];
207 __le16 vlan_TCI;
208
209 } __attribute__ ((aligned(64)));
210
211 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
212 struct rcv_desc {
213 __le16 reference_handle;
214 __le16 reserved;
215 __le32 buffer_length; /* allocated buffer length (usually 2K) */
216 __le64 addr_buffer;
217 };
218
219 /* opcode field in status_desc */
220 #define QLCNIC_SYN_OFFLOAD 0x03
221 #define QLCNIC_RXPKT_DESC 0x04
222 #define QLCNIC_OLD_RXPKT_DESC 0x3f
223 #define QLCNIC_RESPONSE_DESC 0x05
224 #define QLCNIC_LRO_DESC 0x12
225
226 /* for status field in status_desc */
227 #define STATUS_CKSUM_OK (2)
228
229 /* owner bits of status_desc */
230 #define STATUS_OWNER_HOST (0x1ULL << 56)
231 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
232
233 /* Status descriptor:
234 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
235 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
236 53-55 desc_cnt, 56-57 owner, 58-63 opcode
237 */
238 #define qlcnic_get_sts_port(sts_data) \
239 ((sts_data) & 0x0F)
240 #define qlcnic_get_sts_status(sts_data) \
241 (((sts_data) >> 4) & 0x0F)
242 #define qlcnic_get_sts_type(sts_data) \
243 (((sts_data) >> 8) & 0x0F)
244 #define qlcnic_get_sts_totallength(sts_data) \
245 (((sts_data) >> 12) & 0xFFFF)
246 #define qlcnic_get_sts_refhandle(sts_data) \
247 (((sts_data) >> 28) & 0xFFFF)
248 #define qlcnic_get_sts_prot(sts_data) \
249 (((sts_data) >> 44) & 0x0F)
250 #define qlcnic_get_sts_pkt_offset(sts_data) \
251 (((sts_data) >> 48) & 0x1F)
252 #define qlcnic_get_sts_desc_cnt(sts_data) \
253 (((sts_data) >> 53) & 0x7)
254 #define qlcnic_get_sts_opcode(sts_data) \
255 (((sts_data) >> 58) & 0x03F)
256
257 #define qlcnic_get_lro_sts_refhandle(sts_data) \
258 ((sts_data) & 0x0FFFF)
259 #define qlcnic_get_lro_sts_length(sts_data) \
260 (((sts_data) >> 16) & 0x0FFFF)
261 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
262 (((sts_data) >> 32) & 0x0FF)
263 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
264 (((sts_data) >> 40) & 0x0FF)
265 #define qlcnic_get_lro_sts_timestamp(sts_data) \
266 (((sts_data) >> 48) & 0x1)
267 #define qlcnic_get_lro_sts_type(sts_data) \
268 (((sts_data) >> 49) & 0x7)
269 #define qlcnic_get_lro_sts_push_flag(sts_data) \
270 (((sts_data) >> 52) & 0x1)
271 #define qlcnic_get_lro_sts_seq_number(sts_data) \
272 ((sts_data) & 0x0FFFFFFFF)
273
274
275 struct status_desc {
276 __le64 status_desc_data[2];
277 } __attribute__ ((aligned(16)));
278
279 /* UNIFIED ROMIMAGE */
280 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
281 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
282 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
283 #define QLCNIC_UNI_DIR_SECT_FW 0x7
284
285 /*Offsets */
286 #define QLCNIC_UNI_CHIP_REV_OFF 10
287 #define QLCNIC_UNI_FLAGS_OFF 11
288 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
289 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
290 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
291
292 struct uni_table_desc{
293 u32 findex;
294 u32 num_entries;
295 u32 entry_size;
296 u32 reserved[5];
297 };
298
299 struct uni_data_desc{
300 u32 findex;
301 u32 size;
302 u32 reserved[5];
303 };
304
305 /* Magic number to let user know flash is programmed */
306 #define QLCNIC_BDINFO_MAGIC 0x12345678
307
308 #define QLCNIC_BRDTYPE_P3_REF_QG 0x0021
309 #define QLCNIC_BRDTYPE_P3_HMEZ 0x0022
310 #define QLCNIC_BRDTYPE_P3_10G_CX4_LP 0x0023
311 #define QLCNIC_BRDTYPE_P3_4_GB 0x0024
312 #define QLCNIC_BRDTYPE_P3_IMEZ 0x0025
313 #define QLCNIC_BRDTYPE_P3_10G_SFP_PLUS 0x0026
314 #define QLCNIC_BRDTYPE_P3_10000_BASE_T 0x0027
315 #define QLCNIC_BRDTYPE_P3_XG_LOM 0x0028
316 #define QLCNIC_BRDTYPE_P3_4_GB_MM 0x0029
317 #define QLCNIC_BRDTYPE_P3_10G_SFP_CT 0x002a
318 #define QLCNIC_BRDTYPE_P3_10G_SFP_QT 0x002b
319 #define QLCNIC_BRDTYPE_P3_10G_CX4 0x0031
320 #define QLCNIC_BRDTYPE_P3_10G_XFP 0x0032
321 #define QLCNIC_BRDTYPE_P3_10G_TP 0x0080
322
323 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
324
325 /* Flash memory map */
326 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
327 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
328 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
329 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
330
331 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
332 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
333 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
334 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
335
336 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
337 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
338
339 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
340 #define QLCNIC_UNIFIED_ROMIMAGE 0
341 #define QLCNIC_FLASH_ROMIMAGE 1
342 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
343
344 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
345 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
346
347 extern char qlcnic_driver_name[];
348
349 /* Number of status descriptors to handle per interrupt */
350 #define MAX_STATUS_HANDLE (64)
351
352 /*
353 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
354 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
355 */
356 struct qlcnic_skb_frag {
357 u64 dma;
358 u64 length;
359 };
360
361 struct qlcnic_recv_crb {
362 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
363 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
364 u32 sw_int_mask[NUM_STS_DESC_RINGS];
365 };
366
367 /* Following defines are for the state of the buffers */
368 #define QLCNIC_BUFFER_FREE 0
369 #define QLCNIC_BUFFER_BUSY 1
370
371 /*
372 * There will be one qlcnic_buffer per skb packet. These will be
373 * used to save the dma info for pci_unmap_page()
374 */
375 struct qlcnic_cmd_buffer {
376 struct sk_buff *skb;
377 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
378 u32 frag_count;
379 };
380
381 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
382 struct qlcnic_rx_buffer {
383 struct list_head list;
384 struct sk_buff *skb;
385 u64 dma;
386 u16 ref_handle;
387 };
388
389 /* Board types */
390 #define QLCNIC_GBE 0x01
391 #define QLCNIC_XGBE 0x02
392
393 /*
394 * One hardware_context{} per adapter
395 * contains interrupt info as well shared hardware info.
396 */
397 struct qlcnic_hardware_context {
398 void __iomem *pci_base0;
399 void __iomem *ocm_win_crb;
400
401 unsigned long pci_len0;
402
403 rwlock_t crb_lock;
404 struct mutex mem_lock;
405
406 u8 revision_id;
407 u8 pci_func;
408 u8 linkup;
409 u16 port_type;
410 u16 board_type;
411 };
412
413 struct qlcnic_adapter_stats {
414 u64 xmitcalled;
415 u64 xmitfinished;
416 u64 rxdropped;
417 u64 txdropped;
418 u64 csummed;
419 u64 rx_pkts;
420 u64 lro_pkts;
421 u64 rxbytes;
422 u64 txbytes;
423 u64 lrobytes;
424 u64 lso_frames;
425 u64 xmit_on;
426 u64 xmit_off;
427 u64 skb_alloc_failure;
428 u64 null_rxbuf;
429 u64 rx_dma_map_error;
430 u64 tx_dma_map_error;
431 };
432
433 /*
434 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
435 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
436 */
437 struct qlcnic_host_rds_ring {
438 u32 producer;
439 u32 num_desc;
440 u32 dma_size;
441 u32 skb_size;
442 u32 flags;
443 void __iomem *crb_rcv_producer;
444 struct rcv_desc *desc_head;
445 struct qlcnic_rx_buffer *rx_buf_arr;
446 struct list_head free_list;
447 spinlock_t lock;
448 dma_addr_t phys_addr;
449 };
450
451 struct qlcnic_host_sds_ring {
452 u32 consumer;
453 u32 num_desc;
454 void __iomem *crb_sts_consumer;
455 void __iomem *crb_intr_mask;
456
457 struct status_desc *desc_head;
458 struct qlcnic_adapter *adapter;
459 struct napi_struct napi;
460 struct list_head free_list[NUM_RCV_DESC_RINGS];
461
462 int irq;
463
464 dma_addr_t phys_addr;
465 char name[IFNAMSIZ+4];
466 };
467
468 struct qlcnic_host_tx_ring {
469 u32 producer;
470 __le32 *hw_consumer;
471 u32 sw_consumer;
472 void __iomem *crb_cmd_producer;
473 u32 num_desc;
474
475 struct netdev_queue *txq;
476
477 struct qlcnic_cmd_buffer *cmd_buf_arr;
478 struct cmd_desc_type0 *desc_head;
479 dma_addr_t phys_addr;
480 dma_addr_t hw_cons_phys_addr;
481 };
482
483 /*
484 * Receive context. There is one such structure per instance of the
485 * receive processing. Any state information that is relevant to
486 * the receive, and is must be in this structure. The global data may be
487 * present elsewhere.
488 */
489 struct qlcnic_recv_context {
490 u32 state;
491 u16 context_id;
492 u16 virt_port;
493
494 struct qlcnic_host_rds_ring *rds_rings;
495 struct qlcnic_host_sds_ring *sds_rings;
496 };
497
498 /* HW context creation */
499
500 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
501 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
502 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
503
504 #define QLCNIC_CDRP_CMD_BIT 0x80000000
505
506 /*
507 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
508 * in the crb QLCNIC_CDRP_CRB_OFFSET.
509 */
510 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
511 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
512
513 #define QLCNIC_CDRP_RSP_OK 0x00000001
514 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
515 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
516
517 /*
518 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
519 * the crb QLCNIC_CDRP_CRB_OFFSET.
520 */
521 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
522 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
523
524 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
525 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
526 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
527 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
528 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
529 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
530 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
531 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
532 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
533 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
534 #define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e
535 #define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f
536 #define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010
537 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
538 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
539 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
540 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
541 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
542 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
543 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
544 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
545 #define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a
546 #define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b
547 #define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
548 #define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
549 #define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
550 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
551
552 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
553 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
554 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
555 #define QLCNIC_CDRP_CMD_RESET_NPAR 0x00000023
556 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
557 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
558 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
559 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
560 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
561 #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
562 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
563
564 #define QLCNIC_RCODE_SUCCESS 0
565 #define QLCNIC_RCODE_TIMEOUT 17
566 #define QLCNIC_DESTROY_CTX_RESET 0
567
568 /*
569 * Capabilities Announced
570 */
571 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
572 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
573 #define QLCNIC_CAP0_LSO (1 << 6)
574 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
575 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
576 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
577
578 /*
579 * Context state
580 */
581 #define QLCNIC_HOST_CTX_STATE_FREED 0
582 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
583
584 /*
585 * Rx context
586 */
587
588 struct qlcnic_hostrq_sds_ring {
589 __le64 host_phys_addr; /* Ring base addr */
590 __le32 ring_size; /* Ring entries */
591 __le16 msi_index;
592 __le16 rsvd; /* Padding */
593 };
594
595 struct qlcnic_hostrq_rds_ring {
596 __le64 host_phys_addr; /* Ring base addr */
597 __le64 buff_size; /* Packet buffer size */
598 __le32 ring_size; /* Ring entries */
599 __le32 ring_kind; /* Class of ring */
600 };
601
602 struct qlcnic_hostrq_rx_ctx {
603 __le64 host_rsp_dma_addr; /* Response dma'd here */
604 __le32 capabilities[4]; /* Flag bit vector */
605 __le32 host_int_crb_mode; /* Interrupt crb usage */
606 __le32 host_rds_crb_mode; /* RDS crb usage */
607 /* These ring offsets are relative to data[0] below */
608 __le32 rds_ring_offset; /* Offset to RDS config */
609 __le32 sds_ring_offset; /* Offset to SDS config */
610 __le16 num_rds_rings; /* Count of RDS rings */
611 __le16 num_sds_rings; /* Count of SDS rings */
612 __le16 valid_field_offset;
613 u8 txrx_sds_binding;
614 u8 msix_handler;
615 u8 reserved[128]; /* reserve space for future expansion*/
616 /* MUST BE 64-bit aligned.
617 The following is packed:
618 - N hostrq_rds_rings
619 - N hostrq_sds_rings */
620 char data[0];
621 };
622
623 struct qlcnic_cardrsp_rds_ring{
624 __le32 host_producer_crb; /* Crb to use */
625 __le32 rsvd1; /* Padding */
626 };
627
628 struct qlcnic_cardrsp_sds_ring {
629 __le32 host_consumer_crb; /* Crb to use */
630 __le32 interrupt_crb; /* Crb to use */
631 };
632
633 struct qlcnic_cardrsp_rx_ctx {
634 /* These ring offsets are relative to data[0] below */
635 __le32 rds_ring_offset; /* Offset to RDS config */
636 __le32 sds_ring_offset; /* Offset to SDS config */
637 __le32 host_ctx_state; /* Starting State */
638 __le32 num_fn_per_port; /* How many PCI fn share the port */
639 __le16 num_rds_rings; /* Count of RDS rings */
640 __le16 num_sds_rings; /* Count of SDS rings */
641 __le16 context_id; /* Handle for context */
642 u8 phys_port; /* Physical id of port */
643 u8 virt_port; /* Virtual/Logical id of port */
644 u8 reserved[128]; /* save space for future expansion */
645 /* MUST BE 64-bit aligned.
646 The following is packed:
647 - N cardrsp_rds_rings
648 - N cardrs_sds_rings */
649 char data[0];
650 };
651
652 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
653 (sizeof(HOSTRQ_RX) + \
654 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
655 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
656
657 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
658 (sizeof(CARDRSP_RX) + \
659 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
660 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
661
662 /*
663 * Tx context
664 */
665
666 struct qlcnic_hostrq_cds_ring {
667 __le64 host_phys_addr; /* Ring base addr */
668 __le32 ring_size; /* Ring entries */
669 __le32 rsvd; /* Padding */
670 };
671
672 struct qlcnic_hostrq_tx_ctx {
673 __le64 host_rsp_dma_addr; /* Response dma'd here */
674 __le64 cmd_cons_dma_addr; /* */
675 __le64 dummy_dma_addr; /* */
676 __le32 capabilities[4]; /* Flag bit vector */
677 __le32 host_int_crb_mode; /* Interrupt crb usage */
678 __le32 rsvd1; /* Padding */
679 __le16 rsvd2; /* Padding */
680 __le16 interrupt_ctl;
681 __le16 msi_index;
682 __le16 rsvd3; /* Padding */
683 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
684 u8 reserved[128]; /* future expansion */
685 };
686
687 struct qlcnic_cardrsp_cds_ring {
688 __le32 host_producer_crb; /* Crb to use */
689 __le32 interrupt_crb; /* Crb to use */
690 };
691
692 struct qlcnic_cardrsp_tx_ctx {
693 __le32 host_ctx_state; /* Starting state */
694 __le16 context_id; /* Handle for context */
695 u8 phys_port; /* Physical id of port */
696 u8 virt_port; /* Virtual/Logical id of port */
697 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
698 u8 reserved[128]; /* future expansion */
699 };
700
701 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
702 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
703
704 /* CRB */
705
706 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
707 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
708 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
709 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
710
711 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
712 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
713 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
714 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
715 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
716
717
718 /* MAC */
719
720 #define MC_COUNT_P3 38
721
722 #define QLCNIC_MAC_NOOP 0
723 #define QLCNIC_MAC_ADD 1
724 #define QLCNIC_MAC_DEL 2
725
726 struct qlcnic_mac_list_s {
727 struct list_head list;
728 uint8_t mac_addr[ETH_ALEN+2];
729 };
730
731 /*
732 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
733 * adjusted based on configured MTU.
734 */
735 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
736 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
737 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64
738 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4
739
740 #define QLCNIC_INTR_DEFAULT 0x04
741
742 union qlcnic_nic_intr_coalesce_data {
743 struct {
744 u16 rx_packets;
745 u16 rx_time_us;
746 u16 tx_packets;
747 u16 tx_time_us;
748 } data;
749 u64 word;
750 };
751
752 struct qlcnic_nic_intr_coalesce {
753 u16 stats_time_us;
754 u16 rate_sample_time;
755 u16 flags;
756 u16 rsvd_1;
757 u32 low_threshold;
758 u32 high_threshold;
759 union qlcnic_nic_intr_coalesce_data normal;
760 union qlcnic_nic_intr_coalesce_data low;
761 union qlcnic_nic_intr_coalesce_data high;
762 union qlcnic_nic_intr_coalesce_data irq;
763 };
764
765 #define QLCNIC_HOST_REQUEST 0x13
766 #define QLCNIC_REQUEST 0x14
767
768 #define QLCNIC_MAC_EVENT 0x1
769
770 #define QLCNIC_IP_UP 2
771 #define QLCNIC_IP_DOWN 3
772
773 /*
774 * Driver --> Firmware
775 */
776 #define QLCNIC_H2C_OPCODE_START 0
777 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 1
778 #define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2
779 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
780 #define QLCNIC_H2C_OPCODE_CONFIG_LED 4
781 #define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
782 #define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6
783 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 7
784 #define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8
785 #define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9
786 #define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
787 #define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11
788 #define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
789 #define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
790 #define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
791 #define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
792 #define QLCNIC_H2C_OPCODE_GET_NET_STATS 16
793 #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
794 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18
795 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 19
796 #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20
797 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21
798 #define QLCNIC_C2C_OPCODE 22
799 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23
800 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24
801 #define QLCNIC_H2C_OPCODE_LAST 25
802 /*
803 * Firmware --> Driver
804 */
805
806 #define QLCNIC_C2H_OPCODE_START 128
807 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
808 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
809 #define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
810 #define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
811 #define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
812 #define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
813 #define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
814 #define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136
815 #define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
816 #define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
817 #define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
818 #define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
819 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
820 #define QLCNIC_C2H_OPCODE_LAST 142
821
822 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
823 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
824 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
825
826 #define QLCNIC_LRO_REQUEST_CLEANUP 4
827
828 /* Capabilites received */
829 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
830 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
831 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
832 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
833
834 /* module types */
835 #define LINKEVENT_MODULE_NOT_PRESENT 1
836 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
837 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
838 #define LINKEVENT_MODULE_OPTICAL_LRM 4
839 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
840 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
841 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
842 #define LINKEVENT_MODULE_TWINAX 8
843
844 #define LINKSPEED_10GBPS 10000
845 #define LINKSPEED_1GBPS 1000
846 #define LINKSPEED_100MBPS 100
847 #define LINKSPEED_10MBPS 10
848
849 #define LINKSPEED_ENCODED_10MBPS 0
850 #define LINKSPEED_ENCODED_100MBPS 1
851 #define LINKSPEED_ENCODED_1GBPS 2
852
853 #define LINKEVENT_AUTONEG_DISABLED 0
854 #define LINKEVENT_AUTONEG_ENABLED 1
855
856 #define LINKEVENT_HALF_DUPLEX 0
857 #define LINKEVENT_FULL_DUPLEX 1
858
859 #define LINKEVENT_LINKSPEED_MBPS 0
860 #define LINKEVENT_LINKSPEED_ENCODED 1
861
862 #define AUTO_FW_RESET_ENABLED 0x01
863 /* firmware response header:
864 * 63:58 - message type
865 * 57:56 - owner
866 * 55:53 - desc count
867 * 52:48 - reserved
868 * 47:40 - completion id
869 * 39:32 - opcode
870 * 31:16 - error code
871 * 15:00 - reserved
872 */
873 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
874 ((msg_hdr >> 32) & 0xFF)
875
876 struct qlcnic_fw_msg {
877 union {
878 struct {
879 u64 hdr;
880 u64 body[7];
881 };
882 u64 words[8];
883 };
884 };
885
886 struct qlcnic_nic_req {
887 __le64 qhdr;
888 __le64 req_hdr;
889 __le64 words[6];
890 };
891
892 struct qlcnic_mac_req {
893 u8 op;
894 u8 tag;
895 u8 mac_addr[6];
896 };
897
898 #define QLCNIC_MSI_ENABLED 0x02
899 #define QLCNIC_MSIX_ENABLED 0x04
900 #define QLCNIC_LRO_ENABLED 0x08
901 #define QLCNIC_LRO_DISABLED 0x00
902 #define QLCNIC_BRIDGE_ENABLED 0X10
903 #define QLCNIC_DIAG_ENABLED 0x20
904 #define QLCNIC_ESWITCH_ENABLED 0x40
905 #define QLCNIC_ADAPTER_INITIALIZED 0x80
906 #define QLCNIC_TAGGING_ENABLED 0x100
907 #define QLCNIC_MACSPOOF 0x200
908 #define QLCNIC_IS_MSI_FAMILY(adapter) \
909 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
910
911 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
912 #define QLCNIC_MSIX_TBL_SPACE 8192
913 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
914 #define QLCNIC_MSIX_TBL_PGSIZE 4096
915
916 #define QLCNIC_NETDEV_WEIGHT 128
917 #define QLCNIC_ADAPTER_UP_MAGIC 777
918
919 #define __QLCNIC_FW_ATTACHED 0
920 #define __QLCNIC_DEV_UP 1
921 #define __QLCNIC_RESETTING 2
922 #define __QLCNIC_START_FW 4
923 #define __QLCNIC_AER 5
924
925 #define QLCNIC_INTERRUPT_TEST 1
926 #define QLCNIC_LOOPBACK_TEST 2
927
928 struct qlcnic_adapter {
929 struct qlcnic_hardware_context ahw;
930
931 struct net_device *netdev;
932 struct pci_dev *pdev;
933 struct list_head mac_list;
934
935 spinlock_t tx_clean_lock;
936
937 u16 num_txd;
938 u16 num_rxd;
939 u16 num_jumbo_rxd;
940
941 u8 max_rds_rings;
942 u8 max_sds_rings;
943 u8 msix_supported;
944 u8 rx_csum;
945 u8 portnum;
946 u8 physical_port;
947 u8 reset_context;
948
949 u8 mc_enabled;
950 u8 max_mc_count;
951 u8 rss_supported;
952 u8 fw_wait_cnt;
953 u8 fw_fail_cnt;
954 u8 tx_timeo_cnt;
955 u8 need_fw_reset;
956
957 u8 has_link_events;
958 u8 fw_type;
959 u16 tx_context_id;
960 u16 is_up;
961
962 u16 link_speed;
963 u16 link_duplex;
964 u16 link_autoneg;
965 u16 module_type;
966
967 u16 op_mode;
968 u16 switch_mode;
969 u16 max_tx_ques;
970 u16 max_rx_ques;
971 u16 max_mtu;
972 u16 pvid;
973
974 u32 fw_hal_version;
975 u32 capabilities;
976 u32 flags;
977 u32 irq;
978 u32 temp;
979
980 u32 int_vec_bit;
981 u32 heartbit;
982
983 u8 max_mac_filters;
984 u8 dev_state;
985 u8 diag_test;
986 u8 diag_cnt;
987 u8 reset_ack_timeo;
988 u8 dev_init_timeo;
989 u16 msg_enable;
990
991 u8 mac_addr[ETH_ALEN];
992
993 u64 dev_rst_time;
994
995 struct qlcnic_npar_info *npars;
996 struct qlcnic_eswitch *eswitch;
997 struct qlcnic_nic_template *nic_ops;
998
999 struct qlcnic_adapter_stats stats;
1000
1001 struct qlcnic_recv_context recv_ctx;
1002 struct qlcnic_host_tx_ring *tx_ring;
1003
1004 void __iomem *tgt_mask_reg;
1005 void __iomem *tgt_status_reg;
1006 void __iomem *crb_int_state_reg;
1007 void __iomem *isr_int_vec;
1008
1009 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1010
1011 struct delayed_work fw_work;
1012
1013 struct qlcnic_nic_intr_coalesce coal;
1014
1015 unsigned long state;
1016 __le32 file_prd_off; /*File fw product offset*/
1017 u32 fw_version;
1018 const struct firmware *fw;
1019 };
1020
1021 struct qlcnic_info {
1022 __le16 pci_func;
1023 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1024 __le16 phys_port;
1025 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1026
1027 __le32 capabilities;
1028 u8 max_mac_filters;
1029 u8 reserved1;
1030 __le16 max_mtu;
1031
1032 __le16 max_tx_ques;
1033 __le16 max_rx_ques;
1034 __le16 min_tx_bw;
1035 __le16 max_tx_bw;
1036 u8 reserved2[104];
1037 };
1038
1039 struct qlcnic_pci_info {
1040 __le16 id; /* pci function id */
1041 __le16 active; /* 1 = Enabled */
1042 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1043 __le16 default_port; /* default port number */
1044
1045 __le16 tx_min_bw; /* Multiple of 100mbpc */
1046 __le16 tx_max_bw;
1047 __le16 reserved1[2];
1048
1049 u8 mac[ETH_ALEN];
1050 u8 reserved2[106];
1051 };
1052
1053 struct qlcnic_npar_info {
1054 u16 pvid;
1055 u16 min_bw;
1056 u16 max_bw;
1057 u8 phy_port;
1058 u8 type;
1059 u8 active;
1060 u8 enable_pm;
1061 u8 dest_npar;
1062 u8 discard_tagged;
1063 u8 mac_learning;
1064 u8 mac_anti_spoof;
1065 u8 promisc_mode;
1066 u8 offload_flags;
1067 };
1068
1069 struct qlcnic_eswitch {
1070 u8 port;
1071 u8 active_vports;
1072 u8 active_vlans;
1073 u8 active_ucast_filters;
1074 u8 max_ucast_filters;
1075 u8 max_active_vlans;
1076
1077 u32 flags;
1078 #define QLCNIC_SWITCH_ENABLE BIT_1
1079 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1080 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1081 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1082 };
1083
1084
1085 /* Return codes for Error handling */
1086 #define QL_STATUS_INVALID_PARAM -1
1087
1088 #define MAX_BW 100
1089 #define MIN_BW 1
1090 #define MAX_VLAN_ID 4095
1091 #define MIN_VLAN_ID 2
1092 #define MAX_TX_QUEUES 1
1093 #define MAX_RX_QUEUES 4
1094 #define DEFAULT_MAC_LEARN 1
1095
1096 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan <= MAX_VLAN_ID)
1097 #define IS_VALID_BW(bw) (bw >= MIN_BW && bw <= MAX_BW)
1098 #define IS_VALID_TX_QUEUES(que) (que > 0 && que <= MAX_TX_QUEUES)
1099 #define IS_VALID_RX_QUEUES(que) (que > 0 && que <= MAX_RX_QUEUES)
1100
1101 struct qlcnic_pci_func_cfg {
1102 u16 func_type;
1103 u16 min_bw;
1104 u16 max_bw;
1105 u16 port_num;
1106 u8 pci_func;
1107 u8 func_state;
1108 u8 def_mac_addr[6];
1109 };
1110
1111 struct qlcnic_npar_func_cfg {
1112 u32 fw_capab;
1113 u16 port_num;
1114 u16 min_bw;
1115 u16 max_bw;
1116 u16 max_tx_queues;
1117 u16 max_rx_queues;
1118 u8 pci_func;
1119 u8 op_mode;
1120 };
1121
1122 struct qlcnic_pm_func_cfg {
1123 u8 pci_func;
1124 u8 action;
1125 u8 dest_npar;
1126 u8 reserved[5];
1127 };
1128
1129 struct qlcnic_esw_func_cfg {
1130 u16 vlan_id;
1131 u8 op_mode;
1132 u8 op_type;
1133 u8 pci_func;
1134 u8 host_vlan_tag;
1135 u8 promisc_mode;
1136 u8 discard_tagged;
1137 u8 mac_learning;
1138 u8 mac_anti_spoof;
1139 u8 offload_flags;
1140 u8 reserved[5];
1141 };
1142
1143 #define QLCNIC_STATS_VERSION 1
1144 #define QLCNIC_STATS_PORT 1
1145 #define QLCNIC_STATS_ESWITCH 2
1146 #define QLCNIC_QUERY_RX_COUNTER 0
1147 #define QLCNIC_QUERY_TX_COUNTER 1
1148 struct __qlcnic_esw_statistics {
1149 __le16 context_id;
1150 __le16 version;
1151 __le16 size;
1152 __le16 unused;
1153 __le64 unicast_frames;
1154 __le64 multicast_frames;
1155 __le64 broadcast_frames;
1156 __le64 dropped_frames;
1157 __le64 errors;
1158 __le64 local_frames;
1159 __le64 numbytes;
1160 __le64 rsvd[3];
1161 };
1162
1163 struct qlcnic_esw_statistics {
1164 struct __qlcnic_esw_statistics rx;
1165 struct __qlcnic_esw_statistics tx;
1166 };
1167
1168 int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val);
1169 int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val);
1170
1171 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1172 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1173 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1174 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1175 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1176 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1177
1178 #define ADDR_IN_RANGE(addr, low, high) \
1179 (((addr) < (high)) && ((addr) >= (low)))
1180
1181 #define QLCRD32(adapter, off) \
1182 (qlcnic_hw_read_wx_2M(adapter, off))
1183 #define QLCWR32(adapter, off, val) \
1184 (qlcnic_hw_write_wx_2M(adapter, off, val))
1185
1186 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1187 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1188
1189 #define qlcnic_rom_lock(a) \
1190 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1191 #define qlcnic_rom_unlock(a) \
1192 qlcnic_pcie_sem_unlock((a), 2)
1193 #define qlcnic_phy_lock(a) \
1194 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1195 #define qlcnic_phy_unlock(a) \
1196 qlcnic_pcie_sem_unlock((a), 3)
1197 #define qlcnic_api_lock(a) \
1198 qlcnic_pcie_sem_lock((a), 5, 0)
1199 #define qlcnic_api_unlock(a) \
1200 qlcnic_pcie_sem_unlock((a), 5)
1201 #define qlcnic_sw_lock(a) \
1202 qlcnic_pcie_sem_lock((a), 6, 0)
1203 #define qlcnic_sw_unlock(a) \
1204 qlcnic_pcie_sem_unlock((a), 6)
1205 #define crb_win_lock(a) \
1206 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1207 #define crb_win_unlock(a) \
1208 qlcnic_pcie_sem_unlock((a), 7)
1209
1210 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1211 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1212 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1213
1214 /* Functions from qlcnic_init.c */
1215 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1216 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1217 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1218 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1219 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1220 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1221 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1222
1223 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp);
1224 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1225 u8 *bytes, size_t size);
1226 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1227 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1228
1229 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1230
1231 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1232 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1233
1234 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1235 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1236
1237 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1238 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1239 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1240
1241 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1242 void qlcnic_watchdog_task(struct work_struct *work);
1243 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid,
1244 struct qlcnic_host_rds_ring *rds_ring);
1245 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1246 void qlcnic_set_multi(struct net_device *netdev);
1247 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1248 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1249 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1250 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1251 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd);
1252 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1253 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1254
1255 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1256 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1257 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1258 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1259 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1260 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1261 struct qlcnic_host_tx_ring *tx_ring);
1262 int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u8 *mac);
1263 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter);
1264 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter);
1265 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1266
1267 /* Functions from qlcnic_main.c */
1268 int qlcnic_reset_context(struct qlcnic_adapter *);
1269 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1270 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1271 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1272 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1273 int qlcnic_check_loopback_buff(unsigned char *data);
1274 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1275 void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
1276
1277 /* Management functions */
1278 int qlcnic_set_mac_address(struct qlcnic_adapter *, u8*);
1279 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1280 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1281 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1282 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1283 int qlcnic_reset_partition(struct qlcnic_adapter *, u8);
1284
1285 /* eSwitch management functions */
1286 int qlcnic_get_eswitch_capabilities(struct qlcnic_adapter *, u8,
1287 struct qlcnic_eswitch *);
1288 int qlcnic_get_eswitch_status(struct qlcnic_adapter *, u8,
1289 struct qlcnic_eswitch *);
1290 int qlcnic_toggle_eswitch(struct qlcnic_adapter *, u8, u8);
1291 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1292 struct qlcnic_esw_func_cfg *);
1293 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1294 struct qlcnic_esw_func_cfg *);
1295 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1296 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1297 struct __qlcnic_esw_statistics *);
1298 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1299 struct __qlcnic_esw_statistics *);
1300 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1301 extern int qlcnic_config_tso;
1302
1303 /*
1304 * QLOGIC Board information
1305 */
1306
1307 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1308 struct qlcnic_brdinfo {
1309 unsigned short vendor;
1310 unsigned short device;
1311 unsigned short sub_vendor;
1312 unsigned short sub_device;
1313 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1314 };
1315
1316 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1317 {0x1077, 0x8020, 0x1077, 0x203,
1318 "8200 Series Single Port 10GbE Converged Network Adapter "
1319 "(TCP/IP Networking)"},
1320 {0x1077, 0x8020, 0x1077, 0x207,
1321 "8200 Series Dual Port 10GbE Converged Network Adapter "
1322 "(TCP/IP Networking)"},
1323 {0x1077, 0x8020, 0x1077, 0x20b,
1324 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1325 {0x1077, 0x8020, 0x1077, 0x20c,
1326 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1327 {0x1077, 0x8020, 0x1077, 0x20f,
1328 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1329 {0x1077, 0x8020, 0x103c, 0x3733,
1330 "NC523SFP 10Gb 2-port Flex-10 Server Adapter"},
1331 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1332 };
1333
1334 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1335
1336 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1337 {
1338 smp_mb();
1339 if (tx_ring->producer < tx_ring->sw_consumer)
1340 return tx_ring->sw_consumer - tx_ring->producer;
1341 else
1342 return tx_ring->sw_consumer + tx_ring->num_desc -
1343 tx_ring->producer;
1344 }
1345
1346 extern const struct ethtool_ops qlcnic_ethtool_ops;
1347
1348 struct qlcnic_nic_template {
1349 int (*get_mac_addr) (struct qlcnic_adapter *, u8*);
1350 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1351 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1352 int (*start_firmware) (struct qlcnic_adapter *);
1353 };
1354
1355 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1356 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1357 printk(KERN_INFO "%s: %s: " _fmt, \
1358 dev_name(&adapter->pdev->dev), \
1359 __func__, ##_args); \
1360 } while (0)
1361
1362 #endif /* __QLCNIC_H_ */
Linux 2.6 libata-dev (mirror)