drivers/ide/cmd64x.c

   1 /*
   2  * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
   3  *           Due to massive hardware bugs, UltraDMA is only supported
   4  *           on the 646U2 and not on the 646U.
   5  *
   6  * Copyright (C) 1998           Eddie C. Dost  (ecd@skynet.be)
   7  * Copyright (C) 1998           David S. Miller (davem@redhat.com)
   8  *
   9  * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
  10  * Copyright (C) 2007-2010      Bartlomiej Zolnierkiewicz
  11  * Copyright (C) 2007,2009      MontaVista Software, Inc. <source@mvista.com>
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/types.h>
  16 #include <linux/pci.h>
  17 #include <linux/ide.h>
  18 #include <linux/init.h>
  19
  20 #include <asm/io.h>
  21
  22 #define DRV_NAME "cmd64x"
  23
  24 /*
  25  * CMD64x specific registers definition.
  26  */
  27 #define CFR             0x50
  28 #define   CFR_INTR_CH0          0x04
  29
  30 #define CMDTIM          0x52
  31 #define ARTTIM0         0x53
  32 #define DRWTIM0         0x54
  33 #define ARTTIM1         0x55
  34 #define DRWTIM1         0x56
  35 #define ARTTIM23        0x57
  36 #define   ARTTIM23_DIS_RA2      0x04
  37 #define   ARTTIM23_DIS_RA3      0x08
  38 #define   ARTTIM23_INTR_CH1     0x10
  39 #define DRWTIM2         0x58
  40 #define BRST            0x59
  41 #define DRWTIM3         0x5b
  42
  43 #define BMIDECR0        0x70
  44 #define MRDMODE         0x71
  45 #define   MRDMODE_INTR_CH0      0x04
  46 #define   MRDMODE_INTR_CH1      0x08
  47 #define UDIDETCR0       0x73
  48 #define DTPR0           0x74
  49 #define BMIDECR1        0x78
  50 #define BMIDECSR        0x79
  51 #define UDIDETCR1       0x7B
  52 #define DTPR1           0x7C
  53
  54 static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
  55 {
  56         ide_hwif_t *hwif = drive->hwif;
  57         struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  58         int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
  59         const unsigned long T = 1000000 / bus_speed;
  60         static const u8 recovery_values[] =
  61                 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
  62         static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
  63         static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
  64         static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
  65         struct ide_timing t;
  66         u8 arttim = 0;
  67
  68         ide_timing_compute(drive, mode, &t, T, 0);
  69
  70         /*
  71          * In case we've got too long recovery phase, try to lengthen
  72          * the active phase
  73          */
  74         if (t.recover > 16) {
  75                 t.active += t.recover - 16;
  76                 t.recover = 16;
  77         }
  78         if (t.active > 16)              /* shouldn't actually happen... */
  79                 t.active = 16;
  80
  81         /*
  82          * Convert values to internal chipset representation
  83          */
  84         t.recover = recovery_values[t.recover];
  85         t.active &= 0x0f;
  86
  87         /* Program the active/recovery counts into the DRWTIM register */
  88         pci_write_config_byte(dev, drwtim_regs[drive->dn],
  89                               (t.active << 4) | t.recover);
  90
  91         if (mode >= XFER_SW_DMA_0)
  92                 return;
  93
  94         /*
  95          * The primary channel has individual address setup timing registers
  96          * for each drive and the hardware selects the slowest timing itself.
  97          * The secondary channel has one common register and we have to select
  98          * the slowest address setup timing ourselves.
  99          */
 100         if (hwif->channel) {
 101                 ide_drive_t *pair = ide_get_pair_dev(drive);
 102
 103                 ide_set_drivedata(drive, (void *)(unsigned long)t.setup);
 104
 105                 if (pair)
 106                         t.setup = max_t(u8, t.setup,
 107                                         (unsigned long)ide_get_drivedata(pair));
 108         }
 109
 110         if (t.setup > 5)                /* shouldn't actually happen... */
 111                 t.setup = 5;
 112
 113         /*
 114          * Program the address setup clocks into the ARTTIM registers.
 115          * Avoid clearing the secondary channel's interrupt bit.
 116          */
 117         (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
 118         if (hwif->channel)
 119                 arttim &= ~ARTTIM23_INTR_CH1;
 120         arttim &= ~0xc0;
 121         arttim |= setup_values[t.setup];
 122         (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
 123 }
 124
 125 /*
 126  * Attempts to set drive's PIO mode.
 127  * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
 128  */
 129
 130 static void cmd64x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 131 {
 132         const u8 pio = drive->pio_mode - XFER_PIO_0;
 133
 134         /*
 135          * Filter out the prefetch control values
 136          * to prevent PIO5 from being programmed
 137          */
 138         if (pio == 8 || pio == 9)
 139                 return;
 140
 141         cmd64x_program_timings(drive, XFER_PIO_0 + pio);
 142 }
 143
 144 static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
 145 {
 146         ide_hwif_t *hwif        = drive->hwif;
 147         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 148         u8 unit                 = drive->dn & 0x01;
 149         u8 regU = 0, pciU       = hwif->channel ? UDIDETCR1 : UDIDETCR0;
 150
 151         pci_read_config_byte(dev, pciU, &regU);
 152         regU &= ~(unit ? 0xCA : 0x35);
 153
 154         switch(speed) {
 155         case XFER_UDMA_5:
 156                 regU |= unit ? 0x0A : 0x05;
 157                 break;
 158         case XFER_UDMA_4:
 159                 regU |= unit ? 0x4A : 0x15;
 160                 break;
 161         case XFER_UDMA_3:
 162                 regU |= unit ? 0x8A : 0x25;
 163                 break;
 164         case XFER_UDMA_2:
 165                 regU |= unit ? 0x42 : 0x11;
 166                 break;
 167         case XFER_UDMA_1:
 168                 regU |= unit ? 0x82 : 0x21;
 169                 break;
 170         case XFER_UDMA_0:
 171                 regU |= unit ? 0xC2 : 0x31;
 172                 break;
 173         case XFER_MW_DMA_2:
 174         case XFER_MW_DMA_1:
 175         case XFER_MW_DMA_0:
 176                 cmd64x_program_timings(drive, speed);
 177                 break;
 178         }
 179
 180         pci_write_config_byte(dev, pciU, regU);
 181 }
 182
 183 static void cmd648_clear_irq(ide_drive_t *drive)
 184 {
 185         ide_hwif_t *hwif        = drive->hwif;
 186         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 187         unsigned long base      = pci_resource_start(dev, 4);
 188         u8  irq_mask            = hwif->channel ? MRDMODE_INTR_CH1 :
 189                                                   MRDMODE_INTR_CH0;
 190         u8  mrdmode             = inb(base + 1);
 191
 192         /* clear the interrupt bit */
 193         outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
 194              base + 1);
 195 }
 196
 197 static void cmd64x_clear_irq(ide_drive_t *drive)
 198 {
 199         ide_hwif_t *hwif        = drive->hwif;
 200         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 201         int irq_reg             = hwif->channel ? ARTTIM23 : CFR;
 202         u8  irq_mask            = hwif->channel ? ARTTIM23_INTR_CH1 :
 203                                                   CFR_INTR_CH0;
 204         u8  irq_stat            = 0;
 205
 206         (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
 207         /* clear the interrupt bit */
 208         (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
 209 }
 210
 211 static int cmd648_test_irq(ide_hwif_t *hwif)
 212 {
 213         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 214         unsigned long base      = pci_resource_start(dev, 4);
 215         u8 irq_mask             = hwif->channel ? MRDMODE_INTR_CH1 :
 216                                                   MRDMODE_INTR_CH0;
 217         u8 mrdmode              = inb(base + 1);
 218
 219         pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
 220                  hwif->name, mrdmode, irq_mask);
 221
 222         return (mrdmode & irq_mask) ? 1 : 0;
 223 }
 224
 225 static int cmd64x_test_irq(ide_hwif_t *hwif)
 226 {
 227         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 228         int irq_reg             = hwif->channel ? ARTTIM23 : CFR;
 229         u8  irq_mask            = hwif->channel ? ARTTIM23_INTR_CH1 :
 230                                                   CFR_INTR_CH0;
 231         u8  irq_stat            = 0;
 232
 233         (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
 234
 235         pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
 236                  hwif->name, irq_stat, irq_mask);
 237
 238         return (irq_stat & irq_mask) ? 1 : 0;
 239 }
 240
 241 /*
 242  * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
 243  * event order for DMA transfers.
 244  */
 245
 246 static int cmd646_1_dma_end(ide_drive_t *drive)
 247 {
 248         ide_hwif_t *hwif = drive->hwif;
 249         u8 dma_stat = 0, dma_cmd = 0;
 250
 251         /* get DMA status */
 252         dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
 253         /* read DMA command state */
 254         dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
 255         /* stop DMA */
 256         outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
 257         /* clear the INTR & ERROR bits */
 258         outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
 259         /* verify good DMA status */
 260         return (dma_stat & 7) != 4;
 261 }
 262
 263 static int init_chipset_cmd64x(struct pci_dev *dev)
 264 {
 265         u8 mrdmode = 0;
 266
 267         /* Set a good latency timer and cache line size value. */
 268         (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 269         /* FIXME: pci_set_master() to ensure a good latency timer value */
 270
 271         /*
 272          * Enable interrupts, select MEMORY READ LINE for reads.
 273          *
 274          * NOTE: although not mentioned in the PCI0646U specs,
 275          * bits 0-1 are write only and won't be read back as
 276          * set or not -- PCI0646U2 specs clarify this point.
 277          */
 278         (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
 279         mrdmode &= ~0x30;
 280         (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
 281
 282         return 0;
 283 }
 284
 285 static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
 286 {
 287         struct pci_dev  *dev    = to_pci_dev(hwif->dev);
 288         u8 bmidecsr = 0, mask   = hwif->channel ? 0x02 : 0x01;
 289
 290         switch (dev->device) {
 291         case PCI_DEVICE_ID_CMD_648:
 292         case PCI_DEVICE_ID_CMD_649:
 293                 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
 294                 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 295         default:
 296                 return ATA_CBL_PATA40;
 297         }
 298 }
 299
 300 static const struct ide_port_ops cmd64x_port_ops = {
 301         .set_pio_mode           = cmd64x_set_pio_mode,
 302         .set_dma_mode           = cmd64x_set_dma_mode,
 303         .clear_irq              = cmd64x_clear_irq,
 304         .test_irq               = cmd64x_test_irq,
 305         .cable_detect           = cmd64x_cable_detect,
 306 };
 307
 308 static const struct ide_port_ops cmd648_port_ops = {
 309         .set_pio_mode           = cmd64x_set_pio_mode,
 310         .set_dma_mode           = cmd64x_set_dma_mode,
 311         .clear_irq              = cmd648_clear_irq,
 312         .test_irq               = cmd648_test_irq,
 313         .cable_detect           = cmd64x_cable_detect,
 314 };
 315
 316 static const struct ide_dma_ops cmd646_rev1_dma_ops = {
 317         .dma_host_set           = ide_dma_host_set,
 318         .dma_setup              = ide_dma_setup,
 319         .dma_start              = ide_dma_start,
 320         .dma_end                = cmd646_1_dma_end,
 321         .dma_test_irq           = ide_dma_test_irq,
 322         .dma_lost_irq           = ide_dma_lost_irq,
 323         .dma_timer_expiry       = ide_dma_sff_timer_expiry,
 324         .dma_sff_read_status    = ide_dma_sff_read_status,
 325 };
 326
 327 static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
 328         {       /* 0: CMD643 */
 329                 .name           = DRV_NAME,
 330                 .init_chipset   = init_chipset_cmd64x,
 331                 .enablebits     = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
 332                 .port_ops       = &cmd64x_port_ops,
 333                 .host_flags     = IDE_HFLAG_CLEAR_SIMPLEX |
 334                                   IDE_HFLAG_ABUSE_PREFETCH |
 335                                   IDE_HFLAG_SERIALIZE,
 336                 .pio_mask       = ATA_PIO5,
 337                 .mwdma_mask     = ATA_MWDMA2,
 338                 .udma_mask      = 0x00, /* no udma */
 339         },
 340         {       /* 1: CMD646 */
 341                 .name           = DRV_NAME,
 342                 .init_chipset   = init_chipset_cmd64x,
 343                 .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 344                 .port_ops       = &cmd648_port_ops,
 345                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH |
 346                                   IDE_HFLAG_SERIALIZE,
 347                 .pio_mask       = ATA_PIO5,
 348                 .mwdma_mask     = ATA_MWDMA2,
 349                 .udma_mask      = ATA_UDMA2,
 350         },
 351         {       /* 2: CMD648 */
 352                 .name           = DRV_NAME,
 353                 .init_chipset   = init_chipset_cmd64x,
 354                 .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 355                 .port_ops       = &cmd648_port_ops,
 356                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH,
 357                 .pio_mask       = ATA_PIO5,
 358                 .mwdma_mask     = ATA_MWDMA2,
 359                 .udma_mask      = ATA_UDMA4,
 360         },
 361         {       /* 3: CMD649 */
 362                 .name           = DRV_NAME,
 363                 .init_chipset   = init_chipset_cmd64x,
 364                 .enablebits     = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
 365                 .port_ops       = &cmd648_port_ops,
 366                 .host_flags     = IDE_HFLAG_ABUSE_PREFETCH,
 367                 .pio_mask       = ATA_PIO5,
 368                 .mwdma_mask     = ATA_MWDMA2,
 369                 .udma_mask      = ATA_UDMA5,
 370         }
 371 };
 372
 373 static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 374 {
 375         struct ide_port_info d;
 376         u8 idx = id->driver_data;
 377
 378         d = cmd64x_chipsets[idx];
 379
 380         if (idx == 1) {
 381                 /*
 382                  * UltraDMA only supported on PCI646U and PCI646U2, which
 383                  * correspond to revisions 0x03, 0x05 and 0x07 respectively.
 384                  * Actually, although the CMD tech support people won't
 385                  * tell me the details, the 0x03 revision cannot support
 386                  * UDMA correctly without hardware modifications, and even
 387                  * then it only works with Quantum disks due to some
 388                  * hold time assumptions in the 646U part which are fixed
 389                  * in the 646U2.
 390                  *
 391                  * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
 392                  */
 393                 if (dev->revision < 5) {
 394                         d.udma_mask = 0x00;
 395                         /*
 396                          * The original PCI0646 didn't have the primary
 397                          * channel enable bit, it appeared starting with
 398                          * PCI0646U (i.e. revision ID 3).
 399                          */
 400                         if (dev->revision < 3) {
 401                                 d.enablebits[0].reg = 0;
 402                                 d.port_ops = &cmd64x_port_ops;
 403                                 if (dev->revision == 1)
 404                                         d.dma_ops = &cmd646_rev1_dma_ops;
 405                         }
 406                 }
 407         }
 408
 409         return ide_pci_init_one(dev, &d, NULL);
 410 }
 411
 412 static const struct pci_device_id cmd64x_pci_tbl[] = {
 413         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
 414         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
 415         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
 416         { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
 417         { 0, },
 418 };
 419 MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
 420
 421 static struct pci_driver cmd64x_pci_driver = {
 422         .name           = "CMD64x_IDE",
 423         .id_table       = cmd64x_pci_tbl,
 424         .probe          = cmd64x_init_one,
 425         .remove         = ide_pci_remove,
 426         .suspend        = ide_pci_suspend,
 427         .resume         = ide_pci_resume,
 428 };
 429
 430 static int __init cmd64x_ide_init(void)
 431 {
 432         return ide_pci_register_driver(&cmd64x_pci_driver);
 433 }
 434
 435 static void __exit cmd64x_ide_exit(void)
 436 {
 437         pci_unregister_driver(&cmd64x_pci_driver);
 438 }
 439
 440 module_init(cmd64x_ide_init);
 441 module_exit(cmd64x_ide_exit);
 442
 443 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz");
 444 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
 445 MODULE_LICENSE("GPL");