2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the
23 * file called COPYING.
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * Only DMAC flow control is implemented
59 * - Break out common code from arch/arm/mach-s3c64xx and share
61 #include <linux/device.h>
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/pci.h>
65 #include <linux/interrupt.h>
66 #include <linux/slab.h>
67 #include <linux/dmapool.h>
68 #include <linux/amba/bus.h>
69 #include <linux/dmaengine.h>
70 #include <linux/amba/pl08x.h>
71 #include <linux/debugfs.h>
72 #include <linux/seq_file.h>
74 #include <asm/hardware/pl080.h>
76 #include <asm/mach/dma.h>
77 #include <asm/processor.h>
78 #include <asm/cacheflush.h>
80 #define DRIVER_NAME "pl08xdmac"
83 * struct vendor_data - vendor-specific config parameters
84 * for PL08x derivatives
85 * @name: the name of this specific variant
86 * @channels: the number of channels available in this variant
87 * @dualmaster: whether this version supports dual AHB masters
97 * PL08X private data structures
98 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
99 * start & end do not - their bus bit info is in cctl.
109 * struct pl08x_driver_data - the local state holder for the PL08x
110 * @slave: slave engine for this instance
111 * @memcpy: memcpy engine for this instance
112 * @base: virtual memory base (remapped) for the PL08x
113 * @adev: the corresponding AMBA (PrimeCell) bus entry
114 * @vd: vendor data for this PL08x variant
115 * @pd: platform data passed in from the platform/machine
116 * @phy_chans: array of data for the physical channels
117 * @pool: a pool for the LLI descriptors
118 * @pool_ctr: counter of LLIs in the pool
119 * @lock: a spinlock for this struct
121 struct pl08x_driver_data
{
122 struct dma_device slave
;
123 struct dma_device memcpy
;
125 struct amba_device
*adev
;
126 struct vendor_data
*vd
;
127 struct pl08x_platform_data
*pd
;
128 struct pl08x_phy_chan
*phy_chans
;
129 struct dma_pool
*pool
;
135 * PL08X specific defines
139 * Memory boundaries: the manual for PL08x says that the controller
140 * cannot read past a 1KiB boundary, so these defines are used to
141 * create transfer LLIs that do not cross such boundaries.
143 #define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */
144 #define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT)
146 /* Minimum period between work queue runs */
147 #define PL08X_WQ_PERIODMIN 20
149 /* Size (bytes) of each LLI buffer allocated for one transfer */
150 # define PL08X_LLI_TSFR_SIZE 0x2000
152 /* Maximum times we call dma_pool_alloc on this pool without freeing */
153 #define PL08X_MAX_ALLOCS 0x40
154 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct lli))
155 #define PL08X_ALIGN 8
157 static inline struct pl08x_dma_chan
*to_pl08x_chan(struct dma_chan
*chan
)
159 return container_of(chan
, struct pl08x_dma_chan
, chan
);
163 * Physical channel handling
166 /* Whether a certain channel is busy or not */
167 static int pl08x_phy_channel_busy(struct pl08x_phy_chan
*ch
)
171 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
172 return val
& PL080_CONFIG_ACTIVE
;
176 * Set the initial DMA register values i.e. those for the first LLI
177 * The next LLI pointer and the configuration interrupt bit have
178 * been set when the LLIs were constructed
180 static void pl08x_set_cregs(struct pl08x_driver_data
*pl08x
,
181 struct pl08x_phy_chan
*ch
)
183 /* Wait for channel inactive */
184 while (pl08x_phy_channel_busy(ch
))
187 dev_vdbg(&pl08x
->adev
->dev
,
188 "WRITE channel %d: csrc=%08x, cdst=%08x, "
189 "cctl=%08x, clli=%08x, ccfg=%08x\n",
197 writel(ch
->csrc
, ch
->base
+ PL080_CH_SRC_ADDR
);
198 writel(ch
->cdst
, ch
->base
+ PL080_CH_DST_ADDR
);
199 writel(ch
->clli
, ch
->base
+ PL080_CH_LLI
);
200 writel(ch
->cctl
, ch
->base
+ PL080_CH_CONTROL
);
201 writel(ch
->ccfg
, ch
->base
+ PL080_CH_CONFIG
);
204 static inline void pl08x_config_phychan_for_txd(struct pl08x_dma_chan
*plchan
)
206 struct pl08x_channel_data
*cd
= plchan
->cd
;
207 struct pl08x_phy_chan
*phychan
= plchan
->phychan
;
208 struct pl08x_txd
*txd
= plchan
->at
;
210 /* Copy the basic control register calculated at transfer config */
211 phychan
->csrc
= txd
->csrc
;
212 phychan
->cdst
= txd
->cdst
;
213 phychan
->clli
= txd
->clli
;
214 phychan
->cctl
= txd
->cctl
;
216 /* Assign the signal to the proper control registers */
217 phychan
->ccfg
= cd
->ccfg
;
218 phychan
->ccfg
&= ~PL080_CONFIG_SRC_SEL_MASK
;
219 phychan
->ccfg
&= ~PL080_CONFIG_DST_SEL_MASK
;
220 /* If it wasn't set from AMBA, ignore it */
221 if (txd
->direction
== DMA_TO_DEVICE
)
222 /* Select signal as destination */
224 (phychan
->signal
<< PL080_CONFIG_DST_SEL_SHIFT
);
225 else if (txd
->direction
== DMA_FROM_DEVICE
)
226 /* Select signal as source */
228 (phychan
->signal
<< PL080_CONFIG_SRC_SEL_SHIFT
);
229 /* Always enable error interrupts */
230 phychan
->ccfg
|= PL080_CONFIG_ERR_IRQ_MASK
;
231 /* Always enable terminal interrupts */
232 phychan
->ccfg
|= PL080_CONFIG_TC_IRQ_MASK
;
236 * Enable the DMA channel
237 * Assumes all other configuration bits have been set
238 * as desired before this code is called
240 static void pl08x_enable_phy_chan(struct pl08x_driver_data
*pl08x
,
241 struct pl08x_phy_chan
*ch
)
246 * Do not access config register until channel shows as disabled
248 while (readl(pl08x
->base
+ PL080_EN_CHAN
) & (1 << ch
->id
))
252 * Do not access config register until channel shows as inactive
254 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
255 while ((val
& PL080_CONFIG_ACTIVE
) || (val
& PL080_CONFIG_ENABLE
))
256 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
258 writel(val
| PL080_CONFIG_ENABLE
, ch
->base
+ PL080_CH_CONFIG
);
262 * Overall DMAC remains enabled always.
264 * Disabling individual channels could lose data.
266 * Disable the peripheral DMA after disabling the DMAC
267 * in order to allow the DMAC FIFO to drain, and
268 * hence allow the channel to show inactive
271 static void pl08x_pause_phy_chan(struct pl08x_phy_chan
*ch
)
275 /* Set the HALT bit and wait for the FIFO to drain */
276 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
277 val
|= PL080_CONFIG_HALT
;
278 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
280 /* Wait for channel inactive */
281 while (pl08x_phy_channel_busy(ch
))
285 static void pl08x_resume_phy_chan(struct pl08x_phy_chan
*ch
)
289 /* Clear the HALT bit */
290 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
291 val
&= ~PL080_CONFIG_HALT
;
292 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
296 /* Stops the channel */
297 static void pl08x_stop_phy_chan(struct pl08x_phy_chan
*ch
)
301 pl08x_pause_phy_chan(ch
);
303 /* Disable channel */
304 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
305 val
&= ~PL080_CONFIG_ENABLE
;
306 val
&= ~PL080_CONFIG_ERR_IRQ_MASK
;
307 val
&= ~PL080_CONFIG_TC_IRQ_MASK
;
308 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
311 static inline u32
get_bytes_in_cctl(u32 cctl
)
313 /* The source width defines the number of bytes */
314 u32 bytes
= cctl
& PL080_CONTROL_TRANSFER_SIZE_MASK
;
316 switch (cctl
>> PL080_CONTROL_SWIDTH_SHIFT
) {
317 case PL080_WIDTH_8BIT
:
319 case PL080_WIDTH_16BIT
:
322 case PL080_WIDTH_32BIT
:
329 /* The channel should be paused when calling this */
330 static u32
pl08x_getbytes_chan(struct pl08x_dma_chan
*plchan
)
332 struct pl08x_phy_chan
*ch
;
333 struct pl08x_txd
*txdi
= NULL
;
334 struct pl08x_txd
*txd
;
338 spin_lock_irqsave(&plchan
->lock
, flags
);
340 ch
= plchan
->phychan
;
344 * Next follow the LLIs to get the number of pending bytes in the
345 * currently active transaction.
348 struct lli
*llis_va
= txd
->llis_va
;
349 struct lli
*llis_bus
= (struct lli
*) txd
->llis_bus
;
350 u32 clli
= readl(ch
->base
+ PL080_CH_LLI
);
352 /* First get the bytes in the current active LLI */
353 bytes
= get_bytes_in_cctl(readl(ch
->base
+ PL080_CH_CONTROL
));
358 /* Forward to the LLI pointed to by clli */
359 while ((clli
!= (u32
) &(llis_bus
[i
])) &&
360 (i
< MAX_NUM_TSFR_LLIS
))
364 bytes
+= get_bytes_in_cctl(llis_va
[i
].cctl
);
366 * A LLI pointer of 0 terminates the LLI list
368 clli
= llis_va
[i
].next
;
374 /* Sum up all queued transactions */
375 if (!list_empty(&plchan
->desc_list
)) {
376 list_for_each_entry(txdi
, &plchan
->desc_list
, node
) {
382 spin_unlock_irqrestore(&plchan
->lock
, flags
);
388 * Allocate a physical channel for a virtual channel
390 static struct pl08x_phy_chan
*
391 pl08x_get_phy_channel(struct pl08x_driver_data
*pl08x
,
392 struct pl08x_dma_chan
*virt_chan
)
394 struct pl08x_phy_chan
*ch
= NULL
;
399 * Try to locate a physical channel to be used for
400 * this transfer. If all are taken return NULL and
401 * the requester will have to cope by using some fallback
402 * PIO mode or retrying later.
404 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
405 ch
= &pl08x
->phy_chans
[i
];
407 spin_lock_irqsave(&ch
->lock
, flags
);
410 ch
->serving
= virt_chan
;
412 spin_unlock_irqrestore(&ch
->lock
, flags
);
416 spin_unlock_irqrestore(&ch
->lock
, flags
);
419 if (i
== pl08x
->vd
->channels
) {
420 /* No physical channel available, cope with it */
427 static inline void pl08x_put_phy_channel(struct pl08x_driver_data
*pl08x
,
428 struct pl08x_phy_chan
*ch
)
432 /* Stop the channel and clear its interrupts */
433 pl08x_stop_phy_chan(ch
);
434 writel((1 << ch
->id
), pl08x
->base
+ PL080_ERR_CLEAR
);
435 writel((1 << ch
->id
), pl08x
->base
+ PL080_TC_CLEAR
);
437 /* Mark it as free */
438 spin_lock_irqsave(&ch
->lock
, flags
);
440 spin_unlock_irqrestore(&ch
->lock
, flags
);
447 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded
)
450 case PL080_WIDTH_8BIT
:
452 case PL080_WIDTH_16BIT
:
454 case PL080_WIDTH_32BIT
:
463 static inline u32
pl08x_cctl_bits(u32 cctl
, u8 srcwidth
, u8 dstwidth
,
468 /* Remove all src, dst and transfer size bits */
469 retbits
&= ~PL080_CONTROL_DWIDTH_MASK
;
470 retbits
&= ~PL080_CONTROL_SWIDTH_MASK
;
471 retbits
&= ~PL080_CONTROL_TRANSFER_SIZE_MASK
;
473 /* Then set the bits according to the parameters */
476 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
479 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
482 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
491 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
494 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
497 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
504 retbits
|= tsize
<< PL080_CONTROL_TRANSFER_SIZE_SHIFT
;
509 * Autoselect a master bus to use for the transfer
510 * this prefers the destination bus if both available
511 * if fixed address on one bus the other will be chosen
513 void pl08x_choose_master_bus(struct pl08x_bus_data
*src_bus
,
514 struct pl08x_bus_data
*dst_bus
, struct pl08x_bus_data
**mbus
,
515 struct pl08x_bus_data
**sbus
, u32 cctl
)
517 if (!(cctl
& PL080_CONTROL_DST_INCR
)) {
520 } else if (!(cctl
& PL080_CONTROL_SRC_INCR
)) {
524 if (dst_bus
->buswidth
== 4) {
527 } else if (src_bus
->buswidth
== 4) {
530 } else if (dst_bus
->buswidth
== 2) {
533 } else if (src_bus
->buswidth
== 2) {
537 /* src_bus->buswidth == 1 */
545 * Fills in one LLI for a certain transfer descriptor
546 * and advance the counter
548 int pl08x_fill_lli_for_desc(struct pl08x_driver_data
*pl08x
,
549 struct pl08x_txd
*txd
, int num_llis
, int len
,
550 u32 cctl
, u32
*remainder
)
552 struct lli
*llis_va
= txd
->llis_va
;
553 struct lli
*llis_bus
= (struct lli
*) txd
->llis_bus
;
555 BUG_ON(num_llis
>= MAX_NUM_TSFR_LLIS
);
557 llis_va
[num_llis
].cctl
= cctl
;
558 llis_va
[num_llis
].src
= txd
->srcbus
.addr
;
559 llis_va
[num_llis
].dst
= txd
->dstbus
.addr
;
562 * On versions with dual masters, you can optionally AND on
563 * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read
564 * in new LLIs with that controller, but we always try to
565 * choose AHB1 to point into memory. The idea is to have AHB2
566 * fixed on the peripheral and AHB1 messing around in the
567 * memory. So we don't manipulate this bit currently.
570 llis_va
[num_llis
].next
=
571 (dma_addr_t
)((u32
) &(llis_bus
[num_llis
+ 1]));
573 if (cctl
& PL080_CONTROL_SRC_INCR
)
574 txd
->srcbus
.addr
+= len
;
575 if (cctl
& PL080_CONTROL_DST_INCR
)
576 txd
->dstbus
.addr
+= len
;
584 * Return number of bytes to fill to boundary, or len
586 static inline u32
pl08x_pre_boundary(u32 addr
, u32 len
)
590 boundary
= ((addr
>> PL08X_BOUNDARY_SHIFT
) + 1)
591 << PL08X_BOUNDARY_SHIFT
;
593 if (boundary
< addr
+ len
)
594 return boundary
- addr
;
600 * This fills in the table of LLIs for the transfer descriptor
601 * Note that we assume we never have to change the burst sizes
604 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data
*pl08x
,
605 struct pl08x_txd
*txd
)
607 struct pl08x_channel_data
*cd
= txd
->cd
;
608 struct pl08x_bus_data
*mbus
, *sbus
;
612 int max_bytes_per_lli
;
615 struct lli
*llis_bus
;
618 dev_err(&pl08x
->adev
->dev
, "%s no descriptor\n", __func__
);
622 txd
->llis_va
= dma_pool_alloc(pl08x
->pool
, GFP_NOWAIT
,
625 dev_err(&pl08x
->adev
->dev
, "%s no memory for llis\n", __func__
);
632 * Initialize bus values for this transfer
633 * from the passed optimal values
636 dev_err(&pl08x
->adev
->dev
, "%s no channel data\n", __func__
);
640 /* Get the default CCTL from the platform data */
644 * On the PL080 we have two bus masters and we
645 * should select one for source and one for
646 * destination. We try to use AHB2 for the
647 * bus which does not increment (typically the
648 * peripheral) else we just choose something.
650 cctl
&= ~(PL080_CONTROL_DST_AHB2
| PL080_CONTROL_SRC_AHB2
);
651 if (pl08x
->vd
->dualmaster
) {
652 if (cctl
& PL080_CONTROL_SRC_INCR
)
653 /* Source increments, use AHB2 for destination */
654 cctl
|= PL080_CONTROL_DST_AHB2
;
655 else if (cctl
& PL080_CONTROL_DST_INCR
)
656 /* Destination increments, use AHB2 for source */
657 cctl
|= PL080_CONTROL_SRC_AHB2
;
659 /* Just pick something, source AHB1 dest AHB2 */
660 cctl
|= PL080_CONTROL_DST_AHB2
;
663 /* Find maximum width of the source bus */
664 txd
->srcbus
.maxwidth
=
665 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_SWIDTH_MASK
) >>
666 PL080_CONTROL_SWIDTH_SHIFT
);
668 /* Find maximum width of the destination bus */
669 txd
->dstbus
.maxwidth
=
670 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_DWIDTH_MASK
) >>
671 PL080_CONTROL_DWIDTH_SHIFT
);
673 /* Set up the bus widths to the maximum */
674 txd
->srcbus
.buswidth
= txd
->srcbus
.maxwidth
;
675 txd
->dstbus
.buswidth
= txd
->dstbus
.maxwidth
;
676 dev_vdbg(&pl08x
->adev
->dev
,
677 "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
678 __func__
, txd
->srcbus
.buswidth
, txd
->dstbus
.buswidth
);
682 * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
684 max_bytes_per_lli
= min(txd
->srcbus
.buswidth
, txd
->dstbus
.buswidth
) *
685 PL080_CONTROL_TRANSFER_SIZE_MASK
;
686 dev_vdbg(&pl08x
->adev
->dev
,
687 "%s max bytes per lli = %d\n",
688 __func__
, max_bytes_per_lli
);
690 /* We need to count this down to zero */
691 remainder
= txd
->len
;
692 dev_vdbg(&pl08x
->adev
->dev
,
693 "%s remainder = %d\n",
694 __func__
, remainder
);
697 * Choose bus to align to
698 * - prefers destination bus if both available
699 * - if fixed address on one bus chooses other
700 * - modifies cctl to choose an appropriate master
702 pl08x_choose_master_bus(&txd
->srcbus
, &txd
->dstbus
,
707 * The lowest bit of the LLI register
708 * is also used to indicate which master to
709 * use for reading the LLIs.
712 if (txd
->len
< mbus
->buswidth
) {
714 * Less than a bus width available
715 * - send as single bytes
718 dev_vdbg(&pl08x
->adev
->dev
,
719 "%s single byte LLIs for a transfer of "
720 "less than a bus width (remain %08x)\n",
721 __func__
, remainder
);
722 cctl
= pl08x_cctl_bits(cctl
, 1, 1, 1);
724 pl08x_fill_lli_for_desc(pl08x
, txd
, num_llis
, 1,
730 * Make one byte LLIs until master bus is aligned
731 * - slave will then be aligned also
733 while ((mbus
->addr
) % (mbus
->buswidth
)) {
734 dev_vdbg(&pl08x
->adev
->dev
,
735 "%s adjustment lli for less than bus width "
737 __func__
, remainder
);
738 cctl
= pl08x_cctl_bits(cctl
, 1, 1, 1);
739 num_llis
= pl08x_fill_lli_for_desc
740 (pl08x
, txd
, num_llis
, 1, cctl
, &remainder
);
746 * - if slave is not then we must set its width down
748 if (sbus
->addr
% sbus
->buswidth
) {
749 dev_dbg(&pl08x
->adev
->dev
,
750 "%s set down bus width to one byte\n",
757 * Make largest possible LLIs until less than one bus
760 while (remainder
> (mbus
->buswidth
- 1)) {
761 int lli_len
, target_len
;
766 * If enough left try to send max possible,
767 * otherwise try to send the remainder
769 target_len
= remainder
;
770 if (remainder
> max_bytes_per_lli
)
771 target_len
= max_bytes_per_lli
;
774 * Set bus lengths for incrementing buses
775 * to number of bytes which fill to next memory
778 if (cctl
& PL080_CONTROL_SRC_INCR
)
779 txd
->srcbus
.fill_bytes
=
784 txd
->srcbus
.fill_bytes
=
787 if (cctl
& PL080_CONTROL_DST_INCR
)
788 txd
->dstbus
.fill_bytes
=
793 txd
->dstbus
.fill_bytes
=
799 lli_len
= min(txd
->srcbus
.fill_bytes
,
800 txd
->dstbus
.fill_bytes
);
802 BUG_ON(lli_len
> remainder
);
805 dev_err(&pl08x
->adev
->dev
,
806 "%s lli_len is %d, <= 0\n",
811 if (lli_len
== target_len
) {
813 * Can send what we wanted
818 lli_len
= (lli_len
/mbus
->buswidth
) *
823 * So now we know how many bytes to transfer
824 * to get to the nearest boundary
825 * The next LLI will past the boundary
826 * - however we may be working to a boundary
828 * We need to ensure the master stays aligned
830 odd_bytes
= lli_len
% mbus
->buswidth
;
832 * - and that we are working in multiples
835 lli_len
-= odd_bytes
;
841 * Check against minimum bus alignment:
842 * Calculate actual transfer size in relation
843 * to bus width an get a maximum remainder of
844 * the smallest bus width - 1
846 /* FIXME: use round_down()? */
847 tsize
= lli_len
/ min(mbus
->buswidth
,
849 lli_len
= tsize
* min(mbus
->buswidth
,
852 if (target_len
!= lli_len
) {
853 dev_vdbg(&pl08x
->adev
->dev
,
854 "%s can't send what we want. Desired %08x, lli of %08x bytes in txd of %08x\n",
855 __func__
, target_len
, lli_len
, txd
->len
);
858 cctl
= pl08x_cctl_bits(cctl
,
859 txd
->srcbus
.buswidth
,
860 txd
->dstbus
.buswidth
,
863 dev_vdbg(&pl08x
->adev
->dev
,
864 "%s fill lli with single lli chunk of size %08x (remainder %08x)\n",
865 __func__
, lli_len
, remainder
);
866 num_llis
= pl08x_fill_lli_for_desc(pl08x
, txd
,
867 num_llis
, lli_len
, cctl
,
869 total_bytes
+= lli_len
;
875 * Creep past the boundary,
876 * maintaining master alignment
879 for (j
= 0; (j
< mbus
->buswidth
)
880 && (remainder
); j
++) {
881 cctl
= pl08x_cctl_bits(cctl
, 1, 1, 1);
882 dev_vdbg(&pl08x
->adev
->dev
,
883 "%s align with boundary, single byte (remain %08x)\n",
884 __func__
, remainder
);
886 pl08x_fill_lli_for_desc(pl08x
,
898 dev_err(&pl08x
->adev
->dev
, "%s remainder not fitted 0x%08x bytes\n",
899 __func__
, remainder
);
904 cctl
= pl08x_cctl_bits(cctl
, 1, 1, 1);
905 dev_vdbg(&pl08x
->adev
->dev
,
906 "%s align with boundary, single odd byte (remain %d)\n",
907 __func__
, remainder
);
908 num_llis
= pl08x_fill_lli_for_desc(pl08x
, txd
, num_llis
,
909 1, cctl
, &remainder
);
913 if (total_bytes
!= txd
->len
) {
914 dev_err(&pl08x
->adev
->dev
,
915 "%s size of encoded lli:s don't match total txd, transferred 0x%08x from size 0x%08x\n",
916 __func__
, total_bytes
, txd
->len
);
920 if (num_llis
>= MAX_NUM_TSFR_LLIS
) {
921 dev_err(&pl08x
->adev
->dev
,
922 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
923 __func__
, (u32
) MAX_NUM_TSFR_LLIS
);
927 * Decide whether this is a loop or a terminated transfer
929 llis_va
= txd
->llis_va
;
930 llis_bus
= (struct lli
*) txd
->llis_bus
;
932 if (cd
->circular_buffer
) {
934 * Loop the circular buffer so that the next element
935 * points back to the beginning of the LLI.
937 llis_va
[num_llis
- 1].next
=
938 (dma_addr_t
)((unsigned int)&(llis_bus
[0]));
941 * On non-circular buffers, the final LLI terminates
944 llis_va
[num_llis
- 1].next
= 0;
946 * The final LLI element shall also fire an interrupt
948 llis_va
[num_llis
- 1].cctl
|= PL080_CONTROL_TC_IRQ_EN
;
951 /* Now store the channel register values */
952 txd
->csrc
= llis_va
[0].src
;
953 txd
->cdst
= llis_va
[0].dst
;
955 txd
->clli
= llis_va
[0].next
;
959 txd
->cctl
= llis_va
[0].cctl
;
960 /* ccfg will be set at physical channel allocation time */
966 for (i
= 0; i
< num_llis
; i
++) {
967 dev_vdbg(&pl08x
->adev
->dev
,
968 "lli %d @%p: csrc=%08x, cdst=%08x, cctl=%08x, clli=%08x\n",
983 /* You should call this with the struct pl08x lock held */
984 static void pl08x_free_txd(struct pl08x_driver_data
*pl08x
,
985 struct pl08x_txd
*txd
)
988 dev_err(&pl08x
->adev
->dev
,
989 "%s no descriptor to free\n",
993 dma_pool_free(pl08x
->pool
, txd
->llis_va
,
1001 static void pl08x_free_txd_list(struct pl08x_driver_data
*pl08x
,
1002 struct pl08x_dma_chan
*plchan
)
1004 struct pl08x_txd
*txdi
= NULL
;
1005 struct pl08x_txd
*next
;
1007 if (!list_empty(&plchan
->desc_list
)) {
1008 list_for_each_entry_safe(txdi
,
1009 next
, &plchan
->desc_list
, node
) {
1010 list_del(&txdi
->node
);
1011 pl08x_free_txd(pl08x
, txdi
);
1018 * The DMA ENGINE API
1020 static int pl08x_alloc_chan_resources(struct dma_chan
*chan
)
1025 static void pl08x_free_chan_resources(struct dma_chan
*chan
)
1030 * This should be called with the channel plchan->lock held
1032 static int prep_phy_channel(struct pl08x_dma_chan
*plchan
,
1033 struct pl08x_txd
*txd
)
1035 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1036 struct pl08x_phy_chan
*ch
;
1039 /* Check if we already have a channel */
1040 if (plchan
->phychan
)
1043 ch
= pl08x_get_phy_channel(pl08x
, plchan
);
1045 /* No physical channel available, cope with it */
1046 dev_dbg(&pl08x
->adev
->dev
, "no physical channel available for xfer on %s\n", plchan
->name
);
1051 * OK we have a physical channel: for memcpy() this is all we
1052 * need, but for slaves the physical signals may be muxed!
1053 * Can the platform allow us to use this channel?
1055 if (plchan
->slave
&&
1057 pl08x
->pd
->get_signal
) {
1058 ret
= pl08x
->pd
->get_signal(plchan
);
1060 dev_dbg(&pl08x
->adev
->dev
,
1061 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
1062 ch
->id
, plchan
->name
);
1063 /* Release physical channel & return */
1064 pl08x_put_phy_channel(pl08x
, ch
);
1070 dev_dbg(&pl08x
->adev
->dev
, "allocated physical channel %d and signal %d for xfer on %s\n",
1075 plchan
->phychan
= ch
;
1080 static dma_cookie_t
pl08x_tx_submit(struct dma_async_tx_descriptor
*tx
)
1082 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(tx
->chan
);
1084 plchan
->chan
.cookie
+= 1;
1085 if (plchan
->chan
.cookie
< 0)
1086 plchan
->chan
.cookie
= 1;
1087 tx
->cookie
= plchan
->chan
.cookie
;
1088 /* This unlock follows the lock in the prep() function */
1089 spin_unlock_irqrestore(&plchan
->lock
, plchan
->lockflags
);
1094 static struct dma_async_tx_descriptor
*pl08x_prep_dma_interrupt(
1095 struct dma_chan
*chan
, unsigned long flags
)
1097 struct dma_async_tx_descriptor
*retval
= NULL
;
1103 * Code accessing dma_async_is_complete() in a tight loop
1104 * may give problems - could schedule where indicated.
1105 * If slaves are relying on interrupts to signal completion this
1106 * function must not be called with interrupts disabled
1108 static enum dma_status
1109 pl08x_dma_tx_status(struct dma_chan
*chan
,
1110 dma_cookie_t cookie
,
1111 struct dma_tx_state
*txstate
)
1113 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1114 dma_cookie_t last_used
;
1115 dma_cookie_t last_complete
;
1116 enum dma_status ret
;
1119 last_used
= plchan
->chan
.cookie
;
1120 last_complete
= plchan
->lc
;
1122 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
1123 if (ret
== DMA_SUCCESS
) {
1124 dma_set_tx_state(txstate
, last_complete
, last_used
, 0);
1129 * schedule(); could be inserted here
1133 * This cookie not complete yet
1135 last_used
= plchan
->chan
.cookie
;
1136 last_complete
= plchan
->lc
;
1138 /* Get number of bytes left in the active transactions and queue */
1139 bytesleft
= pl08x_getbytes_chan(plchan
);
1141 dma_set_tx_state(txstate
, last_complete
, last_used
,
1144 if (plchan
->state
== PL08X_CHAN_PAUSED
)
1147 /* Whether waiting or running, we're in progress */
1148 return DMA_IN_PROGRESS
;
1151 /* PrimeCell DMA extension */
1152 struct burst_table
{
1157 static const struct burst_table burst_sizes
[] = {
1160 .reg
= (PL080_BSIZE_256
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1161 (PL080_BSIZE_256
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1165 .reg
= (PL080_BSIZE_128
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1166 (PL080_BSIZE_128
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1170 .reg
= (PL080_BSIZE_64
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1171 (PL080_BSIZE_64
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1175 .reg
= (PL080_BSIZE_32
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1176 (PL080_BSIZE_32
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1180 .reg
= (PL080_BSIZE_16
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1181 (PL080_BSIZE_16
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1185 .reg
= (PL080_BSIZE_8
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1186 (PL080_BSIZE_8
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1190 .reg
= (PL080_BSIZE_4
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1191 (PL080_BSIZE_4
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1195 .reg
= (PL080_BSIZE_1
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1196 (PL080_BSIZE_1
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1200 static void dma_set_runtime_config(struct dma_chan
*chan
,
1201 struct dma_slave_config
*config
)
1203 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1204 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1205 struct pl08x_channel_data
*cd
= plchan
->cd
;
1206 enum dma_slave_buswidth addr_width
;
1209 /* Mask out all except src and dst channel */
1210 u32 ccfg
= cd
->ccfg
& 0x000003DEU
;
1213 /* Transfer direction */
1214 plchan
->runtime_direction
= config
->direction
;
1215 if (config
->direction
== DMA_TO_DEVICE
) {
1216 plchan
->runtime_addr
= config
->dst_addr
;
1217 cctl
|= PL080_CONTROL_SRC_INCR
;
1218 ccfg
|= PL080_FLOW_MEM2PER
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1219 addr_width
= config
->dst_addr_width
;
1220 maxburst
= config
->dst_maxburst
;
1221 } else if (config
->direction
== DMA_FROM_DEVICE
) {
1222 plchan
->runtime_addr
= config
->src_addr
;
1223 cctl
|= PL080_CONTROL_DST_INCR
;
1224 ccfg
|= PL080_FLOW_PER2MEM
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1225 addr_width
= config
->src_addr_width
;
1226 maxburst
= config
->src_maxburst
;
1228 dev_err(&pl08x
->adev
->dev
,
1229 "bad runtime_config: alien transfer direction\n");
1233 switch (addr_width
) {
1234 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
1235 cctl
|= (PL080_WIDTH_8BIT
<< PL080_CONTROL_SWIDTH_SHIFT
) |
1236 (PL080_WIDTH_8BIT
<< PL080_CONTROL_DWIDTH_SHIFT
);
1238 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
1239 cctl
|= (PL080_WIDTH_16BIT
<< PL080_CONTROL_SWIDTH_SHIFT
) |
1240 (PL080_WIDTH_16BIT
<< PL080_CONTROL_DWIDTH_SHIFT
);
1242 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
1243 cctl
|= (PL080_WIDTH_32BIT
<< PL080_CONTROL_SWIDTH_SHIFT
) |
1244 (PL080_WIDTH_32BIT
<< PL080_CONTROL_DWIDTH_SHIFT
);
1247 dev_err(&pl08x
->adev
->dev
,
1248 "bad runtime_config: alien address width\n");
1253 * Now decide on a maxburst:
1254 * If this channel will only request single transfers, set this
1255 * down to ONE element. Also select one element if no maxburst
1258 if (plchan
->cd
->single
|| maxburst
== 0) {
1259 cctl
|= (PL080_BSIZE_1
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1260 (PL080_BSIZE_1
<< PL080_CONTROL_DB_SIZE_SHIFT
);
1262 for (i
= 0; i
< ARRAY_SIZE(burst_sizes
); i
++)
1263 if (burst_sizes
[i
].burstwords
<= maxburst
)
1265 cctl
|= burst_sizes
[i
].reg
;
1268 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1269 cctl
&= ~PL080_CONTROL_PROT_MASK
;
1270 cctl
|= PL080_CONTROL_PROT_SYS
;
1272 /* Modify the default channel data to fit PrimeCell request */
1276 dev_dbg(&pl08x
->adev
->dev
,
1277 "configured channel %s (%s) for %s, data width %d, "
1278 "maxburst %d words, LE, CCTL=%08x, CCFG=%08x\n",
1279 dma_chan_name(chan
), plchan
->name
,
1280 (config
->direction
== DMA_FROM_DEVICE
) ? "RX" : "TX",
1287 * Slave transactions callback to the slave device to allow
1288 * synchronization of slave DMA signals with the DMAC enable
1290 static void pl08x_issue_pending(struct dma_chan
*chan
)
1292 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1293 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1294 unsigned long flags
;
1296 spin_lock_irqsave(&plchan
->lock
, flags
);
1297 /* Something is already active */
1299 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1303 /* Didn't get a physical channel so waiting for it ... */
1304 if (plchan
->state
== PL08X_CHAN_WAITING
)
1307 /* Take the first element in the queue and execute it */
1308 if (!list_empty(&plchan
->desc_list
)) {
1309 struct pl08x_txd
*next
;
1311 next
= list_first_entry(&plchan
->desc_list
,
1314 list_del(&next
->node
);
1316 plchan
->state
= PL08X_CHAN_RUNNING
;
1318 /* Configure the physical channel for the active txd */
1319 pl08x_config_phychan_for_txd(plchan
);
1320 pl08x_set_cregs(pl08x
, plchan
->phychan
);
1321 pl08x_enable_phy_chan(pl08x
, plchan
->phychan
);
1324 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1327 static int pl08x_prep_channel_resources(struct pl08x_dma_chan
*plchan
,
1328 struct pl08x_txd
*txd
)
1331 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1334 num_llis
= pl08x_fill_llis_for_desc(pl08x
, txd
);
1340 spin_lock_irqsave(&plchan
->lock
, plchan
->lockflags
);
1343 * If this device is not using a circular buffer then
1344 * queue this new descriptor for transfer.
1345 * The descriptor for a circular buffer continues
1346 * to be used until the channel is freed.
1348 if (txd
->cd
->circular_buffer
)
1349 dev_err(&pl08x
->adev
->dev
,
1350 "%s attempting to queue a circular buffer\n",
1353 list_add_tail(&txd
->node
,
1354 &plchan
->desc_list
);
1357 * See if we already have a physical channel allocated,
1358 * else this is the time to try to get one.
1360 ret
= prep_phy_channel(plchan
, txd
);
1363 * No physical channel available, we will
1364 * stack up the memcpy channels until there is a channel
1365 * available to handle it whereas slave transfers may
1366 * have been denied due to platform channel muxing restrictions
1367 * and since there is no guarantee that this will ever be
1368 * resolved, and since the signal must be acquired AFTER
1369 * acquiring the physical channel, we will let them be NACK:ed
1370 * with -EBUSY here. The drivers can alway retry the prep()
1371 * call if they are eager on doing this using DMA.
1373 if (plchan
->slave
) {
1374 pl08x_free_txd_list(pl08x
, plchan
);
1375 spin_unlock_irqrestore(&plchan
->lock
, plchan
->lockflags
);
1378 /* Do this memcpy whenever there is a channel ready */
1379 plchan
->state
= PL08X_CHAN_WAITING
;
1380 plchan
->waiting
= txd
;
1383 * Else we're all set, paused and ready to roll,
1384 * status will switch to PL08X_CHAN_RUNNING when
1385 * we call issue_pending(). If there is something
1386 * running on the channel already we don't change
1389 if (plchan
->state
== PL08X_CHAN_IDLE
)
1390 plchan
->state
= PL08X_CHAN_PAUSED
;
1393 * Notice that we leave plchan->lock locked on purpose:
1394 * it will be unlocked in the subsequent tx_submit()
1395 * call. This is a consequence of the current API.
1402 * Initialize a descriptor to be used by memcpy submit
1404 static struct dma_async_tx_descriptor
*pl08x_prep_dma_memcpy(
1405 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
1406 size_t len
, unsigned long flags
)
1408 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1409 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1410 struct pl08x_txd
*txd
;
1413 txd
= kzalloc(sizeof(struct pl08x_txd
), GFP_NOWAIT
);
1415 dev_err(&pl08x
->adev
->dev
,
1416 "%s no memory for descriptor\n", __func__
);
1420 dma_async_tx_descriptor_init(&txd
->tx
, chan
);
1421 txd
->direction
= DMA_NONE
;
1422 txd
->srcbus
.addr
= src
;
1423 txd
->dstbus
.addr
= dest
;
1425 /* Set platform data for m2m */
1426 txd
->cd
= &pl08x
->pd
->memcpy_channel
;
1427 /* Both to be incremented or the code will break */
1428 txd
->cd
->cctl
|= PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
;
1429 txd
->tx
.tx_submit
= pl08x_tx_submit
;
1430 txd
->tx
.callback
= NULL
;
1431 txd
->tx
.callback_param
= NULL
;
1434 INIT_LIST_HEAD(&txd
->node
);
1435 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1439 * NB: the channel lock is held at this point so tx_submit()
1440 * must be called in direct succession.
1446 struct dma_async_tx_descriptor
*pl08x_prep_slave_sg(
1447 struct dma_chan
*chan
, struct scatterlist
*sgl
,
1448 unsigned int sg_len
, enum dma_data_direction direction
,
1449 unsigned long flags
)
1451 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1452 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1453 struct pl08x_txd
*txd
;
1457 * Current implementation ASSUMES only one sg
1460 dev_err(&pl08x
->adev
->dev
, "%s prepared too long sglist\n",
1465 dev_dbg(&pl08x
->adev
->dev
, "%s prepare transaction of %d bytes from %s\n",
1466 __func__
, sgl
->length
, plchan
->name
);
1468 txd
= kzalloc(sizeof(struct pl08x_txd
), GFP_NOWAIT
);
1470 dev_err(&pl08x
->adev
->dev
, "%s no txd\n", __func__
);
1474 dma_async_tx_descriptor_init(&txd
->tx
, chan
);
1476 if (direction
!= plchan
->runtime_direction
)
1477 dev_err(&pl08x
->adev
->dev
, "%s DMA setup does not match "
1478 "the direction configured for the PrimeCell\n",
1482 * Set up addresses, the PrimeCell configured address
1483 * will take precedence since this may configure the
1484 * channel target address dynamically at runtime.
1486 txd
->direction
= direction
;
1487 if (direction
== DMA_TO_DEVICE
) {
1488 txd
->srcbus
.addr
= sgl
->dma_address
;
1489 if (plchan
->runtime_addr
)
1490 txd
->dstbus
.addr
= plchan
->runtime_addr
;
1492 txd
->dstbus
.addr
= plchan
->cd
->addr
;
1493 } else if (direction
== DMA_FROM_DEVICE
) {
1494 if (plchan
->runtime_addr
)
1495 txd
->srcbus
.addr
= plchan
->runtime_addr
;
1497 txd
->srcbus
.addr
= plchan
->cd
->addr
;
1498 txd
->dstbus
.addr
= sgl
->dma_address
;
1500 dev_err(&pl08x
->adev
->dev
,
1501 "%s direction unsupported\n", __func__
);
1504 txd
->cd
= plchan
->cd
;
1505 txd
->tx
.tx_submit
= pl08x_tx_submit
;
1506 txd
->tx
.callback
= NULL
;
1507 txd
->tx
.callback_param
= NULL
;
1508 txd
->len
= sgl
->length
;
1509 INIT_LIST_HEAD(&txd
->node
);
1511 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1515 * NB: the channel lock is held at this point so tx_submit()
1516 * must be called in direct succession.
1522 static int pl08x_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
1525 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1526 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1527 unsigned long flags
;
1530 /* Controls applicable to inactive channels */
1531 if (cmd
== DMA_SLAVE_CONFIG
) {
1532 dma_set_runtime_config(chan
,
1533 (struct dma_slave_config
*)
1539 * Anything succeeds on channels with no physical allocation and
1540 * no queued transfers.
1542 spin_lock_irqsave(&plchan
->lock
, flags
);
1543 if (!plchan
->phychan
&& !plchan
->at
) {
1544 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1549 case DMA_TERMINATE_ALL
:
1550 plchan
->state
= PL08X_CHAN_IDLE
;
1552 if (plchan
->phychan
) {
1553 pl08x_stop_phy_chan(plchan
->phychan
);
1556 * Mark physical channel as free and free any slave
1559 if ((plchan
->phychan
->signal
>= 0) &&
1560 pl08x
->pd
->put_signal
) {
1561 pl08x
->pd
->put_signal(plchan
);
1562 plchan
->phychan
->signal
= -1;
1564 pl08x_put_phy_channel(pl08x
, plchan
->phychan
);
1565 plchan
->phychan
= NULL
;
1567 /* Stop any pending tasklet */
1568 tasklet_disable(&plchan
->tasklet
);
1569 /* Dequeue jobs and free LLIs */
1571 pl08x_free_txd(pl08x
, plchan
->at
);
1574 /* Dequeue jobs not yet fired as well */
1575 pl08x_free_txd_list(pl08x
, plchan
);
1578 pl08x_pause_phy_chan(plchan
->phychan
);
1579 plchan
->state
= PL08X_CHAN_PAUSED
;
1582 pl08x_resume_phy_chan(plchan
->phychan
);
1583 plchan
->state
= PL08X_CHAN_RUNNING
;
1586 /* Unknown command */
1591 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1596 bool pl08x_filter_id(struct dma_chan
*chan
, void *chan_id
)
1598 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1599 char *name
= chan_id
;
1601 /* Check that the channel is not taken! */
1602 if (!strcmp(plchan
->name
, name
))
1609 * Just check that the device is there and active
1610 * TODO: turn this bit on/off depending on the number of
1611 * physical channels actually used, if it is zero... well
1612 * shut it off. That will save some power. Cut the clock
1615 static void pl08x_ensure_on(struct pl08x_driver_data
*pl08x
)
1619 val
= readl(pl08x
->base
+ PL080_CONFIG
);
1620 val
&= ~(PL080_CONFIG_M2_BE
| PL080_CONFIG_M1_BE
| PL080_CONFIG_ENABLE
);
1621 /* We implicitly clear bit 1 and that means little-endian mode */
1622 val
|= PL080_CONFIG_ENABLE
;
1623 writel(val
, pl08x
->base
+ PL080_CONFIG
);
1626 static void pl08x_tasklet(unsigned long data
)
1628 struct pl08x_dma_chan
*plchan
= (struct pl08x_dma_chan
*) data
;
1629 struct pl08x_phy_chan
*phychan
= plchan
->phychan
;
1630 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1631 unsigned long flags
;
1636 spin_lock_irqsave(&plchan
->lock
, flags
);
1639 dma_async_tx_callback callback
=
1640 plchan
->at
->tx
.callback
;
1641 void *callback_param
=
1642 plchan
->at
->tx
.callback_param
;
1645 * Update last completed
1647 plchan
->lc
= plchan
->at
->tx
.cookie
;
1650 * Callback to signal completion
1653 callback(callback_param
);
1656 * Device callbacks should NOT clear
1657 * the current transaction on the channel
1658 * Linus: sometimes they should?
1664 * Free the descriptor if it's not for a device
1665 * using a circular buffer
1667 if (!plchan
->at
->cd
->circular_buffer
) {
1668 pl08x_free_txd(pl08x
, plchan
->at
);
1672 * else descriptor for circular
1673 * buffers only freed when
1674 * client has disabled dma
1678 * If a new descriptor is queued, set it up
1679 * plchan->at is NULL here
1681 if (!list_empty(&plchan
->desc_list
)) {
1682 struct pl08x_txd
*next
;
1684 next
= list_first_entry(&plchan
->desc_list
,
1687 list_del(&next
->node
);
1689 /* Configure the physical channel for the next txd */
1690 pl08x_config_phychan_for_txd(plchan
);
1691 pl08x_set_cregs(pl08x
, plchan
->phychan
);
1692 pl08x_enable_phy_chan(pl08x
, plchan
->phychan
);
1694 struct pl08x_dma_chan
*waiting
= NULL
;
1697 * No more jobs, so free up the physical channel
1698 * Free any allocated signal on slave transfers too
1700 if ((phychan
->signal
>= 0) && pl08x
->pd
->put_signal
) {
1701 pl08x
->pd
->put_signal(plchan
);
1702 phychan
->signal
= -1;
1704 pl08x_put_phy_channel(pl08x
, phychan
);
1705 plchan
->phychan
= NULL
;
1706 plchan
->state
= PL08X_CHAN_IDLE
;
1709 * And NOW before anyone else can grab that free:d
1710 * up physical channel, see if there is some memcpy
1711 * pending that seriously needs to start because of
1712 * being stacked up while we were choking the
1713 * physical channels with data.
1715 list_for_each_entry(waiting
, &pl08x
->memcpy
.channels
,
1717 if (waiting
->state
== PL08X_CHAN_WAITING
&&
1718 waiting
->waiting
!= NULL
) {
1721 /* This should REALLY not fail now */
1722 ret
= prep_phy_channel(waiting
,
1725 waiting
->state
= PL08X_CHAN_RUNNING
;
1726 waiting
->waiting
= NULL
;
1727 pl08x_issue_pending(&waiting
->chan
);
1733 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1736 static irqreturn_t
pl08x_irq(int irq
, void *dev
)
1738 struct pl08x_driver_data
*pl08x
= dev
;
1743 val
= readl(pl08x
->base
+ PL080_ERR_STATUS
);
1746 * An error interrupt (on one or more channels)
1748 dev_err(&pl08x
->adev
->dev
,
1749 "%s error interrupt, register value 0x%08x\n",
1752 * Simply clear ALL PL08X error interrupts,
1753 * regardless of channel and cause
1754 * FIXME: should be 0x00000003 on PL081 really.
1756 writel(0x000000FF, pl08x
->base
+ PL080_ERR_CLEAR
);
1758 val
= readl(pl08x
->base
+ PL080_INT_STATUS
);
1759 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1760 if ((1 << i
) & val
) {
1761 /* Locate physical channel */
1762 struct pl08x_phy_chan
*phychan
= &pl08x
->phy_chans
[i
];
1763 struct pl08x_dma_chan
*plchan
= phychan
->serving
;
1765 /* Schedule tasklet on this channel */
1766 tasklet_schedule(&plchan
->tasklet
);
1772 * Clear only the terminal interrupts on channels we processed
1774 writel(mask
, pl08x
->base
+ PL080_TC_CLEAR
);
1776 return mask
? IRQ_HANDLED
: IRQ_NONE
;
1780 * Initialise the DMAC memcpy/slave channels.
1781 * Make a local wrapper to hold required data
1783 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data
*pl08x
,
1784 struct dma_device
*dmadev
,
1785 unsigned int channels
,
1788 struct pl08x_dma_chan
*chan
;
1791 INIT_LIST_HEAD(&dmadev
->channels
);
1793 * Register as many many memcpy as we have physical channels,
1794 * we won't always be able to use all but the code will have
1795 * to cope with that situation.
1797 for (i
= 0; i
< channels
; i
++) {
1798 chan
= kzalloc(sizeof(struct pl08x_dma_chan
), GFP_KERNEL
);
1800 dev_err(&pl08x
->adev
->dev
,
1801 "%s no memory for channel\n", __func__
);
1806 chan
->state
= PL08X_CHAN_IDLE
;
1810 chan
->name
= pl08x
->pd
->slave_channels
[i
].bus_id
;
1811 chan
->cd
= &pl08x
->pd
->slave_channels
[i
];
1813 chan
->cd
= &pl08x
->pd
->memcpy_channel
;
1814 chan
->name
= kasprintf(GFP_KERNEL
, "memcpy%d", i
);
1820 dev_info(&pl08x
->adev
->dev
,
1821 "initialize virtual channel \"%s\"\n",
1824 chan
->chan
.device
= dmadev
;
1825 chan
->chan
.cookie
= 0;
1828 spin_lock_init(&chan
->lock
);
1829 INIT_LIST_HEAD(&chan
->desc_list
);
1830 tasklet_init(&chan
->tasklet
, pl08x_tasklet
,
1831 (unsigned long) chan
);
1833 list_add_tail(&chan
->chan
.device_node
, &dmadev
->channels
);
1835 dev_info(&pl08x
->adev
->dev
, "initialized %d virtual %s channels\n",
1836 i
, slave
? "slave" : "memcpy");
1840 static void pl08x_free_virtual_channels(struct dma_device
*dmadev
)
1842 struct pl08x_dma_chan
*chan
= NULL
;
1843 struct pl08x_dma_chan
*next
;
1845 list_for_each_entry_safe(chan
,
1846 next
, &dmadev
->channels
, chan
.device_node
) {
1847 list_del(&chan
->chan
.device_node
);
1852 #ifdef CONFIG_DEBUG_FS
1853 static const char *pl08x_state_str(enum pl08x_dma_chan_state state
)
1856 case PL08X_CHAN_IDLE
:
1858 case PL08X_CHAN_RUNNING
:
1860 case PL08X_CHAN_PAUSED
:
1862 case PL08X_CHAN_WAITING
:
1867 return "UNKNOWN STATE";
1870 static int pl08x_debugfs_show(struct seq_file
*s
, void *data
)
1872 struct pl08x_driver_data
*pl08x
= s
->private;
1873 struct pl08x_dma_chan
*chan
;
1874 struct pl08x_phy_chan
*ch
;
1875 unsigned long flags
;
1878 seq_printf(s
, "PL08x physical channels:\n");
1879 seq_printf(s
, "CHANNEL:\tUSER:\n");
1880 seq_printf(s
, "--------\t-----\n");
1881 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1882 struct pl08x_dma_chan
*virt_chan
;
1884 ch
= &pl08x
->phy_chans
[i
];
1886 spin_lock_irqsave(&ch
->lock
, flags
);
1887 virt_chan
= ch
->serving
;
1889 seq_printf(s
, "%d\t\t%s\n",
1890 ch
->id
, virt_chan
? virt_chan
->name
: "(none)");
1892 spin_unlock_irqrestore(&ch
->lock
, flags
);
1895 seq_printf(s
, "\nPL08x virtual memcpy channels:\n");
1896 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1897 seq_printf(s
, "--------\t------\n");
1898 list_for_each_entry(chan
, &pl08x
->memcpy
.channels
, chan
.device_node
) {
1899 seq_printf(s
, "%s\t\t\%s\n", chan
->name
,
1900 pl08x_state_str(chan
->state
));
1903 seq_printf(s
, "\nPL08x virtual slave channels:\n");
1904 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1905 seq_printf(s
, "--------\t------\n");
1906 list_for_each_entry(chan
, &pl08x
->slave
.channels
, chan
.device_node
) {
1907 seq_printf(s
, "%s\t\t\%s\n", chan
->name
,
1908 pl08x_state_str(chan
->state
));
1914 static int pl08x_debugfs_open(struct inode
*inode
, struct file
*file
)
1916 return single_open(file
, pl08x_debugfs_show
, inode
->i_private
);
1919 static const struct file_operations pl08x_debugfs_operations
= {
1920 .open
= pl08x_debugfs_open
,
1922 .llseek
= seq_lseek
,
1923 .release
= single_release
,
1926 static void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1928 /* Expose a simple debugfs interface to view all clocks */
1929 (void) debugfs_create_file(dev_name(&pl08x
->adev
->dev
), S_IFREG
| S_IRUGO
,
1931 &pl08x_debugfs_operations
);
1935 static inline void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1940 static int pl08x_probe(struct amba_device
*adev
, struct amba_id
*id
)
1942 struct pl08x_driver_data
*pl08x
;
1943 struct vendor_data
*vd
= id
->data
;
1947 ret
= amba_request_regions(adev
, NULL
);
1951 /* Create the driver state holder */
1952 pl08x
= kzalloc(sizeof(struct pl08x_driver_data
), GFP_KERNEL
);
1958 /* Initialize memcpy engine */
1959 dma_cap_set(DMA_MEMCPY
, pl08x
->memcpy
.cap_mask
);
1960 pl08x
->memcpy
.dev
= &adev
->dev
;
1961 pl08x
->memcpy
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1962 pl08x
->memcpy
.device_free_chan_resources
= pl08x_free_chan_resources
;
1963 pl08x
->memcpy
.device_prep_dma_memcpy
= pl08x_prep_dma_memcpy
;
1964 pl08x
->memcpy
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1965 pl08x
->memcpy
.device_tx_status
= pl08x_dma_tx_status
;
1966 pl08x
->memcpy
.device_issue_pending
= pl08x_issue_pending
;
1967 pl08x
->memcpy
.device_control
= pl08x_control
;
1969 /* Initialize slave engine */
1970 dma_cap_set(DMA_SLAVE
, pl08x
->slave
.cap_mask
);
1971 pl08x
->slave
.dev
= &adev
->dev
;
1972 pl08x
->slave
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1973 pl08x
->slave
.device_free_chan_resources
= pl08x_free_chan_resources
;
1974 pl08x
->slave
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1975 pl08x
->slave
.device_tx_status
= pl08x_dma_tx_status
;
1976 pl08x
->slave
.device_issue_pending
= pl08x_issue_pending
;
1977 pl08x
->slave
.device_prep_slave_sg
= pl08x_prep_slave_sg
;
1978 pl08x
->slave
.device_control
= pl08x_control
;
1980 /* Get the platform data */
1981 pl08x
->pd
= dev_get_platdata(&adev
->dev
);
1983 dev_err(&adev
->dev
, "no platform data supplied\n");
1984 goto out_no_platdata
;
1987 /* Assign useful pointers to the driver state */
1991 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1992 pl08x
->pool
= dma_pool_create(DRIVER_NAME
, &pl08x
->adev
->dev
,
1993 PL08X_LLI_TSFR_SIZE
, PL08X_ALIGN
, 0);
1996 goto out_no_lli_pool
;
1999 spin_lock_init(&pl08x
->lock
);
2001 pl08x
->base
= ioremap(adev
->res
.start
, resource_size(&adev
->res
));
2004 goto out_no_ioremap
;
2007 /* Turn on the PL08x */
2008 pl08x_ensure_on(pl08x
);
2011 * Attach the interrupt handler
2013 writel(0x000000FF, pl08x
->base
+ PL080_ERR_CLEAR
);
2014 writel(0x000000FF, pl08x
->base
+ PL080_TC_CLEAR
);
2016 ret
= request_irq(adev
->irq
[0], pl08x_irq
, IRQF_DISABLED
,
2019 dev_err(&adev
->dev
, "%s failed to request interrupt %d\n",
2020 __func__
, adev
->irq
[0]);
2024 /* Initialize physical channels */
2025 pl08x
->phy_chans
= kmalloc((vd
->channels
* sizeof(struct pl08x_phy_chan
)),
2027 if (!pl08x
->phy_chans
) {
2028 dev_err(&adev
->dev
, "%s failed to allocate "
2029 "physical channel holders\n",
2031 goto out_no_phychans
;
2034 for (i
= 0; i
< vd
->channels
; i
++) {
2035 struct pl08x_phy_chan
*ch
= &pl08x
->phy_chans
[i
];
2038 ch
->base
= pl08x
->base
+ PL080_Cx_BASE(i
);
2039 spin_lock_init(&ch
->lock
);
2042 dev_info(&adev
->dev
,
2043 "physical channel %d is %s\n", i
,
2044 pl08x_phy_channel_busy(ch
) ? "BUSY" : "FREE");
2047 /* Register as many memcpy channels as there are physical channels */
2048 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->memcpy
,
2049 pl08x
->vd
->channels
, false);
2051 dev_warn(&pl08x
->adev
->dev
,
2052 "%s failed to enumerate memcpy channels - %d\n",
2056 pl08x
->memcpy
.chancnt
= ret
;
2058 /* Register slave channels */
2059 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->slave
,
2060 pl08x
->pd
->num_slave_channels
,
2063 dev_warn(&pl08x
->adev
->dev
,
2064 "%s failed to enumerate slave channels - %d\n",
2068 pl08x
->slave
.chancnt
= ret
;
2070 ret
= dma_async_device_register(&pl08x
->memcpy
);
2072 dev_warn(&pl08x
->adev
->dev
,
2073 "%s failed to register memcpy as an async device - %d\n",
2075 goto out_no_memcpy_reg
;
2078 ret
= dma_async_device_register(&pl08x
->slave
);
2080 dev_warn(&pl08x
->adev
->dev
,
2081 "%s failed to register slave as an async device - %d\n",
2083 goto out_no_slave_reg
;
2086 amba_set_drvdata(adev
, pl08x
);
2087 init_pl08x_debugfs(pl08x
);
2088 dev_info(&pl08x
->adev
->dev
, "ARM(R) %s DMA block initialized @%08x\n",
2089 vd
->name
, adev
->res
.start
);
2093 dma_async_device_unregister(&pl08x
->memcpy
);
2095 pl08x_free_virtual_channels(&pl08x
->slave
);
2097 pl08x_free_virtual_channels(&pl08x
->memcpy
);
2099 kfree(pl08x
->phy_chans
);
2101 free_irq(adev
->irq
[0], pl08x
);
2103 iounmap(pl08x
->base
);
2105 dma_pool_destroy(pl08x
->pool
);
2110 amba_release_regions(adev
);
2114 /* PL080 has 8 channels and the PL080 have just 2 */
2115 static struct vendor_data vendor_pl080
= {
2121 static struct vendor_data vendor_pl081
= {
2124 .dualmaster
= false,
2127 static struct amba_id pl08x_ids
[] = {
2132 .data
= &vendor_pl080
,
2138 .data
= &vendor_pl081
,
2140 /* Nomadik 8815 PL080 variant */
2144 .data
= &vendor_pl080
,
2149 static struct amba_driver pl08x_amba_driver
= {
2150 .drv
.name
= DRIVER_NAME
,
2151 .id_table
= pl08x_ids
,
2152 .probe
= pl08x_probe
,
2155 static int __init
pl08x_init(void)
2158 retval
= amba_driver_register(&pl08x_amba_driver
);
2160 printk(KERN_WARNING DRIVER_NAME
2161 "failed to register as an AMBA device (%d)\n",
2165 subsys_initcall(pl08x_init
);