2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
31 #include "radeon_drm.h"
32 #include "radeon_reg.h"
36 int radeon_debugfs_ib_init(struct radeon_device
*rdev
);
37 int radeon_debugfs_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
39 u32
radeon_get_ib_value(struct radeon_cs_parser
*p
, int idx
)
41 struct radeon_cs_chunk
*ibc
= &p
->chunks
[p
->chunk_ib_idx
];
42 u32 pg_idx
, pg_offset
;
46 pg_idx
= (idx
* 4) / PAGE_SIZE
;
47 pg_offset
= (idx
* 4) % PAGE_SIZE
;
49 if (ibc
->kpage_idx
[0] == pg_idx
)
50 return ibc
->kpage
[0][pg_offset
/4];
51 if (ibc
->kpage_idx
[1] == pg_idx
)
52 return ibc
->kpage
[1][pg_offset
/4];
54 new_page
= radeon_cs_update_pages(p
, pg_idx
);
56 p
->parser_error
= new_page
;
60 idx_value
= ibc
->kpage
[new_page
][pg_offset
/4];
64 void radeon_ring_write(struct radeon_ring
*ring
, uint32_t v
)
67 if (ring
->count_dw
<= 0) {
68 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
71 ring
->ring
[ring
->wptr
++] = v
;
72 ring
->wptr
&= ring
->ptr_mask
;
80 bool radeon_ib_try_free(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
84 /* only free ib which have been emited */
85 if (ib
->fence
&& ib
->fence
->emitted
) {
86 if (radeon_fence_signaled(ib
->fence
)) {
87 radeon_fence_unref(&ib
->fence
);
88 radeon_sa_bo_free(rdev
, &ib
->sa_bo
);
95 int radeon_ib_get(struct radeon_device
*rdev
, int ring
,
96 struct radeon_ib
**ib
, unsigned size
)
98 struct radeon_fence
*fence
;
103 /* align size on 256 bytes */
104 size
= ALIGN(size
, 256);
106 r
= radeon_fence_create(rdev
, &fence
, ring
);
108 dev_err(rdev
->dev
, "failed to create fence for new IB\n");
112 radeon_mutex_lock(&rdev
->ib_pool
.mutex
);
113 idx
= rdev
->ib_pool
.head_id
;
116 dev_err(rdev
->dev
, "failed to get an ib after 5 retry\n");
117 radeon_mutex_unlock(&rdev
->ib_pool
.mutex
);
118 radeon_fence_unref(&fence
);
122 for (i
= 0; i
< RADEON_IB_POOL_SIZE
; i
++) {
123 radeon_ib_try_free(rdev
, &rdev
->ib_pool
.ibs
[idx
]);
124 if (rdev
->ib_pool
.ibs
[idx
].fence
== NULL
) {
125 r
= radeon_sa_bo_new(rdev
, &rdev
->ib_pool
.sa_manager
,
126 &rdev
->ib_pool
.ibs
[idx
].sa_bo
,
129 *ib
= &rdev
->ib_pool
.ibs
[idx
];
130 (*ib
)->ptr
= rdev
->ib_pool
.sa_manager
.cpu_ptr
;
131 (*ib
)->ptr
+= ((*ib
)->sa_bo
.offset
>> 2);
132 (*ib
)->gpu_addr
= rdev
->ib_pool
.sa_manager
.gpu_addr
;
133 (*ib
)->gpu_addr
+= (*ib
)->sa_bo
.offset
;
134 (*ib
)->fence
= fence
;
136 (*ib
)->is_const_ib
= false;
137 /* ib are most likely to be allocated in a ring fashion
138 * thus rdev->ib_pool.head_id should be the id of the
141 rdev
->ib_pool
.head_id
= (1 + idx
);
142 rdev
->ib_pool
.head_id
&= (RADEON_IB_POOL_SIZE
- 1);
143 radeon_mutex_unlock(&rdev
->ib_pool
.mutex
);
147 idx
= (idx
+ 1) & (RADEON_IB_POOL_SIZE
- 1);
149 /* this should be rare event, ie all ib scheduled none signaled yet.
151 for (i
= 0; i
< RADEON_IB_POOL_SIZE
; i
++) {
152 if (rdev
->ib_pool
.ibs
[idx
].fence
&& rdev
->ib_pool
.ibs
[idx
].fence
->emitted
) {
153 r
= radeon_fence_wait(rdev
->ib_pool
.ibs
[idx
].fence
, false);
157 /* an error happened */
160 idx
= (idx
+ 1) & (RADEON_IB_POOL_SIZE
- 1);
162 radeon_mutex_unlock(&rdev
->ib_pool
.mutex
);
163 radeon_fence_unref(&fence
);
167 void radeon_ib_free(struct radeon_device
*rdev
, struct radeon_ib
**ib
)
169 struct radeon_ib
*tmp
= *ib
;
175 radeon_mutex_lock(&rdev
->ib_pool
.mutex
);
176 if (tmp
->fence
&& !tmp
->fence
->emitted
) {
177 radeon_sa_bo_free(rdev
, &tmp
->sa_bo
);
178 radeon_fence_unref(&tmp
->fence
);
180 radeon_mutex_unlock(&rdev
->ib_pool
.mutex
);
183 int radeon_ib_schedule(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
185 struct radeon_ring
*ring
= &rdev
->ring
[ib
->fence
->ring
];
188 if (!ib
->length_dw
|| !ring
->ready
) {
189 /* TODO: Nothings in the ib we should report. */
190 DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib
->idx
);
194 /* 64 dwords should be enough for fence too */
195 r
= radeon_ring_lock(rdev
, ring
, 64);
197 DRM_ERROR("radeon: scheduling IB failed (%d).\n", r
);
200 radeon_ring_ib_execute(rdev
, ib
->fence
->ring
, ib
);
201 radeon_fence_emit(rdev
, ib
->fence
);
202 radeon_ring_unlock_commit(rdev
, ring
);
206 int radeon_ib_pool_init(struct radeon_device
*rdev
)
208 struct radeon_sa_manager tmp
;
211 r
= radeon_sa_bo_manager_init(rdev
, &tmp
,
212 RADEON_IB_POOL_SIZE
*64*1024,
213 RADEON_GEM_DOMAIN_GTT
);
218 radeon_mutex_lock(&rdev
->ib_pool
.mutex
);
219 if (rdev
->ib_pool
.ready
) {
220 radeon_mutex_unlock(&rdev
->ib_pool
.mutex
);
221 radeon_sa_bo_manager_fini(rdev
, &tmp
);
225 rdev
->ib_pool
.sa_manager
= tmp
;
226 INIT_LIST_HEAD(&rdev
->ib_pool
.sa_manager
.sa_bo
);
227 for (i
= 0; i
< RADEON_IB_POOL_SIZE
; i
++) {
228 rdev
->ib_pool
.ibs
[i
].fence
= NULL
;
229 rdev
->ib_pool
.ibs
[i
].idx
= i
;
230 rdev
->ib_pool
.ibs
[i
].length_dw
= 0;
231 INIT_LIST_HEAD(&rdev
->ib_pool
.ibs
[i
].sa_bo
.list
);
233 rdev
->ib_pool
.head_id
= 0;
234 rdev
->ib_pool
.ready
= true;
235 DRM_INFO("radeon: ib pool ready.\n");
237 if (radeon_debugfs_ib_init(rdev
)) {
238 DRM_ERROR("Failed to register debugfs file for IB !\n");
240 radeon_mutex_unlock(&rdev
->ib_pool
.mutex
);
244 void radeon_ib_pool_fini(struct radeon_device
*rdev
)
248 radeon_mutex_lock(&rdev
->ib_pool
.mutex
);
249 if (rdev
->ib_pool
.ready
) {
250 for (i
= 0; i
< RADEON_IB_POOL_SIZE
; i
++) {
251 radeon_sa_bo_free(rdev
, &rdev
->ib_pool
.ibs
[i
].sa_bo
);
252 radeon_fence_unref(&rdev
->ib_pool
.ibs
[i
].fence
);
254 radeon_sa_bo_manager_fini(rdev
, &rdev
->ib_pool
.sa_manager
);
255 rdev
->ib_pool
.ready
= false;
257 radeon_mutex_unlock(&rdev
->ib_pool
.mutex
);
260 int radeon_ib_pool_start(struct radeon_device
*rdev
)
262 return radeon_sa_bo_manager_start(rdev
, &rdev
->ib_pool
.sa_manager
);
265 int radeon_ib_pool_suspend(struct radeon_device
*rdev
)
267 return radeon_sa_bo_manager_suspend(rdev
, &rdev
->ib_pool
.sa_manager
);
270 int radeon_ib_ring_tests(struct radeon_device
*rdev
)
275 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
276 struct radeon_ring
*ring
= &rdev
->ring
[i
];
281 r
= radeon_ib_test(rdev
, i
, ring
);
285 if (i
== RADEON_RING_TYPE_GFX_INDEX
) {
286 /* oh, oh, that's really bad */
287 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r
);
288 rdev
->accel_working
= false;
292 /* still not good, but we can live with it */
293 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i
, r
);
303 int radeon_ring_index(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
305 /* r1xx-r5xx only has CP ring */
306 if (rdev
->family
< CHIP_R600
)
307 return RADEON_RING_TYPE_GFX_INDEX
;
309 if (rdev
->family
>= CHIP_CAYMAN
) {
310 if (ring
== &rdev
->ring
[CAYMAN_RING_TYPE_CP1_INDEX
])
311 return CAYMAN_RING_TYPE_CP1_INDEX
;
312 else if (ring
== &rdev
->ring
[CAYMAN_RING_TYPE_CP2_INDEX
])
313 return CAYMAN_RING_TYPE_CP2_INDEX
;
315 return RADEON_RING_TYPE_GFX_INDEX
;
318 void radeon_ring_free_size(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
322 if (rdev
->wb
.enabled
)
323 rptr
= le32_to_cpu(rdev
->wb
.wb
[ring
->rptr_offs
/4]);
325 rptr
= RREG32(ring
->rptr_reg
);
326 ring
->rptr
= (rptr
& ring
->ptr_reg_mask
) >> ring
->ptr_reg_shift
;
327 /* This works because ring_size is a power of 2 */
328 ring
->ring_free_dw
= (ring
->rptr
+ (ring
->ring_size
/ 4));
329 ring
->ring_free_dw
-= ring
->wptr
;
330 ring
->ring_free_dw
&= ring
->ptr_mask
;
331 if (!ring
->ring_free_dw
) {
332 ring
->ring_free_dw
= ring
->ring_size
/ 4;
337 int radeon_ring_alloc(struct radeon_device
*rdev
, struct radeon_ring
*ring
, unsigned ndw
)
341 /* Align requested size with padding so unlock_commit can
343 ndw
= (ndw
+ ring
->align_mask
) & ~ring
->align_mask
;
344 while (ndw
> (ring
->ring_free_dw
- 1)) {
345 radeon_ring_free_size(rdev
, ring
);
346 if (ndw
< ring
->ring_free_dw
) {
349 mutex_unlock(&rdev
->ring_lock
);
350 r
= radeon_fence_wait_next(rdev
, radeon_ring_index(rdev
, ring
));
351 mutex_lock(&rdev
->ring_lock
);
355 ring
->count_dw
= ndw
;
356 ring
->wptr_old
= ring
->wptr
;
360 int radeon_ring_lock(struct radeon_device
*rdev
, struct radeon_ring
*ring
, unsigned ndw
)
364 mutex_lock(&rdev
->ring_lock
);
365 r
= radeon_ring_alloc(rdev
, ring
, ndw
);
367 mutex_unlock(&rdev
->ring_lock
);
373 void radeon_ring_commit(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
375 unsigned count_dw_pad
;
378 /* We pad to match fetch size */
379 count_dw_pad
= (ring
->align_mask
+ 1) -
380 (ring
->wptr
& ring
->align_mask
);
381 for (i
= 0; i
< count_dw_pad
; i
++) {
382 radeon_ring_write(ring
, ring
->nop
);
385 WREG32(ring
->wptr_reg
, (ring
->wptr
<< ring
->ptr_reg_shift
) & ring
->ptr_reg_mask
);
386 (void)RREG32(ring
->wptr_reg
);
389 void radeon_ring_unlock_commit(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
391 radeon_ring_commit(rdev
, ring
);
392 mutex_unlock(&rdev
->ring_lock
);
395 void radeon_ring_undo(struct radeon_ring
*ring
)
397 ring
->wptr
= ring
->wptr_old
;
400 void radeon_ring_unlock_undo(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
402 radeon_ring_undo(ring
);
403 mutex_unlock(&rdev
->ring_lock
);
406 void radeon_ring_force_activity(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
410 mutex_lock(&rdev
->ring_lock
);
411 radeon_ring_free_size(rdev
, ring
);
412 if (ring
->rptr
== ring
->wptr
) {
413 r
= radeon_ring_alloc(rdev
, ring
, 1);
415 radeon_ring_write(ring
, ring
->nop
);
416 radeon_ring_commit(rdev
, ring
);
419 mutex_unlock(&rdev
->ring_lock
);
422 void radeon_ring_lockup_update(struct radeon_ring
*ring
)
424 ring
->last_rptr
= ring
->rptr
;
425 ring
->last_activity
= jiffies
;
429 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
430 * @rdev: radeon device structure
431 * @ring: radeon_ring structure holding ring information
433 * We don't need to initialize the lockup tracking information as we will either
434 * have CP rptr to a different value of jiffies wrap around which will force
435 * initialization of the lockup tracking informations.
437 * A possible false positivie is if we get call after while and last_cp_rptr ==
438 * the current CP rptr, even if it's unlikely it might happen. To avoid this
439 * if the elapsed time since last call is bigger than 2 second than we return
440 * false and update the tracking information. Due to this the caller must call
441 * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported
442 * the fencing code should be cautious about that.
444 * Caller should write to the ring to force CP to do something so we don't get
445 * false positive when CP is just gived nothing to do.
448 bool radeon_ring_test_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
450 unsigned long cjiffies
, elapsed
;
454 if (!time_after(cjiffies
, ring
->last_activity
)) {
455 /* likely a wrap around */
456 radeon_ring_lockup_update(ring
);
459 rptr
= RREG32(ring
->rptr_reg
);
460 ring
->rptr
= (rptr
& ring
->ptr_reg_mask
) >> ring
->ptr_reg_shift
;
461 if (ring
->rptr
!= ring
->last_rptr
) {
462 /* CP is still working no lockup */
463 radeon_ring_lockup_update(ring
);
466 elapsed
= jiffies_to_msecs(cjiffies
- ring
->last_activity
);
467 if (radeon_lockup_timeout
&& elapsed
>= radeon_lockup_timeout
) {
468 dev_err(rdev
->dev
, "GPU lockup CP stall for more than %lumsec\n", elapsed
);
471 /* give a chance to the GPU ... */
475 int radeon_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*ring
, unsigned ring_size
,
476 unsigned rptr_offs
, unsigned rptr_reg
, unsigned wptr_reg
,
477 u32 ptr_reg_shift
, u32 ptr_reg_mask
, u32 nop
)
481 ring
->ring_size
= ring_size
;
482 ring
->rptr_offs
= rptr_offs
;
483 ring
->rptr_reg
= rptr_reg
;
484 ring
->wptr_reg
= wptr_reg
;
485 ring
->ptr_reg_shift
= ptr_reg_shift
;
486 ring
->ptr_reg_mask
= ptr_reg_mask
;
488 /* Allocate ring buffer */
489 if (ring
->ring_obj
== NULL
) {
490 r
= radeon_bo_create(rdev
, ring
->ring_size
, PAGE_SIZE
, true,
491 RADEON_GEM_DOMAIN_GTT
,
494 dev_err(rdev
->dev
, "(%d) ring create failed\n", r
);
497 r
= radeon_bo_reserve(ring
->ring_obj
, false);
498 if (unlikely(r
!= 0))
500 r
= radeon_bo_pin(ring
->ring_obj
, RADEON_GEM_DOMAIN_GTT
,
503 radeon_bo_unreserve(ring
->ring_obj
);
504 dev_err(rdev
->dev
, "(%d) ring pin failed\n", r
);
507 r
= radeon_bo_kmap(ring
->ring_obj
,
508 (void **)&ring
->ring
);
509 radeon_bo_unreserve(ring
->ring_obj
);
511 dev_err(rdev
->dev
, "(%d) ring map failed\n", r
);
515 ring
->ptr_mask
= (ring
->ring_size
/ 4) - 1;
516 ring
->ring_free_dw
= ring
->ring_size
/ 4;
517 if (radeon_debugfs_ring_init(rdev
, ring
)) {
518 DRM_ERROR("Failed to register debugfs file for rings !\n");
523 void radeon_ring_fini(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
526 struct radeon_bo
*ring_obj
;
528 mutex_lock(&rdev
->ring_lock
);
529 ring_obj
= ring
->ring_obj
;
532 ring
->ring_obj
= NULL
;
533 mutex_unlock(&rdev
->ring_lock
);
536 r
= radeon_bo_reserve(ring_obj
, false);
537 if (likely(r
== 0)) {
538 radeon_bo_kunmap(ring_obj
);
539 radeon_bo_unpin(ring_obj
);
540 radeon_bo_unreserve(ring_obj
);
542 radeon_bo_unref(&ring_obj
);
549 #if defined(CONFIG_DEBUG_FS)
551 static int radeon_debugfs_ring_info(struct seq_file
*m
, void *data
)
553 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
554 struct drm_device
*dev
= node
->minor
->dev
;
555 struct radeon_device
*rdev
= dev
->dev_private
;
556 int ridx
= *(int*)node
->info_ent
->data
;
557 struct radeon_ring
*ring
= &rdev
->ring
[ridx
];
558 unsigned count
, i
, j
;
560 radeon_ring_free_size(rdev
, ring
);
561 count
= (ring
->ring_size
/ 4) - ring
->ring_free_dw
;
562 seq_printf(m
, "wptr(0x%04x): 0x%08x\n", ring
->wptr_reg
, RREG32(ring
->wptr_reg
));
563 seq_printf(m
, "rptr(0x%04x): 0x%08x\n", ring
->rptr_reg
, RREG32(ring
->rptr_reg
));
564 seq_printf(m
, "driver's copy of the wptr: 0x%08x\n", ring
->wptr
);
565 seq_printf(m
, "driver's copy of the rptr: 0x%08x\n", ring
->rptr
);
566 seq_printf(m
, "%u free dwords in ring\n", ring
->ring_free_dw
);
567 seq_printf(m
, "%u dwords in ring\n", count
);
569 for (j
= 0; j
<= count
; j
++) {
570 seq_printf(m
, "r[%04d]=0x%08x\n", i
, ring
->ring
[i
]);
571 i
= (i
+ 1) & ring
->ptr_mask
;
576 static int radeon_ring_type_gfx_index
= RADEON_RING_TYPE_GFX_INDEX
;
577 static int cayman_ring_type_cp1_index
= CAYMAN_RING_TYPE_CP1_INDEX
;
578 static int cayman_ring_type_cp2_index
= CAYMAN_RING_TYPE_CP2_INDEX
;
580 static struct drm_info_list radeon_debugfs_ring_info_list
[] = {
581 {"radeon_ring_gfx", radeon_debugfs_ring_info
, 0, &radeon_ring_type_gfx_index
},
582 {"radeon_ring_cp1", radeon_debugfs_ring_info
, 0, &cayman_ring_type_cp1_index
},
583 {"radeon_ring_cp2", radeon_debugfs_ring_info
, 0, &cayman_ring_type_cp2_index
},
586 static int radeon_debugfs_ib_info(struct seq_file
*m
, void *data
)
588 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
589 struct drm_device
*dev
= node
->minor
->dev
;
590 struct radeon_device
*rdev
= dev
->dev_private
;
591 struct radeon_ib
*ib
= &rdev
->ib_pool
.ibs
[*((unsigned*)node
->info_ent
->data
)];
597 seq_printf(m
, "IB %04u\n", ib
->idx
);
598 seq_printf(m
, "IB fence %p\n", ib
->fence
);
599 seq_printf(m
, "IB size %05u dwords\n", ib
->length_dw
);
600 for (i
= 0; i
< ib
->length_dw
; i
++) {
601 seq_printf(m
, "[%05u]=0x%08X\n", i
, ib
->ptr
[i
]);
606 static struct drm_info_list radeon_debugfs_ib_list
[RADEON_IB_POOL_SIZE
];
607 static char radeon_debugfs_ib_names
[RADEON_IB_POOL_SIZE
][32];
608 static unsigned radeon_debugfs_ib_idx
[RADEON_IB_POOL_SIZE
];
611 int radeon_debugfs_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
613 #if defined(CONFIG_DEBUG_FS)
615 for (i
= 0; i
< ARRAY_SIZE(radeon_debugfs_ring_info_list
); ++i
) {
616 struct drm_info_list
*info
= &radeon_debugfs_ring_info_list
[i
];
617 int ridx
= *(int*)radeon_debugfs_ring_info_list
[i
].data
;
620 if (&rdev
->ring
[ridx
] != ring
)
623 r
= radeon_debugfs_add_files(rdev
, info
, 1);
631 int radeon_debugfs_ib_init(struct radeon_device
*rdev
)
633 #if defined(CONFIG_DEBUG_FS)
636 for (i
= 0; i
< RADEON_IB_POOL_SIZE
; i
++) {
637 sprintf(radeon_debugfs_ib_names
[i
], "radeon_ib_%04u", i
);
638 radeon_debugfs_ib_idx
[i
] = i
;
639 radeon_debugfs_ib_list
[i
].name
= radeon_debugfs_ib_names
[i
];
640 radeon_debugfs_ib_list
[i
].show
= &radeon_debugfs_ib_info
;
641 radeon_debugfs_ib_list
[i
].driver_features
= 0;
642 radeon_debugfs_ib_list
[i
].data
= &radeon_debugfs_ib_idx
[i
];
644 return radeon_debugfs_add_files(rdev
, radeon_debugfs_ib_list
,
645 RADEON_IB_POOL_SIZE
);